post/lib_ppc/threex.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25
  26 /*
  27  * CPU test
  28  * Ternary instructions         instr rA,rS,rB
  29  *
  30  * Logic instructions:          or, orc, xor, nand, nor, eqv
  31  * Shift instructions:          slw, srw, sraw
  32  *
  33  * The test contains a pre-built table of instructions, operands and
  34  * expected results. For each table entry, the test will cyclically use
  35  * different sets of operand registers and result registers.
  36  */
  37
  38 #ifdef CONFIG_POST
  39
  40 #include <post.h>
  41 #include "cpu_asm.h"
  42
  43 #if CONFIG_POST & CFG_POST_CPU
  44
  45 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
  46     ulong op2);
  47 extern ulong cpu_post_makecr (long v);
  48
  49 static struct cpu_post_threex_s
  50 {
  51     ulong cmd;
  52     ulong op1;
  53     ulong op2;
  54     ulong res;
  55 } cpu_post_threex_table[] =
  56 {
  57     {
  58         OP_OR,
  59         0x1234,
  60         0x5678,
  61         0x1234 | 0x5678
  62     },
  63     {
  64         OP_ORC,
  65         0x1234,
  66         0x5678,
  67         0x1234 | ~0x5678
  68     },
  69     {
  70         OP_XOR,
  71         0x1234,
  72         0x5678,
  73         0x1234 ^ 0x5678
  74     },
  75     {
  76         OP_NAND,
  77         0x1234,
  78         0x5678,
  79         ~(0x1234 & 0x5678)
  80     },
  81     {
  82         OP_NOR,
  83         0x1234,
  84         0x5678,
  85         ~(0x1234 | 0x5678)
  86     },
  87     {
  88         OP_EQV,
  89         0x1234,
  90         0x5678,
  91         ~(0x1234 ^ 0x5678)
  92     },
  93     {
  94         OP_SLW,
  95         0x80,
  96         16,
  97         0x800000
  98     },
  99     {
 100         OP_SLW,
 101         0x80,
 102         32,
 103         0
 104     },
 105     {
 106         OP_SRW,
 107         0x800000,
 108         16,
 109         0x80
 110     },
 111     {
 112         OP_SRW,
 113         0x800000,
 114         32,
 115         0
 116     },
 117     {
 118         OP_SRAW,
 119         0x80000000,
 120         3,
 121         0xf0000000
 122     },
 123     {
 124         OP_SRAW,
 125         0x8000,
 126         3,
 127         0x1000
 128     },
 129 };
 130 static unsigned int cpu_post_threex_size =
 131     sizeof (cpu_post_threex_table) / sizeof (struct cpu_post_threex_s);
 132
 133 int cpu_post_test_threex (void)
 134 {
 135     int ret = 0;
 136     unsigned int i, reg;
 137     int flag = disable_interrupts();
 138
 139     for (i = 0; i < cpu_post_threex_size && ret == 0; i++)
 140     {
 141         struct cpu_post_threex_s *test = cpu_post_threex_table + i;
 142
 143         for (reg = 0; reg < 32 && ret == 0; reg++)
 144         {
 145             unsigned int reg0 = (reg + 0) % 32;
 146             unsigned int reg1 = (reg + 1) % 32;
 147             unsigned int reg2 = (reg + 2) % 32;
 148             unsigned int stk = reg < 16 ? 31 : 15;
 149             unsigned long code[] =
 150             {
 151                 ASM_STW(stk, 1, -4),
 152                 ASM_ADDI(stk, 1, -24),
 153                 ASM_STW(3, stk, 12),
 154                 ASM_STW(4, stk, 16),
 155                 ASM_STW(reg0, stk, 8),
 156                 ASM_STW(reg1, stk, 4),
 157                 ASM_STW(reg2, stk, 0),
 158                 ASM_LWZ(reg1, stk, 12),
 159                 ASM_LWZ(reg0, stk, 16),
 160                 ASM_12X(test->cmd, reg2, reg1, reg0),
 161                 ASM_STW(reg2, stk, 12),
 162                 ASM_LWZ(reg2, stk, 0),
 163                 ASM_LWZ(reg1, stk, 4),
 164                 ASM_LWZ(reg0, stk, 8),
 165                 ASM_LWZ(3, stk, 12),
 166                 ASM_ADDI(1, stk, 24),
 167                 ASM_LWZ(stk, 1, -4),
 168                 ASM_BLR,
 169             };
 170             unsigned long codecr[] =
 171             {
 172                 ASM_STW(stk, 1, -4),
 173                 ASM_ADDI(stk, 1, -24),
 174                 ASM_STW(3, stk, 12),
 175                 ASM_STW(4, stk, 16),
 176                 ASM_STW(reg0, stk, 8),
 177                 ASM_STW(reg1, stk, 4),
 178                 ASM_STW(reg2, stk, 0),
 179                 ASM_LWZ(reg1, stk, 12),
 180                 ASM_LWZ(reg0, stk, 16),
 181                 ASM_12X(test->cmd, reg2, reg1, reg0) | BIT_C,
 182                 ASM_STW(reg2, stk, 12),
 183                 ASM_LWZ(reg2, stk, 0),
 184                 ASM_LWZ(reg1, stk, 4),
 185                 ASM_LWZ(reg0, stk, 8),
 186                 ASM_LWZ(3, stk, 12),
 187                 ASM_ADDI(1, stk, 24),
 188                 ASM_LWZ(stk, 1, -4),
 189                 ASM_BLR,
 190             };
 191             ulong res;
 192             ulong cr;
 193
 194             if (ret == 0)
 195             {
 196                 cr = 0;
 197                 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
 198
 199                 ret = res == test->res && cr == 0 ? 0 : -1;
 200
 201                 if (ret != 0)
 202                 {
 203                     post_log ("Error at threex test %d !\n", i);
 204                 }
 205             }
 206
 207             if (ret == 0)
 208             {
 209                 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
 210
 211                 ret = res == test->res &&
 212                       (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
 213
 214                 if (ret != 0)
 215                 {
 216                     post_log ("Error at threex test %d !\n", i);
 217                 }
 218             }
 219         }
 220     }
 221
 222     if (flag)
 223         enable_interrupts();
 224
 225     return ret;
 226 }
 227
 228 #endif
 229 #endif