post/lib_ppc/rlwinm.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25
  26 /*
  27  * CPU test
  28  * Shift instructions:          rlwinm
  29  *
  30  * The test contains a pre-built table of instructions, operands and
  31  * expected results. For each table entry, the test will cyclically use
  32  * different sets of operand registers and result registers.
  33  */
  34
  35 #ifdef CONFIG_POST
  36
  37 #include <post.h>
  38 #include "cpu_asm.h"
  39
  40 #if CONFIG_POST & CFG_POST_CPU
  41
  42 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
  43 extern ulong cpu_post_makecr (long v);
  44
  45 static struct cpu_post_rlwinm_s
  46 {
  47     ulong cmd;
  48     ulong op1;
  49     uchar op2;
  50     uchar mb;
  51     uchar me;
  52     ulong res;
  53 } cpu_post_rlwinm_table[] =
  54 {
  55    {
  56         OP_RLWINM,
  57         0xffff0000,
  58         24,
  59         16,
  60         23,
  61         0x0000ff00
  62    },
  63 };
  64 static unsigned int cpu_post_rlwinm_size =
  65     sizeof (cpu_post_rlwinm_table) / sizeof (struct cpu_post_rlwinm_s);
  66
  67 int cpu_post_test_rlwinm (void)
  68 {
  69     int ret = 0;
  70     unsigned int i, reg;
  71     int flag = disable_interrupts();
  72
  73     for (i = 0; i < cpu_post_rlwinm_size && ret == 0; i++)
  74     {
  75         struct cpu_post_rlwinm_s *test = cpu_post_rlwinm_table + i;
  76
  77         for (reg = 0; reg < 32 && ret == 0; reg++)
  78         {
  79             unsigned int reg0 = (reg + 0) % 32;
  80             unsigned int reg1 = (reg + 1) % 32;
  81             unsigned int stk = reg < 16 ? 31 : 15;
  82             unsigned long code[] =
  83             {
  84                 ASM_STW(stk, 1, -4),
  85                 ASM_ADDI(stk, 1, -16),
  86                 ASM_STW(3, stk, 8),
  87                 ASM_STW(reg0, stk, 4),
  88                 ASM_STW(reg1, stk, 0),
  89                 ASM_LWZ(reg0, stk, 8),
  90                 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me),
  91                 ASM_STW(reg1, stk, 8),
  92                 ASM_LWZ(reg1, stk, 0),
  93                 ASM_LWZ(reg0, stk, 4),
  94                 ASM_LWZ(3, stk, 8),
  95                 ASM_ADDI(1, stk, 16),
  96                 ASM_LWZ(stk, 1, -4),
  97                 ASM_BLR,
  98             };
  99             unsigned long codecr[] =
 100             {
 101                 ASM_STW(stk, 1, -4),
 102                 ASM_ADDI(stk, 1, -16),
 103                 ASM_STW(3, stk, 8),
 104                 ASM_STW(reg0, stk, 4),
 105                 ASM_STW(reg1, stk, 0),
 106                 ASM_LWZ(reg0, stk, 8),
 107                 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb,
 108                     test->me) | BIT_C,
 109                 ASM_STW(reg1, stk, 8),
 110                 ASM_LWZ(reg1, stk, 0),
 111                 ASM_LWZ(reg0, stk, 4),
 112                 ASM_LWZ(3, stk, 8),
 113                 ASM_ADDI(1, stk, 16),
 114                 ASM_LWZ(stk, 1, -4),
 115                 ASM_BLR,
 116             };
 117             ulong res;
 118             ulong cr;
 119
 120             if (ret == 0)
 121             {
 122                 cr = 0;
 123                 cpu_post_exec_21 (code, & cr, & res, test->op1);
 124
 125                 ret = res == test->res && cr == 0 ? 0 : -1;
 126
 127                 if (ret != 0)
 128                 {
 129                     post_log ("Error at rlwinm test %d !\n", i);
 130                 }
 131             }
 132
 133             if (ret == 0)
 134             {
 135                 cpu_post_exec_21 (codecr, & cr, & res, test->op1);
 136
 137                 ret = res == test->res &&
 138                       (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
 139
 140                 if (ret != 0)
 141                 {
 142                     post_log ("Error at rlwinm test %d !\n", i);
 143                 }
 144             }
 145         }
 146     }
 147
 148     if (flag)
 149         enable_interrupts();
 150
 151     return ret;
 152 }
 153
 154 #endif
 155 #endif