include/ppc405.h

   1 /*----------------------------------------------------------------------------+
   2 |
   3 |       This source code has been made available to you by IBM on an AS-IS
   4 |       basis.  Anyone receiving this source is licensed under IBM
   5 |       copyrights to use it in any way he or she deems fit, including
   6 |       copying it, modifying it, compiling it, and redistributing it either
   7 |       with or without modifications.  No license under IBM patents or
   8 |       patent applications is to be implied by the copyright license.
   9 |
  10 |       Any user of this software should understand that IBM cannot provide
  11 |       technical support for this software and will not be responsible for
  12 |       any consequences resulting from the use of this software.
  13 |
  14 |       Any person who transfers this source code or any derivative work
  15 |       must include the IBM copyright notice, this paragraph, and the
  16 |       preceding two paragraphs in the transferred software.
  17 |
  18 |       COPYRIGHT   I B M   CORPORATION 1999
  19 |       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  20 +----------------------------------------------------------------------------*/
  21
  22 #ifndef __PPC405_H__
  23 #define __PPC405_H__
  24
  25 #ifndef CONFIG_IOP480
  26 #define CFG_DCACHE_SIZE         (16 << 10)      /* For AMCC 405 CPUs    */
  27 #else
  28 #define CFG_DCACHE_SIZE         (2 << 10)       /* For PLX IOP480 (403) */
  29 #endif
  30
  31 /*--------------------------------------------------------------------- */
  32 /* Special Purpose Registers                                            */
  33 /*--------------------------------------------------------------------- */
  34         #define  srr2  0x3de      /* save/restore register 2 */
  35         #define  srr3  0x3df      /* save/restore register 3 */
  36
  37         /*
  38          * 405 does not really have CSRR0/1 but SRR2/3 are used during critical
  39          * exception for the exact same purposes - let's alias them and have a
  40          * common handling in crit_return() and CRIT_EXCEPTION
  41          */
  42         #define  csrr0 srr2
  43         #define  csrr1 srr3
  44
  45         #define  dbsr  0x3f0      /* debug status register */
  46         #define  dbcr0 0x3f2      /* debug control register 0 */
  47         #define  dbcr1 0x3bd      /* debug control register 1 */
  48         #define  iac1  0x3f4      /* instruction address comparator 1 */
  49         #define  iac2  0x3f5      /* instruction address comparator 2 */
  50         #define  iac3  0x3b4      /* instruction address comparator 3 */
  51         #define  iac4  0x3b5      /* instruction address comparator 4 */
  52         #define  dac1  0x3f6      /* data address comparator 1 */
  53         #define  dac2  0x3f7      /* data address comparator 2 */
  54         #define  dccr  0x3fa      /* data cache control register */
  55         #define  iccr  0x3fb      /* instruction cache control register */
  56         #define  esr   0x3d4      /* execption syndrome register */
  57         #define  dear  0x3d5      /* data exeption address register */
  58         #define  evpr  0x3d6      /* exeption vector prefix register */
  59         #define  tsr   0x3d8      /* timer status register */
  60         #define  tcr   0x3da      /* timer control register */
  61         #define  pit   0x3db      /* programmable interval timer */
  62         #define  sgr   0x3b9      /* storage guarded reg      */
  63         #define  dcwr  0x3ba      /* data cache write-thru reg*/
  64         #define  sler  0x3bb      /* storage little-endian reg */
  65         #define  cdbcr 0x3d7      /* cache debug cntrl reg    */
  66         #define  icdbdr 0x3d3     /* instr cache dbug data reg*/
  67         #define  ccr0  0x3b3      /* core configuration register */
  68         #define  dvc1  0x3b6      /* data value compare register 1 */
  69         #define  dvc2  0x3b7      /* data value compare register 2 */
  70         #define  pid   0x3b1      /* process ID */
  71         #define  su0r  0x3bc      /* storage user-defined register 0 */
  72         #define  zpr   0x3b0      /* zone protection regsiter */
  73
  74         #define  tbl   0x11c      /* time base lower - privileged write */
  75         #define  tbu   0x11d      /* time base upper - privileged write */
  76
  77         #define  sprg4r 0x104     /* Special purpose general 4 - read only */
  78         #define  sprg5r 0x105     /* Special purpose general 5 - read only */
  79         #define  sprg6r 0x106     /* Special purpose general 6 - read only */
  80         #define  sprg7r 0x107     /* Special purpose general 7 - read only */
  81         #define  sprg4w 0x114     /* Special purpose general 4 - write only */
  82         #define  sprg5w 0x115     /* Special purpose general 5 - write only */
  83         #define  sprg6w 0x116     /* Special purpose general 6 - write only */
  84         #define  sprg7w 0x117     /* Special purpose general 7 - write only */
  85
  86 /******************************************************************************
  87  * Special for PPC405GP
  88  ******************************************************************************/
  89
  90 /******************************************************************************
  91  * DMA
  92  ******************************************************************************/
  93 #define DMA_DCR_BASE 0x100
  94 #define dmacr0  (DMA_DCR_BASE+0x00)  /* DMA channel control register 0       */
  95 #define dmact0  (DMA_DCR_BASE+0x01)  /* DMA count register 0                 */
  96 #define dmada0  (DMA_DCR_BASE+0x02)  /* DMA destination address register 0   */
  97 #define dmasa0  (DMA_DCR_BASE+0x03)  /* DMA source address register 0        */
  98 #define dmasb0  (DMA_DCR_BASE+0x04)  /* DMA scatter/gather descriptor addr 0 */
  99 #define dmacr1  (DMA_DCR_BASE+0x08)  /* DMA channel control register 1       */
 100 #define dmact1  (DMA_DCR_BASE+0x09)  /* DMA count register 1                 */
 101 #define dmada1  (DMA_DCR_BASE+0x0a)  /* DMA destination address register 1   */
 102 #define dmasa1  (DMA_DCR_BASE+0x0b)  /* DMA source address register 1        */
 103 #define dmasb1  (DMA_DCR_BASE+0x0c)  /* DMA scatter/gather descriptor addr 1 */
 104 #define dmacr2  (DMA_DCR_BASE+0x10)  /* DMA channel control register 2       */
 105 #define dmact2  (DMA_DCR_BASE+0x11)  /* DMA count register 2                 */
 106 #define dmada2  (DMA_DCR_BASE+0x12)  /* DMA destination address register 2   */
 107 #define dmasa2  (DMA_DCR_BASE+0x13)  /* DMA source address register 2        */
 108 #define dmasb2  (DMA_DCR_BASE+0x14)  /* DMA scatter/gather descriptor addr 2 */
 109 #define dmacr3  (DMA_DCR_BASE+0x18)  /* DMA channel control register 3       */
 110 #define dmact3  (DMA_DCR_BASE+0x19)  /* DMA count register 3                 */
 111 #define dmada3  (DMA_DCR_BASE+0x1a)  /* DMA destination address register 3   */
 112 #define dmasa3  (DMA_DCR_BASE+0x1b)  /* DMA source address register 3        */
 113 #define dmasb3  (DMA_DCR_BASE+0x1c)  /* DMA scatter/gather descriptor addr 3 */
 114 #define dmasr   (DMA_DCR_BASE+0x20)  /* DMA status register                  */
 115 #define dmasgc  (DMA_DCR_BASE+0x23)  /* DMA scatter/gather command register  */
 116 #define dmaadr  (DMA_DCR_BASE+0x24)  /* DMA address decode register          */
 117
 118 /******************************************************************************
 119  * Universal interrupt controller
 120  ******************************************************************************/
 121 #define UIC_DCR_BASE 0xc0
 122 #define uicsr        (UIC_DCR_BASE+0x0)  /* UIC status                       */
 123 #define uicsrs       (UIC_DCR_BASE+0x1)  /* UIC status set                   */
 124 #define uicer        (UIC_DCR_BASE+0x2)  /* UIC enable                       */
 125 #define uiccr        (UIC_DCR_BASE+0x3)  /* UIC critical                     */
 126 #define uicpr        (UIC_DCR_BASE+0x4)  /* UIC polarity                     */
 127 #define uictr        (UIC_DCR_BASE+0x5)  /* UIC triggering                   */
 128 #define uicmsr       (UIC_DCR_BASE+0x6)  /* UIC masked status                */
 129 #define uicvr        (UIC_DCR_BASE+0x7)  /* UIC vector                       */
 130 #define uicvcr       (UIC_DCR_BASE+0x8)  /* UIC vector configuration         */
 131
 132 #if defined(CONFIG_405EX)
 133 #define uic0sr        uicsr             /* UIC status            */
 134 #define uic0srs       uicsrs            /* UIC status set        */
 135 #define uic0er        uicer             /* UIC enable            */
 136 #define uic0cr        uiccr             /* UIC critical          */
 137 #define uic0pr        uicpr             /* UIC polarity          */
 138 #define uic0tr        uictr             /* UIC triggering        */
 139 #define uic0msr       uicmsr            /* UIC masked status     */
 140 #define uic0vr        uicvr             /* UIC vector            */
 141 #define uic0vcr       uicvcr            /* UIC vector configuration*/
 142
 143 #define UIC_DCR_BASE1 0xd0
 144 #define uic1sr        (UIC_DCR_BASE1+0x0)  /* UIC status            */
 145 #define uic1srs       (UIC_DCR_BASE1+0x1)  /* UIC status set        */
 146 #define uic1er        (UIC_DCR_BASE1+0x2)  /* UIC enable            */
 147 #define uic1cr        (UIC_DCR_BASE1+0x3)  /* UIC critical          */
 148 #define uic1pr        (UIC_DCR_BASE1+0x4)  /* UIC polarity          */
 149 #define uic1tr        (UIC_DCR_BASE1+0x5)  /* UIC triggering        */
 150 #define uic1msr       (UIC_DCR_BASE1+0x6)  /* UIC masked status     */
 151 #define uic1vr        (UIC_DCR_BASE1+0x7)  /* UIC vector            */
 152 #define uic1vcr       (UIC_DCR_BASE1+0x8)  /* UIC vector configuration*/
 153
 154 #define UIC_DCR_BASE2 0xe0
 155 #define uic2sr        (UIC_DCR_BASE2+0x0)  /* UIC status            */
 156 #define uic2srs       (UIC_DCR_BASE2+0x1)  /* UIC status set        */
 157 #define uic2er        (UIC_DCR_BASE2+0x2)  /* UIC enable            */
 158 #define uic2cr        (UIC_DCR_BASE2+0x3)  /* UIC critical          */
 159 #define uic2pr        (UIC_DCR_BASE2+0x4)  /* UIC polarity          */
 160 #define uic2tr        (UIC_DCR_BASE2+0x5)  /* UIC triggering        */
 161 #define uic2msr       (UIC_DCR_BASE2+0x6)  /* UIC masked status     */
 162 #define uic2vr        (UIC_DCR_BASE2+0x7)  /* UIC vector            */
 163 #define uic2vcr       (UIC_DCR_BASE2+0x8)  /* UIC vector configuration*/
 164 #endif
 165
 166 /*-----------------------------------------------------------------------------+
 167 |  Universal interrupt controller interrupts
 168 +-----------------------------------------------------------------------------*/
 169 #if defined(CONFIG_405EZ)
 170 #define UIC_DMA0        0x80000000      /* DMA chan. 0                  */
 171 #define UIC_DMA1        0x40000000      /* DMA chan. 1                  */
 172 #define UIC_DMA2        0x20000000      /* DMA chan. 2                  */
 173 #define UIC_DMA3        0x10000000      /* DMA chan. 3                  */
 174 #define UIC_1588        0x08000000      /* IEEE 1588 network synchronization */
 175 #define UIC_UART0       0x04000000      /* UART 0                       */
 176 #define UIC_UART1       0x02000000      /* UART 1                       */
 177 #define UIC_CAN0        0x01000000      /* CAN 0                        */
 178 #define UIC_CAN1        0x00800000      /* CAN 1                        */
 179 #define UIC_SPI         0x00400000      /* SPI                          */
 180 #define UIC_IIC         0x00200000      /* IIC                          */
 181 #define UIC_CHT0        0x00100000      /* Chameleon timer high pri interrupt */
 182 #define UIC_CHT1        0x00080000      /* Chameleon timer high pri interrupt */
 183 #define UIC_USBH1       0x00040000      /* USB Host 1                   */
 184 #define UIC_USBH2       0x00020000      /* USB Host 2                   */
 185 #define UIC_USBDEV      0x00010000      /* USB Device                   */
 186 #define UIC_ENET        0x00008000      /* Ethernet interrupt status    */
 187 #define UIC_ENET1       0x00008000      /* dummy define                 */
 188 #define UIC_EMAC_WAKE   0x00004000      /* EMAC wake up                 */
 189
 190 #define UIC_MADMAL      0x00002000      /* Logical OR of following MadMAL int */
 191 #define UIC_MAL_SERR    0x00002000      /*   MAL SERR                   */
 192 #define UIC_MAL_TXDE    0x00002000      /*   MAL TXDE                   */
 193 #define UIC_MAL_RXDE    0x00002000      /*   MAL RXDE                   */
 194
 195 #define UIC_MAL_TXEOB   0x00001000      /* MAL TXEOB                    */
 196 #define UIC_MAL_TXEOB1  0x00000800      /* MAL TXEOB1                   */
 197 #define UIC_MAL_RXEOB   0x00000400      /* MAL RXEOB                    */
 198 #define UIC_NAND        0x00000200      /* NAND Flash controller        */
 199 #define UIC_ADC         0x00000100      /* ADC                          */
 200 #define UIC_DAC         0x00000080      /* DAC                          */
 201 #define UIC_OPB2PLB     0x00000040      /* OPB to PLB bridge interrupt  */
 202 #define UIC_RESERVED0   0x00000020      /* Reserved                     */
 203 #define UIC_EXT0        0x00000010      /* External  interrupt 0        */
 204 #define UIC_EXT1        0x00000008      /* External  interrupt 1        */
 205 #define UIC_EXT2        0x00000004      /* External  interrupt 2        */
 206 #define UIC_EXT3        0x00000002      /* External  interrupt 3        */
 207 #define UIC_EXT4        0x00000001      /* External  interrupt 4        */
 208
 209 #elif defined(CONFIG_405EX)
 210
 211 /* UIC 0 */
 212 #define UIC_U0                  0x80000000      /* */
 213 #define UIC_U1                  0x40000000      /* */
 214 #define UIC_IIC0                0x20000000      /* */
 215 #define UIC_PKA                 0x10000000      /* */
 216 #define UIC_TRNG                0x08000000      /* */
 217 #define UIC_EBM                 0x04000000      /* */
 218 #define UIC_BGI                 0x02000000      /* */
 219 #define UIC_IIC1                0x01000000      /* */
 220 #define UIC_SPI                 0x00800000      /* */
 221 #define UIC_EIRQ0               0x00400000      /**/
 222 #define UIC_MTE                 0x00200000      /*MAL Tx EOB */
 223 #define UIC_MRE                 0x00100000      /*MAL Rx EOB */
 224 #define UIC_DMA0                0x00080000      /* */
 225 #define UIC_DMA1                0x00040000      /* */
 226 #define UIC_DMA2                0x00020000      /* */
 227 #define UIC_DMA3                0x00010000      /* */
 228 #define UIC_PCIE0AL             0x00008000      /* */
 229 #define UIC_PCIE0VPD            0x00004000      /* */
 230 #define UIC_RPCIE0HRST          0x00002000      /* */
 231 #define UIC_FPCIE0HRST          0x00001000      /* */
 232 #define UIC_PCIE0TCR            0x00000800      /* */
 233 #define UIC_PCIEMSI0            0x00000400      /* */
 234 #define UIC_PCIEMSI1            0x00000200      /* */
 235 #define UIC_SECURITY            0x00000100      /* */
 236 #define UIC_ENET                0x00000080      /* */
 237 #define UIC_ENET1               0x00000040      /* */
 238 #define UIC_PCIEMSI2            0x00000020      /* */
 239 #define UIC_EIRQ4               0x00000010      /**/
 240 #define UIC_UIC2NC              0x00000008      /* */
 241 #define UIC_UIC2C               0x00000004      /* */
 242 #define UIC_UIC1NC              0x00000002      /* */
 243 #define UIC_UIC1C               0x00000001      /* */
 244
 245 #define UIC_MAL_TXEOB           UIC_MTE/* MAL TXEOB                          */
 246 #define UIC_MAL_RXEOB           UIC_MRE/* MAL RXEOB                          */
 247 /* UIC 1 */
 248 #define UIC_MS                  0x80000000      /* MAL SERR */
 249 #define UIC_MTDE                0x40000000      /* MAL TXDE */
 250 #define UIC_MRDE                0x20000000      /* MAL RXDE */
 251 #define UIC_PCIE0BMVC0          0x10000000      /* */
 252 #define UIC_PCIE0DCRERR         0x08000000      /* */
 253 #define UIC_EBC                 0x04000000      /* */
 254 #define UIC_NDFC                0x02000000      /* */
 255 #define UIC_PCEI1DCRERR         0x01000000      /* */
 256 #define UIC_GPTCMPT8            0x00800000      /* */
 257 #define UIC_GPTCMPT9            0x00400000      /* */
 258 #define UIC_PCIE1AL             0x00200000      /* */
 259 #define UIC_PCIE1VPD            0x00100000      /* */
 260 #define UIC_RPCE1HRST           0x00080000      /* */
 261 #define UIC_FPCE1HRST           0x00040000      /* */
 262 #define UIC_PCIE1TCR            0x00020000      /* */
 263 #define UIC_PCIE1VC0            0x00010000      /* */
 264 #define UIC_GPTCMPT3            0x00008000      /* */
 265 #define UIC_GPTCMPT4            0x00004000      /* */
 266 #define UIC_EIRQ7               0x00002000      /* */
 267 #define UIC_EIRQ8               0x00001000      /* */
 268 #define UIC_EIRQ9               0x00000800      /* */
 269 #define UIC_GPTCMP5             0x00000400      /* */
 270 #define UIC_GPTCMP6             0x00000200      /* */
 271 #define UIC_GPTCMP7             0x00000100      /* */
 272 #define UIC_SROM                0x00000080      /* SERIAL ROM*/
 273 #define UIC_GPTDECPULS          0x00000040      /* GPT Decrement pulse*/
 274 #define UIC_EIRQ2               0x00000020      /* */
 275 #define UIC_EIRQ5               0x00000010      /* */
 276 #define UIC_EIRQ6               0x00000008      /* */
 277 #define UIC_EMAC0WAKE           0x00000004      /* */
 278 #define UIC_EIRQ1               0x00000002      /* */
 279 #define UIC_EMAC1WAKE           0x00000001      /* */
 280 #define UIC_MAL_SERR            UIC_MS          /* MAL SERR     */
 281 #define UIC_MAL_TXDE            UIC_MTDE                /* MAL TXDE     */
 282 #define UIC_MAL_RXDE            UIC_MRDE                /* MAL RXDE     */
 283 /* UIC 2 */
 284 #define UIC_PCIE0INTA           0x80000000      /* PCIE0 INTA*/
 285 #define UIC_PCIE0INTB           0x40000000      /* PCIE0 INTB*/
 286 #define UIC_PCIE0INTC           0x20000000      /* PCIE0 INTC*/
 287 #define UIC_PCIE0INTD           0x10000000      /* PCIE0 INTD*/
 288 #define UIC_EIRQ3               0x08000000      /* External IRQ 3*/
 289 #define UIC_DDRMCUE             0x04000000      /* */
 290 #define UIC_DDRMCCE             0x02000000      /* */
 291 #define UIC_MALINTCOATX0        0x01000000      /* Interrupt coalecence TX0*/
 292 #define UIC_MALINTCOATX1        0x00800000      /* Interrupt coalecence TX1*/
 293 #define UIC_MALINTCOARX0        0x00400000      /* Interrupt coalecence RX0*/
 294 #define UIC_MALINTCOARX1        0x00200000      /* Interrupt coalecence RX1*/
 295 #define UIC_PCIE1INTA           0x00100000      /* PCIE0 INTA*/
 296 #define UIC_PCIE1INTB           0x00080000      /* PCIE0 INTB*/
 297 #define UIC_PCIE1INTC           0x00040000      /* PCIE0 INTC*/
 298 #define UIC_PCIE1INTD           0x00020000      /* PCIE0 INTD*/
 299 #define UIC_RPCIEMSI2           0x00010000      /* MSI level 2 Note this looks same as uic0-26*/
 300 #define UIC_PCIEMSI3            0x00008000      /* MSI level 2*/
 301 #define UIC_PCIEMSI4            0x00004000      /* MSI level 2*/
 302 #define UIC_PCIEMSI5            0x00002000      /* MSI level 2*/
 303 #define UIC_PCIEMSI6            0x00001000      /* MSI level 2*/
 304 #define UIC_PCIEMSI7            0x00000800      /* MSI level 2*/
 305 #define UIC_PCIEMSI8            0x00000400      /* MSI level 2*/
 306 #define UIC_PCIEMSI9            0x00000200      /* MSI level 2*/
 307 #define UIC_PCIEMSI10           0x00000100      /* MSI level 2*/
 308 #define UIC_PCIEMSI11           0x00000080      /* MSI level 2*/
 309 #define UIC_PCIEMSI12           0x00000040      /* MSI level 2*/
 310 #define UIC_PCIEMSI13           0x00000020      /* MSI level 2*/
 311 #define UIC_PCIEMSI14           0x00000010      /* MSI level 2*/
 312 #define UIC_PCIEMSI15           0x00000008      /* MSI level 2*/
 313 #define UIC_PLB4XAHB            0x00000004      /* PLBxAHB bridge*/
 314 #define UIC_USBWAKE             0x00000002      /* USB wakup*/
 315 #define UIC_USBOTG              0x00000001      /*  USB OTG*/
 316 #define UIC_ETH0        UIC_ENET
 317 #define UIC_ETH1        UIC_ENET1
 318
 319 #else   /* !defined(CONFIG_405EZ) */
 320
 321 #define UIC_UART0     0x80000000      /* UART 0                             */
 322 #define UIC_UART1     0x40000000      /* UART 1                             */
 323 #define UIC_IIC       0x20000000      /* IIC                                */
 324 #define UIC_EXT_MAST  0x10000000      /* External Master                    */
 325 #define UIC_PCI       0x08000000      /* PCI write to command reg           */
 326 #define UIC_DMA0      0x04000000      /* DMA chan. 0                        */
 327 #define UIC_DMA1      0x02000000      /* DMA chan. 1                        */
 328 #define UIC_DMA2      0x01000000      /* DMA chan. 2                        */
 329 #define UIC_DMA3      0x00800000      /* DMA chan. 3                        */
 330 #define UIC_EMAC_WAKE 0x00400000      /* EMAC wake up                       */
 331 #define UIC_MAL_SERR  0x00200000      /* MAL SERR                           */
 332 #define UIC_MAL_TXEOB 0x00100000      /* MAL TXEOB                          */
 333 #define UIC_MAL_RXEOB 0x00080000      /* MAL RXEOB                          */
 334 #define UIC_MAL_TXDE  0x00040000      /* MAL TXDE                           */
 335 #define UIC_MAL_RXDE  0x00020000      /* MAL RXDE                           */
 336 #define UIC_ENET      0x00010000      /* Ethernet0                          */
 337 #define UIC_ENET1     0x00004000      /* Ethernet1 on 405EP                 */
 338 #define UIC_ECC_CE    0x00004000      /* ECC Correctable Error on 405GP     */
 339 #define UIC_EXT_PCI_SERR 0x00008000   /* External PCI SERR#                 */
 340 #define UIC_PCI_PM    0x00002000      /* PCI Power Management               */
 341 #define UIC_EXT0      0x00000040      /* External  interrupt 0              */
 342 #define UIC_EXT1      0x00000020      /* External  interrupt 1              */
 343 #define UIC_EXT2      0x00000010      /* External  interrupt 2              */
 344 #define UIC_EXT3      0x00000008      /* External  interrupt 3              */
 345 #define UIC_EXT4      0x00000004      /* External  interrupt 4              */
 346 #define UIC_EXT5      0x00000002      /* External  interrupt 5              */
 347 #define UIC_EXT6      0x00000001      /* External  interrupt 6              */
 348 #endif  /* defined(CONFIG_405EZ) */
 349
 350 /******************************************************************************
 351  * SDRAM Controller
 352  ******************************************************************************/
 353   /* values for memcfga register - indirect addressing of these regs */
 354 #ifndef CONFIG_405EP
 355   #define mem_besra   0x00    /* bus error syndrome reg a            */
 356   #define mem_besrsa  0x04    /* bus error syndrome reg set a        */
 357   #define mem_besrb   0x08    /* bus error syndrome reg b            */
 358   #define mem_besrsb  0x0c    /* bus error syndrome reg set b        */
 359   #define mem_bear    0x10    /* bus error address reg               */
 360 #endif
 361   #define mem_mcopt1  0x20    /* memory controller options 1         */
 362   #define mem_status  0x24    /* memory status                       */
 363   #define mem_rtr     0x30    /* refresh timer reg                   */
 364   #define mem_pmit    0x34    /* power management idle timer         */
 365   #define mem_mb0cf   0x40    /* memory bank 0 configuration         */
 366   #define mem_mb1cf   0x44    /* memory bank 1 configuration         */
 367 #ifndef CONFIG_405EP
 368   #define mem_mb2cf   0x48    /* memory bank 2 configuration         */
 369   #define mem_mb3cf   0x4c    /* memory bank 3 configuration         */
 370 #endif
 371   #define mem_sdtr1   0x80    /* timing reg 1                        */
 372 #ifndef CONFIG_405EP
 373   #define mem_ecccf   0x94    /* ECC configuration                   */
 374   #define mem_eccerr  0x98    /* ECC error status                    */
 375 #endif
 376
 377 #ifndef CONFIG_405EP
 378 /******************************************************************************
 379  * Decompression Controller
 380  ******************************************************************************/
 381 #define DECOMP_DCR_BASE 0x14
 382 #define kiar  (DECOMP_DCR_BASE+0x0)  /* Decompression controller addr reg    */
 383 #define kidr  (DECOMP_DCR_BASE+0x1)  /* Decompression controller data reg    */
 384   /* values for kiar register - indirect addressing of these regs */
 385   #define kitor0      0x00    /* index table origin register 0        */
 386   #define kitor1      0x01    /* index table origin register 1        */
 387   #define kitor2      0x02    /* index table origin register 2        */
 388   #define kitor3      0x03    /* index table origin register 3        */
 389   #define kaddr0      0x04    /* address decode definition regsiter 0 */
 390   #define kaddr1      0x05    /* address decode definition regsiter 1 */
 391   #define kconf       0x40    /* decompression core config register   */
 392   #define kid         0x41    /* decompression core ID     register   */
 393   #define kver        0x42    /* decompression core version # reg     */
 394   #define kpear       0x50    /* bus error addr reg (PLB addr)        */
 395   #define kbear       0x51    /* bus error addr reg (DCP to EBIU addr)*/
 396   #define kesr0       0x52    /* bus error status reg 0  (R/clear)    */
 397   #define kesr0s      0x53    /* bus error status reg 0  (set)        */
 398   /* There are 0x400 of the following registers, from krom0 to krom3ff*/
 399   /* Only the first one is given here.                                */
 400   #define krom0      0x400    /* SRAM/ROM read/write                  */
 401 #endif
 402
 403 /******************************************************************************
 404  * Power Management
 405  ******************************************************************************/
 406 #ifdef CONFIG_405EX
 407 #define POWERMAN_DCR_BASE 0xb0
 408 #else
 409 #define POWERMAN_DCR_BASE 0xb8
 410 #endif
 411 #define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status             */
 412 #define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable             */
 413 #define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force              */
 414
 415 /******************************************************************************
 416  * Extrnal Bus Controller
 417  ******************************************************************************/
 418   /* values for ebccfga register - indirect addressing of these regs */
 419   #define pb0cr       0x00    /* periph bank 0 config reg            */
 420   #define pb1cr       0x01    /* periph bank 1 config reg            */
 421   #define pb2cr       0x02    /* periph bank 2 config reg            */
 422   #define pb3cr       0x03    /* periph bank 3 config reg            */
 423   #define pb4cr       0x04    /* periph bank 4 config reg            */
 424 #ifndef CONFIG_405EP
 425   #define pb5cr       0x05    /* periph bank 5 config reg            */
 426   #define pb6cr       0x06    /* periph bank 6 config reg            */
 427   #define pb7cr       0x07    /* periph bank 7 config reg            */
 428 #endif
 429   #define pb0ap       0x10    /* periph bank 0 access parameters     */
 430   #define pb1ap       0x11    /* periph bank 1 access parameters     */
 431   #define pb2ap       0x12    /* periph bank 2 access parameters     */
 432   #define pb3ap       0x13    /* periph bank 3 access parameters     */
 433   #define pb4ap       0x14    /* periph bank 4 access parameters     */
 434 #ifndef CONFIG_405EP
 435   #define pb5ap       0x15    /* periph bank 5 access parameters     */
 436   #define pb6ap       0x16    /* periph bank 6 access parameters     */
 437   #define pb7ap       0x17    /* periph bank 7 access parameters     */
 438 #endif
 439   #define pbear       0x20    /* periph bus error addr reg           */
 440   #define pbesr0      0x21    /* periph bus error status reg 0       */
 441   #define pbesr1      0x22    /* periph bus error status reg 1       */
 442   #define epcr        0x23    /* external periph control reg         */
 443 #define EBC0_CFG        0x23    /* external bus configuration reg       */
 444
 445 #ifdef CONFIG_405EP
 446 /******************************************************************************
 447  * Control
 448  ******************************************************************************/
 449 #define CNTRL_DCR_BASE 0x0f0
 450 #define cpc0_pllmr0   (CNTRL_DCR_BASE+0x0)  /* PLL mode  register 0                */
 451 #define cpc0_boot     (CNTRL_DCR_BASE+0x1)  /* Clock status register               */
 452 #define cpc0_epctl    (CNTRL_DCR_BASE+0x3)  /* EMAC to PHY control register        */
 453 #define cpc0_pllmr1   (CNTRL_DCR_BASE+0x4)  /* PLL mode  register 1                */
 454 #define cpc0_ucr      (CNTRL_DCR_BASE+0x5)  /* UART control register               */
 455 #define cpc0_pci      (CNTRL_DCR_BASE+0x9)  /* PCI control register                */
 456
 457 #define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register          */
 458 #define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register   */
 459 #define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register      */
 460 #define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register*/
 461 #define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register          */
 462 #define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register        */
 463 #define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register          */
 464 #define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register             */
 465 #define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR                    */
 466 #define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register         */
 467
 468 /* Bit definitions */
 469 #define PLLMR0_CPU_DIV_MASK      0x00300000     /* CPU clock divider */
 470 #define PLLMR0_CPU_DIV_BYPASS    0x00000000
 471 #define PLLMR0_CPU_DIV_2         0x00100000
 472 #define PLLMR0_CPU_DIV_3         0x00200000
 473 #define PLLMR0_CPU_DIV_4         0x00300000
 474
 475 #define PLLMR0_CPU_TO_PLB_MASK   0x00030000     /* CPU:PLB Frequency Divisor */
 476 #define PLLMR0_CPU_PLB_DIV_1     0x00000000
 477 #define PLLMR0_CPU_PLB_DIV_2     0x00010000
 478 #define PLLMR0_CPU_PLB_DIV_3     0x00020000
 479 #define PLLMR0_CPU_PLB_DIV_4     0x00030000
 480
 481 #define PLLMR0_OPB_TO_PLB_MASK   0x00003000     /* OPB:PLB Frequency Divisor */
 482 #define PLLMR0_OPB_PLB_DIV_1     0x00000000
 483 #define PLLMR0_OPB_PLB_DIV_2     0x00001000
 484 #define PLLMR0_OPB_PLB_DIV_3     0x00002000
 485 #define PLLMR0_OPB_PLB_DIV_4     0x00003000
 486
 487 #define PLLMR0_EXB_TO_PLB_MASK   0x00000300     /* External Bus:PLB Divisor  */
 488 #define PLLMR0_EXB_PLB_DIV_2     0x00000000
 489 #define PLLMR0_EXB_PLB_DIV_3     0x00000100
 490 #define PLLMR0_EXB_PLB_DIV_4     0x00000200
 491 #define PLLMR0_EXB_PLB_DIV_5     0x00000300
 492
 493 #define PLLMR0_MAL_TO_PLB_MASK   0x00000030     /* MAL:PLB Divisor  */
 494 #define PLLMR0_MAL_PLB_DIV_1     0x00000000
 495 #define PLLMR0_MAL_PLB_DIV_2     0x00000010
 496 #define PLLMR0_MAL_PLB_DIV_3     0x00000020
 497 #define PLLMR0_MAL_PLB_DIV_4     0x00000030
 498
 499 #define PLLMR0_PCI_TO_PLB_MASK   0x00000003     /* PCI:PLB Frequency Divisor */
 500 #define PLLMR0_PCI_PLB_DIV_1     0x00000000
 501 #define PLLMR0_PCI_PLB_DIV_2     0x00000001
 502 #define PLLMR0_PCI_PLB_DIV_3     0x00000002
 503 #define PLLMR0_PCI_PLB_DIV_4     0x00000003
 504
 505 #define PLLMR1_SSCS_MASK         0x80000000     /* Select system clock source */
 506 #define PLLMR1_PLLR_MASK         0x40000000     /* PLL reset */
 507 #define PLLMR1_FBMUL_MASK        0x00F00000     /* PLL feedback multiplier value */
 508 #define PLLMR1_FBMUL_DIV_16      0x00000000
 509 #define PLLMR1_FBMUL_DIV_1       0x00100000
 510 #define PLLMR1_FBMUL_DIV_2       0x00200000
 511 #define PLLMR1_FBMUL_DIV_3       0x00300000
 512 #define PLLMR1_FBMUL_DIV_4       0x00400000
 513 #define PLLMR1_FBMUL_DIV_5       0x00500000
 514 #define PLLMR1_FBMUL_DIV_6       0x00600000
 515 #define PLLMR1_FBMUL_DIV_7       0x00700000
 516 #define PLLMR1_FBMUL_DIV_8       0x00800000
 517 #define PLLMR1_FBMUL_DIV_9       0x00900000
 518 #define PLLMR1_FBMUL_DIV_10      0x00A00000
 519 #define PLLMR1_FBMUL_DIV_11      0x00B00000
 520 #define PLLMR1_FBMUL_DIV_12      0x00C00000
 521 #define PLLMR1_FBMUL_DIV_13      0x00D00000
 522 #define PLLMR1_FBMUL_DIV_14      0x00E00000
 523 #define PLLMR1_FBMUL_DIV_15      0x00F00000
 524
 525 #define PLLMR1_FWDVA_MASK        0x00070000     /* PLL forward divider A value */
 526 #define PLLMR1_FWDVA_DIV_8       0x00000000
 527 #define PLLMR1_FWDVA_DIV_7       0x00010000
 528 #define PLLMR1_FWDVA_DIV_6       0x00020000
 529 #define PLLMR1_FWDVA_DIV_5       0x00030000
 530 #define PLLMR1_FWDVA_DIV_4       0x00040000
 531 #define PLLMR1_FWDVA_DIV_3       0x00050000
 532 #define PLLMR1_FWDVA_DIV_2       0x00060000
 533 #define PLLMR1_FWDVA_DIV_1       0x00070000
 534 #define PLLMR1_FWDVB_MASK        0x00007000     /* PLL forward divider B value */
 535 #define PLLMR1_TUNING_MASK       0x000003FF     /* PLL tune bits */
 536
 537 /* Defines for CPC0_EPRCSR register */
 538 #define CPC0_EPRCSR_E0NFE          0x80000000
 539 #define CPC0_EPRCSR_E1NFE          0x40000000
 540 #define CPC0_EPRCSR_E1RPP          0x00000080
 541 #define CPC0_EPRCSR_E0RPP          0x00000040
 542 #define CPC0_EPRCSR_E1ERP          0x00000020
 543 #define CPC0_EPRCSR_E0ERP          0x00000010
 544 #define CPC0_EPRCSR_E1PCI          0x00000002
 545 #define CPC0_EPRCSR_E0PCI          0x00000001
 546
 547 /* Defines for CPC0_PCI Register */
 548 #define CPC0_PCI_SPE                       0x00000010 /* PCIINT/WE select       */
 549 #define CPC0_PCI_HOST_CFG_EN               0x00000008 /* PCI host config Enable */
 550 #define CPC0_PCI_ARBIT_EN                  0x00000001 /* PCI Internal Arb Enabled*/
 551
 552 /* Defines for CPC0_BOOR Register */
 553 #define CPC0_BOOT_SEP                      0x00000002 /* serial EEPROM present  */
 554
 555 /* Defines for CPC0_PLLMR1 Register fields */
 556 #define PLL_ACTIVE                 0x80000000
 557 #define CPC0_PLLMR1_SSCS           0x80000000
 558 #define PLL_RESET                  0x40000000
 559 #define CPC0_PLLMR1_PLLR           0x40000000
 560     /* Feedback multiplier */
 561 #define PLL_FBKDIV                 0x00F00000
 562 #define CPC0_PLLMR1_FBDV           0x00F00000
 563 #define PLL_FBKDIV_16              0x00000000
 564 #define PLL_FBKDIV_1               0x00100000
 565 #define PLL_FBKDIV_2               0x00200000
 566 #define PLL_FBKDIV_3               0x00300000
 567 #define PLL_FBKDIV_4               0x00400000
 568 #define PLL_FBKDIV_5               0x00500000
 569 #define PLL_FBKDIV_6               0x00600000
 570 #define PLL_FBKDIV_7               0x00700000
 571 #define PLL_FBKDIV_8               0x00800000
 572 #define PLL_FBKDIV_9               0x00900000
 573 #define PLL_FBKDIV_10              0x00A00000
 574 #define PLL_FBKDIV_11              0x00B00000
 575 #define PLL_FBKDIV_12              0x00C00000
 576 #define PLL_FBKDIV_13              0x00D00000
 577 #define PLL_FBKDIV_14              0x00E00000
 578 #define PLL_FBKDIV_15              0x00F00000
 579     /* Forward A divisor */
 580 #define PLL_FWDDIVA                0x00070000
 581 #define CPC0_PLLMR1_FWDVA          0x00070000
 582 #define PLL_FWDDIVA_8              0x00000000
 583 #define PLL_FWDDIVA_7              0x00010000
 584 #define PLL_FWDDIVA_6              0x00020000
 585 #define PLL_FWDDIVA_5              0x00030000
 586 #define PLL_FWDDIVA_4              0x00040000
 587 #define PLL_FWDDIVA_3              0x00050000
 588 #define PLL_FWDDIVA_2              0x00060000
 589 #define PLL_FWDDIVA_1              0x00070000
 590     /* Forward B divisor */
 591 #define PLL_FWDDIVB                0x00007000
 592 #define CPC0_PLLMR1_FWDVB          0x00007000
 593 #define PLL_FWDDIVB_8              0x00000000
 594 #define PLL_FWDDIVB_7              0x00001000
 595 #define PLL_FWDDIVB_6              0x00002000
 596 #define PLL_FWDDIVB_5              0x00003000
 597 #define PLL_FWDDIVB_4              0x00004000
 598 #define PLL_FWDDIVB_3              0x00005000
 599 #define PLL_FWDDIVB_2              0x00006000
 600 #define PLL_FWDDIVB_1              0x00007000
 601     /* PLL tune bits */
 602 #define PLL_TUNE_MASK            0x000003FF
 603 #define PLL_TUNE_2_M_3           0x00000133     /*  2 <= M <= 3               */
 604 #define PLL_TUNE_4_M_6           0x00000134     /*  3 <  M <= 6               */
 605 #define PLL_TUNE_7_M_10          0x00000138     /*  6 <  M <= 10              */
 606 #define PLL_TUNE_11_M_14         0x0000013C     /* 10 <  M <= 14              */
 607 #define PLL_TUNE_15_M_40         0x0000023E     /* 14 <  M <= 40              */
 608 #define PLL_TUNE_VCO_LOW         0x00000000     /* 500MHz <= VCO <=  800MHz   */
 609 #define PLL_TUNE_VCO_HI          0x00000080     /* 800MHz <  VCO <= 1000MHz   */
 610
 611 /* Defines for CPC0_PLLMR0 Register fields */
 612     /* CPU divisor */
 613 #define PLL_CPUDIV                 0x00300000
 614 #define CPC0_PLLMR0_CCDV           0x00300000
 615 #define PLL_CPUDIV_1               0x00000000
 616 #define PLL_CPUDIV_2               0x00100000
 617 #define PLL_CPUDIV_3               0x00200000
 618 #define PLL_CPUDIV_4               0x00300000
 619     /* PLB divisor */
 620 #define PLL_PLBDIV                 0x00030000
 621 #define CPC0_PLLMR0_CBDV           0x00030000
 622 #define PLL_PLBDIV_1               0x00000000
 623 #define PLL_PLBDIV_2               0x00010000
 624 #define PLL_PLBDIV_3               0x00020000
 625 #define PLL_PLBDIV_4               0x00030000
 626     /* OPB divisor */
 627 #define PLL_OPBDIV                 0x00003000
 628 #define CPC0_PLLMR0_OPDV           0x00003000
 629 #define PLL_OPBDIV_1               0x00000000
 630 #define PLL_OPBDIV_2               0x00001000
 631 #define PLL_OPBDIV_3               0x00002000
 632 #define PLL_OPBDIV_4               0x00003000
 633     /* EBC divisor */
 634 #define PLL_EXTBUSDIV              0x00000300
 635 #define CPC0_PLLMR0_EPDV           0x00000300
 636 #define PLL_EXTBUSDIV_2            0x00000000
 637 #define PLL_EXTBUSDIV_3            0x00000100
 638 #define PLL_EXTBUSDIV_4            0x00000200
 639 #define PLL_EXTBUSDIV_5            0x00000300
 640     /* MAL divisor */
 641 #define PLL_MALDIV                 0x00000030
 642 #define CPC0_PLLMR0_MPDV           0x00000030
 643 #define PLL_MALDIV_1               0x00000000
 644 #define PLL_MALDIV_2               0x00000010
 645 #define PLL_MALDIV_3               0x00000020
 646 #define PLL_MALDIV_4               0x00000030
 647     /* PCI divisor */
 648 #define PLL_PCIDIV                 0x00000003
 649 #define CPC0_PLLMR0_PPFD           0x00000003
 650 #define PLL_PCIDIV_1               0x00000000
 651 #define PLL_PCIDIV_2               0x00000001
 652 #define PLL_PCIDIV_3               0x00000002
 653 #define PLL_PCIDIV_4               0x00000003
 654
 655 /*
 656  *-------------------------------------------------------------------------------
 657  * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
 658  * assuming a 33.3MHz input clock to the 405EP.
 659  *-------------------------------------------------------------------------------
 660  */
 661 #define PLLMR0_266_133_66  (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
 662                             PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
 663                             PLL_MALDIV_1 | PLL_PCIDIV_4)
 664 #define PLLMR1_266_133_66  (PLL_FBKDIV_8  |  \
 665                             PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 666                             PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 667
 668 #define PLLMR0_133_66_66_33  (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
 669                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
 670                               PLL_MALDIV_1 | PLL_PCIDIV_4)
 671 #define PLLMR1_133_66_66_33  (PLL_FBKDIV_4  |  \
 672                               PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
 673                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 674 #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
 675                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
 676                               PLL_MALDIV_1 | PLL_PCIDIV_4)
 677 #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
 678                               PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
 679                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 680 #define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
 681                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
 682                               PLL_MALDIV_1 | PLL_PCIDIV_4)
 683 #define PLLMR1_266_133_66_33 (PLL_FBKDIV_8  |  \
 684                               PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 685                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 686 #define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 |  \
 687                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
 688                               PLL_MALDIV_1 | PLL_PCIDIV_2)
 689 #define PLLMR1_266_66_33_33 (PLL_FBKDIV_8  |  \
 690                               PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 691                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 692 #define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
 693                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
 694                               PLL_MALDIV_1 | PLL_PCIDIV_3)
 695 #define PLLMR1_333_111_55_37 (PLL_FBKDIV_10  |  \
 696                               PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 697                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 698 #define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
 699                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
 700                               PLL_MALDIV_1 | PLL_PCIDIV_1)
 701 #define PLLMR1_333_111_55_111 (PLL_FBKDIV_10  |  \
 702                               PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 703                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 704
 705 /*
 706  * PLL Voltage Controlled Oscillator (VCO) definitions
 707  * Maximum and minimum values (in MHz) for correct PLL operation.
 708  */
 709 #define VCO_MIN     500
 710 #define VCO_MAX     1000
 711 #elif defined(CONFIG_405EZ)
 712 #define sdrnand0        0x4000
 713 #define sdrultra0       0x4040
 714 #define sdrultra1       0x4050
 715 #define sdricintstat    0x4510
 716
 717 #define SDR_NAND0_NDEN          0x80000000
 718 #define SDR_NAND0_NDBTEN        0x40000000
 719 #define SDR_NAND0_NDBADR_MASK   0x30000000
 720 #define SDR_NAND0_NDBPG_MASK    0x0f000000
 721 #define SDR_NAND0_NDAREN        0x00800000
 722 #define SDR_NAND0_NDRBEN        0x00400000
 723
 724 #define SDR_ULTRA0_NDGPIOBP     0x80000000
 725 #define SDR_ULTRA0_CSN_MASK     0x78000000
 726 #define SDR_ULTRA0_CSNSEL0      0x40000000
 727 #define SDR_ULTRA0_CSNSEL1      0x20000000
 728 #define SDR_ULTRA0_CSNSEL2      0x10000000
 729 #define SDR_ULTRA0_CSNSEL3      0x08000000
 730 #define SDR_ULTRA0_EBCRDYEN     0x04000000
 731 #define SDR_ULTRA0_SPISSINEN    0x02000000
 732 #define SDR_ULTRA0_NFSRSTEN     0x01000000
 733
 734 #define SDR_ULTRA1_LEDNENABLE   0x40000000
 735
 736 #define SDR_ICRX_STAT   0x80000000
 737 #define SDR_ICTX0_STAT  0x40000000
 738 #define SDR_ICTX1_STAT  0x20000000
 739
 740 #define SDR_PINSTP      0x40
 741
 742 /******************************************************************************
 743  * Control
 744  ******************************************************************************/
 745 /* CPR Registers */
 746 #define cprclkupd       0x020           /* CPR_CLKUPD */
 747 #define cprpllc         0x040           /* CPR_PLLC */
 748 #define cprplld         0x060           /* CPR_PLLD */
 749 #define cprprimad       0x080           /* CPR_PRIMAD */
 750 #define cprperd0        0x0e0           /* CPR_PERD0 */
 751 #define cprperd1        0x0e1           /* CPR_PERD1 */
 752 #define cprperc0        0x180           /* CPR_PERC0 */
 753 #define cprmisc0        0x181           /* CPR_MISC0 */
 754 #define cprmisc1        0x182           /* CPR_MISC1 */
 755
 756 #define CPR_CLKUPD_ENPLLCH_EN  0x40000000     /* Enable CPR PLL Changes */
 757 #define CPR_CLKUPD_ENDVCH_EN   0x20000000     /* Enable CPR Sys. Div. Changes */
 758 #define CPR_PERD0_SPIDV_MASK   0x000F0000     /* SPI Clock Divider */
 759
 760 #define PLLC_SRC_MASK          0x20000000     /* PLL feedback source */
 761
 762 #define PLLD_FBDV_MASK         0x1F000000     /* PLL feedback divider value */
 763 #define PLLD_FWDVA_MASK        0x000F0000     /* PLL forward divider A value */
 764 #define PLLD_FWDVB_MASK        0x00000700     /* PLL forward divider B value */
 765
 766 #define PRIMAD_CPUDV_MASK      0x0F000000     /* CPU Clock Divisor Mask */
 767 #define PRIMAD_PLBDV_MASK      0x000F0000     /* PLB Clock Divisor Mask */
 768 #define PRIMAD_OPBDV_MASK      0x00000F00     /* OPB Clock Divisor Mask */
 769 #define PRIMAD_EBCDV_MASK      0x0000000F     /* EBC Clock Divisor Mask */
 770
 771 #define PERD0_PWMDV_MASK       0xFF000000     /* PWM Divider Mask */
 772 #define PERD0_SPIDV_MASK       0x000F0000     /* SPI Divider Mask */
 773 #define PERD0_U0DV_MASK        0x0000FF00     /* UART 0 Divider Mask */
 774 #define PERD0_U1DV_MASK        0x000000FF     /* UART 1 Divider Mask */
 775
 776 #else /* #ifdef CONFIG_405EP */
 777 /******************************************************************************
 778  * Control
 779  ******************************************************************************/
 780 #define CNTRL_DCR_BASE 0x0b0
 781 #define pllmd   (CNTRL_DCR_BASE+0x0)  /* PLL mode  register                  */
 782 #define cntrl0  (CNTRL_DCR_BASE+0x1)  /* Control 0 register                  */
 783 #define cntrl1  (CNTRL_DCR_BASE+0x2)  /* Control 1 register                  */
 784 #define reset   (CNTRL_DCR_BASE+0x3)  /* reset register                      */
 785 #define strap   (CNTRL_DCR_BASE+0x4)  /* strap register                      */
 786
 787 #define ecr     (0xaa)                /* edge conditioner register (405gpr)  */
 788
 789 /* Bit definitions */
 790 #define PLLMR_FWD_DIV_MASK      0xE0000000     /* Forward Divisor */
 791 #define PLLMR_FWD_DIV_BYPASS    0xE0000000
 792 #define PLLMR_FWD_DIV_3         0xA0000000
 793 #define PLLMR_FWD_DIV_4         0x80000000
 794 #define PLLMR_FWD_DIV_6         0x40000000
 795
 796 #define PLLMR_FB_DIV_MASK       0x1E000000     /* Feedback Divisor */
 797 #define PLLMR_FB_DIV_1          0x02000000
 798 #define PLLMR_FB_DIV_2          0x04000000
 799 #define PLLMR_FB_DIV_3          0x06000000
 800 #define PLLMR_FB_DIV_4          0x08000000
 801
 802 #define PLLMR_TUNING_MASK       0x01F80000
 803
 804 #define PLLMR_CPU_TO_PLB_MASK   0x00060000     /* CPU:PLB Frequency Divisor */
 805 #define PLLMR_CPU_PLB_DIV_1     0x00000000
 806 #define PLLMR_CPU_PLB_DIV_2     0x00020000
 807 #define PLLMR_CPU_PLB_DIV_3     0x00040000
 808 #define PLLMR_CPU_PLB_DIV_4     0x00060000
 809
 810 #define PLLMR_OPB_TO_PLB_MASK   0x00018000     /* OPB:PLB Frequency Divisor */
 811 #define PLLMR_OPB_PLB_DIV_1     0x00000000
 812 #define PLLMR_OPB_PLB_DIV_2     0x00008000
 813 #define PLLMR_OPB_PLB_DIV_3     0x00010000
 814 #define PLLMR_OPB_PLB_DIV_4     0x00018000
 815
 816 #define PLLMR_PCI_TO_PLB_MASK   0x00006000     /* PCI:PLB Frequency Divisor */
 817 #define PLLMR_PCI_PLB_DIV_1     0x00000000
 818 #define PLLMR_PCI_PLB_DIV_2     0x00002000
 819 #define PLLMR_PCI_PLB_DIV_3     0x00004000
 820 #define PLLMR_PCI_PLB_DIV_4     0x00006000
 821
 822 #define PLLMR_EXB_TO_PLB_MASK   0x00001800     /* External Bus:PLB Divisor  */
 823 #define PLLMR_EXB_PLB_DIV_2     0x00000000
 824 #define PLLMR_EXB_PLB_DIV_3     0x00000800
 825 #define PLLMR_EXB_PLB_DIV_4     0x00001000
 826 #define PLLMR_EXB_PLB_DIV_5     0x00001800
 827
 828 /* definitions for PPC405GPr (new mode strapping) */
 829 #define PLLMR_FWDB_DIV_MASK     0x00000007     /* Forward Divisor B */
 830
 831 #define PSR_PLL_FWD_MASK        0xC0000000
 832 #define PSR_PLL_FDBACK_MASK     0x30000000
 833 #define PSR_PLL_TUNING_MASK     0x0E000000
 834 #define PSR_PLB_CPU_MASK        0x01800000
 835 #define PSR_OPB_PLB_MASK        0x00600000
 836 #define PSR_PCI_PLB_MASK        0x00180000
 837 #define PSR_EB_PLB_MASK         0x00060000
 838 #define PSR_ROM_WIDTH_MASK      0x00018000
 839 #define PSR_ROM_LOC             0x00004000
 840 #define PSR_PCI_ASYNC_EN        0x00001000
 841 #define PSR_PERCLK_SYNC_MODE_EN 0x00000800     /* PPC405GPr only */
 842 #define PSR_PCI_ARBIT_EN        0x00000400
 843 #define PSR_NEW_MODE_EN         0x00000020     /* PPC405GPr only */
 844
 845 #ifndef CONFIG_IOP480
 846 /*
 847  * PLL Voltage Controlled Oscillator (VCO) definitions
 848  * Maximum and minimum values (in MHz) for correct PLL operation.
 849  */
 850 #define VCO_MIN     400
 851 #define VCO_MAX     800
 852 #endif /* #ifndef CONFIG_IOP480 */
 853 #endif /* #ifdef CONFIG_405EP */
 854
 855 /******************************************************************************
 856  * Memory Access Layer
 857  ******************************************************************************/
 858 #if defined(CONFIG_405EZ)
 859 #define MAL_DCR_BASE    0x380
 860 #define malmcr          (MAL_DCR_BASE+0x00)     /* MAL Config reg             */
 861 #define malesr          (MAL_DCR_BASE+0x01)     /* Err Status reg (Read/Clear)*/
 862 #define malier          (MAL_DCR_BASE+0x02)     /* Interrupt enable reg       */
 863 #define maldbr          (MAL_DCR_BASE+0x03)     /* Mal Debug reg (Read only)  */
 864 #define maltxcasr       (MAL_DCR_BASE+0x04)     /* TX Channel active reg (set)*/
 865 #define maltxcarr       (MAL_DCR_BASE+0x05)     /* TX Channel active reg (Reset)     */
 866 #define maltxeobisr     (MAL_DCR_BASE+0x06)     /* TX End of buffer int status reg   */
 867 #define maltxdeir       (MAL_DCR_BASE+0x07)     /* TX Descr. Error Int reg    */
 868 /*                                    0x08-0x0F    Reserved                   */
 869 #define malrxcasr       (MAL_DCR_BASE+0x10)     /* RX Channel active reg (set)*/
 870 #define malrxcarr       (MAL_DCR_BASE+0x11)     /* RX Channel active reg (Reset)     */
 871 #define malrxeobisr     (MAL_DCR_BASE+0x12)     /* RX End of buffer int status reg   */
 872 #define malrxdeir       (MAL_DCR_BASE+0x13)     /* RX Descr. Error Int reg  */
 873 /*                                    0x14-0x1F    Reserved                 */
 874 #define maltxctp0r      (MAL_DCR_BASE+0x20)  /* TX 0 Channel table ptr reg  */
 875 #define maltxctp1r      (MAL_DCR_BASE+0x21)  /* TX 1 Channel table ptr reg  */
 876 #define maltxctp2r      (MAL_DCR_BASE+0x22)  /* TX 2 Channel table ptr reg  */
 877 #define maltxctp3r      (MAL_DCR_BASE+0x23)  /* TX 3 Channel table ptr reg  */
 878 #define maltxctp4r      (MAL_DCR_BASE+0x24)  /* TX 4 Channel table ptr reg  */
 879 #define maltxctp5r      (MAL_DCR_BASE+0x25)  /* TX 5 Channel table ptr reg  */
 880 #define maltxctp6r      (MAL_DCR_BASE+0x26)  /* TX 6 Channel table ptr reg  */
 881 #define maltxctp7r      (MAL_DCR_BASE+0x27)  /* TX 7 Channel table ptr reg  */
 882 #define maltxctp8r      (MAL_DCR_BASE+0x28)  /* TX 8 Channel table ptr reg  */
 883 #define maltxctp9r      (MAL_DCR_BASE+0x29)  /* TX 9 Channel table ptr reg  */
 884 #define maltxctp10r     (MAL_DCR_BASE+0x2A)  /* TX 10 Channel table ptr reg */
 885 #define maltxctp11r     (MAL_DCR_BASE+0x2B)  /* TX 11 Channel table ptr reg */
 886 #define maltxctp12r     (MAL_DCR_BASE+0x2C)  /* TX 12 Channel table ptr reg */
 887 #define maltxctp13r     (MAL_DCR_BASE+0x2D)  /* TX 13 Channel table ptr reg */
 888 #define maltxctp14r     (MAL_DCR_BASE+0x2E)  /* TX 14 Channel table ptr reg */
 889 #define maltxctp15r     (MAL_DCR_BASE+0x2F)  /* TX 15 Channel table ptr reg */
 890 #define maltxctp16r     (MAL_DCR_BASE+0x30)  /* TX 16 Channel table ptr reg */
 891 #define maltxctp17r     (MAL_DCR_BASE+0x31)  /* TX 17 Channel table ptr reg */
 892 #define maltxctp18r     (MAL_DCR_BASE+0x32)  /* TX 18 Channel table ptr reg */
 893 #define maltxctp19r     (MAL_DCR_BASE+0x33)  /* TX 19 Channel table ptr reg */
 894 #define maltxctp20r     (MAL_DCR_BASE+0x34)  /* TX 20 Channel table ptr reg */
 895 #define maltxctp21r     (MAL_DCR_BASE+0x35)  /* TX 21 Channel table ptr reg */
 896 #define maltxctp22r     (MAL_DCR_BASE+0x36)  /* TX 22 Channel table ptr reg */
 897 #define maltxctp23r     (MAL_DCR_BASE+0x37)  /* TX 23 Channel table ptr reg */
 898 #define maltxctp24r     (MAL_DCR_BASE+0x38)  /* TX 24 Channel table ptr reg */
 899 #define maltxctp25r     (MAL_DCR_BASE+0x39)  /* TX 25 Channel table ptr reg */
 900 #define maltxctp26r     (MAL_DCR_BASE+0x3A)  /* TX 26 Channel table ptr reg */
 901 #define maltxctp27r     (MAL_DCR_BASE+0x3B)  /* TX 27 Channel table ptr reg */
 902 #define maltxctp28r     (MAL_DCR_BASE+0x3C)  /* TX 28 Channel table ptr reg */
 903 #define maltxctp29r     (MAL_DCR_BASE+0x3D)  /* TX 29 Channel table ptr reg */
 904 #define maltxctp30r     (MAL_DCR_BASE+0x3E)  /* TX 30 Channel table ptr reg */
 905 #define maltxctp31r     (MAL_DCR_BASE+0x3F)  /* TX 31 Channel table ptr reg */
 906 #define malrxctp0r      (MAL_DCR_BASE+0x40)  /* RX 0 Channel table ptr reg  */
 907 #define malrxctp1r      (MAL_DCR_BASE+0x41)  /* RX 1 Channel table ptr reg  */
 908 #define malrxctp2r      (MAL_DCR_BASE+0x42)  /* RX 2 Channel table ptr reg  */
 909 #define malrxctp3r      (MAL_DCR_BASE+0x43)  /* RX 3 Channel table ptr reg  */
 910 #define malrxctp4r      (MAL_DCR_BASE+0x44)  /* RX 4 Channel table ptr reg  */
 911 #define malrxctp5r      (MAL_DCR_BASE+0x45)  /* RX 5 Channel table ptr reg  */
 912 #define malrxctp6r      (MAL_DCR_BASE+0x46)  /* RX 6 Channel table ptr reg  */
 913 #define malrxctp7r      (MAL_DCR_BASE+0x47)  /* RX 7 Channel table ptr reg  */
 914 #define malrxctp8r      (MAL_DCR_BASE+0x48)  /* RX 8 Channel table ptr reg  */
 915 #define malrxctp9r      (MAL_DCR_BASE+0x49)  /* RX 9 Channel table ptr reg  */
 916 #define malrxctp10r     (MAL_DCR_BASE+0x4A)  /* RX 10 Channel table ptr reg */
 917 #define malrxctp11r     (MAL_DCR_BASE+0x4B)  /* RX 11 Channel table ptr reg */
 918 #define malrxctp12r     (MAL_DCR_BASE+0x4C)  /* RX 12 Channel table ptr reg */
 919 #define malrxctp13r     (MAL_DCR_BASE+0x4D)  /* RX 13 Channel table ptr reg */
 920 #define malrxctp14r     (MAL_DCR_BASE+0x4E)  /* RX 14 Channel table ptr reg */
 921 #define malrxctp15r     (MAL_DCR_BASE+0x4F)  /* RX 15 Channel table ptr reg */
 922 #define malrxctp16r     (MAL_DCR_BASE+0x50)  /* RX 16 Channel table ptr reg */
 923 #define malrxctp17r     (MAL_DCR_BASE+0x51)  /* RX 17 Channel table ptr reg */
 924 #define malrxctp18r     (MAL_DCR_BASE+0x52)  /* RX 18 Channel table ptr reg */
 925 #define malrxctp19r     (MAL_DCR_BASE+0x53)  /* RX 19 Channel table ptr reg */
 926 #define malrxctp20r     (MAL_DCR_BASE+0x54)  /* RX 20 Channel table ptr reg */
 927 #define malrxctp21r     (MAL_DCR_BASE+0x55)  /* RX 21 Channel table ptr reg */
 928 #define malrxctp22r     (MAL_DCR_BASE+0x56)  /* RX 22 Channel table ptr reg */
 929 #define malrxctp23r     (MAL_DCR_BASE+0x57)  /* RX 23 Channel table ptr reg */
 930 #define malrxctp24r     (MAL_DCR_BASE+0x58)  /* RX 24 Channel table ptr reg */
 931 #define malrxctp25r     (MAL_DCR_BASE+0x59)  /* RX 25 Channel table ptr reg */
 932 #define malrxctp26r     (MAL_DCR_BASE+0x5A)  /* RX 26 Channel table ptr reg */
 933 #define malrxctp27r     (MAL_DCR_BASE+0x5B)  /* RX 27 Channel table ptr reg */
 934 #define malrxctp28r     (MAL_DCR_BASE+0x5C)  /* RX 28 Channel table ptr reg */
 935 #define malrxctp29r     (MAL_DCR_BASE+0x5D)  /* RX 29 Channel table ptr reg */
 936 #define malrxctp30r     (MAL_DCR_BASE+0x5E)  /* RX 30 Channel table ptr reg */
 937 #define malrxctp31r     (MAL_DCR_BASE+0x5F)  /* RX 31 Channel table ptr reg */
 938 #define malrcbs0        (MAL_DCR_BASE+0x60)  /* RX 0 Channel buffer size reg */
 939 #define malrcbs1        (MAL_DCR_BASE+0x61)  /* RX 1 Channel buffer size reg */
 940 #define malrcbs2        (MAL_DCR_BASE+0x62)  /* RX 2 Channel buffer size reg */
 941 #define malrcbs3        (MAL_DCR_BASE+0x63)  /* RX 3 Channel buffer size reg */
 942 #define malrcbs4        (MAL_DCR_BASE+0x64)  /* RX 4 Channel buffer size reg */
 943 #define malrcbs5        (MAL_DCR_BASE+0x65)  /* RX 5 Channel buffer size reg */
 944 #define malrcbs6        (MAL_DCR_BASE+0x66)  /* RX 6 Channel buffer size reg */
 945 #define malrcbs7        (MAL_DCR_BASE+0x67)  /* RX 7 Channel buffer size reg */
 946 #define malrcbs8        (MAL_DCR_BASE+0x68)  /* RX 8 Channel buffer size reg */
 947 #define malrcbs9        (MAL_DCR_BASE+0x69)  /* RX 9 Channel buffer size reg */
 948 #define malrcbs10       (MAL_DCR_BASE+0x6A)  /* RX 10 Channel buffer size reg */
 949 #define malrcbs11       (MAL_DCR_BASE+0x6B)  /* RX 11 Channel buffer size reg */
 950 #define malrcbs12       (MAL_DCR_BASE+0x6C)  /* RX 12 Channel buffer size reg */
 951 #define malrcbs13       (MAL_DCR_BASE+0x6D)  /* RX 13 Channel buffer size reg */
 952 #define malrcbs14       (MAL_DCR_BASE+0x6E)  /* RX 14 Channel buffer size reg */
 953 #define malrcbs15       (MAL_DCR_BASE+0x6F)  /* RX 15 Channel buffer size reg */
 954 #define malrcbs16       (MAL_DCR_BASE+0x70)  /* RX 16 Channel buffer size reg */
 955 #define malrcbs17       (MAL_DCR_BASE+0x71)  /* RX 17 Channel buffer size reg */
 956 #define malrcbs18       (MAL_DCR_BASE+0x72)  /* RX 18 Channel buffer size reg */
 957 #define malrcbs19       (MAL_DCR_BASE+0x73)  /* RX 19 Channel buffer size reg */
 958 #define malrcbs20       (MAL_DCR_BASE+0x74)  /* RX 20 Channel buffer size reg */
 959 #define malrcbs21       (MAL_DCR_BASE+0x75)  /* RX 21 Channel buffer size reg */
 960 #define malrcbs22       (MAL_DCR_BASE+0x76)  /* RX 22 Channel buffer size reg */
 961 #define malrcbs23       (MAL_DCR_BASE+0x77)  /* RX 23 Channel buffer size reg */
 962 #define malrcbs24       (MAL_DCR_BASE+0x78)  /* RX 24 Channel buffer size reg */
 963 #define malrcbs25       (MAL_DCR_BASE+0x79)  /* RX 25 Channel buffer size reg */
 964 #define malrcbs26       (MAL_DCR_BASE+0x7A)  /* RX 26 Channel buffer size reg */
 965 #define malrcbs27       (MAL_DCR_BASE+0x7B)  /* RX 27 Channel buffer size reg */
 966 #define malrcbs28       (MAL_DCR_BASE+0x7C)  /* RX 28 Channel buffer size reg */
 967 #define malrcbs29       (MAL_DCR_BASE+0x7D)  /* RX 29 Channel buffer size reg */
 968 #define malrcbs30       (MAL_DCR_BASE+0x7E)  /* RX 30 Channel buffer size reg */
 969 #define malrcbs31       (MAL_DCR_BASE+0x7F)  /* RX 31 Channel buffer size reg */
 970
 971 #else /* !defined(CONFIG_405EZ) */
 972
 973 #define MAL_DCR_BASE 0x180
 974 #define malmcr  (MAL_DCR_BASE+0x00)  /* MAL Config reg                       */
 975 #define malesr  (MAL_DCR_BASE+0x01)  /* Error Status reg (Read/Clear)        */
 976 #define malier  (MAL_DCR_BASE+0x02)  /* Interrupt enable reg                 */
 977 #define maldbr  (MAL_DCR_BASE+0x03)  /* Mal Debug reg (Read only)            */
 978 #define maltxcasr  (MAL_DCR_BASE+0x04)  /* TX Channel active reg (set)       */
 979 #define maltxcarr  (MAL_DCR_BASE+0x05)  /* TX Channel active reg (Reset)     */
 980 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg   */
 981 #define maltxdeir  (MAL_DCR_BASE+0x07)  /* TX Descr. Error Int reg           */
 982 #define malrxcasr  (MAL_DCR_BASE+0x10)  /* RX Channel active reg (set)       */
 983 #define malrxcarr  (MAL_DCR_BASE+0x11)  /* RX Channel active reg (Reset)     */
 984 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg   */
 985 #define malrxdeir  (MAL_DCR_BASE+0x13)  /* RX Descr. Error Int reg           */
 986 #define maltxctp0r (MAL_DCR_BASE+0x20)  /* TX 0 Channel table pointer reg    */
 987 #define maltxctp1r (MAL_DCR_BASE+0x21)  /* TX 1 Channel table pointer reg    */
 988 #define maltxctp2r (MAL_DCR_BASE+0x22)  /* TX 2 Channel table pointer reg    */
 989 #define malrxctp0r (MAL_DCR_BASE+0x40)  /* RX 0 Channel table pointer reg    */
 990 #define malrxctp1r (MAL_DCR_BASE+0x41)  /* RX 1 Channel table pointer reg    */
 991 #define malrcbs0   (MAL_DCR_BASE+0x60)  /* RX 0 Channel buffer size reg      */
 992 #define malrcbs1   (MAL_DCR_BASE+0x61)  /* RX 1 Channel buffer size reg      */
 993 #endif /* defined(CONFIG_405EZ) */
 994
 995 /*-----------------------------------------------------------------------------
 996 | IIC Register Offsets
 997 '----------------------------------------------------------------------------*/
 998 #define    IICMDBUF         0x00
 999 #define    IICSDBUF         0x02
1000 #define    IICLMADR         0x04
1001 #define    IICHMADR         0x05
1002 #define    IICCNTL          0x06
1003 #define    IICMDCNTL        0x07
1004 #define    IICSTS           0x08
1005 #define    IICEXTSTS        0x09
1006 #define    IICLSADR         0x0A
1007 #define    IICHSADR         0x0B
1008 #define    IICCLKDIV        0x0C
1009 #define    IICINTRMSK       0x0D
1010 #define    IICXFRCNT        0x0E
1011 #define    IICXTCNTLSS      0x0F
1012 #define    IICDIRECTCNTL    0x10
1013
1014 /*-----------------------------------------------------------------------------
1015 | UART Register Offsets
1016 '----------------------------------------------------------------------------*/
1017 #define         DATA_REG        0x00
1018 #define         DL_LSB          0x00
1019 #define         DL_MSB          0x01
1020 #define         INT_ENABLE      0x01
1021 #define         FIFO_CONTROL    0x02
1022 #define         LINE_CONTROL    0x03
1023 #define         MODEM_CONTROL   0x04
1024 #define         LINE_STATUS     0x05
1025 #define         MODEM_STATUS    0x06
1026 #define         SCRATCH         0x07
1027
1028 /******************************************************************************
1029  * On Chip Memory
1030  ******************************************************************************/
1031 #if defined(CONFIG_405EZ)
1032 #define OCM_DCR_BASE 0x020
1033 #define ocmplb3cr1      (OCM_DCR_BASE+0x00)  /* OCM PLB3 Bank 1 Config Reg    */
1034 #define ocmplb3cr2      (OCM_DCR_BASE+0x01)  /* OCM PLB3 Bank 2 Config Reg    */
1035 #define ocmplb3bear     (OCM_DCR_BASE+0x02)  /* OCM PLB3 Bus Error Add Reg    */
1036 #define ocmplb3besr0    (OCM_DCR_BASE+0x03)  /* OCM PLB3 Bus Error Stat Reg 0 */
1037 #define ocmplb3besr1    (OCM_DCR_BASE+0x04)  /* OCM PLB3 Bus Error Stat Reg 1 */
1038 #define ocmcid          (OCM_DCR_BASE+0x05)  /* OCM Core ID                   */
1039 #define ocmrevid        (OCM_DCR_BASE+0x06)  /* OCM Revision ID               */
1040 #define ocmplb3dpc      (OCM_DCR_BASE+0x07)  /* OCM PLB3 Data Parity Check    */
1041 #define ocmdscr1        (OCM_DCR_BASE+0x08)  /* OCM D-side Bank 1 Config Reg  */
1042 #define ocmdscr2        (OCM_DCR_BASE+0x09)  /* OCM D-side Bank 2 Config Reg  */
1043 #define ocmiscr1        (OCM_DCR_BASE+0x0A)  /* OCM I-side Bank 1 Config Reg  */
1044 #define ocmiscr2        (OCM_DCR_BASE+0x0B)  /* OCM I-side Bank 2 Config Reg  */
1045 #define ocmdsisdpc      (OCM_DCR_BASE+0x0C)  /* OCM D-side/I-side Data Par Chk*/
1046 #define ocmdsisbear     (OCM_DCR_BASE+0x0D)  /* OCM D-side/I-side Bus Err Addr*/
1047 #define ocmdsisbesr     (OCM_DCR_BASE+0x0E)  /* OCM D-side/I-side Bus Err Stat*/
1048 #else
1049 #define OCM_DCR_BASE 0x018
1050 #define ocmisarc   (OCM_DCR_BASE+0x00)  /* OCM I-side address compare reg    */
1051 #define ocmiscntl  (OCM_DCR_BASE+0x01)  /* OCM I-side control reg            */
1052 #define ocmdsarc   (OCM_DCR_BASE+0x02)  /* OCM D-side address compare reg    */
1053 #define ocmdscntl  (OCM_DCR_BASE+0x03)  /* OCM D-side control reg            */
1054 #endif /* CONFIG_405EZ */
1055
1056 /******************************************************************************
1057  * GPIO macro register defines
1058  ******************************************************************************/
1059 #if defined(CONFIG_405EZ)
1060 /* Only the 405EZ has 2 GPIOs */
1061 #define GPIO_BASE  0xEF600700
1062 #define GPIO0_OR                (GPIO_BASE+0x0)
1063 #define GPIO0_TCR               (GPIO_BASE+0x4)
1064 #define GPIO0_OSRL              (GPIO_BASE+0x8)
1065 #define GPIO0_OSRH              (GPIO_BASE+0xC)
1066 #define GPIO0_TSRL              (GPIO_BASE+0x10)
1067 #define GPIO0_TSRH              (GPIO_BASE+0x14)
1068 #define GPIO0_ODR               (GPIO_BASE+0x18)
1069 #define GPIO0_IR                (GPIO_BASE+0x1C)
1070 #define GPIO0_RR1               (GPIO_BASE+0x20)
1071 #define GPIO0_RR2               (GPIO_BASE+0x24)
1072 #define GPIO0_RR3               (GPIO_BASE+0x28)
1073 #define GPIO0_ISR1L             (GPIO_BASE+0x30)
1074 #define GPIO0_ISR1H             (GPIO_BASE+0x34)
1075 #define GPIO0_ISR2L             (GPIO_BASE+0x38)
1076 #define GPIO0_ISR2H             (GPIO_BASE+0x3C)
1077 #define GPIO0_ISR3L             (GPIO_BASE+0x40)
1078 #define GPIO0_ISR3H             (GPIO_BASE+0x44)
1079
1080 #define GPIO1_BASE  0xEF600800
1081 #define GPIO1_OR                (GPIO1_BASE+0x0)
1082 #define GPIO1_TCR               (GPIO1_BASE+0x4)
1083 #define GPIO1_OSRL              (GPIO1_BASE+0x8)
1084 #define GPIO1_OSRH              (GPIO1_BASE+0xC)
1085 #define GPIO1_TSRL              (GPIO1_BASE+0x10)
1086 #define GPIO1_TSRH              (GPIO1_BASE+0x14)
1087 #define GPIO1_ODR               (GPIO1_BASE+0x18)
1088 #define GPIO1_IR                (GPIO1_BASE+0x1C)
1089 #define GPIO1_RR1               (GPIO1_BASE+0x20)
1090 #define GPIO1_RR2               (GPIO1_BASE+0x24)
1091 #define GPIO1_RR3               (GPIO1_BASE+0x28)
1092 #define GPIO1_ISR1L             (GPIO1_BASE+0x30)
1093 #define GPIO1_ISR1H             (GPIO1_BASE+0x34)
1094 #define GPIO1_ISR2L             (GPIO1_BASE+0x38)
1095 #define GPIO1_ISR2H             (GPIO1_BASE+0x3C)
1096 #define GPIO1_ISR3L             (GPIO1_BASE+0x40)
1097 #define GPIO1_ISR3H             (GPIO1_BASE+0x44)
1098
1099 #elif defined(CONFIG_405EX)
1100 #define GPIO_BASE  0xEF600800
1101 #define GPIO0_OR               (GPIO_BASE+0x0)
1102 #define GPIO0_TCR              (GPIO_BASE+0x4)
1103 #define GPIO0_OSRL             (GPIO_BASE+0x8)
1104 #define GPIO0_OSRH             (GPIO_BASE+0xC)
1105 #define GPIO0_TSRL             (GPIO_BASE+0x10)
1106 #define GPIO0_TSRH             (GPIO_BASE+0x14)
1107 #define GPIO0_ODR              (GPIO_BASE+0x18)
1108 #define GPIO0_IR               (GPIO_BASE+0x1C)
1109 #define GPIO0_RR1              (GPIO_BASE+0x20)
1110 #define GPIO0_RR2              (GPIO_BASE+0x24)
1111 #define GPIO0_ISR1L            (GPIO_BASE+0x30)
1112 #define GPIO0_ISR1H            (GPIO_BASE+0x34)
1113 #define GPIO0_ISR2L            (GPIO_BASE+0x38)
1114 #define GPIO0_ISR2H            (GPIO_BASE+0x3C)
1115 #define GPIO0_ISR3L            (GPIO_BASE+0x40)
1116 #define GPIO0_ISR3H            (GPIO_BASE+0x44)
1117
1118 #else   /* !405EZ */
1119
1120 #define GPIO_BASE  0xEF600700
1121 #define GPIO0_OR               (GPIO_BASE+0x0)
1122 #define GPIO0_TCR              (GPIO_BASE+0x4)
1123 #define GPIO0_OSRH             (GPIO_BASE+0x8)
1124 #define GPIO0_OSRL             (GPIO_BASE+0xC)
1125 #define GPIO0_TSRH             (GPIO_BASE+0x10)
1126 #define GPIO0_TSRL             (GPIO_BASE+0x14)
1127 #define GPIO0_ODR              (GPIO_BASE+0x18)
1128 #define GPIO0_IR               (GPIO_BASE+0x1C)
1129 #define GPIO0_RR1              (GPIO_BASE+0x20)
1130 #define GPIO0_RR2              (GPIO_BASE+0x24)
1131 #define GPIO0_ISR1H            (GPIO_BASE+0x30)
1132 #define GPIO0_ISR1L            (GPIO_BASE+0x34)
1133 #define GPIO0_ISR2H            (GPIO_BASE+0x38)
1134 #define GPIO0_ISR2L            (GPIO_BASE+0x3C)
1135
1136 #endif /* CONFIG_405EZ */
1137
1138 #define GPIO0_BASE              GPIO_BASE
1139
1140 #if defined(CONFIG_405EX)
1141 #define SDR0_SRST               0x0200
1142
1143 #define SDRAM_BESR0     0x00
1144 #define SDRAM_BEARL     0x02
1145 #define SDRAM_BEARU     0x03
1146 #define SDRAM_WMIRQ     0x06    /**/
1147 #define SDRAM_PLBOPT    0x08    /**/
1148 #define SDRAM_PUABA     0x09    /**/
1149 #define SDRAM_MCSTAT    0x1F    /* memory controller status           */
1150 #define SDRAM_MCOPT1    0x20    /* memory controller options 1        */
1151 #define SDRAM_MCOPT2    0x21    /* memory controller options 2        */
1152 #define SDRAM_MODT0     0x22    /* on die termination for bank 0      */
1153 #define SDRAM_MODT1     0x23    /* on die termination for bank 1      */
1154 #define SDRAM_MODT2     0x24    /* on die termination for bank 2      */
1155 #define SDRAM_MODT3     0x25    /* on die termination for bank 3      */
1156 #define SDRAM_CODT      0x26    /* on die termination for controller  */
1157 #define SDRAM_VVPR      0x27    /* variable VRef programmming         */
1158 #define SDRAM_OPARS     0x28    /* on chip driver control setup       */
1159 #define SDRAM_OPART     0x29    /* on chip driver control trigger     */
1160 #define SDRAM_RTR       0x30    /* refresh timer                      */
1161 #define SDRAM_PMIT      0x34    /* power management idle timer        */
1162 #define SDRAM_MB0CF     0x40    /* memory bank 0 configuration        */
1163 #define SDRAM_MB1CF     0x44    /* memory bank 1 configuration        */
1164 #define SDRAM_MB2CF     0x48    /* memory bank 2 configuration        */
1165 #define SDRAM_MB3CF     0x4C    /* memory bank 3 configuration        */
1166 #define SDRAM_INITPLR0  0x50    /* manual initialization control      */
1167 #define SDRAM_INITPLR1  0x51    /* manual initialization control      */
1168 #define SDRAM_INITPLR2  0x52    /* manual initialization control      */
1169 #define SDRAM_INITPLR3  0x53    /* manual initialization control      */
1170 #define SDRAM_INITPLR4  0x54    /* manual initialization control      */
1171 #define SDRAM_INITPLR5  0x55    /* manual initialization control      */
1172 #define SDRAM_INITPLR6  0x56    /* manual initialization control      */
1173 #define SDRAM_INITPLR7  0x57    /* manual initialization control      */
1174 #define SDRAM_INITPLR8  0x58    /* manual initialization control      */
1175 #define SDRAM_INITPLR9  0x59    /* manual initialization control      */
1176 #define SDRAM_INITPLR10 0x5a    /* manual initialization control      */
1177 #define SDRAM_INITPLR11 0x5b    /* manual initialization control      */
1178 #define SDRAM_INITPLR12 0x5c    /* manual initialization control      */
1179 #define SDRAM_INITPLR13 0x5d    /* manual initialization control      */
1180 #define SDRAM_INITPLR14 0x5e    /* manual initialization control      */
1181 #define SDRAM_INITPLR15 0x5f    /* manual initialization control      */
1182 #define SDRAM_RQDC      0x70    /* read DQS delay control             */
1183 #define SDRAM_RFDC      0x74    /* read feedback delay control        */
1184 #define SDRAM_RDCC      0x78    /* read data capture control          */
1185 #define SDRAM_DLCR      0x7A    /* delay line calibration             */
1186 #define SDRAM_CLKTR     0x80    /* DDR clock timing                   */
1187 #define SDRAM_WRDTR     0x81    /* write data, DQS, DM clock, timing  */
1188 #define SDRAM_SDTR1     0x85    /* DDR SDRAM timing 1                 */
1189 #define SDRAM_SDTR2     0x86    /* DDR SDRAM timing 2                 */
1190 #define SDRAM_SDTR3     0x87    /* DDR SDRAM timing 3                 */
1191 #define SDRAM_MMODE     0x88    /* memory mode                        */
1192 #define SDRAM_MEMODE    0x89    /* memory extended mode               */
1193 #define SDRAM_ECCCR     0x98    /* ECC error status                   */
1194 #define SDRAM_RID       0xF8    /* revision ID                        */
1195
1196 /*-----------------------------------------------------------------------------+
1197 |  Memory Bank 0-7 configuration
1198 +-----------------------------------------------------------------------------*/
1199 #define SDRAM_RXBAS_SDSZ_4         0x00000000      /*   4M                    */
1200 #define SDRAM_RXBAS_SDSZ_8         0x00001000      /*   8M                    */
1201 #define SDRAM_RXBAS_SDSZ_16        0x00002000      /*  16M                    */
1202 #define SDRAM_RXBAS_SDSZ_32        0x00003000      /*  32M                    */
1203 #define SDRAM_RXBAS_SDSZ_64        0x00004000      /*  64M                    */
1204 #define SDRAM_RXBAS_SDSZ_128       0x00005000      /* 128M                    */
1205 #define SDRAM_RXBAS_SDSZ_256       0x00006000      /* 256M                    */
1206 #define SDRAM_RXBAS_SDSZ_512       0x00007000      /* 512M                    */
1207 #define SDRAM_RXBAS_SDSZ_1024      0x00008000      /* 1024M                   */
1208 #define SDRAM_RXBAS_SDSZ_2048      0x00009000      /* 2048M                   */
1209 #define SDRAM_RXBAS_SDSZ_4096      0x0000a000      /* 4096M                   */
1210 #define SDRAM_RXBAS_SDSZ_8192      0x0000b000      /* 8192M                   */
1211
1212 /*-----------------------------------------------------------------------------+
1213 |  Memory Controller Status
1214 +-----------------------------------------------------------------------------*/
1215 #define SDRAM_MCSTAT_MIC_MASK       0x80000000  /* Memory init status mask    */
1216 #define   SDRAM_MCSTAT_MIC_NOTCOMP  0x00000000  /* Mem init not complete      */
1217 #define   SDRAM_MCSTAT_MIC_COMP     0x80000000  /* Mem init complete          */
1218 #define SDRAM_MCSTAT_SRMS_MASK      0x80000000  /* Mem self refresh stat mask */
1219 #define   SDRAM_MCSTAT_SRMS_NOT_SF  0x00000000  /* Mem not in self refresh    */
1220 #define   SDRAM_MCSTAT_SRMS_SF      0x80000000  /* Mem in self refresh        */
1221
1222 /*-----------------------------------------------------------------------------+
1223 |  Memory Controller Options 1
1224 +-----------------------------------------------------------------------------*/
1225 #define SDRAM_MCOPT1_MCHK_MASK       0x30000000 /* Memory data err check mask */
1226 #define   SDRAM_MCOPT1_MCHK_NON      0x00000000 /* No ECC generation          */
1227 #define   SDRAM_MCOPT1_MCHK_GEN      0x20000000 /* ECC generation             */
1228 #define   SDRAM_MCOPT1_MCHK_CHK      0x10000000 /* ECC generation and check   */
1229 #define   SDRAM_MCOPT1_MCHK_CHK_REP  0x30000000 /* ECC generation, chk, report*/
1230 #define   SDRAM_MCOPT1_MCHK_CHK_DECODE(n)  ((((unsigned long)(n))>>28)&0x3)
1231 #define SDRAM_MCOPT1_RDEN_MASK       0x08000000 /* Registered DIMM mask       */
1232 #define   SDRAM_MCOPT1_RDEN          0x08000000 /* Registered DIMM enable     */
1233 #define SDRAM_MCOPT1_PMU_MASK        0x06000000 /* Page management unit mask  */
1234 #define   SDRAM_MCOPT1_PMU_CLOSE     0x00000000 /* PMU Close                  */
1235 #define   SDRAM_MCOPT1_PMU_OPEN      0x04000000 /* PMU Open                   */
1236 #define   SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose              */
1237 #define SDRAM_MCOPT1_DMWD_MASK       0x01000000 /* DRAM width mask            */
1238 #define   SDRAM_MCOPT1_DMWD_32       0x00000000 /* 32 bits                    */
1239 #define   SDRAM_MCOPT1_DMWD_64       0x01000000 /* 64 bits                    */
1240 #define SDRAM_MCOPT1_UIOS_MASK       0x00C00000 /* Unused IO State            */
1241 #define SDRAM_MCOPT1_BCNT_MASK       0x00200000 /* Bank count                 */
1242 #define   SDRAM_MCOPT1_4_BANKS       0x00000000 /* 4 Banks                    */
1243 #define   SDRAM_MCOPT1_8_BANKS       0x00200000 /* 8 Banks                    */
1244 #define SDRAM_MCOPT1_DDR_TYPE_MASK   0x00100000 /* DDR Memory Type mask       */
1245 #define   SDRAM_MCOPT1_DDR1_TYPE     0x00000000 /* DDR1 Memory Type           */
1246 #define   SDRAM_MCOPT1_DDR2_TYPE     0x00100000 /* DDR2 Memory Type           */
1247 #define   SDRAM_MCOPT1_QDEP          0x00020000 /* 4 commands deep            */
1248 #define SDRAM_MCOPT1_RWOO_MASK       0x00008000 /* Out of Order Read mask     */
1249 #define   SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled                   */
1250 #define   SDRAM_MCOPT1_RWOO_ENABLED  0x00008000 /* enabled                    */
1251 #define SDRAM_MCOPT1_WOOO_MASK       0x00004000 /* Out of Order Write mask    */
1252 #define   SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled                   */
1253 #define   SDRAM_MCOPT1_WOOO_ENABLED  0x00004000 /* enabled                    */
1254 #define SDRAM_MCOPT1_DCOO_MASK       0x00002000 /* All Out of Order mask      */
1255 #define   SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled                   */
1256 #define   SDRAM_MCOPT1_DCOO_ENABLED  0x00000000 /* enabled                    */
1257 #define SDRAM_MCOPT1_DREF_MASK       0x00001000 /* Deferred refresh mask      */
1258 #define   SDRAM_MCOPT1_DREF_NORMAL   0x00000000 /* normal refresh             */
1259 #define   SDRAM_MCOPT1_DREF_DEFER_4  0x00001000 /* defer up to 4 refresh cmd  */
1260
1261 /*-----------------------------------------------------------------------------+
1262 |  Memory Controller Options 2
1263 +-----------------------------------------------------------------------------*/
1264 #define SDRAM_MCOPT2_SREN_MASK        0x80000000 /* Self Test mask            */
1265 #define   SDRAM_MCOPT2_SREN_EXIT      0x00000000 /* Self Test exit            */
1266 #define   SDRAM_MCOPT2_SREN_ENTER     0x80000000 /* Self Test enter           */
1267 #define SDRAM_MCOPT2_PMEN_MASK        0x40000000 /* Power Management mask     */
1268 #define   SDRAM_MCOPT2_PMEN_DISABLE   0x00000000 /* disable                   */
1269 #define   SDRAM_MCOPT2_PMEN_ENABLE    0x40000000 /* enable                    */
1270 #define SDRAM_MCOPT2_IPTR_MASK        0x20000000 /* Init Trigger Reg mask     */
1271 #define   SDRAM_MCOPT2_IPTR_IDLE      0x00000000 /* idle                      */
1272 #define   SDRAM_MCOPT2_IPTR_EXECUTE   0x20000000 /* execute preloaded init    */
1273 #define SDRAM_MCOPT2_XSRP_MASK        0x10000000 /* Exit Self Refresh Prevent */
1274 #define   SDRAM_MCOPT2_XSRP_ALLOW     0x00000000 /* allow self refresh exit   */
1275 #define   SDRAM_MCOPT2_XSRP_PREVENT   0x10000000 /* prevent self refresh exit */
1276 #define SDRAM_MCOPT2_DCEN_MASK        0x08000000 /* SDRAM Controller Enable   */
1277 #define   SDRAM_MCOPT2_DCEN_DISABLE   0x00000000 /* SDRAM Controller Enable   */
1278 #define   SDRAM_MCOPT2_DCEN_ENABLE    0x08000000 /* SDRAM Controller Enable   */
1279 #define SDRAM_MCOPT2_ISIE_MASK        0x04000000 /* Init Seq Interruptable mas*/
1280 #define   SDRAM_MCOPT2_ISIE_DISABLE   0x00000000 /* disable                   */
1281 #define   SDRAM_MCOPT2_ISIE_ENABLE    0x04000000 /* enable                    */
1282
1283 /*-----------------------------------------------------------------------------+
1284 |  SDRAM Refresh Timer Register
1285 +-----------------------------------------------------------------------------*/
1286 #define SDRAM_RTR_RINT_MASK       0xFFF80000
1287 #define   SDRAM_RTR_RINT_ENCODE(n)  ((((unsigned long)(n))&0xFFF8)<<16)
1288 #define   SDRAM_RTR_RINT_DECODE(n)  ((((unsigned long)(n))>>16)&0xFFF8)
1289
1290 /*-----------------------------------------------------------------------------+
1291 |  SDRAM Read DQS Delay Control Register
1292 +-----------------------------------------------------------------------------*/
1293 #define SDRAM_RQDC_RQDE_MASK        0x80000000
1294 #define   SDRAM_RQDC_RQDE_DISABLE   0x00000000
1295 #define   SDRAM_RQDC_RQDE_ENABLE    0x80000000
1296 #define SDRAM_RQDC_RQFD_MASK        0x000001FF
1297 #define   SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
1298
1299 #define SDRAM_RQDC_RQFD_MAX         0xFF
1300
1301 /*-----------------------------------------------------------------------------+
1302 |  SDRAM Read Data Capture Control Register
1303 +-----------------------------------------------------------------------------*/
1304 #define SDRAM_RDCC_RDSS_MASK        0xC0000000
1305 #define   SDRAM_RDCC_RDSS_T1        0x00000000
1306 #define   SDRAM_RDCC_RDSS_T2        0x40000000
1307 #define   SDRAM_RDCC_RDSS_T3        0x80000000
1308 #define   SDRAM_RDCC_RDSS_T4        0xC0000000
1309 #define SDRAM_RDCC_RSAE_MASK        0x00000001
1310 #define   SDRAM_RDCC_RSAE_DISABLE   0x00000001
1311 #define   SDRAM_RDCC_RSAE_ENABLE    0x00000000
1312
1313 /*-----------------------------------------------------------------------------+
1314 |  SDRAM Read Feedback Delay Control Register
1315 +-----------------------------------------------------------------------------*/
1316 #define SDRAM_RFDC_ARSE_MASK        0x80000000
1317 #define   SDRAM_RFDC_ARSE_DISABLE   0x80000000
1318 #define   SDRAM_RFDC_ARSE_ENABLE    0x00000000
1319 #define SDRAM_RFDC_RFOS_MASK        0x007F0000
1320 #define   SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
1321 #define SDRAM_RFDC_RFFD_MASK        0x000003FF
1322 #define   SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
1323
1324 #define SDRAM_RFDC_RFFD_MAX         0x4FF
1325
1326 /*-----------------------------------------------------------------------------+
1327 |  SDRAM Delay Line Calibration Register
1328 +-----------------------------------------------------------------------------*/
1329 #define SDRAM_DLCR_DCLM_MASK          0x80000000
1330 #define   SDRAM_DLCR_DCLM_MANUEL      0x80000000
1331 #define   SDRAM_DLCR_DCLM_AUTO        0x00000000
1332 #define SDRAM_DLCR_DLCR_MASK          0x08000000
1333 #define   SDRAM_DLCR_DLCR_CALIBRATE   0x08000000
1334 #define   SDRAM_DLCR_DLCR_IDLE        0x00000000
1335 #define SDRAM_DLCR_DLCS_MASK          0x07000000
1336 #define   SDRAM_DLCR_DLCS_NOT_RUN     0x00000000
1337 #define   SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
1338 #define   SDRAM_DLCR_DLCS_COMPLETE    0x02000000
1339 #define   SDRAM_DLCR_DLCS_CONT_DONE   0x03000000
1340 #define   SDRAM_DLCR_DLCS_ERROR       0x04000000
1341 #define SDRAM_DLCR_DLCV_MASK          0x000001FF
1342 #define   SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
1343 #define   SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF)
1344
1345 /*-----------------------------------------------------------------------------+
1346 |  SDRAM Controller On Die Termination Register
1347 +-----------------------------------------------------------------------------*/
1348 #define   SDRAM_CODT_ODT_ON                   0x80000000
1349 #define   SDRAM_CODT_ODT_OFF                  0x00000000
1350 #define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK       0x00000020
1351 #define   SDRAM_CODT_DQS_2_5_V_DDR1           0x00000000
1352 #define   SDRAM_CODT_DQS_1_8_V_DDR2           0x00000020
1353 #define SDRAM_CODT_DQS_MASK                   0x00000010
1354 #define   SDRAM_CODT_DQS_DIFFERENTIAL         0x00000000
1355 #define   SDRAM_CODT_DQS_SINGLE_END           0x00000010
1356 #define   SDRAM_CODT_CKSE_DIFFERENTIAL          0x00000000
1357 #define   SDRAM_CODT_CKSE_SINGLE_END            0x00000008
1358 #define   SDRAM_CODT_FEEBBACK_RCV_SINGLE_END  0x00000004
1359 #define   SDRAM_CODT_FEEBBACK_DRV_SINGLE_END  0x00000002
1360 #define   SDRAM_CODT_IO_HIZ                                     0x00000000
1361 #define   SDRAM_CODT_IO_NMODE                                   0x00000001
1362
1363 /*-----------------------------------------------------------------------------+
1364 |  SDRAM Mode Register
1365 +-----------------------------------------------------------------------------*/
1366 #define SDRAM_MMODE_WR_MASK              0x00000E00
1367 #define   SDRAM_MMODE_WR_DDR1            0x00000000
1368 #define   SDRAM_MMODE_WR_DDR2_3_CYC      0x00000400
1369 #define   SDRAM_MMODE_WR_DDR2_4_CYC      0x00000600
1370 #define   SDRAM_MMODE_WR_DDR2_5_CYC      0x00000800
1371 #define   SDRAM_MMODE_WR_DDR2_6_CYC      0x00000A00
1372 #define SDRAM_MMODE_DCL_MASK             0x00000070
1373 #define   SDRAM_MMODE_DCL_DDR1_2_0_CLK   0x00000020
1374 #define   SDRAM_MMODE_DCL_DDR1_2_5_CLK   0x00000060
1375 #define   SDRAM_MMODE_DCL_DDR1_3_0_CLK   0x00000030
1376 #define   SDRAM_MMODE_DCL_DDR2_2_0_CLK   0x00000020
1377 #define   SDRAM_MMODE_DCL_DDR2_3_0_CLK   0x00000030
1378 #define   SDRAM_MMODE_DCL_DDR2_4_0_CLK   0x00000040
1379 #define   SDRAM_MMODE_DCL_DDR2_5_0_CLK   0x00000050
1380 #define   SDRAM_MMODE_DCL_DDR2_6_0_CLK   0x00000060
1381 #define   SDRAM_MMODE_DCL_DDR2_7_0_CLK   0x00000070
1382
1383 /*-----------------------------------------------------------------------------+
1384 |  SDRAM Extended Mode Register
1385 +-----------------------------------------------------------------------------*/
1386 #define SDRAM_MEMODE_DIC_MASK            0x00000002
1387 #define   SDRAM_MEMODE_DIC_NORMAL        0x00000000
1388 #define   SDRAM_MEMODE_DIC_WEAK          0x00000002
1389 #define SDRAM_MEMODE_DLL_MASK            0x00000001
1390 #define   SDRAM_MEMODE_DLL_DISABLE       0x00000001
1391 #define   SDRAM_MEMODE_DLL_ENABLE        0x00000000
1392 #define SDRAM_MEMODE_RTT_MASK                0x00000044
1393 #define   SDRAM_MEMODE_RTT_DISABLED      0x00000000
1394 #define   SDRAM_MEMODE_RTT_75OHM         0x00000004
1395 #define   SDRAM_MEMODE_RTT_150OHM        0x00000040
1396 #define SDRAM_MEMODE_DQS_MASK            0x00000400
1397 #define   SDRAM_MEMODE_DQS_DISABLE       0x00000400
1398 #define   SDRAM_MEMODE_DQS_ENABLE        0x00000000
1399
1400 /*-----------------------------------------------------------------------------+
1401 |  SDRAM Clock Timing Register
1402 +-----------------------------------------------------------------------------*/
1403 #define SDRAM_CLKTR_CLKP_MASK            0xC0000000
1404 #define   SDRAM_CLKTR_CLKP_0_DEG         0x00000000
1405 #define   SDRAM_CLKTR_CLKP_180_DEG_ADV   0x80000000
1406
1407 /*-----------------------------------------------------------------------------+
1408 |  SDRAM Write Timing Register
1409 +-----------------------------------------------------------------------------*/
1410 #define SDRAM_WRDTR_WDTP_1_CYC           0x80000000
1411 #define SDRAM_WRDTR_LLWP_MASK            0x10000000
1412 #define   SDRAM_WRDTR_LLWP_DIS           0x10000000
1413 #define   SDRAM_WRDTR_LLWP_1_CYC         0x00000000
1414 #define SDRAM_WRDTR_WTR_MASK             0x0E000000
1415 #define   SDRAM_WRDTR_WTR_0_DEG          0x06000000
1416 #define   SDRAM_WRDTR_WTR_180_DEG_ADV    0x02000000
1417 #define   SDRAM_WRDTR_WTR_270_DEG_ADV    0x00000000
1418
1419 /*-----------------------------------------------------------------------------+
1420 |  SDRAM SDTR1 Options
1421 +-----------------------------------------------------------------------------*/
1422 #define SDRAM_SDTR1_LDOF_MASK        0x80000000
1423 #define   SDRAM_SDTR1_LDOF_1_CLK     0x00000000
1424 #define   SDRAM_SDTR1_LDOF_2_CLK     0x80000000
1425 #define SDRAM_SDTR1_RTW_MASK         0x00F00000
1426 #define   SDRAM_SDTR1_RTW_2_CLK      0x00200000
1427 #define   SDRAM_SDTR1_RTW_3_CLK      0x00300000
1428 #define SDRAM_SDTR1_WTWO_MASK        0x000F0000
1429 #define   SDRAM_SDTR1_WTWO_0_CLK     0x00000000
1430 #define   SDRAM_SDTR1_WTWO_1_CLK     0x00010000
1431 #define SDRAM_SDTR1_RTRO_MASK        0x0000F000
1432 #define   SDRAM_SDTR1_RTRO_1_CLK     0x00000000
1433 #define   SDRAM_SDTR1_RTRO_2_CLK     0x00002000
1434
1435 /*-----------------------------------------------------------------------------+
1436 |  SDRAM SDTR2 Options
1437 +-----------------------------------------------------------------------------*/
1438 #define SDRAM_SDTR2_RCD_MASK         0xF0000000
1439 #define   SDRAM_SDTR2_RCD_1_CLK      0x10000000
1440 #define   SDRAM_SDTR2_RCD_2_CLK      0x20000000
1441 #define   SDRAM_SDTR2_RCD_3_CLK      0x30000000
1442 #define   SDRAM_SDTR2_RCD_4_CLK      0x40000000
1443 #define   SDRAM_SDTR2_RCD_5_CLK      0x50000000
1444 #define SDRAM_SDTR2_WTR_MASK         0x0F000000
1445 #define   SDRAM_SDTR2_WTR_1_CLK      0x01000000
1446 #define   SDRAM_SDTR2_WTR_2_CLK      0x02000000
1447 #define   SDRAM_SDTR2_WTR_3_CLK      0x03000000
1448 #define   SDRAM_SDTR2_WTR_4_CLK      0x04000000
1449 #define   SDRAM_SDTR3_WTR_ENCODE(n)  ((((unsigned long)(n))&0xF)<<24)
1450 #define SDRAM_SDTR2_XSNR_MASK        0x00FF0000
1451 #define   SDRAM_SDTR2_XSNR_8_CLK     0x00080000
1452 #define   SDRAM_SDTR2_XSNR_16_CLK    0x00100000
1453 #define   SDRAM_SDTR2_XSNR_32_CLK    0x00200000
1454 #define   SDRAM_SDTR2_XSNR_64_CLK    0x00400000
1455 #define SDRAM_SDTR2_WPC_MASK         0x0000F000
1456 #define   SDRAM_SDTR2_WPC_2_CLK      0x00002000
1457 #define   SDRAM_SDTR2_WPC_3_CLK      0x00003000
1458 #define   SDRAM_SDTR2_WPC_4_CLK      0x00004000
1459 #define   SDRAM_SDTR2_WPC_5_CLK      0x00005000
1460 #define   SDRAM_SDTR2_WPC_6_CLK      0x00006000
1461 #define   SDRAM_SDTR3_WPC_ENCODE(n)  ((((unsigned long)(n))&0xF)<<12)
1462 #define SDRAM_SDTR2_RPC_MASK         0x00000F00
1463 #define   SDRAM_SDTR2_RPC_2_CLK      0x00000200
1464 #define   SDRAM_SDTR2_RPC_3_CLK      0x00000300
1465 #define   SDRAM_SDTR2_RPC_4_CLK      0x00000400
1466 #define SDRAM_SDTR2_RP_MASK          0x000000F0
1467 #define   SDRAM_SDTR2_RP_3_CLK       0x00000030
1468 #define   SDRAM_SDTR2_RP_4_CLK       0x00000040
1469 #define   SDRAM_SDTR2_RP_5_CLK       0x00000050
1470 #define   SDRAM_SDTR2_RP_6_CLK       0x00000060
1471 #define   SDRAM_SDTR2_RP_7_CLK       0x00000070
1472 #define SDRAM_SDTR2_RRD_MASK         0x0000000F
1473 #define   SDRAM_SDTR2_RRD_2_CLK      0x00000002
1474 #define   SDRAM_SDTR2_RRD_3_CLK      0x00000003
1475
1476 /*-----------------------------------------------------------------------------+
1477 |  SDRAM SDTR3 Options
1478 +-----------------------------------------------------------------------------*/
1479 #define SDRAM_SDTR3_RAS_MASK         0x1F000000
1480 #define   SDRAM_SDTR3_RAS_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<24)
1481 #define SDRAM_SDTR3_RC_MASK          0x001F0000
1482 #define   SDRAM_SDTR3_RC_ENCODE(n)   ((((unsigned long)(n))&0x1F)<<16)
1483 #define SDRAM_SDTR3_XCS_MASK         0x00001F00
1484 #define SDRAM_SDTR3_XCS              0x00000D00
1485 #define SDRAM_SDTR3_RFC_MASK         0x0000003F
1486 #define   SDRAM_SDTR3_RFC_ENCODE(n)  ((((unsigned long)(n))&0x3F)<<0)
1487
1488 /*-----------------------------------------------------------------------------+
1489 |  Memory Bank 0-1 configuration
1490 +-----------------------------------------------------------------------------*/
1491 #define SDRAM_BXCF_M_AM_MASK      0x00000F00      /* Addressing mode          */
1492 #define   SDRAM_BXCF_M_AM_0       0x00000000      /*   Mode 0                 */
1493 #define   SDRAM_BXCF_M_AM_1       0x00000100      /*   Mode 1                 */
1494 #define   SDRAM_BXCF_M_AM_2       0x00000200      /*   Mode 2                 */
1495 #define   SDRAM_BXCF_M_AM_3       0x00000300      /*   Mode 3                 */
1496 #define   SDRAM_BXCF_M_AM_4       0x00000400      /*   Mode 4                 */
1497 #define   SDRAM_BXCF_M_AM_5       0x00000500      /*   Mode 5                 */
1498 #define   SDRAM_BXCF_M_AM_6       0x00000600      /*   Mode 6                 */
1499 #define   SDRAM_BXCF_M_AM_7       0x00000700      /*   Mode 7                 */
1500 #define   SDRAM_BXCF_M_AM_8       0x00000800      /*   Mode 8                 */
1501 #define   SDRAM_BXCF_M_AM_9       0x00000900      /*   Mode 9                 */
1502 #define SDRAM_BXCF_M_BE_MASK      0x00000001      /* Memory Bank Enable       */
1503 #define   SDRAM_BXCF_M_BE_DISABLE 0x00000000      /* Memory Bank Enable       */
1504 #define   SDRAM_BXCF_M_BE_ENABLE  0x00000001      /* Memory Bank Enable       */
1505
1506 #define sdr_uart0       0x0120  /* UART0 Config */
1507 #define sdr_uart1       0x0121  /* UART1 Config */
1508 #define sdr_mfr         0x4300  /* SDR0_MFR reg */
1509
1510 /* Defines for CPC0_EPRCSR register */
1511 #define CPC0_EPRCSR_E0NFE          0x80000000
1512 #define CPC0_EPRCSR_E1NFE          0x40000000
1513 #define CPC0_EPRCSR_E1RPP          0x00000080
1514 #define CPC0_EPRCSR_E0RPP          0x00000040
1515 #define CPC0_EPRCSR_E1ERP          0x00000020
1516 #define CPC0_EPRCSR_E0ERP          0x00000010
1517 #define CPC0_EPRCSR_E1PCI          0x00000002
1518 #define CPC0_EPRCSR_E0PCI          0x00000001
1519
1520 #define cpr0_clkupd     0x020
1521 #define cpr0_pllc       0x040
1522 #define cpr0_plld       0x060
1523 #define cpr0_cpud       0x080
1524 #define cpr0_plbd       0x0a0
1525 #define cpr0_opbd       0x0c0
1526 #define cpr0_perd       0x0e0
1527 #define cpr0_ahbd       0x100
1528 #define cpr0_icfg       0x140
1529
1530 #define SDR_PINSTP      0x0040
1531 #define sdr_sdcs        0x0060
1532
1533 #define SDR0_SDCS_SDD                   (0x80000000 >> 31)
1534
1535 /* CUST0 Customer Configuration Register0 */
1536 #define SDR0_CUST0                   0x4000
1537 #define   SDR0_CUST0_MUX_E_N_G_MASK   0xC0000000     /* Mux_Emac_NDFC_GPIO */
1538 #define   SDR0_CUST0_MUX_EMAC_SEL     0x40000000       /* Emac Selection */
1539 #define   SDR0_CUST0_MUX_NDFC_SEL     0x80000000       /* NDFC Selection */
1540 #define   SDR0_CUST0_MUX_GPIO_SEL     0xC0000000       /* GPIO Selection */
1541
1542 #define   SDR0_CUST0_NDFC_EN_MASK     0x20000000     /* NDFC Enable Mask */
1543 #define   SDR0_CUST0_NDFC_ENABLE      0x20000000       /* NDFC Enable */
1544 #define   SDR0_CUST0_NDFC_DISABLE     0x00000000       /* NDFC Disable */
1545
1546 #define   SDR0_CUST0_NDFC_BW_MASK     0x10000000     /* NDFC Boot Width */
1547 #define   SDR0_CUST0_NDFC_BW_16_BIT   0x10000000       /* NDFC Boot Width = 16 Bit */
1548 #define   SDR0_CUST0_NDFC_BW_8_BIT    0x00000000       /* NDFC Boot Width =  8 Bit */
1549
1550 #define   SDR0_CUST0_NDFC_BP_MASK     0x0F000000     /* NDFC Boot Page */
1551 #define   SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
1552 #define   SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
1553
1554 #define   SDR0_CUST0_NDFC_BAC_MASK    0x00C00000     /* NDFC Boot Address Cycle */
1555 #define   SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
1556 #define   SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
1557
1558 #define   SDR0_CUST0_NDFC_ARE_MASK    0x00200000     /* NDFC Auto Read Enable */
1559 #define   SDR0_CUST0_NDFC_ARE_ENABLE  0x00200000       /* NDFC Auto Read Enable */
1560 #define   SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000       /* NDFC Auto Read Disable */
1561
1562 #define   SDR0_CUST0_NRB_MASK         0x00100000     /* NDFC Ready / Busy */
1563 #define   SDR0_CUST0_NRB_BUSY         0x00100000       /* Busy */
1564 #define   SDR0_CUST0_NRB_READY        0x00000000       /* Ready */
1565
1566 #define   SDR0_CUST0_NDRSC_MASK       0x0000FFF0     /* NDFC Device Reset Count Mask */
1567 #define   SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
1568 #define   SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
1569
1570 #define   SDR0_CUST0_CHIPSELGAT_MASK  0x0000000F     /* Chip Select Gating Mask */
1571 #define   SDR0_CUST0_CHIPSELGAT_DIS   0x00000000       /* Chip Select Gating Disable */
1572 #define   SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F       /* All Chip Select Gating Enable */
1573 #define   SDR0_CUST0_CHIPSELGAT_EN0   0x00000008       /* Chip Select0 Gating Enable */
1574 #define   SDR0_CUST0_CHIPSELGAT_EN1   0x00000004       /* Chip Select1 Gating Enable */
1575 #define   SDR0_CUST0_CHIPSELGAT_EN2   0x00000002       /* Chip Select2 Gating Enable */
1576 #define   SDR0_CUST0_CHIPSELGAT_EN3   0x00000001       /* Chip Select3 Gating Enable */
1577
1578 #define SDR0_PFC0               0x4100
1579 #define SDR0_PFC1               0x4101
1580 #define SDR0_PFC1_U1ME          0x02000000
1581 #define SDR0_PFC1_U0ME          0x00080000
1582 #define SDR0_PFC1_U0IM          0x00040000
1583 #define SDR0_PFC1_SIS           0x00020000
1584 #define SDR0_PFC1_DMAAEN        0x00010000
1585 #define SDR0_PFC1_DMADEN        0x00008000
1586 #define SDR0_PFC1_USBEN         0x00004000
1587 #define SDR0_PFC1_AHBSWAP       0x00000020
1588 #define SDR0_PFC1_USBBIGEN      0x00000010
1589 #define SDR0_PFC1_GPT_FREQ      0x0000000f
1590 #endif
1591
1592 #endif  /* __PPC405_H__ */