ppc4xx: Update Kilauea CPLD configuration with USB PHY reset bit
[u-boot-openmoko.git] / include / mpc8260_irq.h
blob9bee9a335ff43ac4fc4e1c175002e07e9b1a3a96
1 #ifndef _MPC8260_IRQ_H
2 #define _MPC8260_IRQ_H
4 /****************************************************************************/
5 /* most of this was ripped out of include/asm-ppc/irq.h from the Linux/PPC */
6 /* source. There was no copyright information in the file. */
8 /*
9 * this is the # irq's for all ppc arch's (pmac/chrp/prep)
10 * so it is the max of them all
12 * [let's just worry about 8260 for now - mjj]
14 #define NR_IRQS 64
16 /* The 8260 has an internal interrupt controller with a maximum of
17 * 64 IRQs. We will use NR_IRQs from above since it is large enough.
18 * Don't be confused by the 8260 documentation where they list an
19 * "interrupt number" and "interrupt vector". We are only interested
20 * in the interrupt vector. There are "reserved" holes where the
21 * vector number increases, but the interrupt number in the table does not.
22 * (Document errata updates have fixed this...make sure you have up to
23 * date processor documentation -- Dan).
25 #define NR_SIU_INTS 64
27 /* There are many more than these, we will add them as we need them.
29 #define SIU_INT_SMC1 ((uint)0x04)
30 #define SIU_INT_SMC2 ((uint)0x05)
31 #define SIU_INT_IRQ1 ((uint)0x13)
32 #define SIU_INT_IRQ2 ((uint)0x14)
33 #define SIU_INT_IRQ3 ((uint)0x15)
34 #define SIU_INT_IRQ4 ((uint)0x16)
35 #define SIU_INT_IRQ5 ((uint)0x17)
36 #define SIU_INT_IRQ6 ((uint)0x18)
37 #define SIU_INT_IRQ7 ((uint)0x19)
38 #define SIU_INT_FCC1 ((uint)0x20)
39 #define SIU_INT_FCC2 ((uint)0x21)
40 #define SIU_INT_FCC3 ((uint)0x22)
41 #define SIU_INT_SCC1 ((uint)0x28)
42 #define SIU_INT_SCC2 ((uint)0x29)
43 #define SIU_INT_SCC3 ((uint)0x2a)
44 #define SIU_INT_SCC4 ((uint)0x2b)
46 #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
48 #endif /* _MPC8260_IRQ_H */