board/netstal/hcu5/sdram.c

   1 /*
   2  * (C) Copyright 2007
   3  * Niklaus Giger (Niklaus.Giger@netstal.com)
   4  * (C) Copyright 2006
   5  * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
   6  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   7  * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
   8  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   9  * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
  10  *
  11  * (C) Copyright 2006
  12  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 /* define DEBUG for debug output */
  31 #undef DEBUG
  32
  33 #include <common.h>
  34 #include <asm/processor.h>
  35 #include <asm/io.h>
  36 #include <asm/mmu.h>
  37 #include <ppc440.h>
  38
  39 void hcu_led_set(u32 value);
  40 void dcbz_area(u32 start_address, u32 num_bytes);
  41 void dflush(void);
  42
  43 #define DDR_DCR_BASE 0x10
  44 #define ddrcfga  (DDR_DCR_BASE+0x0)   /* DDR configuration address reg */
  45 #define ddrcfgd  (DDR_DCR_BASE+0x1)   /* DDR configuration data reg    */
  46
  47 #define DDR0_01_INT_MASK_MASK             0x000000FF
  48 #define DDR0_00_INT_ACK_ALL               0x7F000000
  49 #define DDR0_01_INT_MASK_ALL_ON           0x000000FF
  50 #define DDR0_01_INT_MASK_ALL_OFF          0x00000000
  51
  52 #define DDR0_17_DLLLOCKREG_MASK           0x00010000 /* Read only */
  53 #define DDR0_17_DLLLOCKREG_UNLOCKED       0x00000000
  54 #define DDR0_17_DLLLOCKREG_LOCKED         0x00010000
  55
  56 #define DDR0_22                         0x16
  57 /* ECC */
  58 #define DDR0_22_CTRL_RAW_MASK             0x03000000
  59 #define DDR0_22_CTRL_RAW_ECC_DISABLE      0x00000000 /* ECC not enabled */
  60 #define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY   0x01000000 /* ECC no correction */
  61 #define DDR0_22_CTRL_RAW_NO_ECC_RAM       0x02000000 /* Not a ECC RAM*/
  62 #define DDR0_22_CTRL_RAW_ECC_ENABLE       0x03000000 /* ECC correcting on */
  63 #define DDR0_03_CASLAT_DECODE(n)            ((((unsigned long)(n))>>16)&0x7)
  64
  65 #define ECC_RAM                         0x03267F0B
  66 #define NO_ECC_RAM                      0x00267F0B
  67
  68 #define HCU_HW_SDRAM_CONFIG_MASK        0x7
  69
  70 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
  71         /* disable caching on DDR2 */
  72
  73 void board_add_ram_info(int use_default)
  74 {
  75         PPC4xx_SYS_INFO board_cfg;
  76         u32 val;
  77
  78         mfsdram(DDR0_22, val);
  79         val &= DDR0_22_CTRL_RAW_MASK;
  80         switch (val) {
  81         case DDR0_22_CTRL_RAW_ECC_DISABLE:
  82                 puts(" (ECC disabled");
  83                 break;
  84         case DDR0_22_CTRL_RAW_ECC_CHECK_ONLY:
  85                 puts(" (ECC check only");
  86                 break;
  87         case DDR0_22_CTRL_RAW_NO_ECC_RAM:
  88                 puts(" (no ECC ram");
  89                 break;
  90         case DDR0_22_CTRL_RAW_ECC_ENABLE:
  91                 puts(" (ECC enabled");
  92                 break;
  93         }
  94
  95         get_sys_info(&board_cfg);
  96         printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000);
  97
  98         mfsdram(DDR0_03, val);
  99         val = DDR0_03_CASLAT_DECODE(val);
 100         printf(", CL%d)", val);
 101 }
 102
 103 /*--------------------------------------------------------------------
 104  * wait_for_dlllock.
 105  *--------------------------------------------------------------------*/
 106 static int wait_for_dlllock(void)
 107 {
 108         unsigned long val;
 109         int wait = 0;
 110
 111         /* -----------------------------------------------------------+
 112          * Wait for the DCC master delay line to finish calibration
 113          * ----------------------------------------------------------*/
 114         mtdcr(ddrcfga, DDR0_17);
 115         val = DDR0_17_DLLLOCKREG_UNLOCKED;
 116
 117         while (wait != 0xffff) {
 118                 val = mfdcr(ddrcfgd);
 119                 if ((val & DDR0_17_DLLLOCKREG_MASK) ==
 120                     DDR0_17_DLLLOCKREG_LOCKED)
 121                         /* dlllockreg bit on */
 122                         return 0;
 123                 else
 124                         wait++;
 125         }
 126         debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
 127         debug("Waiting for dlllockreg bit to raise\n");
 128
 129         return -1;
 130 }
 131
 132 /***********************************************************************
 133  *
 134  * sdram_panic -- Panic if we cannot configure the sdram correctly
 135  *
 136  ************************************************************************/
 137 void sdram_panic(const char *reason)
 138 {
 139         printf("\n%s: reason %s",  __FUNCTION__,  reason);
 140         hcu_led_set(0xff);
 141         while (1) {
 142         }
 143         /* Never return */
 144 }
 145
 146 #ifdef CONFIG_DDR_ECC
 147 static void blank_string(int size)
 148 {
 149         int i;
 150
 151         for (i=0; i<size; i++)
 152                 putc('\b');
 153         for (i=0; i<size; i++)
 154                 putc(' ');
 155         for (i=0; i<size; i++)
 156                 putc('\b');
 157 }
 158 /*---------------------------------------------------------------------------+
 159  * program_ecc.
 160  *---------------------------------------------------------------------------*/
 161 static void program_ecc(unsigned long start_address, unsigned long num_bytes)
 162 {
 163         u32 val;
 164         char str[] = "ECC generation -";
 165 #if defined(CONFIG_PRAM)
 166         u32 *magicPtr;
 167         u32 magic;
 168
 169         if ((mfspr(dbcr0) & 0x80000000) == 0) {
 170                 /* only if no external debugger is alive!
 171                  * Check whether vxWorks is using EDR logging, if yes zero
 172                  * also PostMortem and user reserved memory
 173                  */
 174                 magicPtr = (u32 *)(start_address + num_bytes -
 175                                 (CONFIG_PRAM*1024) + sizeof(u32));
 176                 magic = in_be32(magicPtr);
 177                 debug("%s:  CONFIG_PRAM %d kB magic 0x%x 0x%p\n",
 178                       __FUNCTION__, CONFIG_PRAM,
 179                       magicPtr, magic);
 180                 if (magic == 0xbeefbabe) {
 181                         printf("%s: preserving at %p\n", __FUNCTION__, magicPtr);
 182                         num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM;
 183                 }
 184         }
 185 #endif
 186
 187         sync();
 188         eieio();
 189
 190         puts(str);
 191
 192         /* ECC bit set method for cached memory */
 193         /* Fast method, no noticeable delay */
 194         dcbz_area(start_address, num_bytes);
 195         dflush();
 196         blank_string(strlen(str));
 197
 198         /* Clear error status */
 199         mfsdram(DDR0_00, val);
 200         mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
 201
 202         /*
 203          * Clear possible ECC errors
 204          * If not done, then we could get an interrupt later on when
 205          * exceptions are enabled.
 206          */
 207         mtspr(mcsr, mfspr(mcsr));
 208
 209         /* Set 'int_mask' parameter to functionnal value */
 210         mfsdram(DDR0_01, val);
 211         mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) |
 212                           DDR0_01_INT_MASK_ALL_OFF));
 213
 214         return;
 215 }
 216 #endif
 217
 218
 219 /***********************************************************************
 220  *
 221  * initdram -- 440EPx's DDR controller is a DENALI Core
 222  *
 223  ************************************************************************/
 224 long int initdram (int board_type)
 225 {
 226         unsigned int dram_size = 0;
 227
 228         mtsdram(DDR0_02, 0x00000000);
 229
 230         /* Values must be kept in sync with Excel-table <<A0001492.>> ! */
 231         mtsdram(DDR0_00, 0x0000190A);
 232         mtsdram(DDR0_01, 0x01000000);
 233         mtsdram(DDR0_03, 0x02030602);
 234         mtsdram(DDR0_04, 0x0A020200);
 235         mtsdram(DDR0_05, 0x02020307);
 236         switch (in_be16((u16 *)HCU_HW_VERSION_REGISTER) & HCU_HW_SDRAM_CONFIG_MASK) {
 237         case 1:
 238                 dram_size = 256 * 1024 * 1024 ;
 239                 mtsdram(DDR0_06, 0x0102C812);  /* 256MB RAM */
 240                 mtsdram(DDR0_11, 0x0014C800);  /* 256MB RAM */
 241                 mtsdram(DDR0_43, 0x030A0200);  /* 256MB RAM */
 242                 break;
 243         case 0:
 244         default:
 245                 dram_size = 128 * 1024 * 1024 ;
 246                 mtsdram(DDR0_06, 0x0102C80D);  /* 128MB RAM */
 247                 mtsdram(DDR0_11, 0x000FC800);  /* 128MB RAM */
 248                 mtsdram(DDR0_43, 0x030A0300);  /* 128MB RAM */
 249                 break;
 250         }
 251         mtsdram(DDR0_07, 0x00090100);
 252
 253         /*
 254          * TCPD=200 cycles of clock input is required to lock the DLL.
 255          * CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001);
 256          */
 257         mtsdram(DDR0_08, 0x02C80001);
 258         mtsdram(DDR0_09, 0x00011D5F);
 259         mtsdram(DDR0_10, 0x00000100);
 260         mtsdram(DDR0_12, 0x00000003);
 261         mtsdram(DDR0_14, 0x00000000);
 262         mtsdram(DDR0_17, 0x1D000000);
 263         mtsdram(DDR0_18, 0x1D1D1D1D);
 264         mtsdram(DDR0_19, 0x1D1D1D1D);
 265         mtsdram(DDR0_20, 0x0B0B0B0B);
 266         mtsdram(DDR0_21, 0x0B0B0B0B);
 267 #ifdef CONFIG_DDR_ECC
 268         mtsdram(DDR0_22, ECC_RAM);
 269 #else
 270         mtsdram(DDR0_22, NO_ECC_RAM);
 271 #endif
 272
 273         mtsdram(DDR0_23, 0x00000000);
 274         mtsdram(DDR0_24, 0x01020001);
 275         mtsdram(DDR0_26, 0x2D930517);
 276         mtsdram(DDR0_27, 0x00008236);
 277         mtsdram(DDR0_28, 0x00000000);
 278         mtsdram(DDR0_31, 0x00000000);
 279         mtsdram(DDR0_42, 0x01000006);
 280         mtsdram(DDR0_44, 0x00000003);
 281         mtsdram(DDR0_02, 0x00000001);
 282         wait_for_dlllock();
 283         mtsdram(DDR0_00, 0x40000000);  /* Zero init bit */
 284
 285         /*
 286          * Program tlb entries for this size (dynamic)
 287          */
 288         remove_tlb(CFG_SDRAM_BASE, 256 << 20);
 289         program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE);
 290
 291         /*
 292          * Setup 2nd TLB with same physical address but different virtual
 293          * address with cache enabled. This is done for fast ECC generation.
 294          */
 295         program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
 296
 297 #ifdef CONFIG_DDR_ECC
 298         /*
 299          * If ECC is enabled, initialize the parity bits.
 300          */
 301         program_ecc(CFG_DDR_CACHED_ADDR, dram_size);
 302 #endif
 303
 304         return (dram_size);
 305 }