| commit | b4e92805c20b92b459fa313d127e60041fb9801e | |
| author | Jeff Connelly <shellreef+git@gmail.com> | |
| Sat, 10 May 2008 23:29:42 +0000 (10 16:29 -0700) | ||
| committer | Jeff Connelly <shellreef+git@gmail.com> | |
| Sat, 10 May 2008 23:29:42 +0000 (10 16:29 -0700) | ||
| tree | 7d74c734fe8f22008d28b51592a957215cb35dc2 | treesnapshot (tar.gz zip) |
| parent | 78874aa9568d59d84e625b382be2784a06e48e56 | commitdiff |
Annonate the trit_reg3_test graph, which doesn't match jeff.tk/wiki/Image:3-Trit_Register_Timing_Diagram.png.
In the old graph, register trits started at 0. Now they start at i. Unexpected.
In this graph, Q2 isn't latched to 1 when D2 is high and CLK rises.
Something must have changed since 2008-04-07.
In the old graph, register trits started at 0. Now they start at i. Unexpected.
In this graph, Q2 isn't latched to 1 when D2 is high and CLK rises.
Something must have changed since 2008-04-07.
| circuits/trit_reg3.asc | diffblobblamehistory | |
| circuits/trit_reg3_test.asc | diffblobblamehistory | |
| circuits/trit_reg3_test.plt | diffblobblamehistory |