2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
9 * 2_by_8 routines added by Simon Munton
11 * 4_by_16 work by Carolyn J. Smith
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
16 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
20 * $Id: cfi_cmdset_0002.c,v 1.122 2005/11/07 11:14:22 gleixner Exp $
24 #include <linux/module.h>
25 #include <linux/types.h>
26 #include <linux/kernel.h>
27 #include <linux/sched.h>
28 #include <linux/init.h>
30 #include <asm/byteorder.h>
32 #include <linux/errno.h>
33 #include <linux/slab.h>
34 #include <linux/delay.h>
35 #include <linux/interrupt.h>
36 #include <linux/mtd/compatmac.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
45 #define MAX_WORD_RETRIES 3
47 #define MANUFACTURER_AMD 0x0001
48 #define MANUFACTURER_ATMEL 0x001F
49 #define MANUFACTURER_SST 0x00BF
50 #define MANUFACTURER_SAMSUNG 0x00EC
51 #define SST49LF004B 0x0060
52 #define SST49LF040B 0x0050
53 #define SST49LF008A 0x005a
54 #define AT49BV6416 0x00d6
56 static int cfi_amdstd_read (struct mtd_info
*, loff_t
, size_t, size_t *, u_char
*);
57 static int cfi_amdstd_write_words(struct mtd_info
*, loff_t
, size_t, size_t *, const u_char
*);
58 static int cfi_amdstd_write_buffers(struct mtd_info
*, loff_t
, size_t, size_t *, const u_char
*);
59 static int cfi_amdstd_erase_chip(struct mtd_info
*, struct erase_info
*);
60 static int cfi_amdstd_erase_varsize(struct mtd_info
*, struct erase_info
*);
61 static void cfi_amdstd_sync (struct mtd_info
*);
62 static int cfi_amdstd_suspend (struct mtd_info
*);
63 static void cfi_amdstd_resume (struct mtd_info
*);
64 static int cfi_amdstd_secsi_read (struct mtd_info
*, loff_t
, size_t, size_t *, u_char
*);
66 static void cfi_amdstd_destroy(struct mtd_info
*);
68 struct mtd_info
*cfi_cmdset_0002(struct map_info
*, int);
69 static struct mtd_info
*cfi_amdstd_setup (struct mtd_info
*);
71 static int get_chip(struct map_info
*map
, struct flchip
*chip
, unsigned long adr
, int mode
);
72 static void put_chip(struct map_info
*map
, struct flchip
*chip
, unsigned long adr
);
75 static int cfi_atmel_lock(struct mtd_info
*mtd
, loff_t ofs
, size_t len
);
76 static int cfi_atmel_unlock(struct mtd_info
*mtd
, loff_t ofs
, size_t len
);
78 static struct mtd_chip_driver cfi_amdstd_chipdrv
= {
79 .probe
= NULL
, /* Not usable directly */
80 .destroy
= cfi_amdstd_destroy
,
81 .name
= "cfi_cmdset_0002",
86 /* #define DEBUG_CFI_FEATURES */
89 #ifdef DEBUG_CFI_FEATURES
90 static void cfi_tell_features(struct cfi_pri_amdstd
*extp
)
92 const char* erase_suspend
[3] = {
93 "Not supported", "Read only", "Read/write"
95 const char* top_bottom
[6] = {
96 "No WP", "8x8KiB sectors at top & bottom, no WP",
97 "Bottom boot", "Top boot",
98 "Uniform, Bottom WP", "Uniform, Top WP"
101 printk(" Silicon revision: %d\n", extp
->SiliconRevision
>> 1);
102 printk(" Address sensitive unlock: %s\n",
103 (extp
->SiliconRevision
& 1) ? "Not required" : "Required");
105 if (extp
->EraseSuspend
< ARRAY_SIZE(erase_suspend
))
106 printk(" Erase Suspend: %s\n", erase_suspend
[extp
->EraseSuspend
]);
108 printk(" Erase Suspend: Unknown value %d\n", extp
->EraseSuspend
);
110 if (extp
->BlkProt
== 0)
111 printk(" Block protection: Not supported\n");
113 printk(" Block protection: %d sectors per group\n", extp
->BlkProt
);
116 printk(" Temporary block unprotect: %s\n",
117 extp
->TmpBlkUnprotect
? "Supported" : "Not supported");
118 printk(" Block protect/unprotect scheme: %d\n", extp
->BlkProtUnprot
);
119 printk(" Number of simultaneous operations: %d\n", extp
->SimultaneousOps
);
120 printk(" Burst mode: %s\n",
121 extp
->BurstMode
? "Supported" : "Not supported");
122 if (extp
->PageMode
== 0)
123 printk(" Page mode: Not supported\n");
125 printk(" Page mode: %d word page\n", extp
->PageMode
<< 2);
127 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
128 extp
->VppMin
>> 4, extp
->VppMin
& 0xf);
129 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
130 extp
->VppMax
>> 4, extp
->VppMax
& 0xf);
132 if (extp
->TopBottom
< ARRAY_SIZE(top_bottom
))
133 printk(" Top/Bottom Boot Block: %s\n", top_bottom
[extp
->TopBottom
]);
135 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp
->TopBottom
);
139 #ifdef AMD_BOOTLOC_BUG
140 /* Wheee. Bring me the head of someone at AMD. */
141 static void fixup_amd_bootblock(struct mtd_info
*mtd
, void* param
)
143 struct map_info
*map
= mtd
->priv
;
144 struct cfi_private
*cfi
= map
->fldrv_priv
;
145 struct cfi_pri_amdstd
*extp
= cfi
->cmdset_priv
;
146 __u8 major
= extp
->MajorVersion
;
147 __u8 minor
= extp
->MinorVersion
;
149 if (((major
<< 8) | minor
) < 0x3131) {
150 /* CFI version 1.0 => don't trust bootloc */
151 if (cfi
->id
& 0x80) {
152 printk(KERN_WARNING
"%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map
->name
, cfi
->id
);
153 extp
->TopBottom
= 3; /* top boot */
155 extp
->TopBottom
= 2; /* bottom boot */
161 static void fixup_use_write_buffers(struct mtd_info
*mtd
, void *param
)
163 struct map_info
*map
= mtd
->priv
;
164 struct cfi_private
*cfi
= map
->fldrv_priv
;
165 if (cfi
->cfiq
->BufWriteTimeoutTyp
) {
166 DEBUG(MTD_DEBUG_LEVEL1
, "Using buffer write method\n" );
167 mtd
->write
= cfi_amdstd_write_buffers
;
168 if (extp
->SiliconRevision
>= 0x1C) {
169 mtd
->writesize
= 512;
170 mtd
->flags
&= ~MTD_BIT_WRITEABLE
;
171 printk(KERN_INFO
"Enabling Spansion 65nm mode, writesize = 512 bytes\n");
176 /* Atmel chips don't use the same PRI format as AMD chips */
177 static void fixup_convert_atmel_pri(struct mtd_info
*mtd
, void *param
)
179 struct map_info
*map
= mtd
->priv
;
180 struct cfi_private
*cfi
= map
->fldrv_priv
;
181 struct cfi_pri_amdstd
*extp
= cfi
->cmdset_priv
;
182 struct cfi_pri_atmel atmel_pri
;
184 memcpy(&atmel_pri
, extp
, sizeof(atmel_pri
));
185 memset((char *)extp
+ 5, 0, sizeof(*extp
) - 5);
187 if (atmel_pri
.Features
& 0x02)
188 extp
->EraseSuspend
= 2;
190 if (atmel_pri
.BottomBoot
)
196 static void fixup_use_secsi(struct mtd_info
*mtd
, void *param
)
198 /* Setup for chips with a secsi area */
199 mtd
->read_user_prot_reg
= cfi_amdstd_secsi_read
;
200 mtd
->read_fact_prot_reg
= cfi_amdstd_secsi_read
;
203 static void fixup_use_erase_chip(struct mtd_info
*mtd
, void *param
)
205 struct map_info
*map
= mtd
->priv
;
206 struct cfi_private
*cfi
= map
->fldrv_priv
;
207 if ((cfi
->cfiq
->NumEraseRegions
== 1) &&
208 ((cfi
->cfiq
->EraseRegionInfo
[0] & 0xffff) == 0)) {
209 mtd
->erase
= cfi_amdstd_erase_chip
;
215 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
218 static void fixup_use_atmel_lock(struct mtd_info
*mtd
, void *param
)
220 mtd
->lock
= cfi_atmel_lock
;
221 mtd
->unlock
= cfi_atmel_unlock
;
222 mtd
->flags
|= MTD_STUPID_LOCK
;
225 static struct cfi_fixup cfi_fixup_table
[] = {
226 #ifdef AMD_BOOTLOC_BUG
227 { CFI_MFR_AMD
, CFI_ID_ANY
, fixup_amd_bootblock
, NULL
},
229 { CFI_MFR_AMD
, 0x0050, fixup_use_secsi
, NULL
, },
230 { CFI_MFR_AMD
, 0x0053, fixup_use_secsi
, NULL
, },
231 { CFI_MFR_AMD
, 0x0055, fixup_use_secsi
, NULL
, },
232 { CFI_MFR_AMD
, 0x0056, fixup_use_secsi
, NULL
, },
233 { CFI_MFR_AMD
, 0x005C, fixup_use_secsi
, NULL
, },
234 { CFI_MFR_AMD
, 0x005F, fixup_use_secsi
, NULL
, },
235 #if !FORCE_WORD_WRITE
236 { CFI_MFR_ANY
, CFI_ID_ANY
, fixup_use_write_buffers
, NULL
, },
238 { CFI_MFR_ATMEL
, CFI_ID_ANY
, fixup_convert_atmel_pri
, NULL
},
241 static struct cfi_fixup jedec_fixup_table
[] = {
242 { MANUFACTURER_SST
, SST49LF004B
, fixup_use_fwh_lock
, NULL
, },
243 { MANUFACTURER_SST
, SST49LF040B
, fixup_use_fwh_lock
, NULL
, },
244 { MANUFACTURER_SST
, SST49LF008A
, fixup_use_fwh_lock
, NULL
, },
248 static struct cfi_fixup fixup_table
[] = {
249 /* The CFI vendor ids and the JEDEC vendor IDs appear
250 * to be common. It is like the devices id's are as
251 * well. This table is to pick all cases where
252 * we know that is the case.
254 { CFI_MFR_ANY
, CFI_ID_ANY
, fixup_use_erase_chip
, NULL
},
255 { CFI_MFR_ATMEL
, AT49BV6416
, fixup_use_atmel_lock
, NULL
},
260 struct mtd_info
*cfi_cmdset_0002(struct map_info
*map
, int primary
)
262 struct cfi_private
*cfi
= map
->fldrv_priv
;
263 struct mtd_info
*mtd
;
266 mtd
= kzalloc(sizeof(*mtd
), GFP_KERNEL
);
268 printk(KERN_WARNING
"Failed to allocate memory for MTD device\n");
272 mtd
->type
= MTD_NORFLASH
;
274 /* Fill in the default mtd operations */
275 mtd
->erase
= cfi_amdstd_erase_varsize
;
276 mtd
->write
= cfi_amdstd_write_words
;
277 mtd
->read
= cfi_amdstd_read
;
278 mtd
->sync
= cfi_amdstd_sync
;
279 mtd
->suspend
= cfi_amdstd_suspend
;
280 mtd
->resume
= cfi_amdstd_resume
;
281 mtd
->flags
= MTD_CAP_NORFLASH
;
282 mtd
->name
= map
->name
;
285 if (cfi
->cfi_mode
==CFI_MODE_CFI
){
286 unsigned char bootloc
;
288 * It's a real CFI chip, not one for which the probe
289 * routine faked a CFI structure. So we read the feature
292 __u16 adr
= primary
?cfi
->cfiq
->P_ADR
:cfi
->cfiq
->A_ADR
;
293 struct cfi_pri_amdstd
*extp
;
295 extp
= (struct cfi_pri_amdstd
*)cfi_read_pri(map
, adr
, sizeof(*extp
), "Amd/Fujitsu");
301 if (extp
->MajorVersion
< '0' || extp
->MajorVersion
> '3' ||
302 (extp
->MinorVersion
< '0' || extp
->MinorVersion
> '5')) {
303 if (cfi
->mfr
== MANUFACTURER_SAMSUNG
&&
304 ((extp
->MajorVersion
== '3' && extp
->MinorVersion
== '3') ||
305 (extp
->MajorVersion
== '0'))) {
306 printk(KERN_NOTICE
" Newer Samsung Flash detected, "
307 "should be compatibile with Amd/Fujitsu.\n");
308 if (extp
->MajorVersion
== '0') {
312 extp
->MajorVersion
= '1';
317 printk(KERN_ERR
" Unknown Amd/Fujitsu Extended Query "
318 "version %c.%c.\n", extp
->MajorVersion
,
326 /* Install our own private info structure */
327 cfi
->cmdset_priv
= extp
;
329 /* Apply cfi device specific fixups */
330 cfi_fixup(mtd
, cfi_fixup_table
);
332 #ifdef DEBUG_CFI_FEATURES
333 /* Tell the user about it in lots of lovely detail */
334 cfi_tell_features(extp
);
337 bootloc
= extp
->TopBottom
;
338 if ((bootloc
!= 2) && (bootloc
!= 3)) {
339 printk(KERN_WARNING
"%s: CFI does not contain boot "
340 "bank location. Assuming top.\n", map
->name
);
344 if (bootloc
== 3 && cfi
->cfiq
->NumEraseRegions
> 1) {
345 printk(KERN_WARNING
"%s: Swapping erase regions for broken CFI table.\n", map
->name
);
347 for (i
=0; i
<cfi
->cfiq
->NumEraseRegions
/ 2; i
++) {
348 int j
= (cfi
->cfiq
->NumEraseRegions
-1)-i
;
351 swap
= cfi
->cfiq
->EraseRegionInfo
[i
];
352 cfi
->cfiq
->EraseRegionInfo
[i
] = cfi
->cfiq
->EraseRegionInfo
[j
];
353 cfi
->cfiq
->EraseRegionInfo
[j
] = swap
;
356 /* Set the default CFI lock/unlock addresses */
357 cfi
->addr_unlock1
= 0x555;
358 cfi
->addr_unlock2
= 0x2aa;
359 /* Modify the unlock address if we are in compatibility mode */
360 if ( /* x16 in x8 mode */
361 ((cfi
->device_type
== CFI_DEVICETYPE_X8
) &&
362 (cfi
->cfiq
->InterfaceDesc
== 2)) ||
363 /* x32 in x16 mode */
364 ((cfi
->device_type
== CFI_DEVICETYPE_X16
) &&
365 (cfi
->cfiq
->InterfaceDesc
== 4)))
367 cfi
->addr_unlock1
= 0xaaa;
368 cfi
->addr_unlock2
= 0x555;
372 else if (cfi
->cfi_mode
== CFI_MODE_JEDEC
) {
373 /* Apply jedec specific fixups */
374 cfi_fixup(mtd
, jedec_fixup_table
);
376 /* Apply generic fixups */
377 cfi_fixup(mtd
, fixup_table
);
379 for (i
=0; i
< cfi
->numchips
; i
++) {
380 cfi
->chips
[i
].word_write_time
= 1<<cfi
->cfiq
->WordWriteTimeoutTyp
;
381 cfi
->chips
[i
].buffer_write_time
= 1<<cfi
->cfiq
->BufWriteTimeoutTyp
;
382 cfi
->chips
[i
].erase_time
= 1<<cfi
->cfiq
->BlockEraseTimeoutTyp
;
383 cfi
->chips
[i
].ref_point_counter
= 0;
384 init_waitqueue_head(&(cfi
->chips
[i
].wq
));
387 map
->fldrv
= &cfi_amdstd_chipdrv
;
389 return cfi_amdstd_setup(mtd
);
391 EXPORT_SYMBOL_GPL(cfi_cmdset_0002
);
393 static struct mtd_info
*cfi_amdstd_setup(struct mtd_info
*mtd
)
395 struct map_info
*map
= mtd
->priv
;
396 struct cfi_private
*cfi
= map
->fldrv_priv
;
397 unsigned long devsize
= (1<<cfi
->cfiq
->DevSize
) * cfi
->interleave
;
398 unsigned long offset
= 0;
401 printk(KERN_NOTICE
"number of %s chips: %d\n",
402 (cfi
->cfi_mode
== CFI_MODE_CFI
)?"CFI":"JEDEC",cfi
->numchips
);
403 /* Select the correct geometry setup */
404 mtd
->size
= devsize
* cfi
->numchips
;
406 mtd
->numeraseregions
= cfi
->cfiq
->NumEraseRegions
* cfi
->numchips
;
407 mtd
->eraseregions
= kmalloc(sizeof(struct mtd_erase_region_info
)
408 * mtd
->numeraseregions
, GFP_KERNEL
);
409 if (!mtd
->eraseregions
) {
410 printk(KERN_WARNING
"Failed to allocate memory for MTD erase region info\n");
414 for (i
=0; i
<cfi
->cfiq
->NumEraseRegions
; i
++) {
415 unsigned long ernum
, ersize
;
416 ersize
= ((cfi
->cfiq
->EraseRegionInfo
[i
] >> 8) & ~0xff) * cfi
->interleave
;
417 ernum
= (cfi
->cfiq
->EraseRegionInfo
[i
] & 0xffff) + 1;
419 if (mtd
->erasesize
< ersize
) {
420 mtd
->erasesize
= ersize
;
422 for (j
=0; j
<cfi
->numchips
; j
++) {
423 mtd
->eraseregions
[(j
*cfi
->cfiq
->NumEraseRegions
)+i
].offset
= (j
*devsize
)+offset
;
424 mtd
->eraseregions
[(j
*cfi
->cfiq
->NumEraseRegions
)+i
].erasesize
= ersize
;
425 mtd
->eraseregions
[(j
*cfi
->cfiq
->NumEraseRegions
)+i
].numblocks
= ernum
;
427 offset
+= (ersize
* ernum
);
429 if (offset
!= devsize
) {
431 printk(KERN_WARNING
"Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset
, devsize
);
436 for (i
=0; i
<mtd
->numeraseregions
;i
++){
437 printk("%d: offset=0x%x,size=0x%x,blocks=%d\n",
438 i
,mtd
->eraseregions
[i
].offset
,
439 mtd
->eraseregions
[i
].erasesize
,
440 mtd
->eraseregions
[i
].numblocks
);
444 /* FIXME: erase-suspend-program is broken. See
445 http://lists.infradead.org/pipermail/linux-mtd/2003-December/009001.html */
446 printk(KERN_NOTICE
"cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.\n");
448 __module_get(THIS_MODULE
);
453 kfree(mtd
->eraseregions
);
456 kfree(cfi
->cmdset_priv
);
462 * Return true if the chip is ready.
464 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
465 * non-suspended sector) and is indicated by no toggle bits toggling.
467 * Note that anything more complicated than checking if no bits are toggling
468 * (including checking DQ5 for an error status) is tricky to get working
469 * correctly and is therefore not done (particulary with interleaved chips
470 * as each chip must be checked independantly of the others).
472 static int __xipram
chip_ready(struct map_info
*map
, unsigned long addr
)
476 d
= map_read(map
, addr
);
477 t
= map_read(map
, addr
);
479 return map_word_equal(map
, d
, t
);
483 * Return true if the chip is ready and has the correct value.
485 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
486 * non-suspended sector) and it is indicated by no bits toggling.
488 * Error are indicated by toggling bits or bits held with the wrong value,
489 * or with bits toggling.
491 * Note that anything more complicated than checking if no bits are toggling
492 * (including checking DQ5 for an error status) is tricky to get working
493 * correctly and is therefore not done (particulary with interleaved chips
494 * as each chip must be checked independantly of the others).
497 static int __xipram
chip_good(struct map_info
*map
, unsigned long addr
, map_word expected
)
501 oldd
= map_read(map
, addr
);
502 curd
= map_read(map
, addr
);
504 return map_word_equal(map
, oldd
, curd
) &&
505 map_word_equal(map
, curd
, expected
);
508 static int get_chip(struct map_info
*map
, struct flchip
*chip
, unsigned long adr
, int mode
)
510 DECLARE_WAITQUEUE(wait
, current
);
511 struct cfi_private
*cfi
= map
->fldrv_priv
;
513 struct cfi_pri_amdstd
*cfip
= (struct cfi_pri_amdstd
*)cfi
->cmdset_priv
;
516 timeo
= jiffies
+ HZ
;
518 switch (chip
->state
) {
522 if (chip_ready(map
, adr
))
525 if (time_after(jiffies
, timeo
)) {
526 printk(KERN_ERR
"Waiting for chip to be ready timed out.\n");
527 spin_unlock(chip
->mutex
);
530 spin_unlock(chip
->mutex
);
532 spin_lock(chip
->mutex
);
533 /* Someone else might have been playing with it. */
543 if (mode
== FL_WRITING
) /* FIXME: Erase-suspend-program appears broken. */
546 if (!( mode
== FL_READY
549 || (mode
== FL_WRITING
&& (cfip
->EraseSuspend
& 0x2))
550 || (mode
== FL_WRITING
&& (cfip
->EraseSuspend
& 0x1)
554 /* We could check to see if we're trying to access the sector
555 * that is currently being erased. However, no user will try
556 * anything like that so we just wait for the timeout. */
559 /* It's harmless to issue the Erase-Suspend and Erase-Resume
560 * commands when the erase algorithm isn't in progress. */
561 map_write(map
, CMD(0xB0), chip
->in_progress_block_addr
);
562 chip
->oldstate
= FL_ERASING
;
563 chip
->state
= FL_ERASE_SUSPENDING
;
564 chip
->erase_suspended
= 1;
566 if (chip_ready(map
, adr
))
569 if (time_after(jiffies
, timeo
)) {
570 /* Should have suspended the erase by now.
571 * Send an Erase-Resume command as either
572 * there was an error (so leave the erase
573 * routine to recover from it) or we trying to
574 * use the erase-in-progress sector. */
575 put_chip(map
, chip
, adr
);
576 printk(KERN_ERR
"MTD %s(): chip not ready after erase suspend\n", __func__
);
580 spin_unlock(chip
->mutex
);
582 spin_lock(chip
->mutex
);
583 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
584 So we can just loop here. */
586 chip
->state
= FL_READY
;
589 case FL_XIP_WHILE_ERASING
:
590 if (mode
!= FL_READY
&& mode
!= FL_POINT
&&
591 (!cfip
|| !(cfip
->EraseSuspend
&2)))
593 chip
->oldstate
= chip
->state
;
594 chip
->state
= FL_READY
;
598 /* Only if there's no operation suspended... */
599 if (mode
== FL_READY
&& chip
->oldstate
== FL_READY
)
604 set_current_state(TASK_UNINTERRUPTIBLE
);
605 add_wait_queue(&chip
->wq
, &wait
);
606 spin_unlock(chip
->mutex
);
608 remove_wait_queue(&chip
->wq
, &wait
);
609 spin_lock(chip
->mutex
);
615 static void put_chip(struct map_info
*map
, struct flchip
*chip
, unsigned long adr
)
617 struct cfi_private
*cfi
= map
->fldrv_priv
;
619 switch(chip
->oldstate
) {
621 map_write(map
, CMD(0x30), chip
->in_progress_block_addr
);
622 chip
->oldstate
= FL_READY
;
623 chip
->state
= FL_ERASING
;
626 case FL_XIP_WHILE_ERASING
:
627 chip
->state
= chip
->oldstate
;
628 chip
->oldstate
= FL_READY
;
633 /* We should really make set_vpp() count, rather than doing this */
637 printk(KERN_ERR
"MTD: put_chip() called with oldstate %d!!\n", chip
->oldstate
);
642 #ifdef CONFIG_MTD_XIP
645 * No interrupt what so ever can be serviced while the flash isn't in array
646 * mode. This is ensured by the xip_disable() and xip_enable() functions
647 * enclosing any code path where the flash is known not to be in array mode.
648 * And within a XIP disabled code path, only functions marked with __xipram
649 * may be called and nothing else (it's a good thing to inspect generated
650 * assembly to make sure inline functions were actually inlined and that gcc
651 * didn't emit calls to its own support functions). Also configuring MTD CFI
652 * support to a single buswidth and a single interleave is also recommended.
655 static void xip_disable(struct map_info
*map
, struct flchip
*chip
,
658 /* TODO: chips with no XIP use should ignore and return */
659 (void) map_read(map
, adr
); /* ensure mmu mapping is up to date */
663 static void __xipram
xip_enable(struct map_info
*map
, struct flchip
*chip
,
666 struct cfi_private
*cfi
= map
->fldrv_priv
;
668 if (chip
->state
!= FL_POINT
&& chip
->state
!= FL_READY
) {
669 map_write(map
, CMD(0xf0), adr
);
670 chip
->state
= FL_READY
;
672 (void) map_read(map
, adr
);
678 * When a delay is required for the flash operation to complete, the
679 * xip_udelay() function is polling for both the given timeout and pending
680 * (but still masked) hardware interrupts. Whenever there is an interrupt
681 * pending then the flash erase operation is suspended, array mode restored
682 * and interrupts unmasked. Task scheduling might also happen at that
683 * point. The CPU eventually returns from the interrupt or the call to
684 * schedule() and the suspended flash operation is resumed for the remaining
685 * of the delay period.
687 * Warning: this function _will_ fool interrupt latency tracing tools.
690 static void __xipram
xip_udelay(struct map_info
*map
, struct flchip
*chip
,
691 unsigned long adr
, int usec
)
693 struct cfi_private
*cfi
= map
->fldrv_priv
;
694 struct cfi_pri_amdstd
*extp
= cfi
->cmdset_priv
;
695 map_word status
, OK
= CMD(0x80);
696 unsigned long suspended
, start
= xip_currtime();
701 if (xip_irqpending() && extp
&&
702 ((chip
->state
== FL_ERASING
&& (extp
->EraseSuspend
& 2))) &&
703 (cfi_interleave_is_1(cfi
) || chip
->oldstate
== FL_READY
)) {
705 * Let's suspend the erase operation when supported.
706 * Note that we currently don't try to suspend
707 * interleaved chips if there is already another
708 * operation suspended (imagine what happens
709 * when one chip was already done with the current
710 * operation while another chip suspended it, then
711 * we resume the whole thing at once). Yes, it
714 map_write(map
, CMD(0xb0), adr
);
715 usec
-= xip_elapsed_since(start
);
716 suspended
= xip_currtime();
718 if (xip_elapsed_since(suspended
) > 100000) {
720 * The chip doesn't want to suspend
721 * after waiting for 100 msecs.
722 * This is a critical error but there
723 * is not much we can do here.
727 status
= map_read(map
, adr
);
728 } while (!map_word_andequal(map
, status
, OK
, OK
));
730 /* Suspend succeeded */
731 oldstate
= chip
->state
;
732 if (!map_word_bitsset(map
, status
, CMD(0x40)))
734 chip
->state
= FL_XIP_WHILE_ERASING
;
735 chip
->erase_suspended
= 1;
736 map_write(map
, CMD(0xf0), adr
);
737 (void) map_read(map
, adr
);
738 asm volatile (".rep 8; nop; .endr");
740 spin_unlock(chip
->mutex
);
741 asm volatile (".rep 8; nop; .endr");
745 * We're back. However someone else might have
746 * decided to go write to the chip if we are in
747 * a suspended erase state. If so let's wait
750 spin_lock(chip
->mutex
);
751 while (chip
->state
!= FL_XIP_WHILE_ERASING
) {
752 DECLARE_WAITQUEUE(wait
, current
);
753 set_current_state(TASK_UNINTERRUPTIBLE
);
754 add_wait_queue(&chip
->wq
, &wait
);
755 spin_unlock(chip
->mutex
);
757 remove_wait_queue(&chip
->wq
, &wait
);
758 spin_lock(chip
->mutex
);
760 /* Disallow XIP again */
763 /* Resume the write or erase operation */
764 map_write(map
, CMD(0x30), adr
);
765 chip
->state
= oldstate
;
766 start
= xip_currtime();
767 } else if (usec
>= 1000000/HZ
) {
769 * Try to save on CPU power when waiting delay
770 * is at least a system timer tick period.
771 * No need to be extremely accurate here.
775 status
= map_read(map
, adr
);
776 } while (!map_word_andequal(map
, status
, OK
, OK
)
777 && xip_elapsed_since(start
) < usec
);
780 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
783 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
784 * the flash is actively programming or erasing since we have to poll for
785 * the operation to complete anyway. We can't do that in a generic way with
786 * a XIP setup so do it before the actual flash operation in this case
787 * and stub it out from INVALIDATE_CACHE_UDELAY.
789 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
790 INVALIDATE_CACHED_RANGE(map, from, size)
792 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
793 UDELAY(map, chip, adr, usec)
798 * Activating this XIP support changes the way the code works a bit. For
799 * example the code to suspend the current process when concurrent access
800 * happens is never executed because xip_udelay() will always return with the
801 * same chip state as it was entered with. This is why there is no care for
802 * the presence of add_wait_queue() or schedule() calls from within a couple
803 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
804 * The queueing and scheduling are always happening within xip_udelay().
806 * Similarly, get_chip() and put_chip() just happen to always be executed
807 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
808 * is in array mode, therefore never executing many cases therein and not
809 * causing any problem with XIP.
814 #define xip_disable(map, chip, adr)
815 #define xip_enable(map, chip, adr)
816 #define XIP_INVAL_CACHED_RANGE(x...)
818 #define UDELAY(map, chip, adr, usec) \
820 spin_unlock(chip->mutex); \
822 spin_lock(chip->mutex); \
825 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
827 spin_unlock(chip->mutex); \
828 INVALIDATE_CACHED_RANGE(map, adr, len); \
830 spin_lock(chip->mutex); \
835 static inline int do_read_onechip(struct map_info
*map
, struct flchip
*chip
, loff_t adr
, size_t len
, u_char
*buf
)
837 unsigned long cmd_addr
;
838 struct cfi_private
*cfi
= map
->fldrv_priv
;
843 /* Ensure cmd read/writes are aligned. */
844 cmd_addr
= adr
& ~(map_bankwidth(map
)-1);
846 spin_lock(chip
->mutex
);
847 ret
= get_chip(map
, chip
, cmd_addr
, FL_READY
);
849 spin_unlock(chip
->mutex
);
853 if (chip
->state
!= FL_POINT
&& chip
->state
!= FL_READY
) {
854 map_write(map
, CMD(0xf0), cmd_addr
);
855 chip
->state
= FL_READY
;
858 map_copy_from(map
, buf
, adr
, len
);
860 put_chip(map
, chip
, cmd_addr
);
862 spin_unlock(chip
->mutex
);
867 static int cfi_amdstd_read (struct mtd_info
*mtd
, loff_t from
, size_t len
, size_t *retlen
, u_char
*buf
)
869 struct map_info
*map
= mtd
->priv
;
870 struct cfi_private
*cfi
= map
->fldrv_priv
;
875 /* ofs: offset within the first chip that the first read should start */
877 chipnum
= (from
>> cfi
->chipshift
);
878 ofs
= from
- (chipnum
<< cfi
->chipshift
);
884 unsigned long thislen
;
886 if (chipnum
>= cfi
->numchips
)
889 if ((len
+ ofs
-1) >> cfi
->chipshift
)
890 thislen
= (1<<cfi
->chipshift
) - ofs
;
894 ret
= do_read_onechip(map
, &cfi
->chips
[chipnum
], ofs
, thislen
, buf
);
909 static inline int do_read_secsi_onechip(struct map_info
*map
, struct flchip
*chip
, loff_t adr
, size_t len
, u_char
*buf
)
911 DECLARE_WAITQUEUE(wait
, current
);
912 unsigned long timeo
= jiffies
+ HZ
;
913 struct cfi_private
*cfi
= map
->fldrv_priv
;
916 spin_lock(chip
->mutex
);
918 if (chip
->state
!= FL_READY
){
920 printk(KERN_DEBUG
"Waiting for chip to read, status = %d\n", chip
->state
);
922 set_current_state(TASK_UNINTERRUPTIBLE
);
923 add_wait_queue(&chip
->wq
, &wait
);
925 spin_unlock(chip
->mutex
);
928 remove_wait_queue(&chip
->wq
, &wait
);
930 if(signal_pending(current
))
933 timeo
= jiffies
+ HZ
;
940 chip
->state
= FL_READY
;
942 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
943 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
944 cfi_send_gen_cmd(0x88, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
946 map_copy_from(map
, buf
, adr
, len
);
948 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
949 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
950 cfi_send_gen_cmd(0x90, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
951 cfi_send_gen_cmd(0x00, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
954 spin_unlock(chip
->mutex
);
959 static int cfi_amdstd_secsi_read (struct mtd_info
*mtd
, loff_t from
, size_t len
, size_t *retlen
, u_char
*buf
)
961 struct map_info
*map
= mtd
->priv
;
962 struct cfi_private
*cfi
= map
->fldrv_priv
;
968 /* ofs: offset within the first chip that the first read should start */
970 /* 8 secsi bytes per chip */
978 unsigned long thislen
;
980 if (chipnum
>= cfi
->numchips
)
983 if ((len
+ ofs
-1) >> 3)
984 thislen
= (1<<3) - ofs
;
988 ret
= do_read_secsi_onechip(map
, &cfi
->chips
[chipnum
], ofs
, thislen
, buf
);
1003 static int __xipram
do_write_oneword(struct map_info
*map
, struct flchip
*chip
, unsigned long adr
, map_word datum
)
1005 struct cfi_private
*cfi
= map
->fldrv_priv
;
1006 unsigned long timeo
= jiffies
+ HZ
;
1008 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
1009 * have a max write time of a few hundreds usec). However, we should
1010 * use the maximum timeout value given by the chip at probe time
1011 * instead. Unfortunately, struct flchip does have a field for
1012 * maximum timeout, only for typical which can be far too short
1013 * depending of the conditions. The ' + 1' is to avoid having a
1014 * timeout of 0 jiffies if HZ is smaller than 1000.
1016 unsigned long uWriteTimeout
= ( HZ
/ 1000 ) + 1;
1023 spin_lock(chip
->mutex
);
1024 ret
= get_chip(map
, chip
, adr
, FL_WRITING
);
1026 spin_unlock(chip
->mutex
);
1030 DEBUG( MTD_DEBUG_LEVEL3
, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1031 __func__
, adr
, datum
.x
[0] );
1034 * Check for a NOP for the case when the datum to write is already
1035 * present - it saves time and works around buggy chips that corrupt
1036 * data at other locations when 0xff is written to a location that
1037 * already contains 0xff.
1039 oldd
= map_read(map
, adr
);
1040 if (map_word_equal(map
, oldd
, datum
)) {
1041 DEBUG( MTD_DEBUG_LEVEL3
, "MTD %s(): NOP\n",
1046 XIP_INVAL_CACHED_RANGE(map
, adr
, map_bankwidth(map
));
1048 xip_disable(map
, chip
, adr
);
1050 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1051 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1052 cfi_send_gen_cmd(0xA0, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1053 map_write(map
, datum
, adr
);
1054 chip
->state
= FL_WRITING
;
1056 INVALIDATE_CACHE_UDELAY(map
, chip
,
1057 adr
, map_bankwidth(map
),
1058 chip
->word_write_time
);
1060 /* See comment above for timeout value. */
1061 timeo
= jiffies
+ uWriteTimeout
;
1063 if (chip
->state
!= FL_WRITING
) {
1064 /* Someone's suspended the write. Sleep */
1065 DECLARE_WAITQUEUE(wait
, current
);
1067 set_current_state(TASK_UNINTERRUPTIBLE
);
1068 add_wait_queue(&chip
->wq
, &wait
);
1069 spin_unlock(chip
->mutex
);
1071 remove_wait_queue(&chip
->wq
, &wait
);
1072 timeo
= jiffies
+ (HZ
/ 2); /* FIXME */
1073 spin_lock(chip
->mutex
);
1077 if (time_after(jiffies
, timeo
) && !chip_ready(map
, adr
)){
1078 xip_enable(map
, chip
, adr
);
1079 printk(KERN_WARNING
"MTD %s(): software timeout\n", __func__
);
1080 xip_disable(map
, chip
, adr
);
1084 if (chip_ready(map
, adr
))
1087 /* Latency issues. Drop the lock, wait a while and retry */
1088 UDELAY(map
, chip
, adr
, 1);
1090 /* Did we succeed? */
1091 if (!chip_good(map
, adr
, datum
)) {
1092 /* reset on all failures. */
1093 map_write( map
, CMD(0xF0), chip
->start
);
1094 /* FIXME - should have reset delay before continuing */
1096 if (++retry_cnt
<= MAX_WORD_RETRIES
)
1101 xip_enable(map
, chip
, adr
);
1103 chip
->state
= FL_READY
;
1104 put_chip(map
, chip
, adr
);
1105 spin_unlock(chip
->mutex
);
1111 static int cfi_amdstd_write_words(struct mtd_info
*mtd
, loff_t to
, size_t len
,
1112 size_t *retlen
, const u_char
*buf
)
1114 struct map_info
*map
= mtd
->priv
;
1115 struct cfi_private
*cfi
= map
->fldrv_priv
;
1118 unsigned long ofs
, chipstart
;
1119 DECLARE_WAITQUEUE(wait
, current
);
1125 chipnum
= to
>> cfi
->chipshift
;
1126 ofs
= to
- (chipnum
<< cfi
->chipshift
);
1127 chipstart
= cfi
->chips
[chipnum
].start
;
1129 /* If it's not bus-aligned, do the first byte write */
1130 if (ofs
& (map_bankwidth(map
)-1)) {
1131 unsigned long bus_ofs
= ofs
& ~(map_bankwidth(map
)-1);
1132 int i
= ofs
- bus_ofs
;
1137 spin_lock(cfi
->chips
[chipnum
].mutex
);
1139 if (cfi
->chips
[chipnum
].state
!= FL_READY
) {
1141 printk(KERN_DEBUG
"Waiting for chip to write, status = %d\n", cfi
->chips
[chipnum
].state
);
1143 set_current_state(TASK_UNINTERRUPTIBLE
);
1144 add_wait_queue(&cfi
->chips
[chipnum
].wq
, &wait
);
1146 spin_unlock(cfi
->chips
[chipnum
].mutex
);
1149 remove_wait_queue(&cfi
->chips
[chipnum
].wq
, &wait
);
1151 if(signal_pending(current
))
1157 /* Load 'tmp_buf' with old contents of flash */
1158 tmp_buf
= map_read(map
, bus_ofs
+chipstart
);
1160 spin_unlock(cfi
->chips
[chipnum
].mutex
);
1162 /* Number of bytes to copy from buffer */
1163 n
= min_t(int, len
, map_bankwidth(map
)-i
);
1165 tmp_buf
= map_word_load_partial(map
, tmp_buf
, buf
, i
, n
);
1167 ret
= do_write_oneword(map
, &cfi
->chips
[chipnum
],
1177 if (ofs
>> cfi
->chipshift
) {
1180 if (chipnum
== cfi
->numchips
)
1185 /* We are now aligned, write as much as possible */
1186 while(len
>= map_bankwidth(map
)) {
1189 datum
= map_word_load(map
, buf
);
1191 ret
= do_write_oneword(map
, &cfi
->chips
[chipnum
],
1196 ofs
+= map_bankwidth(map
);
1197 buf
+= map_bankwidth(map
);
1198 (*retlen
) += map_bankwidth(map
);
1199 len
-= map_bankwidth(map
);
1201 if (ofs
>> cfi
->chipshift
) {
1204 if (chipnum
== cfi
->numchips
)
1206 chipstart
= cfi
->chips
[chipnum
].start
;
1210 /* Write the trailing bytes if any */
1211 if (len
& (map_bankwidth(map
)-1)) {
1215 spin_lock(cfi
->chips
[chipnum
].mutex
);
1217 if (cfi
->chips
[chipnum
].state
!= FL_READY
) {
1219 printk(KERN_DEBUG
"Waiting for chip to write, status = %d\n", cfi
->chips
[chipnum
].state
);
1221 set_current_state(TASK_UNINTERRUPTIBLE
);
1222 add_wait_queue(&cfi
->chips
[chipnum
].wq
, &wait
);
1224 spin_unlock(cfi
->chips
[chipnum
].mutex
);
1227 remove_wait_queue(&cfi
->chips
[chipnum
].wq
, &wait
);
1229 if(signal_pending(current
))
1235 tmp_buf
= map_read(map
, ofs
+ chipstart
);
1237 spin_unlock(cfi
->chips
[chipnum
].mutex
);
1239 tmp_buf
= map_word_load_partial(map
, tmp_buf
, buf
, 0, len
);
1241 ret
= do_write_oneword(map
, &cfi
->chips
[chipnum
],
1252 static int __xipram
do_write_buffer(struct map_info
*map
, struct flchip
*chip
,
1253 unsigned long adr
, const u_char
*buf
,
1256 struct cfi_private
*cfi
= map
->fldrv_priv
;
1257 unsigned long timeo
= jiffies
+ HZ
;
1258 /* see comments in do_write_oneword() regarding uWriteTimeout, 20ms */
1259 unsigned long uWriteTimeout
= ( HZ
/ 50 ) + 1;
1261 unsigned long cmd_adr
;
1262 int z
, words
, prolog
, epilog
, buflen
= len
;
1263 map_word datum
, pdat
, edat
;
1268 spin_lock(chip
->mutex
);
1269 ret
= get_chip(map
, chip
, adr
, FL_WRITING
);
1271 spin_unlock(chip
->mutex
);
1275 datum
= map_word_load(map
, buf
);
1277 DEBUG( MTD_DEBUG_LEVEL3
, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1278 __func__
, adr
, datum
.x
[0] );
1280 XIP_INVAL_CACHED_RANGE(map
, adr
, len
);
1282 xip_disable(map
, chip
, cmd_adr
);
1283 /* If start is not bus-aligned, prepend old contents of flash */
1284 prolog
= (adr
& (map_bankwidth(map
)-1));
1289 pdat
= map_read(map
, adr
);
1291 /* If end is not bus-aligned, append old contents of flash */
1292 epilog
= ((adr
+ len
) & (map_bankwidth(map
)-1));
1294 len
+= map_bankwidth(map
)-epilog
;
1295 edat
= map_read(map
, adr
+ len
- map_bankwidth(map
));
1298 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1299 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1300 //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1302 /* Write Buffer Load */
1303 map_write(map
, CMD(0x25), cmd_adr
);
1304 (void) map_read(map
, cmd_adr
);
1306 chip
->state
= FL_WRITING_TO_BUFFER
;
1308 /* Write length of data to come */
1309 words
= len
/ map_bankwidth(map
);
1310 map_write(map
, CMD(words
- 1), cmd_adr
);
1314 datum
= map_word_load_partial(map
, pdat
, buf
, prolog
,
1315 min_t(int, buflen
, map_bankwidth(map
) - prolog
));
1316 map_write(map
, datum
, adr
);
1318 z
+= map_bankwidth(map
);
1319 buf
+= map_bankwidth(map
) - prolog
;
1321 while(z
< words
* map_bankwidth(map
)) {
1322 if (epilog
&& z
>= (words
-1) * map_bankwidth(map
))
1323 datum
= map_word_load_partial(map
, edat
, buf
, 0, epilog
);
1325 datum
= map_word_load(map
, buf
);
1326 map_write(map
, datum
, adr
+ z
);
1328 z
+= map_bankwidth(map
);
1329 buf
+= map_bankwidth(map
);
1331 z
-= map_bankwidth(map
);
1335 /* Write Buffer Program Confirm: GO GO GO */
1336 map_write(map
, CMD(0x29), cmd_adr
);
1337 chip
->state
= FL_WRITING
;
1339 INVALIDATE_CACHE_UDELAY(map
, chip
,
1340 adr
, map_bankwidth(map
),
1341 chip
->word_write_time
);
1343 timeo
= jiffies
+ uWriteTimeout
;
1346 if (chip
->state
!= FL_WRITING
) {
1347 /* Someone's suspended the write. Sleep */
1348 DECLARE_WAITQUEUE(wait
, current
);
1350 set_current_state(TASK_UNINTERRUPTIBLE
);
1351 add_wait_queue(&chip
->wq
, &wait
);
1352 spin_unlock(chip
->mutex
);
1354 remove_wait_queue(&chip
->wq
, &wait
);
1355 timeo
= jiffies
+ (HZ
/ 2); /* FIXME */
1356 spin_lock(chip
->mutex
);
1360 if (time_after(jiffies
, timeo
) && !chip_ready(map
, adr
))
1363 if (chip_ready(map
, adr
)) {
1364 xip_enable(map
, chip
, adr
);
1368 /* Latency issues. Drop the lock, wait a while and retry */
1369 UDELAY(map
, chip
, adr
, 1);
1372 /* reset on all failures. */
1373 map_write( map
, CMD(0xF0), chip
->start
);
1374 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1375 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1376 cfi_send_gen_cmd(0xF0, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1377 xip_enable(map
, chip
, adr
);
1379 printk(KERN_WARNING
"MTD %s(): software timeout\n",
1384 chip
->state
= FL_READY
;
1385 put_chip(map
, chip
, adr
);
1386 spin_unlock(chip
->mutex
);
1392 static int cfi_amdstd_write_buffers(struct mtd_info
*mtd
, loff_t to
, size_t len
,
1393 size_t *retlen
, const u_char
*buf
)
1395 struct map_info
*map
= mtd
->priv
;
1396 struct cfi_private
*cfi
= map
->fldrv_priv
;
1397 int wbufsize
= cfi_interleave(cfi
) << cfi
->cfiq
->MaxBufWriteSize
;
1406 chipnum
= to
>> cfi
->chipshift
;
1407 ofs
= to
- (chipnum
<< cfi
->chipshift
);
1410 /* We must not cross write block boundaries */
1411 int size
= wbufsize
- (ofs
& (wbufsize
-1));
1416 ret
= do_write_buffer(map
, &cfi
->chips
[chipnum
],
1426 if (ofs
>> cfi
->chipshift
) {
1429 if (chipnum
== cfi
->numchips
)
1439 * Handle devices with one erase region, that only implement
1440 * the chip erase command.
1442 static int __xipram
do_erase_chip(struct map_info
*map
, struct flchip
*chip
)
1444 struct cfi_private
*cfi
= map
->fldrv_priv
;
1445 unsigned long timeo
= jiffies
+ HZ
;
1446 unsigned long int adr
;
1447 DECLARE_WAITQUEUE(wait
, current
);
1450 adr
= cfi
->addr_unlock1
;
1452 spin_lock(chip
->mutex
);
1453 ret
= get_chip(map
, chip
, adr
, FL_WRITING
);
1455 spin_unlock(chip
->mutex
);
1459 DEBUG( MTD_DEBUG_LEVEL3
, "MTD %s(): ERASE 0x%.8lx\n",
1460 __func__
, chip
->start
);
1462 XIP_INVAL_CACHED_RANGE(map
, adr
, map
->size
);
1464 xip_disable(map
, chip
, adr
);
1466 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1467 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1468 cfi_send_gen_cmd(0x80, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1469 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1470 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1471 cfi_send_gen_cmd(0x10, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1473 chip
->state
= FL_ERASING
;
1474 chip
->erase_suspended
= 0;
1475 chip
->in_progress_block_addr
= adr
;
1477 INVALIDATE_CACHE_UDELAY(map
, chip
,
1479 chip
->erase_time
*500);
1481 timeo
= jiffies
+ (HZ
*20);
1484 if (chip
->state
!= FL_ERASING
) {
1485 /* Someone's suspended the erase. Sleep */
1486 set_current_state(TASK_UNINTERRUPTIBLE
);
1487 add_wait_queue(&chip
->wq
, &wait
);
1488 spin_unlock(chip
->mutex
);
1490 remove_wait_queue(&chip
->wq
, &wait
);
1491 spin_lock(chip
->mutex
);
1494 if (chip
->erase_suspended
) {
1495 /* This erase was suspended and resumed.
1496 Adjust the timeout */
1497 timeo
= jiffies
+ (HZ
*20); /* FIXME */
1498 chip
->erase_suspended
= 0;
1501 if (chip_ready(map
, adr
))
1504 if (time_after(jiffies
, timeo
)) {
1505 printk(KERN_WARNING
"MTD %s(): software timeout\n",
1510 /* Latency issues. Drop the lock, wait a while and retry */
1511 UDELAY(map
, chip
, adr
, 1000000/HZ
);
1513 /* Did we succeed? */
1514 if (!chip_good(map
, adr
, map_word_ff(map
))) {
1515 /* reset on all failures. */
1516 map_write( map
, CMD(0xF0), chip
->start
);
1517 /* FIXME - should have reset delay before continuing */
1522 chip
->state
= FL_READY
;
1523 xip_enable(map
, chip
, adr
);
1524 put_chip(map
, chip
, adr
);
1525 spin_unlock(chip
->mutex
);
1531 static int __xipram
do_erase_oneblock(struct map_info
*map
, struct flchip
*chip
, unsigned long adr
, int len
, void *thunk
)
1533 struct cfi_private
*cfi
= map
->fldrv_priv
;
1534 unsigned long timeo
= jiffies
+ HZ
;
1535 DECLARE_WAITQUEUE(wait
, current
);
1540 spin_lock(chip
->mutex
);
1541 ret
= get_chip(map
, chip
, adr
, FL_ERASING
);
1543 spin_unlock(chip
->mutex
);
1547 DEBUG( MTD_DEBUG_LEVEL3
, "MTD %s(): ERASE 0x%.8lx\n",
1550 XIP_INVAL_CACHED_RANGE(map
, adr
, len
);
1552 xip_disable(map
, chip
, adr
);
1554 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1555 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1556 cfi_send_gen_cmd(0x80, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1557 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1558 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1559 map_write(map
, CMD(0x30), adr
);
1561 chip
->state
= FL_ERASING
;
1562 chip
->erase_suspended
= 0;
1563 chip
->in_progress_block_addr
= adr
;
1565 INVALIDATE_CACHE_UDELAY(map
, chip
,
1567 chip
->erase_time
*500);
1569 timeo
= jiffies
+ (HZ
*20);
1572 if (chip
->state
!= FL_ERASING
) {
1573 /* Someone's suspended the erase. Sleep */
1574 set_current_state(TASK_UNINTERRUPTIBLE
);
1575 add_wait_queue(&chip
->wq
, &wait
);
1576 spin_unlock(chip
->mutex
);
1578 remove_wait_queue(&chip
->wq
, &wait
);
1579 spin_lock(chip
->mutex
);
1582 if (chip
->erase_suspended
) {
1583 /* This erase was suspended and resumed.
1584 Adjust the timeout */
1585 timeo
= jiffies
+ (HZ
*20); /* FIXME */
1586 chip
->erase_suspended
= 0;
1589 if (chip_ready(map
, adr
)) {
1590 xip_enable(map
, chip
, adr
);
1594 if (time_after(jiffies
, timeo
)) {
1595 xip_enable(map
, chip
, adr
);
1596 printk(KERN_WARNING
"MTD %s(): software timeout\n",
1601 /* Latency issues. Drop the lock, wait a while and retry */
1602 UDELAY(map
, chip
, adr
, 1000000/HZ
);
1604 /* Did we succeed? */
1605 if (!chip_good(map
, adr
, map_word_ff(map
))) {
1606 /* reset on all failures. */
1607 map_write( map
, CMD(0xF0), chip
->start
);
1608 /* FIXME - should have reset delay before continuing */
1613 chip
->state
= FL_READY
;
1614 put_chip(map
, chip
, adr
);
1615 spin_unlock(chip
->mutex
);
1620 int cfi_amdstd_erase_varsize(struct mtd_info
*mtd
, struct erase_info
*instr
)
1622 unsigned long ofs
, len
;
1628 ret
= cfi_varsize_frob(mtd
, do_erase_oneblock
, ofs
, len
, NULL
);
1632 instr
->state
= MTD_ERASE_DONE
;
1633 mtd_erase_callback(instr
);
1639 static int cfi_amdstd_erase_chip(struct mtd_info
*mtd
, struct erase_info
*instr
)
1641 struct map_info
*map
= mtd
->priv
;
1642 struct cfi_private
*cfi
= map
->fldrv_priv
;
1645 if (instr
->addr
!= 0)
1648 if (instr
->len
!= mtd
->size
)
1651 ret
= do_erase_chip(map
, &cfi
->chips
[0]);
1655 instr
->state
= MTD_ERASE_DONE
;
1656 mtd_erase_callback(instr
);
1661 static int do_atmel_lock(struct map_info
*map
, struct flchip
*chip
,
1662 unsigned long adr
, int len
, void *thunk
)
1664 struct cfi_private
*cfi
= map
->fldrv_priv
;
1667 spin_lock(chip
->mutex
);
1668 ret
= get_chip(map
, chip
, adr
+ chip
->start
, FL_LOCKING
);
1671 chip
->state
= FL_LOCKING
;
1673 DEBUG(MTD_DEBUG_LEVEL3
, "MTD %s(): LOCK 0x%08lx len %d\n",
1674 __func__
, adr
, len
);
1676 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
,
1677 cfi
->device_type
, NULL
);
1678 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
,
1679 cfi
->device_type
, NULL
);
1680 cfi_send_gen_cmd(0x80, cfi
->addr_unlock1
, chip
->start
, map
, cfi
,
1681 cfi
->device_type
, NULL
);
1682 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
,
1683 cfi
->device_type
, NULL
);
1684 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
,
1685 cfi
->device_type
, NULL
);
1686 map_write(map
, CMD(0x40), chip
->start
+ adr
);
1688 chip
->state
= FL_READY
;
1689 put_chip(map
, chip
, adr
+ chip
->start
);
1693 spin_unlock(chip
->mutex
);
1697 static int do_atmel_unlock(struct map_info
*map
, struct flchip
*chip
,
1698 unsigned long adr
, int len
, void *thunk
)
1700 struct cfi_private
*cfi
= map
->fldrv_priv
;
1703 spin_lock(chip
->mutex
);
1704 ret
= get_chip(map
, chip
, adr
+ chip
->start
, FL_UNLOCKING
);
1707 chip
->state
= FL_UNLOCKING
;
1709 DEBUG(MTD_DEBUG_LEVEL3
, "MTD %s(): LOCK 0x%08lx len %d\n",
1710 __func__
, adr
, len
);
1712 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
,
1713 cfi
->device_type
, NULL
);
1714 map_write(map
, CMD(0x70), adr
);
1716 chip
->state
= FL_READY
;
1717 put_chip(map
, chip
, adr
+ chip
->start
);
1721 spin_unlock(chip
->mutex
);
1725 static int cfi_atmel_lock(struct mtd_info
*mtd
, loff_t ofs
, size_t len
)
1727 return cfi_varsize_frob(mtd
, do_atmel_lock
, ofs
, len
, NULL
);
1730 static int cfi_atmel_unlock(struct mtd_info
*mtd
, loff_t ofs
, size_t len
)
1732 return cfi_varsize_frob(mtd
, do_atmel_unlock
, ofs
, len
, NULL
);
1736 static void cfi_amdstd_sync (struct mtd_info
*mtd
)
1738 struct map_info
*map
= mtd
->priv
;
1739 struct cfi_private
*cfi
= map
->fldrv_priv
;
1741 struct flchip
*chip
;
1743 DECLARE_WAITQUEUE(wait
, current
);
1745 for (i
=0; !ret
&& i
<cfi
->numchips
; i
++) {
1746 chip
= &cfi
->chips
[i
];
1749 spin_lock(chip
->mutex
);
1751 switch(chip
->state
) {
1755 case FL_JEDEC_QUERY
:
1756 chip
->oldstate
= chip
->state
;
1757 chip
->state
= FL_SYNCING
;
1758 /* No need to wake_up() on this state change -
1759 * as the whole point is that nobody can do anything
1760 * with the chip now anyway.
1763 spin_unlock(chip
->mutex
);
1767 /* Not an idle state */
1768 set_current_state(TASK_UNINTERRUPTIBLE
);
1769 add_wait_queue(&chip
->wq
, &wait
);
1771 spin_unlock(chip
->mutex
);
1775 remove_wait_queue(&chip
->wq
, &wait
);
1781 /* Unlock the chips again */
1783 for (i
--; i
>=0; i
--) {
1784 chip
= &cfi
->chips
[i
];
1786 spin_lock(chip
->mutex
);
1788 if (chip
->state
== FL_SYNCING
) {
1789 chip
->state
= chip
->oldstate
;
1792 spin_unlock(chip
->mutex
);
1797 static int cfi_amdstd_suspend(struct mtd_info
*mtd
)
1799 struct map_info
*map
= mtd
->priv
;
1800 struct cfi_private
*cfi
= map
->fldrv_priv
;
1802 struct flchip
*chip
;
1805 for (i
=0; !ret
&& i
<cfi
->numchips
; i
++) {
1806 chip
= &cfi
->chips
[i
];
1808 spin_lock(chip
->mutex
);
1810 switch(chip
->state
) {
1814 case FL_JEDEC_QUERY
:
1815 chip
->oldstate
= chip
->state
;
1816 chip
->state
= FL_PM_SUSPENDED
;
1817 /* No need to wake_up() on this state change -
1818 * as the whole point is that nobody can do anything
1819 * with the chip now anyway.
1821 case FL_PM_SUSPENDED
:
1828 spin_unlock(chip
->mutex
);
1831 /* Unlock the chips again */
1834 for (i
--; i
>=0; i
--) {
1835 chip
= &cfi
->chips
[i
];
1837 spin_lock(chip
->mutex
);
1839 if (chip
->state
== FL_PM_SUSPENDED
) {
1840 chip
->state
= chip
->oldstate
;
1843 spin_unlock(chip
->mutex
);
1851 static void cfi_amdstd_resume(struct mtd_info
*mtd
)
1853 struct map_info
*map
= mtd
->priv
;
1854 struct cfi_private
*cfi
= map
->fldrv_priv
;
1856 struct flchip
*chip
;
1858 for (i
=0; i
<cfi
->numchips
; i
++) {
1860 chip
= &cfi
->chips
[i
];
1862 spin_lock(chip
->mutex
);
1864 if (chip
->state
== FL_PM_SUSPENDED
) {
1865 chip
->state
= FL_READY
;
1866 map_write(map
, CMD(0xF0), chip
->start
);
1870 printk(KERN_ERR
"Argh. Chip not in PM_SUSPENDED state upon resume()\n");
1872 spin_unlock(chip
->mutex
);
1876 static void cfi_amdstd_destroy(struct mtd_info
*mtd
)
1878 struct map_info
*map
= mtd
->priv
;
1879 struct cfi_private
*cfi
= map
->fldrv_priv
;
1881 kfree(cfi
->cmdset_priv
);
1884 kfree(mtd
->eraseregions
);
1887 MODULE_LICENSE("GPL");
1888 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
1889 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");