2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 * http://www.algor.co.uk
8 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2000 MIPS Technologies, Inc.
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 * A complete emulator for MIPS coprocessor 1 instructions. This is
25 * required for #float(switch) or #float(trap), where it catches all
26 * COP1 instructions via the "CoProcessor Unusable" exception.
28 * More surprisingly it is also required for #float(ieee), to help out
29 * the hardware fpu at the boundaries of the IEEE-754 representation
30 * (denormalised values, infinities, underflow, etc). It is made
31 * quite nasty because emulation of some non-COP1 instructions is
32 * required, e.g. in branch delay slots.
34 * Note if you know that you won't have an fpu, then you'll get much
35 * better performance by compiling with -msoft-float!
37 #include <linux/sched.h>
38 #include <linux/module.h>
41 #include <asm/bootinfo.h>
42 #include <asm/processor.h>
43 #include <asm/ptrace.h>
44 #include <asm/signal.h>
45 #include <asm/mipsregs.h>
46 #include <asm/fpu_emulator.h>
47 #include <asm/uaccess.h>
48 #include <asm/branch.h>
52 /* Strap kernel emulator for full MIPS IV emulation */
59 /* Function which emulates a floating point instruction. */
61 static int fpu_emu(struct pt_regs
*, struct mips_fpu_struct
*,
64 #if __mips >= 4 && __mips != 32
65 static int fpux_emu(struct pt_regs
*,
66 struct mips_fpu_struct
*, mips_instruction
, void *__user
*);
69 /* Further private data for which no space exists in mips_fpu_struct */
71 #ifdef CONFIG_DEBUG_FS
72 DEFINE_PER_CPU(struct mips_fpu_emulator_stats
, fpuemustats
);
75 /* Control registers */
77 #define FPCREG_RID 0 /* $0 = revision id */
78 #define FPCREG_CSR 31 /* $31 = csr */
80 /* Determine rounding mode from the RM bits of the FCSR */
81 #define modeindex(v) ((v) & FPU_CSR_RM)
83 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
84 static const unsigned char ieee_rm
[4] = {
85 [FPU_CSR_RN
] = IEEE754_RN
,
86 [FPU_CSR_RZ
] = IEEE754_RZ
,
87 [FPU_CSR_RU
] = IEEE754_RU
,
88 [FPU_CSR_RD
] = IEEE754_RD
,
90 /* Convert IEEE library modes to Mips rounding mode (0..3). */
91 static const unsigned char mips_rm
[4] = {
92 [IEEE754_RN
] = FPU_CSR_RN
,
93 [IEEE754_RZ
] = FPU_CSR_RZ
,
94 [IEEE754_RD
] = FPU_CSR_RD
,
95 [IEEE754_RU
] = FPU_CSR_RU
,
99 /* convert condition code register number to csr bit */
100 static const unsigned int fpucondbit
[8] = {
114 * Redundant with logic already in kernel/branch.c,
115 * embedded in compute_return_epc. At some point,
116 * a single subroutine should be used across both
119 static int isBranchInstr(mips_instruction
* i
)
121 switch (MIPSInst_OPCODE(*i
)) {
123 switch (MIPSInst_FUNC(*i
)) {
131 switch (MIPSInst_RT(*i
)) {
161 if (MIPSInst_RS(*i
) == bc_op
)
170 * In the Linux kernel, we support selection of FPR format on the
171 * basis of the Status.FR bit. If an FPU is not present, the FR bit
172 * is hardwired to zero, which would imply a 32-bit FPU even for
173 * 64-bit CPUs. For 64-bit kernels with no FPU we use TIF_32BIT_REGS
174 * as a proxy for the FR bit so that a 64-bit FPU is emulated. In any
175 * case, for a 32-bit kernel which uses the O32 MIPS ABI, only the
176 * even FPRs are used (Status.FR = 0).
178 static inline int cop1_64bit(struct pt_regs
*xcp
)
181 return xcp
->cp0_status
& ST0_FR
;
183 return !test_thread_flag(TIF_32BIT_REGS
);
189 #define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \
190 (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32))
192 #define SITOREG(si, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \
193 cop1_64bit(xcp) || !(x & 1) ? \
194 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
195 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
197 #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
198 #define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
200 #define SPFROMREG(sp,x) SIFROMREG((sp).bits,x)
201 #define SPTOREG(sp,x) SITOREG((sp).bits,x)
202 #define DPFROMREG(dp,x) DIFROMREG((dp).bits,x)
203 #define DPTOREG(dp,x) DITOREG((dp).bits,x)
206 * Emulate the single floating point instruction pointed at by EPC.
207 * Two instructions if the instruction is in a branch delay slot.
210 static int cop1Emulate(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
211 void *__user
*fault_addr
)
214 void * emulpc
, *contpc
;
217 if (!access_ok(VERIFY_READ
, xcp
->cp0_epc
, sizeof(mips_instruction
))) {
218 MIPS_FPU_EMU_INC_STATS(errors
);
219 *fault_addr
= (mips_instruction __user
*)xcp
->cp0_epc
;
222 if (__get_user(ir
, (mips_instruction __user
*) xcp
->cp0_epc
)) {
223 MIPS_FPU_EMU_INC_STATS(errors
);
224 *fault_addr
= (mips_instruction __user
*)xcp
->cp0_epc
;
228 /* XXX NEC Vr54xx bug workaround */
229 if ((xcp
->cp0_cause
& CAUSEF_BD
) && !isBranchInstr(&ir
))
230 xcp
->cp0_cause
&= ~CAUSEF_BD
;
232 if (xcp
->cp0_cause
& CAUSEF_BD
) {
234 * The instruction to be emulated is in a branch delay slot
235 * which means that we have to emulate the branch instruction
236 * BEFORE we do the cop1 instruction.
238 * This branch could be a COP1 branch, but in that case we
239 * would have had a trap for that instruction, and would not
240 * come through this route.
242 * Linux MIPS branch emulator operates on context, updating the
245 emulpc
= (void *) (xcp
->cp0_epc
+ 4); /* Snapshot emulation target */
247 if (__compute_return_epc(xcp
)) {
249 printk("failed to emulate branch at %p\n",
250 (void *) (xcp
->cp0_epc
));
254 if (!access_ok(VERIFY_READ
, emulpc
, sizeof(mips_instruction
))) {
255 MIPS_FPU_EMU_INC_STATS(errors
);
256 *fault_addr
= (mips_instruction __user
*)emulpc
;
259 if (__get_user(ir
, (mips_instruction __user
*) emulpc
)) {
260 MIPS_FPU_EMU_INC_STATS(errors
);
261 *fault_addr
= (mips_instruction __user
*)emulpc
;
264 /* __compute_return_epc() will have updated cp0_epc */
265 contpc
= (void *) xcp
->cp0_epc
;
266 /* In order not to confuse ptrace() et al, tweak context */
267 xcp
->cp0_epc
= (unsigned long) emulpc
- 4;
269 emulpc
= (void *) xcp
->cp0_epc
;
270 contpc
= (void *) (xcp
->cp0_epc
+ 4);
274 MIPS_FPU_EMU_INC_STATS(emulated
);
275 switch (MIPSInst_OPCODE(ir
)) {
277 u64 __user
*va
= (u64 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
281 MIPS_FPU_EMU_INC_STATS(loads
);
283 if (!access_ok(VERIFY_READ
, va
, sizeof(u64
))) {
284 MIPS_FPU_EMU_INC_STATS(errors
);
288 if (__get_user(val
, va
)) {
289 MIPS_FPU_EMU_INC_STATS(errors
);
293 DITOREG(val
, MIPSInst_RT(ir
));
298 u64 __user
*va
= (u64 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
302 MIPS_FPU_EMU_INC_STATS(stores
);
303 DIFROMREG(val
, MIPSInst_RT(ir
));
304 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u64
))) {
305 MIPS_FPU_EMU_INC_STATS(errors
);
309 if (__put_user(val
, va
)) {
310 MIPS_FPU_EMU_INC_STATS(errors
);
318 u32 __user
*va
= (u32 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
322 MIPS_FPU_EMU_INC_STATS(loads
);
323 if (!access_ok(VERIFY_READ
, va
, sizeof(u32
))) {
324 MIPS_FPU_EMU_INC_STATS(errors
);
328 if (__get_user(val
, va
)) {
329 MIPS_FPU_EMU_INC_STATS(errors
);
333 SITOREG(val
, MIPSInst_RT(ir
));
338 u32 __user
*va
= (u32 __user
*) (xcp
->regs
[MIPSInst_RS(ir
)] +
342 MIPS_FPU_EMU_INC_STATS(stores
);
343 SIFROMREG(val
, MIPSInst_RT(ir
));
344 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u32
))) {
345 MIPS_FPU_EMU_INC_STATS(errors
);
349 if (__put_user(val
, va
)) {
350 MIPS_FPU_EMU_INC_STATS(errors
);
358 switch (MIPSInst_RS(ir
)) {
360 #if defined(__mips64)
362 /* copregister fs -> gpr[rt] */
363 if (MIPSInst_RT(ir
) != 0) {
364 DIFROMREG(xcp
->regs
[MIPSInst_RT(ir
)],
370 /* copregister fs <- rt */
371 DITOREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
376 /* copregister rd -> gpr[rt] */
377 if (MIPSInst_RT(ir
) != 0) {
378 SIFROMREG(xcp
->regs
[MIPSInst_RT(ir
)],
384 /* copregister rd <- rt */
385 SITOREG(xcp
->regs
[MIPSInst_RT(ir
)], MIPSInst_RD(ir
));
389 /* cop control register rd -> gpr[rt] */
392 if (MIPSInst_RD(ir
) == FPCREG_CSR
) {
394 value
= (value
& ~0x3) | mips_rm
[value
& 0x3];
396 printk("%p gpr[%d]<-csr=%08x\n",
397 (void *) (xcp
->cp0_epc
),
398 MIPSInst_RT(ir
), value
);
401 else if (MIPSInst_RD(ir
) == FPCREG_RID
)
406 xcp
->regs
[MIPSInst_RT(ir
)] = value
;
411 /* copregister rd <- rt */
414 if (MIPSInst_RT(ir
) == 0)
417 value
= xcp
->regs
[MIPSInst_RT(ir
)];
419 /* we only have one writable control reg
421 if (MIPSInst_RD(ir
) == FPCREG_CSR
) {
423 printk("%p gpr[%d]->csr=%08x\n",
424 (void *) (xcp
->cp0_epc
),
425 MIPSInst_RT(ir
), value
);
429 * Don't write reserved bits,
430 * and convert to ieee library modes
432 ctx
->fcr31
= (value
&
433 ~(FPU_CSR_RSVD
| FPU_CSR_RM
)) |
434 ieee_rm
[modeindex(value
)];
436 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
445 if (xcp
->cp0_cause
& CAUSEF_BD
)
449 cond
= ctx
->fcr31
& fpucondbit
[MIPSInst_RT(ir
) >> 2];
451 cond
= ctx
->fcr31
& FPU_CSR_COND
;
453 switch (MIPSInst_RT(ir
) & 3) {
464 /* thats an illegal instruction */
468 xcp
->cp0_cause
|= CAUSEF_BD
;
470 /* branch taken: emulate dslot
476 (MIPSInst_SIMM(ir
) << 2));
478 if (!access_ok(VERIFY_READ
, xcp
->cp0_epc
,
479 sizeof(mips_instruction
))) {
480 MIPS_FPU_EMU_INC_STATS(errors
);
481 *fault_addr
= (mips_instruction __user
*)xcp
->cp0_epc
;
485 (mips_instruction __user
*) xcp
->cp0_epc
)) {
486 MIPS_FPU_EMU_INC_STATS(errors
);
487 *fault_addr
= (mips_instruction __user
*)xcp
->cp0_epc
;
491 switch (MIPSInst_OPCODE(ir
)) {
494 #if (__mips >= 2 || defined(__mips64))
499 #if __mips >= 4 && __mips != 32
502 /* its one of ours */
506 if (MIPSInst_FUNC(ir
) == movc_op
)
513 * Single step the non-cp1
514 * instruction in the dslot
516 return mips_dsemul(xcp
, ir
, (unsigned long) contpc
);
519 /* branch not taken */
522 * branch likely nullifies
528 * else continue & execute
529 * dslot as normal insn
537 if (!(MIPSInst_RS(ir
) & 0x10))
542 /* a real fpu computation instruction */
543 if ((sig
= fpu_emu(xcp
, ctx
, ir
)))
549 #if __mips >= 4 && __mips != 32
551 int sig
= fpux_emu(xcp
, ctx
, ir
, fault_addr
);
560 if (MIPSInst_FUNC(ir
) != movc_op
)
562 cond
= fpucondbit
[MIPSInst_RT(ir
) >> 2];
563 if (((ctx
->fcr31
& cond
) != 0) == ((MIPSInst_RT(ir
) & 1) != 0))
564 xcp
->regs
[MIPSInst_RD(ir
)] =
565 xcp
->regs
[MIPSInst_RS(ir
)];
574 xcp
->cp0_epc
= (unsigned long) contpc
;
575 xcp
->cp0_cause
&= ~CAUSEF_BD
;
581 * Conversion table from MIPS compare ops 48-63
582 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
584 static const unsigned char cmptab
[8] = {
585 0, /* cmp_0 (sig) cmp_sf */
586 IEEE754_CUN
, /* cmp_un (sig) cmp_ngle */
587 IEEE754_CEQ
, /* cmp_eq (sig) cmp_seq */
588 IEEE754_CEQ
| IEEE754_CUN
, /* cmp_ueq (sig) cmp_ngl */
589 IEEE754_CLT
, /* cmp_olt (sig) cmp_lt */
590 IEEE754_CLT
| IEEE754_CUN
, /* cmp_ult (sig) cmp_nge */
591 IEEE754_CLT
| IEEE754_CEQ
, /* cmp_ole (sig) cmp_le */
592 IEEE754_CLT
| IEEE754_CEQ
| IEEE754_CUN
, /* cmp_ule (sig) cmp_ngt */
596 #if __mips >= 4 && __mips != 32
599 * Additional MIPS4 instructions
602 #define DEF3OP(name, p, f1, f2, f3) \
603 static ieee754##p fpemu_##p##_##name (ieee754##p r, ieee754##p s, \
606 struct _ieee754_csr ieee754_csr_save; \
608 ieee754_csr_save = ieee754_csr; \
610 ieee754_csr_save.cx |= ieee754_csr.cx; \
611 ieee754_csr_save.sx |= ieee754_csr.sx; \
613 ieee754_csr.cx |= ieee754_csr_save.cx; \
614 ieee754_csr.sx |= ieee754_csr_save.sx; \
618 static ieee754dp
fpemu_dp_recip(ieee754dp d
)
620 return ieee754dp_div(ieee754dp_one(0), d
);
623 static ieee754dp
fpemu_dp_rsqrt(ieee754dp d
)
625 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d
));
628 static ieee754sp
fpemu_sp_recip(ieee754sp s
)
630 return ieee754sp_div(ieee754sp_one(0), s
);
633 static ieee754sp
fpemu_sp_rsqrt(ieee754sp s
)
635 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s
));
638 DEF3OP(madd
, sp
, ieee754sp_mul
, ieee754sp_add
,);
639 DEF3OP(msub
, sp
, ieee754sp_mul
, ieee754sp_sub
,);
640 DEF3OP(nmadd
, sp
, ieee754sp_mul
, ieee754sp_add
, ieee754sp_neg
);
641 DEF3OP(nmsub
, sp
, ieee754sp_mul
, ieee754sp_sub
, ieee754sp_neg
);
642 DEF3OP(madd
, dp
, ieee754dp_mul
, ieee754dp_add
,);
643 DEF3OP(msub
, dp
, ieee754dp_mul
, ieee754dp_sub
,);
644 DEF3OP(nmadd
, dp
, ieee754dp_mul
, ieee754dp_add
, ieee754dp_neg
);
645 DEF3OP(nmsub
, dp
, ieee754dp_mul
, ieee754dp_sub
, ieee754dp_neg
);
647 static int fpux_emu(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
648 mips_instruction ir
, void *__user
*fault_addr
)
650 unsigned rcsr
= 0; /* resulting csr */
652 MIPS_FPU_EMU_INC_STATS(cp1xops
);
654 switch (MIPSInst_FMA_FFMT(ir
)) {
657 ieee754sp(*handler
) (ieee754sp
, ieee754sp
, ieee754sp
);
658 ieee754sp fd
, fr
, fs
, ft
;
662 switch (MIPSInst_FUNC(ir
)) {
664 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
665 xcp
->regs
[MIPSInst_FT(ir
)]);
667 MIPS_FPU_EMU_INC_STATS(loads
);
668 if (!access_ok(VERIFY_READ
, va
, sizeof(u32
))) {
669 MIPS_FPU_EMU_INC_STATS(errors
);
673 if (__get_user(val
, va
)) {
674 MIPS_FPU_EMU_INC_STATS(errors
);
678 SITOREG(val
, MIPSInst_FD(ir
));
682 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
683 xcp
->regs
[MIPSInst_FT(ir
)]);
685 MIPS_FPU_EMU_INC_STATS(stores
);
687 SIFROMREG(val
, MIPSInst_FS(ir
));
688 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u32
))) {
689 MIPS_FPU_EMU_INC_STATS(errors
);
693 if (put_user(val
, va
)) {
694 MIPS_FPU_EMU_INC_STATS(errors
);
701 handler
= fpemu_sp_madd
;
704 handler
= fpemu_sp_msub
;
707 handler
= fpemu_sp_nmadd
;
710 handler
= fpemu_sp_nmsub
;
714 SPFROMREG(fr
, MIPSInst_FR(ir
));
715 SPFROMREG(fs
, MIPSInst_FS(ir
));
716 SPFROMREG(ft
, MIPSInst_FT(ir
));
717 fd
= (*handler
) (fr
, fs
, ft
);
718 SPTOREG(fd
, MIPSInst_FD(ir
));
721 if (ieee754_cxtest(IEEE754_INEXACT
))
722 rcsr
|= FPU_CSR_INE_X
| FPU_CSR_INE_S
;
723 if (ieee754_cxtest(IEEE754_UNDERFLOW
))
724 rcsr
|= FPU_CSR_UDF_X
| FPU_CSR_UDF_S
;
725 if (ieee754_cxtest(IEEE754_OVERFLOW
))
726 rcsr
|= FPU_CSR_OVF_X
| FPU_CSR_OVF_S
;
727 if (ieee754_cxtest(IEEE754_INVALID_OPERATION
))
728 rcsr
|= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
730 ctx
->fcr31
= (ctx
->fcr31
& ~FPU_CSR_ALL_X
) | rcsr
;
731 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
732 /*printk ("SIGFPE: fpu csr = %08x\n",
746 ieee754dp(*handler
) (ieee754dp
, ieee754dp
, ieee754dp
);
747 ieee754dp fd
, fr
, fs
, ft
;
751 switch (MIPSInst_FUNC(ir
)) {
753 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
754 xcp
->regs
[MIPSInst_FT(ir
)]);
756 MIPS_FPU_EMU_INC_STATS(loads
);
757 if (!access_ok(VERIFY_READ
, va
, sizeof(u64
))) {
758 MIPS_FPU_EMU_INC_STATS(errors
);
762 if (__get_user(val
, va
)) {
763 MIPS_FPU_EMU_INC_STATS(errors
);
767 DITOREG(val
, MIPSInst_FD(ir
));
771 va
= (void __user
*) (xcp
->regs
[MIPSInst_FR(ir
)] +
772 xcp
->regs
[MIPSInst_FT(ir
)]);
774 MIPS_FPU_EMU_INC_STATS(stores
);
775 DIFROMREG(val
, MIPSInst_FS(ir
));
776 if (!access_ok(VERIFY_WRITE
, va
, sizeof(u64
))) {
777 MIPS_FPU_EMU_INC_STATS(errors
);
781 if (__put_user(val
, va
)) {
782 MIPS_FPU_EMU_INC_STATS(errors
);
789 handler
= fpemu_dp_madd
;
792 handler
= fpemu_dp_msub
;
795 handler
= fpemu_dp_nmadd
;
798 handler
= fpemu_dp_nmsub
;
802 DPFROMREG(fr
, MIPSInst_FR(ir
));
803 DPFROMREG(fs
, MIPSInst_FS(ir
));
804 DPFROMREG(ft
, MIPSInst_FT(ir
));
805 fd
= (*handler
) (fr
, fs
, ft
);
806 DPTOREG(fd
, MIPSInst_FD(ir
));
816 if (MIPSInst_FUNC(ir
) != pfetch_op
) {
819 /* ignore prefx operation */
833 * Emulate a single COP1 arithmetic instruction.
835 static int fpu_emu(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
838 int rfmt
; /* resulting format */
839 unsigned rcsr
= 0; /* resulting csr */
848 } rv
; /* resulting value */
850 MIPS_FPU_EMU_INC_STATS(cp1ops
);
851 switch (rfmt
= (MIPSInst_FFMT(ir
) & 0xf)) {
854 ieee754sp(*b
) (ieee754sp
, ieee754sp
);
855 ieee754sp(*u
) (ieee754sp
);
858 switch (MIPSInst_FUNC(ir
)) {
861 handler
.b
= ieee754sp_add
;
864 handler
.b
= ieee754sp_sub
;
867 handler
.b
= ieee754sp_mul
;
870 handler
.b
= ieee754sp_div
;
874 #if __mips >= 2 || defined(__mips64)
876 handler
.u
= ieee754sp_sqrt
;
879 #if __mips >= 4 && __mips != 32
881 handler
.u
= fpemu_sp_rsqrt
;
884 handler
.u
= fpemu_sp_recip
;
889 cond
= fpucondbit
[MIPSInst_FT(ir
) >> 2];
890 if (((ctx
->fcr31
& cond
) != 0) !=
891 ((MIPSInst_FT(ir
) & 1) != 0))
893 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
896 if (xcp
->regs
[MIPSInst_FT(ir
)] != 0)
898 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
901 if (xcp
->regs
[MIPSInst_FT(ir
)] == 0)
903 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
907 handler
.u
= ieee754sp_abs
;
910 handler
.u
= ieee754sp_neg
;
914 SPFROMREG(rv
.s
, MIPSInst_FS(ir
));
917 /* binary op on handler */
922 SPFROMREG(fs
, MIPSInst_FS(ir
));
923 SPFROMREG(ft
, MIPSInst_FT(ir
));
925 rv
.s
= (*handler
.b
) (fs
, ft
);
932 SPFROMREG(fs
, MIPSInst_FS(ir
));
933 rv
.s
= (*handler
.u
) (fs
);
937 if (ieee754_cxtest(IEEE754_INEXACT
))
938 rcsr
|= FPU_CSR_INE_X
| FPU_CSR_INE_S
;
939 if (ieee754_cxtest(IEEE754_UNDERFLOW
))
940 rcsr
|= FPU_CSR_UDF_X
| FPU_CSR_UDF_S
;
941 if (ieee754_cxtest(IEEE754_OVERFLOW
))
942 rcsr
|= FPU_CSR_OVF_X
| FPU_CSR_OVF_S
;
943 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE
))
944 rcsr
|= FPU_CSR_DIV_X
| FPU_CSR_DIV_S
;
945 if (ieee754_cxtest(IEEE754_INVALID_OPERATION
))
946 rcsr
|= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
951 return SIGILL
; /* not defined */
955 SPFROMREG(fs
, MIPSInst_FS(ir
));
956 rv
.d
= ieee754dp_fsp(fs
);
963 SPFROMREG(fs
, MIPSInst_FS(ir
));
964 rv
.w
= ieee754sp_tint(fs
);
969 #if __mips >= 2 || defined(__mips64)
974 unsigned int oldrm
= ieee754_csr
.rm
;
977 SPFROMREG(fs
, MIPSInst_FS(ir
));
978 ieee754_csr
.rm
= ieee_rm
[MIPSInst_FUNC(ir
) & 0x3];
979 rv
.w
= ieee754sp_tint(fs
);
980 ieee754_csr
.rm
= oldrm
;
984 #endif /* __mips >= 2 */
986 #if defined(__mips64)
990 SPFROMREG(fs
, MIPSInst_FS(ir
));
991 rv
.l
= ieee754sp_tlong(fs
);
1000 unsigned int oldrm
= ieee754_csr
.rm
;
1003 SPFROMREG(fs
, MIPSInst_FS(ir
));
1004 ieee754_csr
.rm
= ieee_rm
[MIPSInst_FUNC(ir
) & 0x3];
1005 rv
.l
= ieee754sp_tlong(fs
);
1006 ieee754_csr
.rm
= oldrm
;
1010 #endif /* defined(__mips64) */
1013 if (MIPSInst_FUNC(ir
) >= fcmp_op
) {
1014 unsigned cmpop
= MIPSInst_FUNC(ir
) - fcmp_op
;
1017 SPFROMREG(fs
, MIPSInst_FS(ir
));
1018 SPFROMREG(ft
, MIPSInst_FT(ir
));
1019 rv
.w
= ieee754sp_cmp(fs
, ft
,
1020 cmptab
[cmpop
& 0x7], cmpop
& 0x8);
1022 if ((cmpop
& 0x8) && ieee754_cxtest
1023 (IEEE754_INVALID_OPERATION
))
1024 rcsr
= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1039 ieee754dp(*b
) (ieee754dp
, ieee754dp
);
1040 ieee754dp(*u
) (ieee754dp
);
1043 switch (MIPSInst_FUNC(ir
)) {
1046 handler
.b
= ieee754dp_add
;
1049 handler
.b
= ieee754dp_sub
;
1052 handler
.b
= ieee754dp_mul
;
1055 handler
.b
= ieee754dp_div
;
1059 #if __mips >= 2 || defined(__mips64)
1061 handler
.u
= ieee754dp_sqrt
;
1064 #if __mips >= 4 && __mips != 32
1066 handler
.u
= fpemu_dp_rsqrt
;
1069 handler
.u
= fpemu_dp_recip
;
1074 cond
= fpucondbit
[MIPSInst_FT(ir
) >> 2];
1075 if (((ctx
->fcr31
& cond
) != 0) !=
1076 ((MIPSInst_FT(ir
) & 1) != 0))
1078 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1081 if (xcp
->regs
[MIPSInst_FT(ir
)] != 0)
1083 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1086 if (xcp
->regs
[MIPSInst_FT(ir
)] == 0)
1088 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1092 handler
.u
= ieee754dp_abs
;
1096 handler
.u
= ieee754dp_neg
;
1101 DPFROMREG(rv
.d
, MIPSInst_FS(ir
));
1104 /* binary op on handler */
1108 DPFROMREG(fs
, MIPSInst_FS(ir
));
1109 DPFROMREG(ft
, MIPSInst_FT(ir
));
1111 rv
.d
= (*handler
.b
) (fs
, ft
);
1117 DPFROMREG(fs
, MIPSInst_FS(ir
));
1118 rv
.d
= (*handler
.u
) (fs
);
1122 /* unary conv ops */
1126 DPFROMREG(fs
, MIPSInst_FS(ir
));
1127 rv
.s
= ieee754sp_fdp(fs
);
1132 return SIGILL
; /* not defined */
1137 DPFROMREG(fs
, MIPSInst_FS(ir
));
1138 rv
.w
= ieee754dp_tint(fs
); /* wrong */
1143 #if __mips >= 2 || defined(__mips64)
1148 unsigned int oldrm
= ieee754_csr
.rm
;
1151 DPFROMREG(fs
, MIPSInst_FS(ir
));
1152 ieee754_csr
.rm
= ieee_rm
[MIPSInst_FUNC(ir
) & 0x3];
1153 rv
.w
= ieee754dp_tint(fs
);
1154 ieee754_csr
.rm
= oldrm
;
1160 #if defined(__mips64)
1164 DPFROMREG(fs
, MIPSInst_FS(ir
));
1165 rv
.l
= ieee754dp_tlong(fs
);
1174 unsigned int oldrm
= ieee754_csr
.rm
;
1177 DPFROMREG(fs
, MIPSInst_FS(ir
));
1178 ieee754_csr
.rm
= ieee_rm
[MIPSInst_FUNC(ir
) & 0x3];
1179 rv
.l
= ieee754dp_tlong(fs
);
1180 ieee754_csr
.rm
= oldrm
;
1184 #endif /* __mips >= 3 */
1187 if (MIPSInst_FUNC(ir
) >= fcmp_op
) {
1188 unsigned cmpop
= MIPSInst_FUNC(ir
) - fcmp_op
;
1191 DPFROMREG(fs
, MIPSInst_FS(ir
));
1192 DPFROMREG(ft
, MIPSInst_FT(ir
));
1193 rv
.w
= ieee754dp_cmp(fs
, ft
,
1194 cmptab
[cmpop
& 0x7], cmpop
& 0x8);
1199 (IEEE754_INVALID_OPERATION
))
1200 rcsr
= FPU_CSR_INV_X
| FPU_CSR_INV_S
;
1216 switch (MIPSInst_FUNC(ir
)) {
1218 /* convert word to single precision real */
1219 SPFROMREG(fs
, MIPSInst_FS(ir
));
1220 rv
.s
= ieee754sp_fint(fs
.bits
);
1224 /* convert word to double precision real */
1225 SPFROMREG(fs
, MIPSInst_FS(ir
));
1226 rv
.d
= ieee754dp_fint(fs
.bits
);
1235 #if defined(__mips64)
1237 switch (MIPSInst_FUNC(ir
)) {
1239 /* convert long to single precision real */
1240 rv
.s
= ieee754sp_flong(ctx
->fpr
[MIPSInst_FS(ir
)]);
1244 /* convert long to double precision real */
1245 rv
.d
= ieee754dp_flong(ctx
->fpr
[MIPSInst_FS(ir
)]);
1260 * Update the fpu CSR register for this operation.
1261 * If an exception is required, generate a tidy SIGFPE exception,
1262 * without updating the result register.
1263 * Note: cause exception bits do not accumulate, they are rewritten
1264 * for each op; only the flag/sticky bits accumulate.
1266 ctx
->fcr31
= (ctx
->fcr31
& ~FPU_CSR_ALL_X
) | rcsr
;
1267 if ((ctx
->fcr31
>> 5) & ctx
->fcr31
& FPU_CSR_ALL_E
) {
1268 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
1273 * Now we can safely write the result back to the register file.
1278 cond
= fpucondbit
[MIPSInst_FD(ir
) >> 2];
1280 cond
= FPU_CSR_COND
;
1285 ctx
->fcr31
&= ~cond
;
1289 DPTOREG(rv
.d
, MIPSInst_FD(ir
));
1292 SPTOREG(rv
.s
, MIPSInst_FD(ir
));
1295 SITOREG(rv
.w
, MIPSInst_FD(ir
));
1297 #if defined(__mips64)
1299 DITOREG(rv
.l
, MIPSInst_FD(ir
));
1309 int fpu_emulator_cop1Handler(struct pt_regs
*xcp
, struct mips_fpu_struct
*ctx
,
1310 int has_fpu
, void *__user
*fault_addr
)
1312 unsigned long oldepc
, prevepc
;
1313 mips_instruction insn
;
1316 oldepc
= xcp
->cp0_epc
;
1318 prevepc
= xcp
->cp0_epc
;
1320 if (!access_ok(VERIFY_READ
, xcp
->cp0_epc
, sizeof(mips_instruction
))) {
1321 MIPS_FPU_EMU_INC_STATS(errors
);
1322 *fault_addr
= (mips_instruction __user
*)xcp
->cp0_epc
;
1325 if (__get_user(insn
, (mips_instruction __user
*) xcp
->cp0_epc
)) {
1326 MIPS_FPU_EMU_INC_STATS(errors
);
1327 *fault_addr
= (mips_instruction __user
*)xcp
->cp0_epc
;
1331 xcp
->cp0_epc
+= 4; /* skip nops */
1334 * The 'ieee754_csr' is an alias of
1335 * ctx->fcr31. No need to copy ctx->fcr31 to
1336 * ieee754_csr. But ieee754_csr.rm is ieee
1337 * library modes. (not mips rounding mode)
1339 unsigned int oldrm
= ieee754_csr
.rm
;
1340 /* convert to ieee library modes */
1341 ieee754_csr
.rm
= ieee_rm
[ieee754_csr
.rm
];
1342 sig
= cop1Emulate(xcp
, ctx
, fault_addr
);
1343 /* revert to mips rounding mode */
1344 ieee754_csr
.rm
= oldrm
;
1353 } while (xcp
->cp0_epc
> prevepc
);
1355 /* SIGILL indicates a non-fpu instruction */
1356 if (sig
== SIGILL
&& xcp
->cp0_epc
!= oldepc
)
1357 /* but if epc has advanced, then ignore it */