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MIPS: kernel: attempt to fix oops at fpu_emulator_cop1Handler+0x12c on MIPSR1
[tomato.git] / release / src-rt / linux / linux-2.6 / arch / mips / math-emu / cp1emu.c
blob3b75880c778659080e0bfcf38a86490266cd2146
1 /*
2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 * http://www.algor.co.uk
7 *
8 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2000 MIPS Technologies, Inc.
10 *
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
23 *
24 * A complete emulator for MIPS coprocessor 1 instructions. This is
25 * required for #float(switch) or #float(trap), where it catches all
26 * COP1 instructions via the "CoProcessor Unusable" exception.
27 *
28 * More surprisingly it is also required for #float(ieee), to help out
29 * the hardware fpu at the boundaries of the IEEE-754 representation
30 * (denormalised values, infinities, underflow, etc). It is made
31 * quite nasty because emulation of some non-COP1 instructions is
32 * required, e.g. in branch delay slots.
33 *
34 * Note if you know that you won't have an fpu, then you'll get much
35 * better performance by compiling with -msoft-float!
36 */
37 #include <linux/sched.h>
38 #include <linux/module.h>
39
40 #include <asm/inst.h>
41 #include <asm/bootinfo.h>
42 #include <asm/processor.h>
43 #include <asm/ptrace.h>
44 #include <asm/signal.h>
45 #include <asm/mipsregs.h>
46 #include <asm/fpu_emulator.h>
47 #include <asm/uaccess.h>
48 #include <asm/branch.h>
49
50 #include "ieee754.h"
51
52 /* Strap kernel emulator for full MIPS IV emulation */
53
54 #ifdef __mips
55 #undef __mips
56 #endif
57 #define __mips 4
58
59 /* Function which emulates a floating point instruction. */
60
61 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
62 mips_instruction);
63
64 #if __mips >= 4 && __mips != 32
65 static int fpux_emu(struct pt_regs *,
66 struct mips_fpu_struct *, mips_instruction, void *__user *);
67 #endif
68
69 /* Further private data for which no space exists in mips_fpu_struct */
70
71 #ifdef CONFIG_DEBUG_FS
72 DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
73 #endif
74
75 /* Control registers */
76
77 #define FPCREG_RID 0 /* $0 = revision id */
78 #define FPCREG_CSR 31 /* $31 = csr */
79
80 /* Determine rounding mode from the RM bits of the FCSR */
81 #define modeindex(v) ((v) & FPU_CSR_RM)
82
83 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
84 static const unsigned char ieee_rm[4] = {
85 [FPU_CSR_RN] = IEEE754_RN,
86 [FPU_CSR_RZ] = IEEE754_RZ,
87 [FPU_CSR_RU] = IEEE754_RU,
88 [FPU_CSR_RD] = IEEE754_RD,
89 };
90 /* Convert IEEE library modes to Mips rounding mode (0..3). */
91 static const unsigned char mips_rm[4] = {
92 [IEEE754_RN] = FPU_CSR_RN,
93 [IEEE754_RZ] = FPU_CSR_RZ,
94 [IEEE754_RD] = FPU_CSR_RD,
95 [IEEE754_RU] = FPU_CSR_RU,
96 };
97
98 #if __mips >= 4
99 /* convert condition code register number to csr bit */
100 static const unsigned int fpucondbit[8] = {
101 FPU_CSR_COND0,
102 FPU_CSR_COND1,
103 FPU_CSR_COND2,
104 FPU_CSR_COND3,
105 FPU_CSR_COND4,
106 FPU_CSR_COND5,
107 FPU_CSR_COND6,
108 FPU_CSR_COND7
109 };
110 #endif
111
112
113 /*
114 * Redundant with logic already in kernel/branch.c,
115 * embedded in compute_return_epc. At some point,
116 * a single subroutine should be used across both
117 * modules.
118 */
119 static int isBranchInstr(mips_instruction * i)
120 {
121 switch (MIPSInst_OPCODE(*i)) {
122 case spec_op:
123 switch (MIPSInst_FUNC(*i)) {
124 case jalr_op:
125 case jr_op:
126 return 1;
127 }
128 break;
129
130 case bcond_op:
131 switch (MIPSInst_RT(*i)) {
132 case bltz_op:
133 case bgez_op:
134 case bltzl_op:
135 case bgezl_op:
136 case bltzal_op:
137 case bgezal_op:
138 case bltzall_op:
139 case bgezall_op:
140 return 1;
141 }
142 break;
143
144 case j_op:
145 case jal_op:
146 case jalx_op:
147 case beq_op:
148 case bne_op:
149 case blez_op:
150 case bgtz_op:
151 case beql_op:
152 case bnel_op:
153 case blezl_op:
154 case bgtzl_op:
155 return 1;
156
157 case cop0_op:
158 case cop1_op:
159 case cop2_op:
160 case cop1x_op:
161 if (MIPSInst_RS(*i) == bc_op)
162 return 1;
163 break;
164 }
165
166 return 0;
167 }
168
169 /*
170 * In the Linux kernel, we support selection of FPR format on the
171 * basis of the Status.FR bit. If an FPU is not present, the FR bit
172 * is hardwired to zero, which would imply a 32-bit FPU even for
173 * 64-bit CPUs. For 64-bit kernels with no FPU we use TIF_32BIT_REGS
174 * as a proxy for the FR bit so that a 64-bit FPU is emulated. In any
175 * case, for a 32-bit kernel which uses the O32 MIPS ABI, only the
176 * even FPRs are used (Status.FR = 0).
177 */
178 static inline int cop1_64bit(struct pt_regs *xcp)
179 {
180 if (cpu_has_fpu)
181 return xcp->cp0_status & ST0_FR;
182 #ifdef CONFIG_64BIT
183 return !test_thread_flag(TIF_32BIT_REGS);
184 #else
185 return 0;
186 #endif
187 }
188
189 #define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \
190 (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32))
191
192 #define SITOREG(si, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \
193 cop1_64bit(xcp) || !(x & 1) ? \
194 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
195 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
196
197 #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
198 #define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
199
200 #define SPFROMREG(sp,x) SIFROMREG((sp).bits,x)
201 #define SPTOREG(sp,x) SITOREG((sp).bits,x)
202 #define DPFROMREG(dp,x) DIFROMREG((dp).bits,x)
203 #define DPTOREG(dp,x) DITOREG((dp).bits,x)
204
205 /*
206 * Emulate the single floating point instruction pointed at by EPC.
207 * Two instructions if the instruction is in a branch delay slot.
208 */
209
210 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
211 void *__user *fault_addr)
212 {
213 mips_instruction ir;
214 void * emulpc, *contpc;
215 unsigned int cond;
216
217 if (!access_ok(VERIFY_READ, xcp->cp0_epc, sizeof(mips_instruction))) {
218 MIPS_FPU_EMU_INC_STATS(errors);
219 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
220 return SIGBUS;
221 }
222 if (__get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
223 MIPS_FPU_EMU_INC_STATS(errors);
224 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
225 return SIGSEGV;
226 }
227
228 /* XXX NEC Vr54xx bug workaround */
229 if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir))
230 xcp->cp0_cause &= ~CAUSEF_BD;
231
232 if (xcp->cp0_cause & CAUSEF_BD) {
233 /*
234 * The instruction to be emulated is in a branch delay slot
235 * which means that we have to emulate the branch instruction
236 * BEFORE we do the cop1 instruction.
237 *
238 * This branch could be a COP1 branch, but in that case we
239 * would have had a trap for that instruction, and would not
240 * come through this route.
241 *
242 * Linux MIPS branch emulator operates on context, updating the
243 * cp0_epc.
244 */
245 emulpc = (void *) (xcp->cp0_epc + 4); /* Snapshot emulation target */
246
247 if (__compute_return_epc(xcp)) {
248 #ifdef CP1DBG
249 printk("failed to emulate branch at %p\n",
250 (void *) (xcp->cp0_epc));
251 #endif
252 return SIGILL;
253 }
254 if (!access_ok(VERIFY_READ, emulpc, sizeof(mips_instruction))) {
255 MIPS_FPU_EMU_INC_STATS(errors);
256 *fault_addr = (mips_instruction __user *)emulpc;
257 return SIGBUS;
258 }
259 if (__get_user(ir, (mips_instruction __user *) emulpc)) {
260 MIPS_FPU_EMU_INC_STATS(errors);
261 *fault_addr = (mips_instruction __user *)emulpc;
262 return SIGSEGV;
263 }
264 /* __compute_return_epc() will have updated cp0_epc */
265 contpc = (void *) xcp->cp0_epc;
266 /* In order not to confuse ptrace() et al, tweak context */
267 xcp->cp0_epc = (unsigned long) emulpc - 4;
268 } else {
269 emulpc = (void *) xcp->cp0_epc;
270 contpc = (void *) (xcp->cp0_epc + 4);
271 }
272
273 emul:
274 MIPS_FPU_EMU_INC_STATS(emulated);
275 switch (MIPSInst_OPCODE(ir)) {
276 case ldc1_op:{
277 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
278 MIPSInst_SIMM(ir));
279 u64 val;
280
281 MIPS_FPU_EMU_INC_STATS(loads);
282
283 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
284 MIPS_FPU_EMU_INC_STATS(errors);
285 *fault_addr = va;
286 return SIGBUS;
287 }
288 if (__get_user(val, va)) {
289 MIPS_FPU_EMU_INC_STATS(errors);
290 *fault_addr = va;
291 return SIGSEGV;
292 }
293 DITOREG(val, MIPSInst_RT(ir));
294 break;
295 }
296
297 case sdc1_op:{
298 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
299 MIPSInst_SIMM(ir));
300 u64 val;
301
302 MIPS_FPU_EMU_INC_STATS(stores);
303 DIFROMREG(val, MIPSInst_RT(ir));
304 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
305 MIPS_FPU_EMU_INC_STATS(errors);
306 *fault_addr = va;
307 return SIGBUS;
308 }
309 if (__put_user(val, va)) {
310 MIPS_FPU_EMU_INC_STATS(errors);
311 *fault_addr = va;
312 return SIGSEGV;
313 }
314 break;
315 }
316
317 case lwc1_op:{
318 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
319 MIPSInst_SIMM(ir));
320 u32 val;
321
322 MIPS_FPU_EMU_INC_STATS(loads);
323 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
324 MIPS_FPU_EMU_INC_STATS(errors);
325 *fault_addr = va;
326 return SIGBUS;
327 }
328 if (__get_user(val, va)) {
329 MIPS_FPU_EMU_INC_STATS(errors);
330 *fault_addr = va;
331 return SIGSEGV;
332 }
333 SITOREG(val, MIPSInst_RT(ir));
334 break;
335 }
336
337 case swc1_op:{
338 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
339 MIPSInst_SIMM(ir));
340 u32 val;
341
342 MIPS_FPU_EMU_INC_STATS(stores);
343 SIFROMREG(val, MIPSInst_RT(ir));
344 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
345 MIPS_FPU_EMU_INC_STATS(errors);
346 *fault_addr = va;
347 return SIGBUS;
348 }
349 if (__put_user(val, va)) {
350 MIPS_FPU_EMU_INC_STATS(errors);
351 *fault_addr = va;
352 return SIGSEGV;
353 }
354 break;
355 }
356
357 case cop1_op:
358 switch (MIPSInst_RS(ir)) {
359
360 #if defined(__mips64)
361 case dmfc_op:
362 /* copregister fs -> gpr[rt] */
363 if (MIPSInst_RT(ir) != 0) {
364 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
365 MIPSInst_RD(ir));
366 }
367 break;
368
369 case dmtc_op:
370 /* copregister fs <- rt */
371 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
372 break;
373 #endif
374
375 case mfc_op:
376 /* copregister rd -> gpr[rt] */
377 if (MIPSInst_RT(ir) != 0) {
378 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
379 MIPSInst_RD(ir));
380 }
381 break;
382
383 case mtc_op:
384 /* copregister rd <- rt */
385 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
386 break;
387
388 case cfc_op:{
389 /* cop control register rd -> gpr[rt] */
390 u32 value;
391
392 if (MIPSInst_RD(ir) == FPCREG_CSR) {
393 value = ctx->fcr31;
394 value = (value & ~0x3) | mips_rm[value & 0x3];
395 #ifdef CSRTRACE
396 printk("%p gpr[%d]<-csr=%08x\n",
397 (void *) (xcp->cp0_epc),
398 MIPSInst_RT(ir), value);
399 #endif
400 }
401 else if (MIPSInst_RD(ir) == FPCREG_RID)
402 value = 0;
403 else
404 value = 0;
405 if (MIPSInst_RT(ir))
406 xcp->regs[MIPSInst_RT(ir)] = value;
407 break;
408 }
409
410 case ctc_op:{
411 /* copregister rd <- rt */
412 u32 value;
413
414 if (MIPSInst_RT(ir) == 0)
415 value = 0;
416 else
417 value = xcp->regs[MIPSInst_RT(ir)];
418
419 /* we only have one writable control reg
420 */
421 if (MIPSInst_RD(ir) == FPCREG_CSR) {
422 #ifdef CSRTRACE
423 printk("%p gpr[%d]->csr=%08x\n",
424 (void *) (xcp->cp0_epc),
425 MIPSInst_RT(ir), value);
426 #endif
427
428 /*
429 * Don't write reserved bits,
430 * and convert to ieee library modes
431 */
432 ctx->fcr31 = (value &
433 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
434 ieee_rm[modeindex(value)];
435 }
436 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
437 return SIGFPE;
438 }
439 break;
440 }
441
442 case bc_op:{
443 int likely = 0;
444
445 if (xcp->cp0_cause & CAUSEF_BD)
446 return SIGILL;
447
448 #if __mips >= 4
449 cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
450 #else
451 cond = ctx->fcr31 & FPU_CSR_COND;
452 #endif
453 switch (MIPSInst_RT(ir) & 3) {
454 case bcfl_op:
455 likely = 1;
456 case bcf_op:
457 cond = !cond;
458 break;
459 case bctl_op:
460 likely = 1;
461 case bct_op:
462 break;
463 default:
464 /* thats an illegal instruction */
465 return SIGILL;
466 }
467
468 xcp->cp0_cause |= CAUSEF_BD;
469 if (cond) {
470 /* branch taken: emulate dslot
471 * instruction
472 */
473 xcp->cp0_epc += 4;
474 contpc = (void *)
475 (xcp->cp0_epc +
476 (MIPSInst_SIMM(ir) << 2));
477
478 if (!access_ok(VERIFY_READ, xcp->cp0_epc,
479 sizeof(mips_instruction))) {
480 MIPS_FPU_EMU_INC_STATS(errors);
481 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
482 return SIGBUS;
483 }
484 if (__get_user(ir,
485 (mips_instruction __user *) xcp->cp0_epc)) {
486 MIPS_FPU_EMU_INC_STATS(errors);
487 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
488 return SIGSEGV;
489 }
490
491 switch (MIPSInst_OPCODE(ir)) {
492 case lwc1_op:
493 case swc1_op:
494 #if (__mips >= 2 || defined(__mips64))
495 case ldc1_op:
496 case sdc1_op:
497 #endif
498 case cop1_op:
499 #if __mips >= 4 && __mips != 32
500 case cop1x_op:
501 #endif
502 /* its one of ours */
503 goto emul;
504 #if __mips >= 4
505 case spec_op:
506 if (MIPSInst_FUNC(ir) == movc_op)
507 goto emul;
508 break;
509 #endif
510 }
511
512 /*
513 * Single step the non-cp1
514 * instruction in the dslot
515 */
516 return mips_dsemul(xcp, ir, (unsigned long) contpc);
517 }
518 else {
519 /* branch not taken */
520 if (likely) {
521 /*
522 * branch likely nullifies
523 * dslot if not taken
524 */
525 xcp->cp0_epc += 4;
526 contpc += 4;
527 /*
528 * else continue & execute
529 * dslot as normal insn
530 */
531 }
532 }
533 break;
534 }
535
536 default:
537 if (!(MIPSInst_RS(ir) & 0x10))
538 return SIGILL;
539 {
540 int sig;
541
542 /* a real fpu computation instruction */
543 if ((sig = fpu_emu(xcp, ctx, ir)))
544 return sig;
545 }
546 }
547 break;
548
549 #if __mips >= 4 && __mips != 32
550 case cop1x_op:{
551 int sig = fpux_emu(xcp, ctx, ir, fault_addr);
552 if (sig)
553 return sig;
554 break;
555 }
556 #endif
557
558 #if __mips >= 4
559 case spec_op:
560 if (MIPSInst_FUNC(ir) != movc_op)
561 return SIGILL;
562 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
563 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
564 xcp->regs[MIPSInst_RD(ir)] =
565 xcp->regs[MIPSInst_RS(ir)];
566 break;
567 #endif
568
569 default:
570 return SIGILL;
571 }
572
573 /* we did it !! */
574 xcp->cp0_epc = (unsigned long) contpc;
575 xcp->cp0_cause &= ~CAUSEF_BD;
576
577 return 0;
578 }
579
580 /*
581 * Conversion table from MIPS compare ops 48-63
582 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
583 */
584 static const unsigned char cmptab[8] = {
585 0, /* cmp_0 (sig) cmp_sf */
586 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
587 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
588 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
589 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
590 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
591 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
592 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
593 };
594
595
596 #if __mips >= 4 && __mips != 32
597
598 /*
599 * Additional MIPS4 instructions
600 */
601
602 #define DEF3OP(name, p, f1, f2, f3) \
603 static ieee754##p fpemu_##p##_##name (ieee754##p r, ieee754##p s, \
604 ieee754##p t) \
605 { \
606 struct _ieee754_csr ieee754_csr_save; \
607 s = f1 (s, t); \
608 ieee754_csr_save = ieee754_csr; \
609 s = f2 (s, r); \
610 ieee754_csr_save.cx |= ieee754_csr.cx; \
611 ieee754_csr_save.sx |= ieee754_csr.sx; \
612 s = f3 (s); \
613 ieee754_csr.cx |= ieee754_csr_save.cx; \
614 ieee754_csr.sx |= ieee754_csr_save.sx; \
615 return s; \
616 }
617
618 static ieee754dp fpemu_dp_recip(ieee754dp d)
619 {
620 return ieee754dp_div(ieee754dp_one(0), d);
621 }
622
623 static ieee754dp fpemu_dp_rsqrt(ieee754dp d)
624 {
625 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
626 }
627
628 static ieee754sp fpemu_sp_recip(ieee754sp s)
629 {
630 return ieee754sp_div(ieee754sp_one(0), s);
631 }
632
633 static ieee754sp fpemu_sp_rsqrt(ieee754sp s)
634 {
635 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
636 }
637
638 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add,);
639 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub,);
640 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
641 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
642 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add,);
643 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub,);
644 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
645 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
646
647 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
648 mips_instruction ir, void *__user *fault_addr)
649 {
650 unsigned rcsr = 0; /* resulting csr */
651
652 MIPS_FPU_EMU_INC_STATS(cp1xops);
653
654 switch (MIPSInst_FMA_FFMT(ir)) {
655 case s_fmt:{ /* 0 */
656
657 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
658 ieee754sp fd, fr, fs, ft;
659 u32 __user *va;
660 u32 val;
661
662 switch (MIPSInst_FUNC(ir)) {
663 case lwxc1_op:
664 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
665 xcp->regs[MIPSInst_FT(ir)]);
666
667 MIPS_FPU_EMU_INC_STATS(loads);
668 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
669 MIPS_FPU_EMU_INC_STATS(errors);
670 *fault_addr = va;
671 return SIGBUS;
672 }
673 if (__get_user(val, va)) {
674 MIPS_FPU_EMU_INC_STATS(errors);
675 *fault_addr = va;
676 return SIGSEGV;
677 }
678 SITOREG(val, MIPSInst_FD(ir));
679 break;
680
681 case swxc1_op:
682 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
683 xcp->regs[MIPSInst_FT(ir)]);
684
685 MIPS_FPU_EMU_INC_STATS(stores);
686
687 SIFROMREG(val, MIPSInst_FS(ir));
688 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
689 MIPS_FPU_EMU_INC_STATS(errors);
690 *fault_addr = va;
691 return SIGBUS;
692 }
693 if (put_user(val, va)) {
694 MIPS_FPU_EMU_INC_STATS(errors);
695 *fault_addr = va;
696 return SIGSEGV;
697 }
698 break;
699
700 case madd_s_op:
701 handler = fpemu_sp_madd;
702 goto scoptop;
703 case msub_s_op:
704 handler = fpemu_sp_msub;
705 goto scoptop;
706 case nmadd_s_op:
707 handler = fpemu_sp_nmadd;
708 goto scoptop;
709 case nmsub_s_op:
710 handler = fpemu_sp_nmsub;
711 goto scoptop;
712
713 scoptop:
714 SPFROMREG(fr, MIPSInst_FR(ir));
715 SPFROMREG(fs, MIPSInst_FS(ir));
716 SPFROMREG(ft, MIPSInst_FT(ir));
717 fd = (*handler) (fr, fs, ft);
718 SPTOREG(fd, MIPSInst_FD(ir));
719
720 copcsr:
721 if (ieee754_cxtest(IEEE754_INEXACT))
722 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
723 if (ieee754_cxtest(IEEE754_UNDERFLOW))
724 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
725 if (ieee754_cxtest(IEEE754_OVERFLOW))
726 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
727 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
728 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
729
730 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
731 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
732 /*printk ("SIGFPE: fpu csr = %08x\n",
733 ctx->fcr31); */
734 return SIGFPE;
735 }
736
737 break;
738
739 default:
740 return SIGILL;
741 }
742 break;
743 }
744
745 case d_fmt:{ /* 1 */
746 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
747 ieee754dp fd, fr, fs, ft;
748 u64 __user *va;
749 u64 val;
750
751 switch (MIPSInst_FUNC(ir)) {
752 case ldxc1_op:
753 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
754 xcp->regs[MIPSInst_FT(ir)]);
755
756 MIPS_FPU_EMU_INC_STATS(loads);
757 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
758 MIPS_FPU_EMU_INC_STATS(errors);
759 *fault_addr = va;
760 return SIGBUS;
761 }
762 if (__get_user(val, va)) {
763 MIPS_FPU_EMU_INC_STATS(errors);
764 *fault_addr = va;
765 return SIGSEGV;
766 }
767 DITOREG(val, MIPSInst_FD(ir));
768 break;
769
770 case sdxc1_op:
771 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
772 xcp->regs[MIPSInst_FT(ir)]);
773
774 MIPS_FPU_EMU_INC_STATS(stores);
775 DIFROMREG(val, MIPSInst_FS(ir));
776 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
777 MIPS_FPU_EMU_INC_STATS(errors);
778 *fault_addr = va;
779 return SIGBUS;
780 }
781 if (__put_user(val, va)) {
782 MIPS_FPU_EMU_INC_STATS(errors);
783 *fault_addr = va;
784 return SIGSEGV;
785 }
786 break;
787
788 case madd_d_op:
789 handler = fpemu_dp_madd;
790 goto dcoptop;
791 case msub_d_op:
792 handler = fpemu_dp_msub;
793 goto dcoptop;
794 case nmadd_d_op:
795 handler = fpemu_dp_nmadd;
796 goto dcoptop;
797 case nmsub_d_op:
798 handler = fpemu_dp_nmsub;
799 goto dcoptop;
800
801 dcoptop:
802 DPFROMREG(fr, MIPSInst_FR(ir));
803 DPFROMREG(fs, MIPSInst_FS(ir));
804 DPFROMREG(ft, MIPSInst_FT(ir));
805 fd = (*handler) (fr, fs, ft);
806 DPTOREG(fd, MIPSInst_FD(ir));
807 goto copcsr;
808
809 default:
810 return SIGILL;
811 }
812 break;
813 }
814
815 case 0x7: /* 7 */
816 if (MIPSInst_FUNC(ir) != pfetch_op) {
817 return SIGILL;
818 }
819 /* ignore prefx operation */
820 break;
821
822 default:
823 return SIGILL;
824 }
825
826 return 0;
827 }
828 #endif
829
830
831
832 /*
833 * Emulate a single COP1 arithmetic instruction.
834 */
835 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
836 mips_instruction ir)
837 {
838 int rfmt; /* resulting format */
839 unsigned rcsr = 0; /* resulting csr */
840 unsigned cond;
841 union {
842 ieee754dp d;
843 ieee754sp s;
844 int w;
845 #ifdef __mips64
846 s64 l;
847 #endif
848 } rv; /* resulting value */
849
850 MIPS_FPU_EMU_INC_STATS(cp1ops);
851 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
852 case s_fmt:{ /* 0 */
853 union {
854 ieee754sp(*b) (ieee754sp, ieee754sp);
855 ieee754sp(*u) (ieee754sp);
856 } handler;
857
858 switch (MIPSInst_FUNC(ir)) {
859 /* binary ops */
860 case fadd_op:
861 handler.b = ieee754sp_add;
862 goto scopbop;
863 case fsub_op:
864 handler.b = ieee754sp_sub;
865 goto scopbop;
866 case fmul_op:
867 handler.b = ieee754sp_mul;
868 goto scopbop;
869 case fdiv_op:
870 handler.b = ieee754sp_div;
871 goto scopbop;
872
873 /* unary ops */
874 #if __mips >= 2 || defined(__mips64)
875 case fsqrt_op:
876 handler.u = ieee754sp_sqrt;
877 goto scopuop;
878 #endif
879 #if __mips >= 4 && __mips != 32
880 case frsqrt_op:
881 handler.u = fpemu_sp_rsqrt;
882 goto scopuop;
883 case frecip_op:
884 handler.u = fpemu_sp_recip;
885 goto scopuop;
886 #endif
887 #if __mips >= 4
888 case fmovc_op:
889 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
890 if (((ctx->fcr31 & cond) != 0) !=
891 ((MIPSInst_FT(ir) & 1) != 0))
892 return 0;
893 SPFROMREG(rv.s, MIPSInst_FS(ir));
894 break;
895 case fmovz_op:
896 if (xcp->regs[MIPSInst_FT(ir)] != 0)
897 return 0;
898 SPFROMREG(rv.s, MIPSInst_FS(ir));
899 break;
900 case fmovn_op:
901 if (xcp->regs[MIPSInst_FT(ir)] == 0)
902 return 0;
903 SPFROMREG(rv.s, MIPSInst_FS(ir));
904 break;
905 #endif
906 case fabs_op:
907 handler.u = ieee754sp_abs;
908 goto scopuop;
909 case fneg_op:
910 handler.u = ieee754sp_neg;
911 goto scopuop;
912 case fmov_op:
913 /* an easy one */
914 SPFROMREG(rv.s, MIPSInst_FS(ir));
915 goto copcsr;
916
917 /* binary op on handler */
918 scopbop:
919 {
920 ieee754sp fs, ft;
921
922 SPFROMREG(fs, MIPSInst_FS(ir));
923 SPFROMREG(ft, MIPSInst_FT(ir));
924
925 rv.s = (*handler.b) (fs, ft);
926 goto copcsr;
927 }
928 scopuop:
929 {
930 ieee754sp fs;
931
932 SPFROMREG(fs, MIPSInst_FS(ir));
933 rv.s = (*handler.u) (fs);
934 goto copcsr;
935 }
936 copcsr:
937 if (ieee754_cxtest(IEEE754_INEXACT))
938 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
939 if (ieee754_cxtest(IEEE754_UNDERFLOW))
940 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
941 if (ieee754_cxtest(IEEE754_OVERFLOW))
942 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
943 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
944 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
945 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
946 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
947 break;
948
949 /* unary conv ops */
950 case fcvts_op:
951 return SIGILL; /* not defined */
952 case fcvtd_op:{
953 ieee754sp fs;
954
955 SPFROMREG(fs, MIPSInst_FS(ir));
956 rv.d = ieee754dp_fsp(fs);
957 rfmt = d_fmt;
958 goto copcsr;
959 }
960 case fcvtw_op:{
961 ieee754sp fs;
962
963 SPFROMREG(fs, MIPSInst_FS(ir));
964 rv.w = ieee754sp_tint(fs);
965 rfmt = w_fmt;
966 goto copcsr;
967 }
968
969 #if __mips >= 2 || defined(__mips64)
970 case fround_op:
971 case ftrunc_op:
972 case fceil_op:
973 case ffloor_op:{
974 unsigned int oldrm = ieee754_csr.rm;
975 ieee754sp fs;
976
977 SPFROMREG(fs, MIPSInst_FS(ir));
978 ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
979 rv.w = ieee754sp_tint(fs);
980 ieee754_csr.rm = oldrm;
981 rfmt = w_fmt;
982 goto copcsr;
983 }
984 #endif /* __mips >= 2 */
985
986 #if defined(__mips64)
987 case fcvtl_op:{
988 ieee754sp fs;
989
990 SPFROMREG(fs, MIPSInst_FS(ir));
991 rv.l = ieee754sp_tlong(fs);
992 rfmt = l_fmt;
993 goto copcsr;
994 }
995
996 case froundl_op:
997 case ftruncl_op:
998 case fceill_op:
999 case ffloorl_op:{
1000 unsigned int oldrm = ieee754_csr.rm;
1001 ieee754sp fs;
1002
1003 SPFROMREG(fs, MIPSInst_FS(ir));
1004 ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
1005 rv.l = ieee754sp_tlong(fs);
1006 ieee754_csr.rm = oldrm;
1007 rfmt = l_fmt;
1008 goto copcsr;
1009 }
1010 #endif /* defined(__mips64) */
1011
1012 default:
1013 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1014 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1015 ieee754sp fs, ft;
1016
1017 SPFROMREG(fs, MIPSInst_FS(ir));
1018 SPFROMREG(ft, MIPSInst_FT(ir));
1019 rv.w = ieee754sp_cmp(fs, ft,
1020 cmptab[cmpop & 0x7], cmpop & 0x8);
1021 rfmt = -1;
1022 if ((cmpop & 0x8) && ieee754_cxtest
1023 (IEEE754_INVALID_OPERATION))
1024 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1025 else
1026 goto copcsr;
1027
1028 }
1029 else {
1030 return SIGILL;
1031 }
1032 break;
1033 }
1034 break;
1035 }
1036
1037 case d_fmt:{
1038 union {
1039 ieee754dp(*b) (ieee754dp, ieee754dp);
1040 ieee754dp(*u) (ieee754dp);
1041 } handler;
1042
1043 switch (MIPSInst_FUNC(ir)) {
1044 /* binary ops */
1045 case fadd_op:
1046 handler.b = ieee754dp_add;
1047 goto dcopbop;
1048 case fsub_op:
1049 handler.b = ieee754dp_sub;
1050 goto dcopbop;
1051 case fmul_op:
1052 handler.b = ieee754dp_mul;
1053 goto dcopbop;
1054 case fdiv_op:
1055 handler.b = ieee754dp_div;
1056 goto dcopbop;
1057
1058 /* unary ops */
1059 #if __mips >= 2 || defined(__mips64)
1060 case fsqrt_op:
1061 handler.u = ieee754dp_sqrt;
1062 goto dcopuop;
1063 #endif
1064 #if __mips >= 4 && __mips != 32
1065 case frsqrt_op:
1066 handler.u = fpemu_dp_rsqrt;
1067 goto dcopuop;
1068 case frecip_op:
1069 handler.u = fpemu_dp_recip;
1070 goto dcopuop;
1071 #endif
1072 #if __mips >= 4
1073 case fmovc_op:
1074 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1075 if (((ctx->fcr31 & cond) != 0) !=
1076 ((MIPSInst_FT(ir) & 1) != 0))
1077 return 0;
1078 DPFROMREG(rv.d, MIPSInst_FS(ir));
1079 break;
1080 case fmovz_op:
1081 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1082 return 0;
1083 DPFROMREG(rv.d, MIPSInst_FS(ir));
1084 break;
1085 case fmovn_op:
1086 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1087 return 0;
1088 DPFROMREG(rv.d, MIPSInst_FS(ir));
1089 break;
1090 #endif
1091 case fabs_op:
1092 handler.u = ieee754dp_abs;
1093 goto dcopuop;
1094
1095 case fneg_op:
1096 handler.u = ieee754dp_neg;
1097 goto dcopuop;
1098
1099 case fmov_op:
1100 /* an easy one */
1101 DPFROMREG(rv.d, MIPSInst_FS(ir));
1102 goto copcsr;
1103
1104 /* binary op on handler */
1105 dcopbop:{
1106 ieee754dp fs, ft;
1107
1108 DPFROMREG(fs, MIPSInst_FS(ir));
1109 DPFROMREG(ft, MIPSInst_FT(ir));
1110
1111 rv.d = (*handler.b) (fs, ft);
1112 goto copcsr;
1113 }
1114 dcopuop:{
1115 ieee754dp fs;
1116
1117 DPFROMREG(fs, MIPSInst_FS(ir));
1118 rv.d = (*handler.u) (fs);
1119 goto copcsr;
1120 }
1121
1122 /* unary conv ops */
1123 case fcvts_op:{
1124 ieee754dp fs;
1125
1126 DPFROMREG(fs, MIPSInst_FS(ir));
1127 rv.s = ieee754sp_fdp(fs);
1128 rfmt = s_fmt;
1129 goto copcsr;
1130 }
1131 case fcvtd_op:
1132 return SIGILL; /* not defined */
1133
1134 case fcvtw_op:{
1135 ieee754dp fs;
1136
1137 DPFROMREG(fs, MIPSInst_FS(ir));
1138 rv.w = ieee754dp_tint(fs); /* wrong */
1139 rfmt = w_fmt;
1140 goto copcsr;
1141 }
1142
1143 #if __mips >= 2 || defined(__mips64)
1144 case fround_op:
1145 case ftrunc_op:
1146 case fceil_op:
1147 case ffloor_op:{
1148 unsigned int oldrm = ieee754_csr.rm;
1149 ieee754dp fs;
1150
1151 DPFROMREG(fs, MIPSInst_FS(ir));
1152 ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
1153 rv.w = ieee754dp_tint(fs);
1154 ieee754_csr.rm = oldrm;
1155 rfmt = w_fmt;
1156 goto copcsr;
1157 }
1158 #endif
1159
1160 #if defined(__mips64)
1161 case fcvtl_op:{
1162 ieee754dp fs;
1163
1164 DPFROMREG(fs, MIPSInst_FS(ir));
1165 rv.l = ieee754dp_tlong(fs);
1166 rfmt = l_fmt;
1167 goto copcsr;
1168 }
1169
1170 case froundl_op:
1171 case ftruncl_op:
1172 case fceill_op:
1173 case ffloorl_op:{
1174 unsigned int oldrm = ieee754_csr.rm;
1175 ieee754dp fs;
1176
1177 DPFROMREG(fs, MIPSInst_FS(ir));
1178 ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3];
1179 rv.l = ieee754dp_tlong(fs);
1180 ieee754_csr.rm = oldrm;
1181 rfmt = l_fmt;
1182 goto copcsr;
1183 }
1184 #endif /* __mips >= 3 */
1185
1186 default:
1187 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1188 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1189 ieee754dp fs, ft;
1190
1191 DPFROMREG(fs, MIPSInst_FS(ir));
1192 DPFROMREG(ft, MIPSInst_FT(ir));
1193 rv.w = ieee754dp_cmp(fs, ft,
1194 cmptab[cmpop & 0x7], cmpop & 0x8);
1195 rfmt = -1;
1196 if ((cmpop & 0x8)
1197 &&
1198 ieee754_cxtest
1199 (IEEE754_INVALID_OPERATION))
1200 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1201 else
1202 goto copcsr;
1203
1204 }
1205 else {
1206 return SIGILL;
1207 }
1208 break;
1209 }
1210 break;
1211 }
1212
1213 case w_fmt:{
1214 ieee754sp fs;
1215
1216 switch (MIPSInst_FUNC(ir)) {
1217 case fcvts_op:
1218 /* convert word to single precision real */
1219 SPFROMREG(fs, MIPSInst_FS(ir));
1220 rv.s = ieee754sp_fint(fs.bits);
1221 rfmt = s_fmt;
1222 goto copcsr;
1223 case fcvtd_op:
1224 /* convert word to double precision real */
1225 SPFROMREG(fs, MIPSInst_FS(ir));
1226 rv.d = ieee754dp_fint(fs.bits);
1227 rfmt = d_fmt;
1228 goto copcsr;
1229 default:
1230 return SIGILL;
1231 }
1232 break;
1233 }
1234
1235 #if defined(__mips64)
1236 case l_fmt:{
1237 switch (MIPSInst_FUNC(ir)) {
1238 case fcvts_op:
1239 /* convert long to single precision real */
1240 rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1241 rfmt = s_fmt;
1242 goto copcsr;
1243 case fcvtd_op:
1244 /* convert long to double precision real */
1245 rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1246 rfmt = d_fmt;
1247 goto copcsr;
1248 default:
1249 return SIGILL;
1250 }
1251 break;
1252 }
1253 #endif
1254
1255 default:
1256 return SIGILL;
1257 }
1258
1259 /*
1260 * Update the fpu CSR register for this operation.
1261 * If an exception is required, generate a tidy SIGFPE exception,
1262 * without updating the result register.
1263 * Note: cause exception bits do not accumulate, they are rewritten
1264 * for each op; only the flag/sticky bits accumulate.
1265 */
1266 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1267 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1268 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
1269 return SIGFPE;
1270 }
1271
1272 /*
1273 * Now we can safely write the result back to the register file.
1274 */
1275 switch (rfmt) {
1276 case -1:{
1277 #if __mips >= 4
1278 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
1279 #else
1280 cond = FPU_CSR_COND;
1281 #endif
1282 if (rv.w)
1283 ctx->fcr31 |= cond;
1284 else
1285 ctx->fcr31 &= ~cond;
1286 break;
1287 }
1288 case d_fmt:
1289 DPTOREG(rv.d, MIPSInst_FD(ir));
1290 break;
1291 case s_fmt:
1292 SPTOREG(rv.s, MIPSInst_FD(ir));
1293 break;
1294 case w_fmt:
1295 SITOREG(rv.w, MIPSInst_FD(ir));
1296 break;
1297 #if defined(__mips64)
1298 case l_fmt:
1299 DITOREG(rv.l, MIPSInst_FD(ir));
1300 break;
1301 #endif
1302 default:
1303 return SIGILL;
1304 }
1305
1306 return 0;
1307 }
1308
1309 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1310 int has_fpu, void *__user *fault_addr)
1311 {
1312 unsigned long oldepc, prevepc;
1313 mips_instruction insn;
1314 int sig = 0;
1315
1316 oldepc = xcp->cp0_epc;
1317 do {
1318 prevepc = xcp->cp0_epc;
1319
1320 if (!access_ok(VERIFY_READ, xcp->cp0_epc, sizeof(mips_instruction))) {
1321 MIPS_FPU_EMU_INC_STATS(errors);
1322 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
1323 return SIGBUS;
1324 }
1325 if (__get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) {
1326 MIPS_FPU_EMU_INC_STATS(errors);
1327 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
1328 return SIGSEGV;
1329 }
1330 if (insn == 0)
1331 xcp->cp0_epc += 4; /* skip nops */
1332 else {
1333 /*
1334 * The 'ieee754_csr' is an alias of
1335 * ctx->fcr31. No need to copy ctx->fcr31 to
1336 * ieee754_csr. But ieee754_csr.rm is ieee
1337 * library modes. (not mips rounding mode)
1338 */
1339 unsigned int oldrm = ieee754_csr.rm;
1340 /* convert to ieee library modes */
1341 ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
1342 sig = cop1Emulate(xcp, ctx, fault_addr);
1343 /* revert to mips rounding mode */
1344 ieee754_csr.rm = oldrm;
1345 }
1346
1347 if (has_fpu)
1348 break;
1349 if (sig)
1350 break;
1351
1352 cond_resched();
1353 } while (xcp->cp0_epc > prevepc);
1354
1355 /* SIGILL indicates a non-fpu instruction */
1356 if (sig == SIGILL && xcp->cp0_epc != oldepc)
1357 /* but if epc has advanced, then ignore it */
1358 sig = 0;
1359
1360 return sig;
1361 }
Tomato firmware and modifications.