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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / sound / soc / codecs / wm8955.c
blob004e83765642cfa35426334122fca1d041d2dad5
1 /*
2 * wm8955.c -- WM8955 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <sound/wm8955.h>
30
31 #include "wm8955.h"
32
33 static struct snd_soc_codec *wm8955_codec;
34 struct snd_soc_codec_device soc_codec_dev_wm8955;
35
36 #define WM8955_NUM_SUPPLIES 4
37 static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = {
38 "DCVDD",
39 "DBVDD",
40 "HPVDD",
41 "AVDD",
42 };
43
44 /* codec private data */
45 struct wm8955_priv {
46 struct snd_soc_codec codec;
47 u16 reg_cache[WM8955_MAX_REGISTER + 1];
48
49 unsigned int mclk_rate;
50
51 int deemph;
52 int fs;
53
54 struct regulator_bulk_data supplies[WM8955_NUM_SUPPLIES];
55
56 struct wm8955_pdata *pdata;
57 };
58
59 static const u16 wm8955_reg[WM8955_MAX_REGISTER + 1] = {
60 0x0000, /* R0 */
61 0x0000, /* R1 */
62 0x0079, /* R2 - LOUT1 volume */
63 0x0079, /* R3 - ROUT1 volume */
64 0x0000, /* R4 */
65 0x0008, /* R5 - DAC Control */
66 0x0000, /* R6 */
67 0x000A, /* R7 - Audio Interface */
68 0x0000, /* R8 - Sample Rate */
69 0x0000, /* R9 */
70 0x00FF, /* R10 - Left DAC volume */
71 0x00FF, /* R11 - Right DAC volume */
72 0x000F, /* R12 - Bass control */
73 0x000F, /* R13 - Treble control */
74 0x0000, /* R14 */
75 0x0000, /* R15 - Reset */
76 0x0000, /* R16 */
77 0x0000, /* R17 */
78 0x0000, /* R18 */
79 0x0000, /* R19 */
80 0x0000, /* R20 */
81 0x0000, /* R21 */
82 0x0000, /* R22 */
83 0x00C1, /* R23 - Additional control (1) */
84 0x0000, /* R24 - Additional control (2) */
85 0x0000, /* R25 - Power Management (1) */
86 0x0000, /* R26 - Power Management (2) */
87 0x0000, /* R27 - Additional Control (3) */
88 0x0000, /* R28 */
89 0x0000, /* R29 */
90 0x0000, /* R30 */
91 0x0000, /* R31 */
92 0x0000, /* R32 */
93 0x0000, /* R33 */
94 0x0050, /* R34 - Left out Mix (1) */
95 0x0050, /* R35 - Left out Mix (2) */
96 0x0050, /* R36 - Right out Mix (1) */
97 0x0050, /* R37 - Right Out Mix (2) */
98 0x0050, /* R38 - Mono out Mix (1) */
99 0x0050, /* R39 - Mono out Mix (2) */
100 0x0079, /* R40 - LOUT2 volume */
101 0x0079, /* R41 - ROUT2 volume */
102 0x0079, /* R42 - MONOOUT volume */
103 0x0000, /* R43 - Clocking / PLL */
104 0x0103, /* R44 - PLL Control 1 */
105 0x0024, /* R45 - PLL Control 2 */
106 0x01BA, /* R46 - PLL Control 3 */
107 0x0000, /* R47 */
108 0x0000, /* R48 */
109 0x0000, /* R49 */
110 0x0000, /* R50 */
111 0x0000, /* R51 */
112 0x0000, /* R52 */
113 0x0000, /* R53 */
114 0x0000, /* R54 */
115 0x0000, /* R55 */
116 0x0000, /* R56 */
117 0x0000, /* R57 */
118 0x0000, /* R58 */
119 0x0000, /* R59 - PLL Control 4 */
120 };
121
122 static int wm8955_reset(struct snd_soc_codec *codec)
123 {
124 return snd_soc_write(codec, WM8955_RESET, 0);
125 }
126
127 struct pll_factors {
128 int n;
129 int k;
130 int outdiv;
131 };
132
133 /* The size in bits of the FLL divide multiplied by 10
134 * to allow rounding later */
135 #define FIXED_FLL_SIZE ((1 << 22) * 10)
136
137 static int wm8995_pll_factors(struct device *dev,
138 int Fref, int Fout, struct pll_factors *pll)
139 {
140 u64 Kpart;
141 unsigned int K, Ndiv, Nmod, target;
142
143 dev_dbg(dev, "Fref=%u Fout=%u\n", Fref, Fout);
144
145 /* The oscilator should run at should be 90-100MHz, and
146 * there's a divide by 4 plus an optional divide by 2 in the
147 * output path to generate the system clock. The clock table
148 * is sortd so we should always generate a suitable target. */
149 target = Fout * 4;
150 if (target < 90000000) {
151 pll->outdiv = 1;
152 target *= 2;
153 } else {
154 pll->outdiv = 0;
155 }
156
157 WARN_ON(target < 90000000 || target > 100000000);
158
159 dev_dbg(dev, "Fvco=%dHz\n", target);
160
161 /* Now, calculate N.K */
162 Ndiv = target / Fref;
163
164 pll->n = Ndiv;
165 Nmod = target % Fref;
166 dev_dbg(dev, "Nmod=%d\n", Nmod);
167
168 /* Calculate fractional part - scale up so we can round. */
169 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
170
171 do_div(Kpart, Fref);
172
173 K = Kpart & 0xFFFFFFFF;
174
175 if ((K % 10) >= 5)
176 K += 5;
177
178 /* Move down to proper range now rounding is done */
179 pll->k = K / 10;
180
181 dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv);
182
183 return 0;
184 }
185
186 /* Lookup table specifiying SRATE (table 25 in datasheet); some of the
187 * output frequencies have been rounded to the standard frequencies
188 * they are intended to match where the error is slight. */
189 static struct {
190 int mclk;
191 int fs;
192 int usb;
193 int sr;
194 } clock_cfgs[] = {
195 { 18432000, 8000, 0, 3, },
196 { 18432000, 12000, 0, 9, },
197 { 18432000, 16000, 0, 11, },
198 { 18432000, 24000, 0, 29, },
199 { 18432000, 32000, 0, 13, },
200 { 18432000, 48000, 0, 1, },
201 { 18432000, 96000, 0, 15, },
202
203 { 16934400, 8018, 0, 19, },
204 { 16934400, 11025, 0, 25, },
205 { 16934400, 22050, 0, 27, },
206 { 16934400, 44100, 0, 17, },
207 { 16934400, 88200, 0, 31, },
208
209 { 12000000, 8000, 1, 2, },
210 { 12000000, 11025, 1, 25, },
211 { 12000000, 12000, 1, 8, },
212 { 12000000, 16000, 1, 10, },
213 { 12000000, 22050, 1, 27, },
214 { 12000000, 24000, 1, 28, },
215 { 12000000, 32000, 1, 12, },
216 { 12000000, 44100, 1, 17, },
217 { 12000000, 48000, 1, 0, },
218 { 12000000, 88200, 1, 31, },
219 { 12000000, 96000, 1, 14, },
220
221 { 12288000, 8000, 0, 2, },
222 { 12288000, 12000, 0, 8, },
223 { 12288000, 16000, 0, 10, },
224 { 12288000, 24000, 0, 28, },
225 { 12288000, 32000, 0, 12, },
226 { 12288000, 48000, 0, 0, },
227 { 12288000, 96000, 0, 14, },
228
229 { 12289600, 8018, 0, 18, },
230 { 12289600, 11025, 0, 24, },
231 { 12289600, 22050, 0, 26, },
232 { 11289600, 44100, 0, 16, },
233 { 11289600, 88200, 0, 31, },
234 };
235
236 static int wm8955_configure_clocking(struct snd_soc_codec *codec)
237 {
238 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
239 int i, ret, val;
240 int clocking = 0;
241 int srate = 0;
242 int sr = -1;
243 struct pll_factors pll;
244
245 /* If we're not running a sample rate currently just pick one */
246 if (wm8955->fs == 0)
247 wm8955->fs = 8000;
248
249 /* Can we generate an exact output? */
250 for (i = 0; i < ARRAY_SIZE(clock_cfgs); i++) {
251 if (wm8955->fs != clock_cfgs[i].fs)
252 continue;
253 sr = i;
254
255 if (wm8955->mclk_rate == clock_cfgs[i].mclk)
256 break;
257 }
258
259 /* We should never get here with an unsupported sample rate */
260 if (sr == -1) {
261 dev_err(codec->dev, "Sample rate %dHz unsupported\n",
262 wm8955->fs);
263 WARN_ON(sr == -1);
264 return -EINVAL;
265 }
266
267 if (i == ARRAY_SIZE(clock_cfgs)) {
268 /* If we can't generate the right clock from MCLK then
269 * we should configure the PLL to supply us with an
270 * appropriate clock.
271 */
272 clocking |= WM8955_MCLKSEL;
273
274 /* Use the last divider configuration we saw for the
275 * sample rate. */
276 ret = wm8995_pll_factors(codec->dev, wm8955->mclk_rate,
277 clock_cfgs[sr].mclk, &pll);
278 if (ret != 0) {
279 dev_err(codec->dev,
280 "Unable to generate %dHz from %dHz MCLK\n",
281 wm8955->fs, wm8955->mclk_rate);
282 return -EINVAL;
283 }
284
285 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_1,
286 WM8955_N_MASK | WM8955_K_21_18_MASK,
287 (pll.n << WM8955_N_SHIFT) |
288 pll.k >> 18);
289 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
290 WM8955_K_17_9_MASK,
291 (pll.k >> 9) & WM8955_K_17_9_MASK);
292 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
293 WM8955_K_8_0_MASK,
294 pll.k & WM8955_K_8_0_MASK);
295 if (pll.k)
296 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
297 WM8955_KEN, WM8955_KEN);
298 else
299 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
300 WM8955_KEN, 0);
301
302 if (pll.outdiv)
303 val = WM8955_PLL_RB | WM8955_PLLOUTDIV2;
304 else
305 val = WM8955_PLL_RB;
306
307 /* Now start the PLL running */
308 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
309 WM8955_PLL_RB | WM8955_PLLOUTDIV2, val);
310 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
311 WM8955_PLLEN, WM8955_PLLEN);
312 }
313
314 srate = clock_cfgs[sr].usb | (clock_cfgs[sr].sr << WM8955_SR_SHIFT);
315
316 snd_soc_update_bits(codec, WM8955_SAMPLE_RATE,
317 WM8955_USB | WM8955_SR_MASK, srate);
318 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
319 WM8955_MCLKSEL, clocking);
320
321 return 0;
322 }
323
324 static int wm8955_sysclk(struct snd_soc_dapm_widget *w,
325 struct snd_kcontrol *kcontrol, int event)
326 {
327 struct snd_soc_codec *codec = w->codec;
328 int ret = 0;
329
330 /* Always disable the clocks - if we're doing reconfiguration this
331 * avoids misclocking.
332 */
333 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
334 WM8955_DIGENB, 0);
335 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
336 WM8955_PLL_RB | WM8955_PLLEN, 0);
337
338 switch (event) {
339 case SND_SOC_DAPM_POST_PMD:
340 break;
341 case SND_SOC_DAPM_PRE_PMU:
342 ret = wm8955_configure_clocking(codec);
343 break;
344 default:
345 ret = -EINVAL;
346 break;
347 }
348
349 return ret;
350 }
351
352 static int deemph_settings[] = { 0, 32000, 44100, 48000 };
353
354 static int wm8955_set_deemph(struct snd_soc_codec *codec)
355 {
356 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
357 int val, i, best;
358
359 /* If we're using deemphasis select the nearest available sample
360 * rate.
361 */
362 if (wm8955->deemph) {
363 best = 1;
364 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
365 if (abs(deemph_settings[i] - wm8955->fs) <
366 abs(deemph_settings[best] - wm8955->fs))
367 best = i;
368 }
369
370 val = best << WM8955_DEEMPH_SHIFT;
371 } else {
372 val = 0;
373 }
374
375 dev_dbg(codec->dev, "Set deemphasis %d\n", val);
376
377 return snd_soc_update_bits(codec, WM8955_DAC_CONTROL,
378 WM8955_DEEMPH_MASK, val);
379 }
380
381 static int wm8955_get_deemph(struct snd_kcontrol *kcontrol,
382 struct snd_ctl_elem_value *ucontrol)
383 {
384 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
385 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
386
387 ucontrol->value.enumerated.item[0] = wm8955->deemph;
388 return 0;
389 }
390
391 static int wm8955_put_deemph(struct snd_kcontrol *kcontrol,
392 struct snd_ctl_elem_value *ucontrol)
393 {
394 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
395 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
396 int deemph = ucontrol->value.enumerated.item[0];
397
398 if (deemph > 1)
399 return -EINVAL;
400
401 wm8955->deemph = deemph;
402
403 return wm8955_set_deemph(codec);
404 }
405
406 static const char *bass_mode_text[] = {
407 "Linear", "Adaptive",
408 };
409
410 static const struct soc_enum bass_mode =
411 SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 7, 2, bass_mode_text);
412
413 static const char *bass_cutoff_text[] = {
414 "Low", "High"
415 };
416
417 static const struct soc_enum bass_cutoff =
418 SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 6, 2, bass_cutoff_text);
419
420 static const char *treble_cutoff_text[] = {
421 "High", "Low"
422 };
423
424 static const struct soc_enum treble_cutoff =
425 SOC_ENUM_SINGLE(WM8955_TREBLE_CONTROL, 6, 2, treble_cutoff_text);
426
427 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
428 static const DECLARE_TLV_DB_SCALE(atten_tlv, -600, 600, 0);
429 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
430 static const DECLARE_TLV_DB_SCALE(mono_tlv, -2100, 300, 0);
431 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
432 static const DECLARE_TLV_DB_SCALE(treble_tlv, -1200, 150, 1);
433
434 static const struct snd_kcontrol_new wm8955_snd_controls[] = {
435 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8955_LEFT_DAC_VOLUME,
436 WM8955_RIGHT_DAC_VOLUME, 0, 255, 0, digital_tlv),
437 SOC_SINGLE_TLV("Playback Attenuation Volume", WM8955_DAC_CONTROL, 7, 1, 1,
438 atten_tlv),
439 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
440 wm8955_get_deemph, wm8955_put_deemph),
441
442 SOC_ENUM("Bass Mode", bass_mode),
443 SOC_ENUM("Bass Cutoff", bass_cutoff),
444 SOC_SINGLE("Bass Volume", WM8955_BASS_CONTROL, 0, 15, 1),
445
446 SOC_ENUM("Treble Cutoff", treble_cutoff),
447 SOC_SINGLE_TLV("Treble Volume", WM8955_TREBLE_CONTROL, 0, 14, 1, treble_tlv),
448
449 SOC_SINGLE_TLV("Left Bypass Volume", WM8955_LEFT_OUT_MIX_1, 4, 7, 1,
450 bypass_tlv),
451 SOC_SINGLE_TLV("Left Mono Volume", WM8955_LEFT_OUT_MIX_2, 4, 7, 1,
452 bypass_tlv),
453
454 SOC_SINGLE_TLV("Right Mono Volume", WM8955_RIGHT_OUT_MIX_1, 4, 7, 1,
455 bypass_tlv),
456 SOC_SINGLE_TLV("Right Bypass Volume", WM8955_RIGHT_OUT_MIX_2, 4, 7, 1,
457 bypass_tlv),
458
459 /* Not a stereo pair so they line up with the DAPM switches */
460 SOC_SINGLE_TLV("Mono Left Bypass Volume", WM8955_MONO_OUT_MIX_1, 4, 7, 1,
461 mono_tlv),
462 SOC_SINGLE_TLV("Mono Right Bypass Volume", WM8955_MONO_OUT_MIX_2, 4, 7, 1,
463 mono_tlv),
464
465 SOC_DOUBLE_R_TLV("Headphone Volume", WM8955_LOUT1_VOLUME,
466 WM8955_ROUT1_VOLUME, 0, 127, 0, out_tlv),
467 SOC_DOUBLE_R("Headphone ZC Switch", WM8955_LOUT1_VOLUME,
468 WM8955_ROUT1_VOLUME, 7, 1, 0),
469
470 SOC_DOUBLE_R_TLV("Speaker Volume", WM8955_LOUT2_VOLUME,
471 WM8955_ROUT2_VOLUME, 0, 127, 0, out_tlv),
472 SOC_DOUBLE_R("Speaker ZC Switch", WM8955_LOUT2_VOLUME,
473 WM8955_ROUT2_VOLUME, 7, 1, 0),
474
475 SOC_SINGLE_TLV("Mono Volume", WM8955_MONOOUT_VOLUME, 0, 127, 0, out_tlv),
476 SOC_SINGLE("Mono ZC Switch", WM8955_MONOOUT_VOLUME, 7, 1, 0),
477 };
478
479 static const struct snd_kcontrol_new lmixer[] = {
480 SOC_DAPM_SINGLE("Playback Switch", WM8955_LEFT_OUT_MIX_1, 8, 1, 0),
481 SOC_DAPM_SINGLE("Bypass Switch", WM8955_LEFT_OUT_MIX_1, 7, 1, 0),
482 SOC_DAPM_SINGLE("Right Playback Switch", WM8955_LEFT_OUT_MIX_2, 8, 1, 0),
483 SOC_DAPM_SINGLE("Mono Switch", WM8955_LEFT_OUT_MIX_2, 7, 1, 0),
484 };
485
486 static const struct snd_kcontrol_new rmixer[] = {
487 SOC_DAPM_SINGLE("Left Playback Switch", WM8955_RIGHT_OUT_MIX_1, 8, 1, 0),
488 SOC_DAPM_SINGLE("Mono Switch", WM8955_RIGHT_OUT_MIX_1, 7, 1, 0),
489 SOC_DAPM_SINGLE("Playback Switch", WM8955_RIGHT_OUT_MIX_2, 8, 1, 0),
490 SOC_DAPM_SINGLE("Bypass Switch", WM8955_RIGHT_OUT_MIX_2, 7, 1, 0),
491 };
492
493 static const struct snd_kcontrol_new mmixer[] = {
494 SOC_DAPM_SINGLE("Left Playback Switch", WM8955_MONO_OUT_MIX_1, 8, 1, 0),
495 SOC_DAPM_SINGLE("Left Bypass Switch", WM8955_MONO_OUT_MIX_1, 7, 1, 0),
496 SOC_DAPM_SINGLE("Right Playback Switch", WM8955_MONO_OUT_MIX_2, 8, 1, 0),
497 SOC_DAPM_SINGLE("Right Bypass Switch", WM8955_MONO_OUT_MIX_2, 7, 1, 0),
498 };
499
500 static const struct snd_soc_dapm_widget wm8955_dapm_widgets[] = {
501 SND_SOC_DAPM_INPUT("MONOIN-"),
502 SND_SOC_DAPM_INPUT("MONOIN+"),
503 SND_SOC_DAPM_INPUT("LINEINR"),
504 SND_SOC_DAPM_INPUT("LINEINL"),
505
506 SND_SOC_DAPM_PGA("Mono Input", SND_SOC_NOPM, 0, 0, NULL, 0),
507
508 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8955_POWER_MANAGEMENT_1, 0, 1, wm8955_sysclk,
509 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
510 SND_SOC_DAPM_SUPPLY("TSDEN", WM8955_ADDITIONAL_CONTROL_1, 8, 0, NULL, 0),
511
512 SND_SOC_DAPM_DAC("DACL", "Playback", WM8955_POWER_MANAGEMENT_2, 8, 0),
513 SND_SOC_DAPM_DAC("DACR", "Playback", WM8955_POWER_MANAGEMENT_2, 7, 0),
514
515 SND_SOC_DAPM_PGA("LOUT1 PGA", WM8955_POWER_MANAGEMENT_2, 6, 0, NULL, 0),
516 SND_SOC_DAPM_PGA("ROUT1 PGA", WM8955_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
517 SND_SOC_DAPM_PGA("LOUT2 PGA", WM8955_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
518 SND_SOC_DAPM_PGA("ROUT2 PGA", WM8955_POWER_MANAGEMENT_2, 3, 0, NULL, 0),
519 SND_SOC_DAPM_PGA("MOUT PGA", WM8955_POWER_MANAGEMENT_2, 2, 0, NULL, 0),
520 SND_SOC_DAPM_PGA("OUT3 PGA", WM8955_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
521
522 /* The names are chosen to make the control names nice */
523 SND_SOC_DAPM_MIXER("Left", SND_SOC_NOPM, 0, 0,
524 lmixer, ARRAY_SIZE(lmixer)),
525 SND_SOC_DAPM_MIXER("Right", SND_SOC_NOPM, 0, 0,
526 rmixer, ARRAY_SIZE(rmixer)),
527 SND_SOC_DAPM_MIXER("Mono", SND_SOC_NOPM, 0, 0,
528 mmixer, ARRAY_SIZE(mmixer)),
529
530 SND_SOC_DAPM_OUTPUT("LOUT1"),
531 SND_SOC_DAPM_OUTPUT("ROUT1"),
532 SND_SOC_DAPM_OUTPUT("LOUT2"),
533 SND_SOC_DAPM_OUTPUT("ROUT2"),
534 SND_SOC_DAPM_OUTPUT("MONOOUT"),
535 SND_SOC_DAPM_OUTPUT("OUT3"),
536 };
537
538 static const struct snd_soc_dapm_route wm8955_intercon[] = {
539 { "DACL", NULL, "SYSCLK" },
540 { "DACR", NULL, "SYSCLK" },
541
542 { "Mono Input", NULL, "MONOIN-" },
543 { "Mono Input", NULL, "MONOIN+" },
544
545 { "Left", "Playback Switch", "DACL" },
546 { "Left", "Right Playback Switch", "DACR" },
547 { "Left", "Bypass Switch", "LINEINL" },
548 { "Left", "Mono Switch", "Mono Input" },
549
550 { "Right", "Playback Switch", "DACR" },
551 { "Right", "Left Playback Switch", "DACL" },
552 { "Right", "Bypass Switch", "LINEINR" },
553 { "Right", "Mono Switch", "Mono Input" },
554
555 { "Mono", "Left Playback Switch", "DACL" },
556 { "Mono", "Right Playback Switch", "DACR" },
557 { "Mono", "Left Bypass Switch", "LINEINL" },
558 { "Mono", "Right Bypass Switch", "LINEINR" },
559
560 { "LOUT1 PGA", NULL, "Left" },
561 { "LOUT1", NULL, "TSDEN" },
562 { "LOUT1", NULL, "LOUT1 PGA" },
563
564 { "ROUT1 PGA", NULL, "Right" },
565 { "ROUT1", NULL, "TSDEN" },
566 { "ROUT1", NULL, "ROUT1 PGA" },
567
568 { "LOUT2 PGA", NULL, "Left" },
569 { "LOUT2", NULL, "TSDEN" },
570 { "LOUT2", NULL, "LOUT2 PGA" },
571
572 { "ROUT2 PGA", NULL, "Right" },
573 { "ROUT2", NULL, "TSDEN" },
574 { "ROUT2", NULL, "ROUT2 PGA" },
575
576 { "MOUT PGA", NULL, "Mono" },
577 { "MONOOUT", NULL, "MOUT PGA" },
578
579 /* OUT3 not currently implemented */
580 { "OUT3", NULL, "OUT3 PGA" },
581 };
582
583 static int wm8955_add_widgets(struct snd_soc_codec *codec)
584 {
585 snd_soc_add_controls(codec, wm8955_snd_controls,
586 ARRAY_SIZE(wm8955_snd_controls));
587
588 snd_soc_dapm_new_controls(codec, wm8955_dapm_widgets,
589 ARRAY_SIZE(wm8955_dapm_widgets));
590
591 snd_soc_dapm_add_routes(codec, wm8955_intercon,
592 ARRAY_SIZE(wm8955_intercon));
593
594 return 0;
595 }
596
597 static int wm8955_hw_params(struct snd_pcm_substream *substream,
598 struct snd_pcm_hw_params *params,
599 struct snd_soc_dai *dai)
600 {
601 struct snd_soc_codec *codec = dai->codec;
602 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
603 int ret;
604 int wl;
605
606 switch (params_format(params)) {
607 case SNDRV_PCM_FORMAT_S16_LE:
608 wl = 0;
609 break;
610 case SNDRV_PCM_FORMAT_S20_3LE:
611 wl = 0x4;
612 break;
613 case SNDRV_PCM_FORMAT_S24_LE:
614 wl = 0x8;
615 break;
616 case SNDRV_PCM_FORMAT_S32_LE:
617 wl = 0xc;
618 break;
619 default:
620 return -EINVAL;
621 }
622 snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE,
623 WM8955_WL_MASK, wl);
624
625 wm8955->fs = params_rate(params);
626 wm8955_set_deemph(codec);
627
628 /* If the chip is clocked then disable the clocks and force a
629 * reconfiguration, otherwise DAPM will power up the
630 * clocks for us later. */
631 ret = snd_soc_read(codec, WM8955_POWER_MANAGEMENT_1);
632 if (ret < 0)
633 return ret;
634 if (ret & WM8955_DIGENB) {
635 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
636 WM8955_DIGENB, 0);
637 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
638 WM8955_PLL_RB | WM8955_PLLEN, 0);
639
640 wm8955_configure_clocking(codec);
641 }
642
643 return 0;
644 }
645
646
647 static int wm8955_set_sysclk(struct snd_soc_dai *dai, int clk_id,
648 unsigned int freq, int dir)
649 {
650 struct snd_soc_codec *codec = dai->codec;
651 struct wm8955_priv *priv = snd_soc_codec_get_drvdata(codec);
652 int div;
653
654 switch (clk_id) {
655 case WM8955_CLK_MCLK:
656 if (freq > 15000000) {
657 priv->mclk_rate = freq /= 2;
658 div = WM8955_MCLKDIV2;
659 } else {
660 priv->mclk_rate = freq;
661 div = 0;
662 }
663
664 snd_soc_update_bits(codec, WM8955_SAMPLE_RATE,
665 WM8955_MCLKDIV2, div);
666 break;
667
668 default:
669 return -EINVAL;
670 }
671
672 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
673
674 return 0;
675 }
676
677 static int wm8955_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
678 {
679 struct snd_soc_codec *codec = dai->codec;
680 u16 aif = 0;
681
682 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
683 case SND_SOC_DAIFMT_CBS_CFS:
684 break;
685 case SND_SOC_DAIFMT_CBM_CFM:
686 aif |= WM8955_MS;
687 break;
688 default:
689 return -EINVAL;
690 }
691
692 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
693 case SND_SOC_DAIFMT_DSP_B:
694 aif |= WM8955_LRP;
695 case SND_SOC_DAIFMT_DSP_A:
696 aif |= 0x3;
697 break;
698 case SND_SOC_DAIFMT_I2S:
699 aif |= 0x2;
700 break;
701 case SND_SOC_DAIFMT_RIGHT_J:
702 break;
703 case SND_SOC_DAIFMT_LEFT_J:
704 aif |= 0x1;
705 break;
706 default:
707 return -EINVAL;
708 }
709
710 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
711 case SND_SOC_DAIFMT_DSP_A:
712 case SND_SOC_DAIFMT_DSP_B:
713 /* frame inversion not valid for DSP modes */
714 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
715 case SND_SOC_DAIFMT_NB_NF:
716 break;
717 case SND_SOC_DAIFMT_IB_NF:
718 aif |= WM8955_BCLKINV;
719 break;
720 default:
721 return -EINVAL;
722 }
723 break;
724
725 case SND_SOC_DAIFMT_I2S:
726 case SND_SOC_DAIFMT_RIGHT_J:
727 case SND_SOC_DAIFMT_LEFT_J:
728 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
729 case SND_SOC_DAIFMT_NB_NF:
730 break;
731 case SND_SOC_DAIFMT_IB_IF:
732 aif |= WM8955_BCLKINV | WM8955_LRP;
733 break;
734 case SND_SOC_DAIFMT_IB_NF:
735 aif |= WM8955_BCLKINV;
736 break;
737 case SND_SOC_DAIFMT_NB_IF:
738 aif |= WM8955_LRP;
739 break;
740 default:
741 return -EINVAL;
742 }
743 break;
744 default:
745 return -EINVAL;
746 }
747
748 snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE,
749 WM8955_MS | WM8955_FORMAT_MASK | WM8955_BCLKINV |
750 WM8955_LRP, aif);
751
752 return 0;
753 }
754
755
756 static int wm8955_digital_mute(struct snd_soc_dai *codec_dai, int mute)
757 {
758 struct snd_soc_codec *codec = codec_dai->codec;
759 int val;
760
761 if (mute)
762 val = WM8955_DACMU;
763 else
764 val = 0;
765
766 snd_soc_update_bits(codec, WM8955_DAC_CONTROL, WM8955_DACMU, val);
767
768 return 0;
769 }
770
771 static int wm8955_set_bias_level(struct snd_soc_codec *codec,
772 enum snd_soc_bias_level level)
773 {
774 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
775 int ret, i;
776
777 switch (level) {
778 case SND_SOC_BIAS_ON:
779 break;
780
781 case SND_SOC_BIAS_PREPARE:
782 /* VMID resistance 2*50k */
783 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
784 WM8955_VMIDSEL_MASK,
785 0x1 << WM8955_VMIDSEL_SHIFT);
786
787 /* Default bias current */
788 snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1,
789 WM8955_VSEL_MASK,
790 0x2 << WM8955_VSEL_SHIFT);
791 break;
792
793 case SND_SOC_BIAS_STANDBY:
794 if (codec->bias_level == SND_SOC_BIAS_OFF) {
795 ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
796 wm8955->supplies);
797 if (ret != 0) {
798 dev_err(codec->dev,
799 "Failed to enable supplies: %d\n",
800 ret);
801 return ret;
802 }
803
804 /* Sync back cached values if they're
805 * different from the hardware default.
806 */
807 for (i = 0; i < ARRAY_SIZE(wm8955->reg_cache); i++) {
808 if (i == WM8955_RESET)
809 continue;
810
811 if (wm8955->reg_cache[i] == wm8955_reg[i])
812 continue;
813
814 snd_soc_write(codec, i, wm8955->reg_cache[i]);
815 }
816
817 /* Enable VREF and VMID */
818 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
819 WM8955_VREF |
820 WM8955_VMIDSEL_MASK,
821 WM8955_VREF |
822 0x3 << WM8955_VREF_SHIFT);
823
824 /* Let VMID ramp */
825 msleep(500);
826
827 /* High resistance VROI to maintain outputs */
828 snd_soc_update_bits(codec,
829 WM8955_ADDITIONAL_CONTROL_3,
830 WM8955_VROI, WM8955_VROI);
831 }
832
833 /* Maintain VMID with 2*250k */
834 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
835 WM8955_VMIDSEL_MASK,
836 0x2 << WM8955_VMIDSEL_SHIFT);
837
838 /* Minimum bias current */
839 snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1,
840 WM8955_VSEL_MASK, 0);
841 break;
842
843 case SND_SOC_BIAS_OFF:
844 /* Low resistance VROI to help discharge */
845 snd_soc_update_bits(codec,
846 WM8955_ADDITIONAL_CONTROL_3,
847 WM8955_VROI, 0);
848
849 /* Turn off VMID and VREF */
850 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
851 WM8955_VREF |
852 WM8955_VMIDSEL_MASK, 0);
853
854 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies),
855 wm8955->supplies);
856 break;
857 }
858 codec->bias_level = level;
859 return 0;
860 }
861
862 #define WM8955_RATES SNDRV_PCM_RATE_8000_96000
863
864 #define WM8955_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
865 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
866
867 static struct snd_soc_dai_ops wm8955_dai_ops = {
868 .set_sysclk = wm8955_set_sysclk,
869 .set_fmt = wm8955_set_fmt,
870 .hw_params = wm8955_hw_params,
871 .digital_mute = wm8955_digital_mute,
872 };
873
874 struct snd_soc_dai wm8955_dai = {
875 .name = "WM8955",
876 .playback = {
877 .stream_name = "Playback",
878 .channels_min = 2,
879 .channels_max = 2,
880 .rates = WM8955_RATES,
881 .formats = WM8955_FORMATS,
882 },
883 .ops = &wm8955_dai_ops,
884 };
885 EXPORT_SYMBOL_GPL(wm8955_dai);
886
887 #ifdef CONFIG_PM
888 static int wm8955_suspend(struct platform_device *pdev, pm_message_t state)
889 {
890 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
891 struct snd_soc_codec *codec = socdev->card->codec;
892
893 wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF);
894
895 return 0;
896 }
897
898 static int wm8955_resume(struct platform_device *pdev)
899 {
900 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
901 struct snd_soc_codec *codec = socdev->card->codec;
902
903 wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
904
905 return 0;
906 }
907 #else
908 #define wm8955_suspend NULL
909 #define wm8955_resume NULL
910 #endif
911
912 static int wm8955_probe(struct platform_device *pdev)
913 {
914 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
915 struct snd_soc_codec *codec;
916 int ret = 0;
917
918 if (wm8955_codec == NULL) {
919 dev_err(&pdev->dev, "Codec device not registered\n");
920 return -ENODEV;
921 }
922
923 socdev->card->codec = wm8955_codec;
924 codec = wm8955_codec;
925
926 /* register pcms */
927 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
928 if (ret < 0) {
929 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
930 goto pcm_err;
931 }
932
933 wm8955_add_widgets(codec);
934
935 return ret;
936
937 pcm_err:
938 return ret;
939 }
940
941 static int wm8955_remove(struct platform_device *pdev)
942 {
943 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
944
945 snd_soc_free_pcms(socdev);
946 snd_soc_dapm_free(socdev);
947
948 return 0;
949 }
950
951 struct snd_soc_codec_device soc_codec_dev_wm8955 = {
952 .probe = wm8955_probe,
953 .remove = wm8955_remove,
954 .suspend = wm8955_suspend,
955 .resume = wm8955_resume,
956 };
957 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8955);
958
959 static int wm8955_register(struct wm8955_priv *wm8955,
960 enum snd_soc_control_type control)
961 {
962 int ret;
963 struct snd_soc_codec *codec = &wm8955->codec;
964 int i;
965
966 if (wm8955_codec) {
967 dev_err(codec->dev, "Another WM8955 is registered\n");
968 ret = -EINVAL;
969 goto err;
970 }
971
972 mutex_init(&codec->mutex);
973 INIT_LIST_HEAD(&codec->dapm_widgets);
974 INIT_LIST_HEAD(&codec->dapm_paths);
975
976 snd_soc_codec_set_drvdata(codec, wm8955);
977 codec->name = "WM8955";
978 codec->owner = THIS_MODULE;
979 codec->bias_level = SND_SOC_BIAS_OFF;
980 codec->set_bias_level = wm8955_set_bias_level;
981 codec->dai = &wm8955_dai;
982 codec->num_dai = 1;
983 codec->reg_cache_size = WM8955_MAX_REGISTER;
984 codec->reg_cache = &wm8955->reg_cache;
985
986 memcpy(codec->reg_cache, wm8955_reg, sizeof(wm8955_reg));
987
988 ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
989 if (ret != 0) {
990 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
991 goto err;
992 }
993
994 for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++)
995 wm8955->supplies[i].supply = wm8955_supply_names[i];
996
997 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8955->supplies),
998 wm8955->supplies);
999 if (ret != 0) {
1000 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1001 goto err;
1002 }
1003
1004 ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
1005 wm8955->supplies);
1006 if (ret != 0) {
1007 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1008 goto err_get;
1009 }
1010
1011 ret = wm8955_reset(codec);
1012 if (ret < 0) {
1013 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
1014 goto err_enable;
1015 }
1016
1017 wm8955_dai.dev = codec->dev;
1018
1019 /* Change some default settings - latch VU and enable ZC */
1020 wm8955->reg_cache[WM8955_LEFT_DAC_VOLUME] |= WM8955_LDVU;
1021 wm8955->reg_cache[WM8955_RIGHT_DAC_VOLUME] |= WM8955_RDVU;
1022 wm8955->reg_cache[WM8955_LOUT1_VOLUME] |= WM8955_LO1VU | WM8955_LO1ZC;
1023 wm8955->reg_cache[WM8955_ROUT1_VOLUME] |= WM8955_RO1VU | WM8955_RO1ZC;
1024 wm8955->reg_cache[WM8955_LOUT2_VOLUME] |= WM8955_LO2VU | WM8955_LO2ZC;
1025 wm8955->reg_cache[WM8955_ROUT2_VOLUME] |= WM8955_RO2VU | WM8955_RO2ZC;
1026 wm8955->reg_cache[WM8955_MONOOUT_VOLUME] |= WM8955_MOZC;
1027
1028 /* Also enable adaptive bass boost by default */
1029 wm8955->reg_cache[WM8955_BASS_CONTROL] |= WM8955_BB;
1030
1031 /* Set platform data values */
1032 if (wm8955->pdata) {
1033 if (wm8955->pdata->out2_speaker)
1034 wm8955->reg_cache[WM8955_ADDITIONAL_CONTROL_2]
1035 |= WM8955_ROUT2INV;
1036
1037 if (wm8955->pdata->monoin_diff)
1038 wm8955->reg_cache[WM8955_MONO_OUT_MIX_1]
1039 |= WM8955_DMEN;
1040 }
1041
1042 wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1043
1044 /* Bias level configuration will have done an extra enable */
1045 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
1046
1047 wm8955_codec = codec;
1048
1049 ret = snd_soc_register_codec(codec);
1050 if (ret != 0) {
1051 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1052 goto err_enable;
1053 }
1054
1055 ret = snd_soc_register_dai(&wm8955_dai);
1056 if (ret != 0) {
1057 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1058 goto err_codec;
1059 }
1060
1061 return 0;
1062
1063 err_codec:
1064 snd_soc_unregister_codec(codec);
1065 err_enable:
1066 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
1067 err_get:
1068 regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
1069 err:
1070 kfree(wm8955);
1071 return ret;
1072 }
1073
1074 static void wm8955_unregister(struct wm8955_priv *wm8955)
1075 {
1076 wm8955_set_bias_level(&wm8955->codec, SND_SOC_BIAS_OFF);
1077 regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
1078 snd_soc_unregister_dai(&wm8955_dai);
1079 snd_soc_unregister_codec(&wm8955->codec);
1080 kfree(wm8955);
1081 wm8955_codec = NULL;
1082 }
1083
1084 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1085 static __devinit int wm8955_i2c_probe(struct i2c_client *i2c,
1086 const struct i2c_device_id *id)
1087 {
1088 struct wm8955_priv *wm8955;
1089 struct snd_soc_codec *codec;
1090
1091 wm8955 = kzalloc(sizeof(struct wm8955_priv), GFP_KERNEL);
1092 if (wm8955 == NULL)
1093 return -ENOMEM;
1094
1095 codec = &wm8955->codec;
1096 codec->hw_write = (hw_write_t)i2c_master_send;
1097
1098 i2c_set_clientdata(i2c, wm8955);
1099 codec->control_data = i2c;
1100 wm8955->pdata = i2c->dev.platform_data;
1101
1102 codec->dev = &i2c->dev;
1103
1104 return wm8955_register(wm8955, SND_SOC_I2C);
1105 }
1106
1107 static __devexit int wm8955_i2c_remove(struct i2c_client *client)
1108 {
1109 struct wm8955_priv *wm8955 = i2c_get_clientdata(client);
1110 wm8955_unregister(wm8955);
1111 return 0;
1112 }
1113
1114 static const struct i2c_device_id wm8955_i2c_id[] = {
1115 { "wm8955", 0 },
1116 { }
1117 };
1118 MODULE_DEVICE_TABLE(i2c, wm8955_i2c_id);
1119
1120 static struct i2c_driver wm8955_i2c_driver = {
1121 .driver = {
1122 .name = "wm8955",
1123 .owner = THIS_MODULE,
1124 },
1125 .probe = wm8955_i2c_probe,
1126 .remove = __devexit_p(wm8955_i2c_remove),
1127 .id_table = wm8955_i2c_id,
1128 };
1129 #endif
1130
1131 static int __init wm8955_modinit(void)
1132 {
1133 int ret;
1134 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1135 ret = i2c_add_driver(&wm8955_i2c_driver);
1136 if (ret != 0) {
1137 printk(KERN_ERR "Failed to register WM8955 I2C driver: %d\n",
1138 ret);
1139 }
1140 #endif
1141 return 0;
1142 }
1143 module_init(wm8955_modinit);
1144
1145 static void __exit wm8955_exit(void)
1146 {
1147 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1148 i2c_del_driver(&wm8955_i2c_driver);
1149 #endif
1150 }
1151 module_exit(wm8955_exit);
1152
1153 MODULE_DESCRIPTION("ASoC WM8955 driver");
1154 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1155 MODULE_LICENSE("GPL");
Tomato firmware and modifications.