2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
6 * Copyright: (C) 2009 Nokia Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/platform_device.h>
31 #include <linux/interrupt.h>
32 #include <linux/gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/slab.h>
35 #include <sound/core.h>
36 #include <sound/pcm.h>
37 #include <sound/pcm_params.h>
38 #include <sound/soc.h>
39 #include <sound/soc-dapm.h>
40 #include <sound/initval.h>
41 #include <sound/tlv.h>
43 #include <sound/tlv320dac33-plat.h>
44 #include "tlv320dac33.h"
46 #define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
48 #define DAC33_BUFFER_SIZE_SAMPLES 6144
50 #define NSAMPLE_MAX 5700
53 #define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10)
55 #define BURST_BASEFREQ_HZ 49152000
57 #define SAMPLES_TO_US(rate, samples) \
58 (1000000000 / ((rate * 1000) / samples))
60 #define US_TO_SAMPLES(rate, us) \
61 (rate / (1000000 / us))
63 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
64 ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
66 static void dac33_calculate_times(struct snd_pcm_substream
*substream
);
67 static int dac33_prepare_chip(struct snd_pcm_substream
*substream
);
69 static struct snd_soc_codec
*tlv320dac33_codec
;
78 enum dac33_fifo_modes
{
79 DAC33_FIFO_BYPASS
= 0,
85 #define DAC33_NUM_SUPPLIES 3
86 static const char *dac33_supply_names
[DAC33_NUM_SUPPLIES
] = {
92 struct tlv320dac33_priv
{
94 struct workqueue_struct
*dac33_wq
;
95 struct work_struct work
;
96 struct snd_soc_codec codec
;
97 struct regulator_bulk_data supplies
[DAC33_NUM_SUPPLIES
];
98 struct snd_pcm_substream
*substream
;
104 unsigned int alarm_threshold
; /* set to be half of LATENCY_TIME_MS */
105 unsigned int nsample_min
; /* nsample should not be lower than
107 unsigned int nsample_max
; /* nsample should not be higher than
109 enum dac33_fifo_modes fifo_mode
;/* FIFO mode selection */
110 unsigned int nsample
; /* burst read amount from host */
111 int mode1_latency
; /* latency caused by the i2c writes in
113 int auto_fifo_config
; /* Configure the FIFO based on the
115 u8 burst_bclkdiv
; /* BCLK divider value in burst mode */
116 unsigned int burst_rate
; /* Interface speed in Burst modes */
118 int keep_bclk
; /* Keep the BCLK continuously running
121 unsigned long long t_stamp1
; /* Time stamp for FIFO modes to */
122 unsigned long long t_stamp2
; /* calculate the FIFO caused delay */
124 unsigned int mode1_us_burst
; /* Time to burst read n number of
126 unsigned int mode7_us_to_lthr
; /* Time to reach lthr from uthr */
130 enum dac33_state state
;
133 static const u8 dac33_reg
[DAC33_CACHEREGNUM
] = {
134 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
135 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
136 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
137 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
138 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
139 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
140 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
141 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
142 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
143 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
144 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
145 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
146 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
147 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
148 0x00, 0x00, /* 0x38 - 0x39 */
149 /* Registers 0x3a - 0x3f are reserved */
150 0x00, 0x00, /* 0x3a - 0x3b */
151 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
153 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
154 0x00, 0x80, /* 0x44 - 0x45 */
155 /* Registers 0x46 - 0x47 are reserved */
156 0x80, 0x80, /* 0x46 - 0x47 */
158 0x80, 0x00, 0x00, /* 0x48 - 0x4a */
159 /* Registers 0x4b - 0x7c are reserved */
161 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
162 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
163 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
164 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
165 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
166 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
167 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
168 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
169 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
170 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
171 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
172 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
175 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
178 /* Register read and write */
179 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec
*codec
,
182 u8
*cache
= codec
->reg_cache
;
183 if (reg
>= DAC33_CACHEREGNUM
)
189 static inline void dac33_write_reg_cache(struct snd_soc_codec
*codec
,
192 u8
*cache
= codec
->reg_cache
;
193 if (reg
>= DAC33_CACHEREGNUM
)
199 static int dac33_read(struct snd_soc_codec
*codec
, unsigned int reg
,
202 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
207 /* If powered off, return the cached value */
208 if (dac33
->chip_power
) {
209 val
= i2c_smbus_read_byte_data(codec
->control_data
, value
[0]);
211 dev_err(codec
->dev
, "Read failed (%d)\n", val
);
212 value
[0] = dac33_read_reg_cache(codec
, reg
);
215 dac33_write_reg_cache(codec
, reg
, val
);
218 value
[0] = dac33_read_reg_cache(codec
, reg
);
224 static int dac33_write(struct snd_soc_codec
*codec
, unsigned int reg
,
227 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
233 * D15..D8 dac33 register offset
234 * D7...D0 register data
236 data
[0] = reg
& 0xff;
237 data
[1] = value
& 0xff;
239 dac33_write_reg_cache(codec
, data
[0], data
[1]);
240 if (dac33
->chip_power
) {
241 ret
= codec
->hw_write(codec
->control_data
, data
, 2);
243 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
251 static int dac33_write_locked(struct snd_soc_codec
*codec
, unsigned int reg
,
254 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
257 mutex_lock(&dac33
->mutex
);
258 ret
= dac33_write(codec
, reg
, value
);
259 mutex_unlock(&dac33
->mutex
);
264 #define DAC33_I2C_ADDR_AUTOINC 0x80
265 static int dac33_write16(struct snd_soc_codec
*codec
, unsigned int reg
,
268 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
274 * D23..D16 dac33 register offset
275 * D15..D8 register data MSB
276 * D7...D0 register data LSB
278 data
[0] = reg
& 0xff;
279 data
[1] = (value
>> 8) & 0xff;
280 data
[2] = value
& 0xff;
282 dac33_write_reg_cache(codec
, data
[0], data
[1]);
283 dac33_write_reg_cache(codec
, data
[0] + 1, data
[2]);
285 if (dac33
->chip_power
) {
286 /* We need to set autoincrement mode for 16 bit writes */
287 data
[0] |= DAC33_I2C_ADDR_AUTOINC
;
288 ret
= codec
->hw_write(codec
->control_data
, data
, 3);
290 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
298 static void dac33_init_chip(struct snd_soc_codec
*codec
)
300 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
302 if (unlikely(!dac33
->chip_power
))
305 /* 44-46: DAC Control Registers */
306 /* A : DAC sample rate Fsref/1.5 */
307 dac33_write(codec
, DAC33_DAC_CTRL_A
, DAC33_DACRATE(0));
308 /* B : DAC src=normal, not muted */
309 dac33_write(codec
, DAC33_DAC_CTRL_B
, DAC33_DACSRCR_RIGHT
|
312 dac33_write(codec
, DAC33_DAC_CTRL_C
, 0x00);
314 /* 73 : volume soft stepping control,
315 clock source = internal osc (?) */
316 dac33_write(codec
, DAC33_ANA_VOL_SOFT_STEP_CTRL
, DAC33_VOLCLKEN
);
318 dac33_write(codec
, DAC33_PWR_CTRL
, DAC33_PDNALLB
);
320 /* Restore only selected registers (gains mostly) */
321 dac33_write(codec
, DAC33_LDAC_DIG_VOL_CTRL
,
322 dac33_read_reg_cache(codec
, DAC33_LDAC_DIG_VOL_CTRL
));
323 dac33_write(codec
, DAC33_RDAC_DIG_VOL_CTRL
,
324 dac33_read_reg_cache(codec
, DAC33_RDAC_DIG_VOL_CTRL
));
326 dac33_write(codec
, DAC33_LINEL_TO_LLO_VOL
,
327 dac33_read_reg_cache(codec
, DAC33_LINEL_TO_LLO_VOL
));
328 dac33_write(codec
, DAC33_LINER_TO_RLO_VOL
,
329 dac33_read_reg_cache(codec
, DAC33_LINER_TO_RLO_VOL
));
332 static inline void dac33_read_id(struct snd_soc_codec
*codec
)
336 dac33_read(codec
, DAC33_DEVICE_ID_MSB
, ®
);
337 dac33_read(codec
, DAC33_DEVICE_ID_LSB
, ®
);
338 dac33_read(codec
, DAC33_DEVICE_REV_ID
, ®
);
341 static inline void dac33_soft_power(struct snd_soc_codec
*codec
, int power
)
345 reg
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
347 reg
|= DAC33_PDNALLB
;
349 reg
&= ~(DAC33_PDNALLB
| DAC33_OSCPDNB
|
350 DAC33_DACRPDNB
| DAC33_DACLPDNB
);
351 dac33_write(codec
, DAC33_PWR_CTRL
, reg
);
354 static int dac33_hard_power(struct snd_soc_codec
*codec
, int power
)
356 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
359 mutex_lock(&dac33
->mutex
);
362 if (unlikely(power
== dac33
->chip_power
)) {
363 dev_dbg(codec
->dev
, "Trying to set the same power state: %s\n",
364 power
? "ON" : "OFF");
369 ret
= regulator_bulk_enable(ARRAY_SIZE(dac33
->supplies
),
373 "Failed to enable supplies: %d\n", ret
);
377 if (dac33
->power_gpio
>= 0)
378 gpio_set_value(dac33
->power_gpio
, 1);
380 dac33
->chip_power
= 1;
382 dac33_soft_power(codec
, 0);
383 if (dac33
->power_gpio
>= 0)
384 gpio_set_value(dac33
->power_gpio
, 0);
386 ret
= regulator_bulk_disable(ARRAY_SIZE(dac33
->supplies
),
390 "Failed to disable supplies: %d\n", ret
);
394 dac33
->chip_power
= 0;
398 mutex_unlock(&dac33
->mutex
);
402 static int playback_event(struct snd_soc_dapm_widget
*w
,
403 struct snd_kcontrol
*kcontrol
, int event
)
405 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(w
->codec
);
408 case SND_SOC_DAPM_PRE_PMU
:
409 if (likely(dac33
->substream
)) {
410 dac33_calculate_times(dac33
->substream
);
411 dac33_prepare_chip(dac33
->substream
);
418 static int dac33_get_nsample(struct snd_kcontrol
*kcontrol
,
419 struct snd_ctl_elem_value
*ucontrol
)
421 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
422 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
424 ucontrol
->value
.integer
.value
[0] = dac33
->nsample
;
429 static int dac33_set_nsample(struct snd_kcontrol
*kcontrol
,
430 struct snd_ctl_elem_value
*ucontrol
)
432 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
433 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
436 if (dac33
->nsample
== ucontrol
->value
.integer
.value
[0])
439 if (ucontrol
->value
.integer
.value
[0] < dac33
->nsample_min
||
440 ucontrol
->value
.integer
.value
[0] > dac33
->nsample_max
) {
443 dac33
->nsample
= ucontrol
->value
.integer
.value
[0];
444 /* Re calculate the burst time */
445 dac33
->mode1_us_burst
= SAMPLES_TO_US(dac33
->burst_rate
,
452 static int dac33_get_uthr(struct snd_kcontrol
*kcontrol
,
453 struct snd_ctl_elem_value
*ucontrol
)
455 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
456 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
458 ucontrol
->value
.integer
.value
[0] = dac33
->uthr
;
463 static int dac33_set_uthr(struct snd_kcontrol
*kcontrol
,
464 struct snd_ctl_elem_value
*ucontrol
)
466 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
467 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
470 if (dac33
->substream
)
473 if (dac33
->uthr
== ucontrol
->value
.integer
.value
[0])
476 if (ucontrol
->value
.integer
.value
[0] < (MODE7_LTHR
+ 10) ||
477 ucontrol
->value
.integer
.value
[0] > MODE7_UTHR
)
480 dac33
->uthr
= ucontrol
->value
.integer
.value
[0];
485 static int dac33_get_fifo_mode(struct snd_kcontrol
*kcontrol
,
486 struct snd_ctl_elem_value
*ucontrol
)
488 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
489 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
491 ucontrol
->value
.integer
.value
[0] = dac33
->fifo_mode
;
496 static int dac33_set_fifo_mode(struct snd_kcontrol
*kcontrol
,
497 struct snd_ctl_elem_value
*ucontrol
)
499 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
500 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
503 if (dac33
->fifo_mode
== ucontrol
->value
.integer
.value
[0])
505 /* Do not allow changes while stream is running*/
509 if (ucontrol
->value
.integer
.value
[0] < 0 ||
510 ucontrol
->value
.integer
.value
[0] >= DAC33_FIFO_LAST_MODE
)
513 dac33
->fifo_mode
= ucontrol
->value
.integer
.value
[0];
518 /* Codec operation modes */
519 static const char *dac33_fifo_mode_texts
[] = {
520 "Bypass", "Mode 1", "Mode 7"
523 static const struct soc_enum dac33_fifo_mode_enum
=
524 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts
),
525 dac33_fifo_mode_texts
);
528 * DACL/R digital volume control:
529 * from 0 dB to -63.5 in 0.5 dB steps
530 * Need to be inverted later on:
534 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv
, -6350, 50, 0);
536 static const struct snd_kcontrol_new dac33_snd_controls
[] = {
537 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
538 DAC33_LDAC_DIG_VOL_CTRL
, DAC33_RDAC_DIG_VOL_CTRL
,
539 0, 0x7f, 1, dac_digivol_tlv
),
540 SOC_DOUBLE_R("DAC Digital Playback Switch",
541 DAC33_LDAC_DIG_VOL_CTRL
, DAC33_RDAC_DIG_VOL_CTRL
, 7, 1, 1),
542 SOC_DOUBLE_R("Line to Line Out Volume",
543 DAC33_LINEL_TO_LLO_VOL
, DAC33_LINER_TO_RLO_VOL
, 0, 127, 1),
546 static const struct snd_kcontrol_new dac33_mode_snd_controls
[] = {
547 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum
,
548 dac33_get_fifo_mode
, dac33_set_fifo_mode
),
551 static const struct snd_kcontrol_new dac33_fifo_snd_controls
[] = {
552 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
553 dac33_get_nsample
, dac33_set_nsample
),
554 SOC_SINGLE_EXT("UTHR", 0, 0, MODE7_UTHR
, 0,
555 dac33_get_uthr
, dac33_set_uthr
),
559 static const struct snd_kcontrol_new dac33_dapm_abypassl_control
=
560 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL
, 7, 1, 1);
562 static const struct snd_kcontrol_new dac33_dapm_abypassr_control
=
563 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL
, 7, 1, 1);
565 static const struct snd_soc_dapm_widget dac33_dapm_widgets
[] = {
566 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
567 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
569 SND_SOC_DAPM_INPUT("LINEL"),
570 SND_SOC_DAPM_INPUT("LINER"),
572 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL
, 2, 0),
573 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL
, 2, 0),
576 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM
, 0, 0,
577 &dac33_dapm_abypassl_control
),
578 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM
, 0, 0,
579 &dac33_dapm_abypassr_control
),
581 SND_SOC_DAPM_REG(snd_soc_dapm_mixer
, "Output Left Amp Power",
582 DAC33_OUT_AMP_PWR_CTRL
, 6, 3, 3, 0),
583 SND_SOC_DAPM_REG(snd_soc_dapm_mixer
, "Output Right Amp Power",
584 DAC33_OUT_AMP_PWR_CTRL
, 4, 3, 3, 0),
586 SND_SOC_DAPM_PRE("Prepare Playback", playback_event
),
589 static const struct snd_soc_dapm_route audio_map
[] = {
591 {"Analog Left Bypass", "Switch", "LINEL"},
592 {"Analog Right Bypass", "Switch", "LINER"},
594 {"Output Left Amp Power", NULL
, "DACL"},
595 {"Output Right Amp Power", NULL
, "DACR"},
597 {"Output Left Amp Power", NULL
, "Analog Left Bypass"},
598 {"Output Right Amp Power", NULL
, "Analog Right Bypass"},
601 {"LEFT_LO", NULL
, "Output Left Amp Power"},
602 {"RIGHT_LO", NULL
, "Output Right Amp Power"},
605 static int dac33_add_widgets(struct snd_soc_codec
*codec
)
607 snd_soc_dapm_new_controls(codec
, dac33_dapm_widgets
,
608 ARRAY_SIZE(dac33_dapm_widgets
));
610 /* set up audio path interconnects */
611 snd_soc_dapm_add_routes(codec
, audio_map
, ARRAY_SIZE(audio_map
));
616 static int dac33_set_bias_level(struct snd_soc_codec
*codec
,
617 enum snd_soc_bias_level level
)
622 case SND_SOC_BIAS_ON
:
623 dac33_soft_power(codec
, 1);
625 case SND_SOC_BIAS_PREPARE
:
627 case SND_SOC_BIAS_STANDBY
:
628 if (codec
->bias_level
== SND_SOC_BIAS_OFF
) {
629 /* Coming from OFF, switch on the codec */
630 ret
= dac33_hard_power(codec
, 1);
634 dac33_init_chip(codec
);
637 case SND_SOC_BIAS_OFF
:
638 /* Do not power off, when the codec is already off */
639 if (codec
->bias_level
== SND_SOC_BIAS_OFF
)
641 ret
= dac33_hard_power(codec
, 0);
646 codec
->bias_level
= level
;
651 static inline void dac33_prefill_handler(struct tlv320dac33_priv
*dac33
)
653 struct snd_soc_codec
*codec
;
655 codec
= &dac33
->codec
;
657 switch (dac33
->fifo_mode
) {
658 case DAC33_FIFO_MODE1
:
659 dac33_write16(codec
, DAC33_NSAMPLE_MSB
,
660 DAC33_THRREG(dac33
->nsample
));
662 /* Take the timestamps */
663 spin_lock_irq(&dac33
->lock
);
664 dac33
->t_stamp2
= ktime_to_us(ktime_get());
665 dac33
->t_stamp1
= dac33
->t_stamp2
;
666 spin_unlock_irq(&dac33
->lock
);
668 dac33_write16(codec
, DAC33_PREFILL_MSB
,
669 DAC33_THRREG(dac33
->alarm_threshold
));
670 /* Enable Alarm Threshold IRQ with a delay */
671 udelay(SAMPLES_TO_US(dac33
->burst_rate
,
672 dac33
->alarm_threshold
));
673 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, DAC33_MAT
);
675 case DAC33_FIFO_MODE7
:
676 /* Take the timestamp */
677 spin_lock_irq(&dac33
->lock
);
678 dac33
->t_stamp1
= ktime_to_us(ktime_get());
679 /* Move back the timestamp with drain time */
680 dac33
->t_stamp1
-= dac33
->mode7_us_to_lthr
;
681 spin_unlock_irq(&dac33
->lock
);
683 dac33_write16(codec
, DAC33_PREFILL_MSB
,
684 DAC33_THRREG(MODE7_LTHR
));
686 /* Enable Upper Threshold IRQ */
687 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, DAC33_MUT
);
690 dev_warn(codec
->dev
, "Unhandled FIFO mode: %d\n",
696 static inline void dac33_playback_handler(struct tlv320dac33_priv
*dac33
)
698 struct snd_soc_codec
*codec
;
700 codec
= &dac33
->codec
;
702 switch (dac33
->fifo_mode
) {
703 case DAC33_FIFO_MODE1
:
704 /* Take the timestamp */
705 spin_lock_irq(&dac33
->lock
);
706 dac33
->t_stamp2
= ktime_to_us(ktime_get());
707 spin_unlock_irq(&dac33
->lock
);
709 dac33_write16(codec
, DAC33_NSAMPLE_MSB
,
710 DAC33_THRREG(dac33
->nsample
));
712 case DAC33_FIFO_MODE7
:
713 /* At the moment we are not using interrupts in mode7 */
716 dev_warn(codec
->dev
, "Unhandled FIFO mode: %d\n",
722 static void dac33_work(struct work_struct
*work
)
724 struct snd_soc_codec
*codec
;
725 struct tlv320dac33_priv
*dac33
;
728 dac33
= container_of(work
, struct tlv320dac33_priv
, work
);
729 codec
= &dac33
->codec
;
731 mutex_lock(&dac33
->mutex
);
732 switch (dac33
->state
) {
734 dac33
->state
= DAC33_PLAYBACK
;
735 dac33_prefill_handler(dac33
);
738 dac33_playback_handler(dac33
);
743 dac33
->state
= DAC33_IDLE
;
744 /* Mask all interrupts from dac33 */
745 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, 0);
748 reg
= dac33_read_reg_cache(codec
, DAC33_FIFO_CTRL_A
);
749 reg
|= DAC33_FIFOFLUSH
;
750 dac33_write(codec
, DAC33_FIFO_CTRL_A
, reg
);
753 mutex_unlock(&dac33
->mutex
);
756 static irqreturn_t
dac33_interrupt_handler(int irq
, void *dev
)
758 struct snd_soc_codec
*codec
= dev
;
759 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
761 spin_lock(&dac33
->lock
);
762 dac33
->t_stamp1
= ktime_to_us(ktime_get());
763 spin_unlock(&dac33
->lock
);
765 /* Do not schedule the workqueue in Mode7 */
766 if (dac33
->fifo_mode
!= DAC33_FIFO_MODE7
)
767 queue_work(dac33
->dac33_wq
, &dac33
->work
);
772 static void dac33_oscwait(struct snd_soc_codec
*codec
)
779 dac33_read(codec
, DAC33_INT_OSC_STATUS
, ®
);
780 } while (((reg
& 0x03) != DAC33_OSCSTATUS_NORMAL
) && timeout
--);
781 if ((reg
& 0x03) != DAC33_OSCSTATUS_NORMAL
)
783 "internal oscillator calibration failed\n");
786 static int dac33_startup(struct snd_pcm_substream
*substream
,
787 struct snd_soc_dai
*dai
)
789 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
790 struct snd_soc_device
*socdev
= rtd
->socdev
;
791 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
792 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
794 /* Stream started, save the substream pointer */
795 dac33
->substream
= substream
;
800 static void dac33_shutdown(struct snd_pcm_substream
*substream
,
801 struct snd_soc_dai
*dai
)
803 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
804 struct snd_soc_device
*socdev
= rtd
->socdev
;
805 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
806 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
808 dac33
->substream
= NULL
;
810 /* Reset the nSample restrictions */
811 dac33
->nsample_min
= 0;
812 dac33
->nsample_max
= NSAMPLE_MAX
;
815 static int dac33_hw_params(struct snd_pcm_substream
*substream
,
816 struct snd_pcm_hw_params
*params
,
817 struct snd_soc_dai
*dai
)
819 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
820 struct snd_soc_device
*socdev
= rtd
->socdev
;
821 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
823 /* Check parameters for validity */
824 switch (params_rate(params
)) {
829 dev_err(codec
->dev
, "unsupported rate %d\n",
830 params_rate(params
));
834 switch (params_format(params
)) {
835 case SNDRV_PCM_FORMAT_S16_LE
:
838 dev_err(codec
->dev
, "unsupported format %d\n",
839 params_format(params
));
846 #define CALC_OSCSET(rate, refclk) ( \
847 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
848 #define CALC_RATIOSET(rate, refclk) ( \
849 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
852 * tlv320dac33 is strict on the sequence of the register writes, if the register
853 * writes happens in different order, than dac33 might end up in unknown state.
854 * Use the known, working sequence of register writes to initialize the dac33.
856 static int dac33_prepare_chip(struct snd_pcm_substream
*substream
)
858 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
859 struct snd_soc_device
*socdev
= rtd
->socdev
;
860 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
861 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
862 unsigned int oscset
, ratioset
, pwr_ctrl
, reg_tmp
;
863 u8 aictrl_a
, aictrl_b
, fifoctrl_a
;
865 switch (substream
->runtime
->rate
) {
868 oscset
= CALC_OSCSET(substream
->runtime
->rate
, dac33
->refclk
);
869 ratioset
= CALC_RATIOSET(substream
->runtime
->rate
,
873 dev_err(codec
->dev
, "unsupported rate %d\n",
874 substream
->runtime
->rate
);
879 aictrl_a
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
);
880 aictrl_a
&= ~(DAC33_NCYCL_MASK
| DAC33_WLEN_MASK
);
881 /* Read FIFO control A, and clear FIFO flush bit */
882 fifoctrl_a
= dac33_read_reg_cache(codec
, DAC33_FIFO_CTRL_A
);
883 fifoctrl_a
&= ~DAC33_FIFOFLUSH
;
885 fifoctrl_a
&= ~DAC33_WIDTH
;
886 switch (substream
->runtime
->format
) {
887 case SNDRV_PCM_FORMAT_S16_LE
:
888 aictrl_a
|= (DAC33_NCYCL_16
| DAC33_WLEN_16
);
889 fifoctrl_a
|= DAC33_WIDTH
;
892 dev_err(codec
->dev
, "unsupported format %d\n",
893 substream
->runtime
->format
);
897 mutex_lock(&dac33
->mutex
);
899 if (!dac33
->chip_power
) {
901 * Chip is not powered yet.
902 * Do the init in the dac33_set_bias_level later.
904 mutex_unlock(&dac33
->mutex
);
908 dac33_soft_power(codec
, 0);
909 dac33_soft_power(codec
, 1);
911 reg_tmp
= dac33_read_reg_cache(codec
, DAC33_INT_OSC_CTRL
);
912 dac33_write(codec
, DAC33_INT_OSC_CTRL
, reg_tmp
);
914 /* Write registers 0x08 and 0x09 (MSB, LSB) */
915 dac33_write16(codec
, DAC33_INT_OSC_FREQ_RAT_A
, oscset
);
917 /* calib time: 128 is a nice number ;) */
918 dac33_write(codec
, DAC33_CALIB_TIME
, 128);
920 /* adjustment treshold & step */
921 dac33_write(codec
, DAC33_INT_OSC_CTRL_B
, DAC33_ADJTHRSHLD(2) |
924 /* div=4 / gain=1 / div */
925 dac33_write(codec
, DAC33_INT_OSC_CTRL_C
, DAC33_REFDIV(4));
927 pwr_ctrl
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
928 pwr_ctrl
|= DAC33_OSCPDNB
| DAC33_DACRPDNB
| DAC33_DACLPDNB
;
929 dac33_write(codec
, DAC33_PWR_CTRL
, pwr_ctrl
);
931 dac33_oscwait(codec
);
933 if (dac33
->fifo_mode
) {
934 /* Generic for all FIFO modes */
935 /* 50-51 : ASRC Control registers */
936 dac33_write(codec
, DAC33_ASRC_CTRL_A
, DAC33_SRCLKDIV(1));
937 dac33_write(codec
, DAC33_ASRC_CTRL_B
, 1); /* ??? */
939 /* Write registers 0x34 and 0x35 (MSB, LSB) */
940 dac33_write16(codec
, DAC33_SRC_REF_CLK_RATIO_A
, ratioset
);
942 /* Set interrupts to high active */
943 dac33_write(codec
, DAC33_INTP_CTRL_A
, DAC33_INTPM_AHIGH
);
945 /* FIFO bypass mode */
946 /* 50-51 : ASRC Control registers */
947 dac33_write(codec
, DAC33_ASRC_CTRL_A
, DAC33_SRCBYP
);
948 dac33_write(codec
, DAC33_ASRC_CTRL_B
, 0); /* ??? */
951 /* Interrupt behaviour configuration */
952 switch (dac33
->fifo_mode
) {
953 case DAC33_FIFO_MODE1
:
954 dac33_write(codec
, DAC33_FIFO_IRQ_MODE_B
,
955 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL
));
957 case DAC33_FIFO_MODE7
:
958 dac33_write(codec
, DAC33_FIFO_IRQ_MODE_A
,
959 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL
));
962 /* in FIFO bypass mode, the interrupts are not used */
966 aictrl_b
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
);
968 switch (dac33
->fifo_mode
) {
969 case DAC33_FIFO_MODE1
:
972 * Disable the FIFO bypass (Enable the use of FIFO)
973 * Select nSample mode
974 * BCLK is only running when data is needed by DAC33
976 fifoctrl_a
&= ~DAC33_FBYPAS
;
977 fifoctrl_a
&= ~DAC33_FAUTO
;
978 if (dac33
->keep_bclk
)
979 aictrl_b
|= DAC33_BCLKON
;
981 aictrl_b
&= ~DAC33_BCLKON
;
983 case DAC33_FIFO_MODE7
:
986 * Disable the FIFO bypass (Enable the use of FIFO)
987 * Select Threshold mode
988 * BCLK is only running when data is needed by DAC33
990 fifoctrl_a
&= ~DAC33_FBYPAS
;
991 fifoctrl_a
|= DAC33_FAUTO
;
992 if (dac33
->keep_bclk
)
993 aictrl_b
|= DAC33_BCLKON
;
995 aictrl_b
&= ~DAC33_BCLKON
;
999 * For FIFO bypass mode:
1000 * Enable the FIFO bypass (Disable the FIFO use)
1001 * Set the BCLK as continous
1003 fifoctrl_a
|= DAC33_FBYPAS
;
1004 aictrl_b
|= DAC33_BCLKON
;
1008 dac33_write(codec
, DAC33_FIFO_CTRL_A
, fifoctrl_a
);
1009 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_A
, aictrl_a
);
1010 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_B
, aictrl_b
);
1021 if (dac33
->fifo_mode
)
1022 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_C
,
1023 dac33
->burst_bclkdiv
);
1025 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_C
, 32);
1027 switch (dac33
->fifo_mode
) {
1028 case DAC33_FIFO_MODE1
:
1029 dac33_write16(codec
, DAC33_ATHR_MSB
,
1030 DAC33_THRREG(dac33
->alarm_threshold
));
1032 case DAC33_FIFO_MODE7
:
1034 * Configure the threshold levels, and leave 10 sample space
1035 * at the bottom, and also at the top of the FIFO
1037 dac33_write16(codec
, DAC33_UTHR_MSB
, DAC33_THRREG(dac33
->uthr
));
1038 dac33_write16(codec
, DAC33_LTHR_MSB
, DAC33_THRREG(MODE7_LTHR
));
1044 mutex_unlock(&dac33
->mutex
);
1049 static void dac33_calculate_times(struct snd_pcm_substream
*substream
)
1051 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1052 struct snd_soc_device
*socdev
= rtd
->socdev
;
1053 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
1054 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1055 unsigned int period_size
= substream
->runtime
->period_size
;
1056 unsigned int rate
= substream
->runtime
->rate
;
1057 unsigned int nsample_limit
;
1059 /* In bypass mode we don't need to calculate */
1060 if (!dac33
->fifo_mode
)
1063 switch (dac33
->fifo_mode
) {
1064 case DAC33_FIFO_MODE1
:
1065 /* Number of samples under i2c latency */
1066 dac33
->alarm_threshold
= US_TO_SAMPLES(rate
,
1067 dac33
->mode1_latency
);
1068 if (dac33
->auto_fifo_config
) {
1069 if (period_size
<= dac33
->alarm_threshold
)
1071 * Configure nSamaple to number of periods,
1072 * which covers the latency requironment.
1074 dac33
->nsample
= period_size
*
1075 ((dac33
->alarm_threshold
/ period_size
) +
1076 (dac33
->alarm_threshold
% period_size
?
1079 dac33
->nsample
= period_size
;
1081 /* nSample time shall not be shorter than i2c latency */
1082 dac33
->nsample_min
= dac33
->alarm_threshold
;
1084 * nSample should not be bigger than alsa buffer minus
1085 * size of one period to avoid overruns
1087 dac33
->nsample_max
= substream
->runtime
->buffer_size
-
1089 nsample_limit
= DAC33_BUFFER_SIZE_SAMPLES
-
1090 dac33
->alarm_threshold
;
1091 if (dac33
->nsample_max
> nsample_limit
)
1092 dac33
->nsample_max
= nsample_limit
;
1094 /* Correct the nSample if it is outside of the ranges */
1095 if (dac33
->nsample
< dac33
->nsample_min
)
1096 dac33
->nsample
= dac33
->nsample_min
;
1097 if (dac33
->nsample
> dac33
->nsample_max
)
1098 dac33
->nsample
= dac33
->nsample_max
;
1101 dac33
->mode1_us_burst
= SAMPLES_TO_US(dac33
->burst_rate
,
1103 dac33
->t_stamp1
= 0;
1104 dac33
->t_stamp2
= 0;
1106 case DAC33_FIFO_MODE7
:
1107 if (dac33
->auto_fifo_config
) {
1108 dac33
->uthr
= UTHR_FROM_PERIOD_SIZE(
1111 dac33
->burst_rate
) + 9;
1112 if (dac33
->uthr
> MODE7_UTHR
)
1113 dac33
->uthr
= MODE7_UTHR
;
1114 if (dac33
->uthr
< (MODE7_LTHR
+ 10))
1115 dac33
->uthr
= (MODE7_LTHR
+ 10);
1117 dac33
->mode7_us_to_lthr
=
1118 SAMPLES_TO_US(substream
->runtime
->rate
,
1119 dac33
->uthr
- MODE7_LTHR
+ 1);
1120 dac33
->t_stamp1
= 0;
1128 static int dac33_pcm_trigger(struct snd_pcm_substream
*substream
, int cmd
,
1129 struct snd_soc_dai
*dai
)
1131 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1132 struct snd_soc_device
*socdev
= rtd
->socdev
;
1133 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
1134 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1138 case SNDRV_PCM_TRIGGER_START
:
1139 case SNDRV_PCM_TRIGGER_RESUME
:
1140 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1141 if (dac33
->fifo_mode
) {
1142 dac33
->state
= DAC33_PREFILL
;
1143 queue_work(dac33
->dac33_wq
, &dac33
->work
);
1146 case SNDRV_PCM_TRIGGER_STOP
:
1147 case SNDRV_PCM_TRIGGER_SUSPEND
:
1148 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1149 if (dac33
->fifo_mode
) {
1150 dac33
->state
= DAC33_FLUSH
;
1151 queue_work(dac33
->dac33_wq
, &dac33
->work
);
1161 static snd_pcm_sframes_t
dac33_dai_delay(
1162 struct snd_pcm_substream
*substream
,
1163 struct snd_soc_dai
*dai
)
1165 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1166 struct snd_soc_device
*socdev
= rtd
->socdev
;
1167 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
1168 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1169 unsigned long long t0
, t1
, t_now
;
1170 unsigned int time_delta
, uthr
;
1171 int samples_out
, samples_in
, samples
;
1172 snd_pcm_sframes_t delay
= 0;
1174 switch (dac33
->fifo_mode
) {
1175 case DAC33_FIFO_BYPASS
:
1177 case DAC33_FIFO_MODE1
:
1178 spin_lock(&dac33
->lock
);
1179 t0
= dac33
->t_stamp1
;
1180 t1
= dac33
->t_stamp2
;
1181 spin_unlock(&dac33
->lock
);
1182 t_now
= ktime_to_us(ktime_get());
1184 /* We have not started to fill the FIFO yet, delay is 0 */
1191 * After Alarm threshold, and before nSample write
1193 time_delta
= t_now
- t0
;
1194 samples_out
= time_delta
? US_TO_SAMPLES(
1195 substream
->runtime
->rate
,
1198 if (likely(dac33
->alarm_threshold
> samples_out
))
1199 delay
= dac33
->alarm_threshold
- samples_out
;
1202 } else if ((t_now
- t1
) <= dac33
->mode1_us_burst
) {
1205 * After nSample write (during burst operation)
1207 time_delta
= t_now
- t0
;
1208 samples_out
= time_delta
? US_TO_SAMPLES(
1209 substream
->runtime
->rate
,
1212 time_delta
= t_now
- t1
;
1213 samples_in
= time_delta
? US_TO_SAMPLES(
1217 samples
= dac33
->alarm_threshold
;
1218 samples
+= (samples_in
- samples_out
);
1220 if (likely(samples
> 0))
1227 * After burst operation, before next alarm threshold
1229 time_delta
= t_now
- t0
;
1230 samples_out
= time_delta
? US_TO_SAMPLES(
1231 substream
->runtime
->rate
,
1234 samples_in
= dac33
->nsample
;
1235 samples
= dac33
->alarm_threshold
;
1236 samples
+= (samples_in
- samples_out
);
1238 if (likely(samples
> 0))
1239 delay
= samples
> DAC33_BUFFER_SIZE_SAMPLES
?
1240 DAC33_BUFFER_SIZE_SAMPLES
: samples
;
1245 case DAC33_FIFO_MODE7
:
1246 spin_lock(&dac33
->lock
);
1247 t0
= dac33
->t_stamp1
;
1249 spin_unlock(&dac33
->lock
);
1250 t_now
= ktime_to_us(ktime_get());
1252 /* We have not started to fill the FIFO yet, delay is 0 */
1258 * Either the timestamps are messed or equal. Report
1265 time_delta
= t_now
- t0
;
1266 if (time_delta
<= dac33
->mode7_us_to_lthr
) {
1269 * After burst (draining phase)
1271 samples_out
= US_TO_SAMPLES(
1272 substream
->runtime
->rate
,
1275 if (likely(uthr
> samples_out
))
1276 delay
= uthr
- samples_out
;
1282 * During burst operation
1284 time_delta
= time_delta
- dac33
->mode7_us_to_lthr
;
1286 samples_out
= US_TO_SAMPLES(
1287 substream
->runtime
->rate
,
1289 samples_in
= US_TO_SAMPLES(
1292 delay
= MODE7_LTHR
+ samples_in
- samples_out
;
1294 if (unlikely(delay
> uthr
))
1299 dev_warn(codec
->dev
, "Unhandled FIFO mode: %d\n",
1307 static int dac33_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
1308 int clk_id
, unsigned int freq
, int dir
)
1310 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1311 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1312 u8 ioc_reg
, asrcb_reg
;
1314 ioc_reg
= dac33_read_reg_cache(codec
, DAC33_INT_OSC_CTRL
);
1315 asrcb_reg
= dac33_read_reg_cache(codec
, DAC33_ASRC_CTRL_B
);
1317 case TLV320DAC33_MCLK
:
1318 ioc_reg
|= DAC33_REFSEL
;
1319 asrcb_reg
|= DAC33_SRCREFSEL
;
1321 case TLV320DAC33_SLEEPCLK
:
1322 ioc_reg
&= ~DAC33_REFSEL
;
1323 asrcb_reg
&= ~DAC33_SRCREFSEL
;
1326 dev_err(codec
->dev
, "Invalid clock ID (%d)\n", clk_id
);
1329 dac33
->refclk
= freq
;
1331 dac33_write_reg_cache(codec
, DAC33_INT_OSC_CTRL
, ioc_reg
);
1332 dac33_write_reg_cache(codec
, DAC33_ASRC_CTRL_B
, asrcb_reg
);
1337 static int dac33_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
1340 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1341 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1342 u8 aictrl_a
, aictrl_b
;
1344 aictrl_a
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
);
1345 aictrl_b
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
);
1346 /* set master/slave audio interface */
1347 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1348 case SND_SOC_DAIFMT_CBM_CFM
:
1350 aictrl_a
|= (DAC33_MSBCLK
| DAC33_MSWCLK
);
1352 case SND_SOC_DAIFMT_CBS_CFS
:
1354 if (dac33
->fifo_mode
) {
1355 dev_err(codec
->dev
, "FIFO mode requires master mode\n");
1358 aictrl_a
&= ~(DAC33_MSBCLK
| DAC33_MSWCLK
);
1364 aictrl_a
&= ~DAC33_AFMT_MASK
;
1365 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1366 case SND_SOC_DAIFMT_I2S
:
1367 aictrl_a
|= DAC33_AFMT_I2S
;
1369 case SND_SOC_DAIFMT_DSP_A
:
1370 aictrl_a
|= DAC33_AFMT_DSP
;
1371 aictrl_b
&= ~DAC33_DATA_DELAY_MASK
;
1372 aictrl_b
|= DAC33_DATA_DELAY(0);
1374 case SND_SOC_DAIFMT_RIGHT_J
:
1375 aictrl_a
|= DAC33_AFMT_RIGHT_J
;
1377 case SND_SOC_DAIFMT_LEFT_J
:
1378 aictrl_a
|= DAC33_AFMT_LEFT_J
;
1381 dev_err(codec
->dev
, "Unsupported format (%u)\n",
1382 fmt
& SND_SOC_DAIFMT_FORMAT_MASK
);
1386 dac33_write_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
, aictrl_a
);
1387 dac33_write_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
, aictrl_b
);
1392 static int dac33_soc_probe(struct platform_device
*pdev
)
1394 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1395 struct snd_soc_codec
*codec
;
1396 struct tlv320dac33_priv
*dac33
;
1399 BUG_ON(!tlv320dac33_codec
);
1401 codec
= tlv320dac33_codec
;
1402 socdev
->card
->codec
= codec
;
1403 dac33
= snd_soc_codec_get_drvdata(codec
);
1406 ret
= snd_soc_new_pcms(socdev
, SNDRV_DEFAULT_IDX1
, SNDRV_DEFAULT_STR1
);
1408 dev_err(codec
->dev
, "failed to create pcms\n");
1412 snd_soc_add_controls(codec
, dac33_snd_controls
,
1413 ARRAY_SIZE(dac33_snd_controls
));
1414 /* Only add the FIFO controls, if we have valid IRQ number */
1415 if (dac33
->irq
>= 0) {
1416 snd_soc_add_controls(codec
, dac33_mode_snd_controls
,
1417 ARRAY_SIZE(dac33_mode_snd_controls
));
1418 /* FIFO usage controls only, if autoio config is not selected */
1419 if (!dac33
->auto_fifo_config
)
1420 snd_soc_add_controls(codec
, dac33_fifo_snd_controls
,
1421 ARRAY_SIZE(dac33_fifo_snd_controls
));
1424 dac33_add_widgets(codec
);
1429 dac33_hard_power(codec
, 0);
1433 static int dac33_soc_remove(struct platform_device
*pdev
)
1435 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1436 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
1438 dac33_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1440 snd_soc_free_pcms(socdev
);
1441 snd_soc_dapm_free(socdev
);
1446 static int dac33_soc_suspend(struct platform_device
*pdev
, pm_message_t state
)
1448 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1449 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
1451 dac33_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1456 static int dac33_soc_resume(struct platform_device
*pdev
)
1458 struct snd_soc_device
*socdev
= platform_get_drvdata(pdev
);
1459 struct snd_soc_codec
*codec
= socdev
->card
->codec
;
1461 dac33_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1466 struct snd_soc_codec_device soc_codec_dev_tlv320dac33
= {
1467 .probe
= dac33_soc_probe
,
1468 .remove
= dac33_soc_remove
,
1469 .suspend
= dac33_soc_suspend
,
1470 .resume
= dac33_soc_resume
,
1472 EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33
);
1474 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1475 SNDRV_PCM_RATE_48000)
1476 #define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1478 static struct snd_soc_dai_ops dac33_dai_ops
= {
1479 .startup
= dac33_startup
,
1480 .shutdown
= dac33_shutdown
,
1481 .hw_params
= dac33_hw_params
,
1482 .trigger
= dac33_pcm_trigger
,
1483 .delay
= dac33_dai_delay
,
1484 .set_sysclk
= dac33_set_dai_sysclk
,
1485 .set_fmt
= dac33_set_dai_fmt
,
1488 struct snd_soc_dai dac33_dai
= {
1489 .name
= "tlv320dac33",
1491 .stream_name
= "Playback",
1494 .rates
= DAC33_RATES
,
1495 .formats
= DAC33_FORMATS
,},
1496 .ops
= &dac33_dai_ops
,
1498 EXPORT_SYMBOL_GPL(dac33_dai
);
1500 static int __devinit
dac33_i2c_probe(struct i2c_client
*client
,
1501 const struct i2c_device_id
*id
)
1503 struct tlv320dac33_platform_data
*pdata
;
1504 struct tlv320dac33_priv
*dac33
;
1505 struct snd_soc_codec
*codec
;
1508 if (client
->dev
.platform_data
== NULL
) {
1509 dev_err(&client
->dev
, "Platform data not set\n");
1512 pdata
= client
->dev
.platform_data
;
1514 dac33
= kzalloc(sizeof(struct tlv320dac33_priv
), GFP_KERNEL
);
1518 codec
= &dac33
->codec
;
1519 snd_soc_codec_set_drvdata(codec
, dac33
);
1520 codec
->control_data
= client
;
1522 mutex_init(&codec
->mutex
);
1523 mutex_init(&dac33
->mutex
);
1524 spin_lock_init(&dac33
->lock
);
1525 INIT_LIST_HEAD(&codec
->dapm_widgets
);
1526 INIT_LIST_HEAD(&codec
->dapm_paths
);
1528 codec
->name
= "tlv320dac33";
1529 codec
->owner
= THIS_MODULE
;
1530 codec
->read
= dac33_read_reg_cache
;
1531 codec
->write
= dac33_write_locked
;
1532 codec
->hw_write
= (hw_write_t
) i2c_master_send
;
1533 codec
->bias_level
= SND_SOC_BIAS_OFF
;
1534 codec
->set_bias_level
= dac33_set_bias_level
;
1535 codec
->idle_bias_off
= 1;
1536 codec
->dai
= &dac33_dai
;
1538 codec
->reg_cache_size
= ARRAY_SIZE(dac33_reg
);
1539 codec
->reg_cache
= kmemdup(dac33_reg
, ARRAY_SIZE(dac33_reg
),
1541 if (codec
->reg_cache
== NULL
) {
1546 i2c_set_clientdata(client
, dac33
);
1548 dac33
->power_gpio
= pdata
->power_gpio
;
1549 dac33
->burst_bclkdiv
= pdata
->burst_bclkdiv
;
1550 /* Pre calculate the burst rate */
1551 dac33
->burst_rate
= BURST_BASEFREQ_HZ
/ dac33
->burst_bclkdiv
/ 32;
1552 dac33
->keep_bclk
= pdata
->keep_bclk
;
1553 dac33
->auto_fifo_config
= pdata
->auto_fifo_config
;
1554 dac33
->mode1_latency
= pdata
->mode1_latency
;
1555 if (!dac33
->mode1_latency
)
1556 dac33
->mode1_latency
= 10000; /* 10ms */
1557 dac33
->irq
= client
->irq
;
1558 dac33
->nsample
= NSAMPLE_MAX
;
1559 dac33
->nsample_max
= NSAMPLE_MAX
;
1560 dac33
->uthr
= MODE7_UTHR
;
1561 /* Disable FIFO use by default */
1562 dac33
->fifo_mode
= DAC33_FIFO_BYPASS
;
1564 tlv320dac33_codec
= codec
;
1566 codec
->dev
= &client
->dev
;
1567 dac33_dai
.dev
= codec
->dev
;
1569 /* Check if the reset GPIO number is valid and request it */
1570 if (dac33
->power_gpio
>= 0) {
1571 ret
= gpio_request(dac33
->power_gpio
, "tlv320dac33 reset");
1574 "Failed to request reset GPIO (%d)\n",
1576 snd_soc_unregister_dai(&dac33_dai
);
1577 snd_soc_unregister_codec(codec
);
1580 gpio_direction_output(dac33
->power_gpio
, 0);
1583 /* Check if the IRQ number is valid and request it */
1584 if (dac33
->irq
>= 0) {
1585 ret
= request_irq(dac33
->irq
, dac33_interrupt_handler
,
1586 IRQF_TRIGGER_RISING
| IRQF_DISABLED
,
1587 codec
->name
, codec
);
1589 dev_err(codec
->dev
, "Could not request IRQ%d (%d)\n",
1593 if (dac33
->irq
!= -1) {
1594 /* Setup work queue */
1596 create_singlethread_workqueue("tlv320dac33");
1597 if (dac33
->dac33_wq
== NULL
) {
1598 free_irq(dac33
->irq
, &dac33
->codec
);
1603 INIT_WORK(&dac33
->work
, dac33_work
);
1607 for (i
= 0; i
< ARRAY_SIZE(dac33
->supplies
); i
++)
1608 dac33
->supplies
[i
].supply
= dac33_supply_names
[i
];
1610 ret
= regulator_bulk_get(codec
->dev
, ARRAY_SIZE(dac33
->supplies
),
1614 dev_err(codec
->dev
, "Failed to request supplies: %d\n", ret
);
1618 /* Read the tlv320dac33 ID registers */
1619 ret
= dac33_hard_power(codec
, 1);
1621 dev_err(codec
->dev
, "Failed to power up codec: %d\n", ret
);
1624 dac33_read_id(codec
);
1625 dac33_hard_power(codec
, 0);
1627 ret
= snd_soc_register_codec(codec
);
1629 dev_err(codec
->dev
, "Failed to register codec: %d\n", ret
);
1633 ret
= snd_soc_register_dai(&dac33_dai
);
1635 dev_err(codec
->dev
, "Failed to register DAI: %d\n", ret
);
1636 snd_soc_unregister_codec(codec
);
1643 regulator_bulk_free(ARRAY_SIZE(dac33
->supplies
), dac33
->supplies
);
1645 if (dac33
->irq
>= 0) {
1646 free_irq(dac33
->irq
, &dac33
->codec
);
1647 destroy_workqueue(dac33
->dac33_wq
);
1650 if (dac33
->power_gpio
>= 0)
1651 gpio_free(dac33
->power_gpio
);
1653 kfree(codec
->reg_cache
);
1655 tlv320dac33_codec
= NULL
;
1661 static int __devexit
dac33_i2c_remove(struct i2c_client
*client
)
1663 struct tlv320dac33_priv
*dac33
;
1665 dac33
= i2c_get_clientdata(client
);
1667 if (unlikely(dac33
->chip_power
))
1668 dac33_hard_power(&dac33
->codec
, 0);
1670 if (dac33
->power_gpio
>= 0)
1671 gpio_free(dac33
->power_gpio
);
1672 if (dac33
->irq
>= 0)
1673 free_irq(dac33
->irq
, &dac33
->codec
);
1675 regulator_bulk_free(ARRAY_SIZE(dac33
->supplies
), dac33
->supplies
);
1677 destroy_workqueue(dac33
->dac33_wq
);
1678 snd_soc_unregister_dai(&dac33_dai
);
1679 snd_soc_unregister_codec(&dac33
->codec
);
1680 kfree(dac33
->codec
.reg_cache
);
1682 tlv320dac33_codec
= NULL
;
1687 static const struct i2c_device_id tlv320dac33_i2c_id
[] = {
1689 .name
= "tlv320dac33",
1695 static struct i2c_driver tlv320dac33_i2c_driver
= {
1697 .name
= "tlv320dac33",
1698 .owner
= THIS_MODULE
,
1700 .probe
= dac33_i2c_probe
,
1701 .remove
= __devexit_p(dac33_i2c_remove
),
1702 .id_table
= tlv320dac33_i2c_id
,
1705 static int __init
dac33_module_init(void)
1708 r
= i2c_add_driver(&tlv320dac33_i2c_driver
);
1710 printk(KERN_ERR
"DAC33: driver registration failed\n");
1715 module_init(dac33_module_init
);
1717 static void __exit
dac33_module_exit(void)
1719 i2c_del_driver(&tlv320dac33_i2c_driver
);
1721 module_exit(dac33_module_exit
);
1724 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1725 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1726 MODULE_LICENSE("GPL");