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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / sound / pci / maestro3.c
blob58692272f31a7180b687e390e80e9275d9c9f11f
1 /*
2 * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
3 * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
4 * Takashi Iwai <tiwai@suse.de>
5 *
6 * Most of the hardware init stuffs are based on maestro3 driver for
7 * OSS/Free by Zach Brown. Many thanks to Zach!
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 *
24 * ChangeLog:
25 * Aug. 27, 2001
26 * - Fixed deadlock on capture
27 * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
28 *
29 */
30
31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
32 #define DRIVER_NAME "Maestro3"
33
34 #include <asm/io.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/init.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/moduleparam.h>
43 #include <linux/firmware.h>
44 #include <linux/input.h>
45 #include <sound/core.h>
46 #include <sound/info.h>
47 #include <sound/control.h>
48 #include <sound/pcm.h>
49 #include <sound/mpu401.h>
50 #include <sound/ac97_codec.h>
51 #include <sound/initval.h>
52 #include <asm/byteorder.h>
53
54 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
55 MODULE_DESCRIPTION("ESS Maestro3 PCI");
56 MODULE_LICENSE("GPL");
57 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
58 "{ESS,ES1988},"
59 "{ESS,Allegro PCI},"
60 "{ESS,Allegro-1 PCI},"
61 "{ESS,Canyon3D-2/LE PCI}}");
62 MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw");
63 MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw");
64
65 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
66 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
67 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
68 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
69 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
70
71 module_param_array(index, int, NULL, 0444);
72 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
73 module_param_array(id, charp, NULL, 0444);
74 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
75 module_param_array(enable, bool, NULL, 0444);
76 MODULE_PARM_DESC(enable, "Enable this soundcard.");
77 module_param_array(external_amp, bool, NULL, 0444);
78 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
79 module_param_array(amp_gpio, int, NULL, 0444);
80 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
81
82 #define MAX_PLAYBACKS 2
83 #define MAX_CAPTURES 1
84 #define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES)
85
86
87 /*
88 * maestro3 registers
89 */
90
91 /* Allegro PCI configuration registers */
92 #define PCI_LEGACY_AUDIO_CTRL 0x40
93 #define SOUND_BLASTER_ENABLE 0x00000001
94 #define FM_SYNTHESIS_ENABLE 0x00000002
95 #define GAME_PORT_ENABLE 0x00000004
96 #define MPU401_IO_ENABLE 0x00000008
97 #define MPU401_IRQ_ENABLE 0x00000010
98 #define ALIAS_10BIT_IO 0x00000020
99 #define SB_DMA_MASK 0x000000C0
100 #define SB_DMA_0 0x00000040
101 #define SB_DMA_1 0x00000040
102 #define SB_DMA_R 0x00000080
103 #define SB_DMA_3 0x000000C0
104 #define SB_IRQ_MASK 0x00000700
105 #define SB_IRQ_5 0x00000000
106 #define SB_IRQ_7 0x00000100
107 #define SB_IRQ_9 0x00000200
108 #define SB_IRQ_10 0x00000300
109 #define MIDI_IRQ_MASK 0x00003800
110 #define SERIAL_IRQ_ENABLE 0x00004000
111 #define DISABLE_LEGACY 0x00008000
112
113 #define PCI_ALLEGRO_CONFIG 0x50
114 #define SB_ADDR_240 0x00000004
115 #define MPU_ADDR_MASK 0x00000018
116 #define MPU_ADDR_330 0x00000000
117 #define MPU_ADDR_300 0x00000008
118 #define MPU_ADDR_320 0x00000010
119 #define MPU_ADDR_340 0x00000018
120 #define USE_PCI_TIMING 0x00000040
121 #define POSTED_WRITE_ENABLE 0x00000080
122 #define DMA_POLICY_MASK 0x00000700
123 #define DMA_DDMA 0x00000000
124 #define DMA_TDMA 0x00000100
125 #define DMA_PCPCI 0x00000200
126 #define DMA_WBDMA16 0x00000400
127 #define DMA_WBDMA4 0x00000500
128 #define DMA_WBDMA2 0x00000600
129 #define DMA_WBDMA1 0x00000700
130 #define DMA_SAFE_GUARD 0x00000800
131 #define HI_PERF_GP_ENABLE 0x00001000
132 #define PIC_SNOOP_MODE_0 0x00002000
133 #define PIC_SNOOP_MODE_1 0x00004000
134 #define SOUNDBLASTER_IRQ_MASK 0x00008000
135 #define RING_IN_ENABLE 0x00010000
136 #define SPDIF_TEST_MODE 0x00020000
137 #define CLK_MULT_MODE_SELECT_2 0x00040000
138 #define EEPROM_WRITE_ENABLE 0x00080000
139 #define CODEC_DIR_IN 0x00100000
140 #define HV_BUTTON_FROM_GD 0x00200000
141 #define REDUCED_DEBOUNCE 0x00400000
142 #define HV_CTRL_ENABLE 0x00800000
143 #define SPDIF_ENABLE 0x01000000
144 #define CLK_DIV_SELECT 0x06000000
145 #define CLK_DIV_BY_48 0x00000000
146 #define CLK_DIV_BY_49 0x02000000
147 #define CLK_DIV_BY_50 0x04000000
148 #define CLK_DIV_RESERVED 0x06000000
149 #define PM_CTRL_ENABLE 0x08000000
150 #define CLK_MULT_MODE_SELECT 0x30000000
151 #define CLK_MULT_MODE_SHIFT 28
152 #define CLK_MULT_MODE_0 0x00000000
153 #define CLK_MULT_MODE_1 0x10000000
154 #define CLK_MULT_MODE_2 0x20000000
155 #define CLK_MULT_MODE_3 0x30000000
156 #define INT_CLK_SELECT 0x40000000
157 #define INT_CLK_MULT_RESET 0x80000000
158
159 /* M3 */
160 #define INT_CLK_SRC_NOT_PCI 0x00100000
161 #define INT_CLK_MULT_ENABLE 0x80000000
162
163 #define PCI_ACPI_CONTROL 0x54
164 #define PCI_ACPI_D0 0x00000000
165 #define PCI_ACPI_D1 0xB4F70000
166 #define PCI_ACPI_D2 0xB4F7B4F7
167
168 #define PCI_USER_CONFIG 0x58
169 #define EXT_PCI_MASTER_ENABLE 0x00000001
170 #define SPDIF_OUT_SELECT 0x00000002
171 #define TEST_PIN_DIR_CTRL 0x00000004
172 #define AC97_CODEC_TEST 0x00000020
173 #define TRI_STATE_BUFFER 0x00000080
174 #define IN_CLK_12MHZ_SELECT 0x00000100
175 #define MULTI_FUNC_DISABLE 0x00000200
176 #define EXT_MASTER_PAIR_SEL 0x00000400
177 #define PCI_MASTER_SUPPORT 0x00000800
178 #define STOP_CLOCK_ENABLE 0x00001000
179 #define EAPD_DRIVE_ENABLE 0x00002000
180 #define REQ_TRI_STATE_ENABLE 0x00004000
181 #define REQ_LOW_ENABLE 0x00008000
182 #define MIDI_1_ENABLE 0x00010000
183 #define MIDI_2_ENABLE 0x00020000
184 #define SB_AUDIO_SYNC 0x00040000
185 #define HV_CTRL_TEST 0x00100000
186 #define SOUNDBLASTER_TEST 0x00400000
187
188 #define PCI_USER_CONFIG_C 0x5C
189
190 #define PCI_DDMA_CTRL 0x60
191 #define DDMA_ENABLE 0x00000001
192
193
194 /* Allegro registers */
195 #define HOST_INT_CTRL 0x18
196 #define SB_INT_ENABLE 0x0001
197 #define MPU401_INT_ENABLE 0x0002
198 #define ASSP_INT_ENABLE 0x0010
199 #define RING_INT_ENABLE 0x0020
200 #define HV_INT_ENABLE 0x0040
201 #define CLKRUN_GEN_ENABLE 0x0100
202 #define HV_CTRL_TO_PME 0x0400
203 #define SOFTWARE_RESET_ENABLE 0x8000
204
205 /*
206 * should be using the above defines, probably.
207 */
208 #define REGB_ENABLE_RESET 0x01
209 #define REGB_STOP_CLOCK 0x10
210
211 #define HOST_INT_STATUS 0x1A
212 #define SB_INT_PENDING 0x01
213 #define MPU401_INT_PENDING 0x02
214 #define ASSP_INT_PENDING 0x10
215 #define RING_INT_PENDING 0x20
216 #define HV_INT_PENDING 0x40
217
218 #define HARDWARE_VOL_CTRL 0x1B
219 #define SHADOW_MIX_REG_VOICE 0x1C
220 #define HW_VOL_COUNTER_VOICE 0x1D
221 #define SHADOW_MIX_REG_MASTER 0x1E
222 #define HW_VOL_COUNTER_MASTER 0x1F
223
224 #define CODEC_COMMAND 0x30
225 #define CODEC_READ_B 0x80
226
227 #define CODEC_STATUS 0x30
228 #define CODEC_BUSY_B 0x01
229
230 #define CODEC_DATA 0x32
231
232 #define RING_BUS_CTRL_A 0x36
233 #define RAC_PME_ENABLE 0x0100
234 #define RAC_SDFS_ENABLE 0x0200
235 #define LAC_PME_ENABLE 0x0400
236 #define LAC_SDFS_ENABLE 0x0800
237 #define SERIAL_AC_LINK_ENABLE 0x1000
238 #define IO_SRAM_ENABLE 0x2000
239 #define IIS_INPUT_ENABLE 0x8000
240
241 #define RING_BUS_CTRL_B 0x38
242 #define SECOND_CODEC_ID_MASK 0x0003
243 #define SPDIF_FUNC_ENABLE 0x0010
244 #define SECOND_AC_ENABLE 0x0020
245 #define SB_MODULE_INTF_ENABLE 0x0040
246 #define SSPE_ENABLE 0x0040
247 #define M3I_DOCK_ENABLE 0x0080
248
249 #define SDO_OUT_DEST_CTRL 0x3A
250 #define COMMAND_ADDR_OUT 0x0003
251 #define PCM_LR_OUT_LOCAL 0x0000
252 #define PCM_LR_OUT_REMOTE 0x0004
253 #define PCM_LR_OUT_MUTE 0x0008
254 #define PCM_LR_OUT_BOTH 0x000C
255 #define LINE1_DAC_OUT_LOCAL 0x0000
256 #define LINE1_DAC_OUT_REMOTE 0x0010
257 #define LINE1_DAC_OUT_MUTE 0x0020
258 #define LINE1_DAC_OUT_BOTH 0x0030
259 #define PCM_CLS_OUT_LOCAL 0x0000
260 #define PCM_CLS_OUT_REMOTE 0x0040
261 #define PCM_CLS_OUT_MUTE 0x0080
262 #define PCM_CLS_OUT_BOTH 0x00C0
263 #define PCM_RLF_OUT_LOCAL 0x0000
264 #define PCM_RLF_OUT_REMOTE 0x0100
265 #define PCM_RLF_OUT_MUTE 0x0200
266 #define PCM_RLF_OUT_BOTH 0x0300
267 #define LINE2_DAC_OUT_LOCAL 0x0000
268 #define LINE2_DAC_OUT_REMOTE 0x0400
269 #define LINE2_DAC_OUT_MUTE 0x0800
270 #define LINE2_DAC_OUT_BOTH 0x0C00
271 #define HANDSET_OUT_LOCAL 0x0000
272 #define HANDSET_OUT_REMOTE 0x1000
273 #define HANDSET_OUT_MUTE 0x2000
274 #define HANDSET_OUT_BOTH 0x3000
275 #define IO_CTRL_OUT_LOCAL 0x0000
276 #define IO_CTRL_OUT_REMOTE 0x4000
277 #define IO_CTRL_OUT_MUTE 0x8000
278 #define IO_CTRL_OUT_BOTH 0xC000
279
280 #define SDO_IN_DEST_CTRL 0x3C
281 #define STATUS_ADDR_IN 0x0003
282 #define PCM_LR_IN_LOCAL 0x0000
283 #define PCM_LR_IN_REMOTE 0x0004
284 #define PCM_LR_RESERVED 0x0008
285 #define PCM_LR_IN_BOTH 0x000C
286 #define LINE1_ADC_IN_LOCAL 0x0000
287 #define LINE1_ADC_IN_REMOTE 0x0010
288 #define LINE1_ADC_IN_MUTE 0x0020
289 #define MIC_ADC_IN_LOCAL 0x0000
290 #define MIC_ADC_IN_REMOTE 0x0040
291 #define MIC_ADC_IN_MUTE 0x0080
292 #define LINE2_DAC_IN_LOCAL 0x0000
293 #define LINE2_DAC_IN_REMOTE 0x0400
294 #define LINE2_DAC_IN_MUTE 0x0800
295 #define HANDSET_IN_LOCAL 0x0000
296 #define HANDSET_IN_REMOTE 0x1000
297 #define HANDSET_IN_MUTE 0x2000
298 #define IO_STATUS_IN_LOCAL 0x0000
299 #define IO_STATUS_IN_REMOTE 0x4000
300
301 #define SPDIF_IN_CTRL 0x3E
302 #define SPDIF_IN_ENABLE 0x0001
303
304 #define GPIO_DATA 0x60
305 #define GPIO_DATA_MASK 0x0FFF
306 #define GPIO_HV_STATUS 0x3000
307 #define GPIO_PME_STATUS 0x4000
308
309 #define GPIO_MASK 0x64
310 #define GPIO_DIRECTION 0x68
311 #define GPO_PRIMARY_AC97 0x0001
312 #define GPI_LINEOUT_SENSE 0x0004
313 #define GPO_SECONDARY_AC97 0x0008
314 #define GPI_VOL_DOWN 0x0010
315 #define GPI_VOL_UP 0x0020
316 #define GPI_IIS_CLK 0x0040
317 #define GPI_IIS_LRCLK 0x0080
318 #define GPI_IIS_DATA 0x0100
319 #define GPI_DOCKING_STATUS 0x0100
320 #define GPI_HEADPHONE_SENSE 0x0200
321 #define GPO_EXT_AMP_SHUTDOWN 0x1000
322
323 #define GPO_EXT_AMP_M3 1 /* default m3 amp */
324 #define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */
325
326 /* M3 */
327 #define GPO_M3_EXT_AMP_SHUTDN 0x0002
328
329 #define ASSP_INDEX_PORT 0x80
330 #define ASSP_MEMORY_PORT 0x82
331 #define ASSP_DATA_PORT 0x84
332
333 #define MPU401_DATA_PORT 0x98
334 #define MPU401_STATUS_PORT 0x99
335
336 #define CLK_MULT_DATA_PORT 0x9C
337
338 #define ASSP_CONTROL_A 0xA2
339 #define ASSP_0_WS_ENABLE 0x01
340 #define ASSP_CTRL_A_RESERVED1 0x02
341 #define ASSP_CTRL_A_RESERVED2 0x04
342 #define ASSP_CLK_49MHZ_SELECT 0x08
343 #define FAST_PLU_ENABLE 0x10
344 #define ASSP_CTRL_A_RESERVED3 0x20
345 #define DSP_CLK_36MHZ_SELECT 0x40
346
347 #define ASSP_CONTROL_B 0xA4
348 #define RESET_ASSP 0x00
349 #define RUN_ASSP 0x01
350 #define ENABLE_ASSP_CLOCK 0x00
351 #define STOP_ASSP_CLOCK 0x10
352 #define RESET_TOGGLE 0x40
353
354 #define ASSP_CONTROL_C 0xA6
355 #define ASSP_HOST_INT_ENABLE 0x01
356 #define FM_ADDR_REMAP_DISABLE 0x02
357 #define HOST_WRITE_PORT_ENABLE 0x08
358
359 #define ASSP_HOST_INT_STATUS 0xAC
360 #define DSP2HOST_REQ_PIORECORD 0x01
361 #define DSP2HOST_REQ_I2SRATE 0x02
362 #define DSP2HOST_REQ_TIMER 0x04
363
364 /* AC97 registers */
365 /*#define AC97_RESET 0x00*/
366
367 #define AC97_VOL_MUTE_B 0x8000
368 #define AC97_VOL_M 0x1F
369 #define AC97_LEFT_VOL_S 8
370
371 #define AC97_MASTER_VOL 0x02
372 #define AC97_LINE_LEVEL_VOL 0x04
373 #define AC97_MASTER_MONO_VOL 0x06
374 #define AC97_PC_BEEP_VOL 0x0A
375 #define AC97_PC_BEEP_VOL_M 0x0F
376 #define AC97_SROUND_MASTER_VOL 0x38
377 #define AC97_PC_BEEP_VOL_S 1
378
379 /*#define AC97_PHONE_VOL 0x0C
380 #define AC97_MIC_VOL 0x0E*/
381 #define AC97_MIC_20DB_ENABLE 0x40
382
383 /*#define AC97_LINEIN_VOL 0x10
384 #define AC97_CD_VOL 0x12
385 #define AC97_VIDEO_VOL 0x14
386 #define AC97_AUX_VOL 0x16*/
387 #define AC97_PCM_OUT_VOL 0x18
388 /*#define AC97_RECORD_SELECT 0x1A*/
389 #define AC97_RECORD_MIC 0x00
390 #define AC97_RECORD_CD 0x01
391 #define AC97_RECORD_VIDEO 0x02
392 #define AC97_RECORD_AUX 0x03
393 #define AC97_RECORD_MONO_MUX 0x02
394 #define AC97_RECORD_DIGITAL 0x03
395 #define AC97_RECORD_LINE 0x04
396 #define AC97_RECORD_STEREO 0x05
397 #define AC97_RECORD_MONO 0x06
398 #define AC97_RECORD_PHONE 0x07
399
400 /*#define AC97_RECORD_GAIN 0x1C*/
401 #define AC97_RECORD_VOL_M 0x0F
402
403 /*#define AC97_GENERAL_PURPOSE 0x20*/
404 #define AC97_POWER_DOWN_CTRL 0x26
405 #define AC97_ADC_READY 0x0001
406 #define AC97_DAC_READY 0x0002
407 #define AC97_ANALOG_READY 0x0004
408 #define AC97_VREF_ON 0x0008
409 #define AC97_PR0 0x0100
410 #define AC97_PR1 0x0200
411 #define AC97_PR2 0x0400
412 #define AC97_PR3 0x0800
413 #define AC97_PR4 0x1000
414
415 #define AC97_RESERVED1 0x28
416
417 #define AC97_VENDOR_TEST 0x5A
418
419 #define AC97_CLOCK_DELAY 0x5C
420 #define AC97_LINEOUT_MUX_SEL 0x0001
421 #define AC97_MONO_MUX_SEL 0x0002
422 #define AC97_CLOCK_DELAY_SEL 0x1F
423 #define AC97_DAC_CDS_SHIFT 6
424 #define AC97_ADC_CDS_SHIFT 11
425
426 #define AC97_MULTI_CHANNEL_SEL 0x74
427
428 /*#define AC97_VENDOR_ID1 0x7C
429 #define AC97_VENDOR_ID2 0x7E*/
430
431 /*
432 * ASSP control regs
433 */
434 #define DSP_PORT_TIMER_COUNT 0x06
435
436 #define DSP_PORT_MEMORY_INDEX 0x80
437
438 #define DSP_PORT_MEMORY_TYPE 0x82
439 #define MEMTYPE_INTERNAL_CODE 0x0002
440 #define MEMTYPE_INTERNAL_DATA 0x0003
441 #define MEMTYPE_MASK 0x0003
442
443 #define DSP_PORT_MEMORY_DATA 0x84
444
445 #define DSP_PORT_CONTROL_REG_A 0xA2
446 #define DSP_PORT_CONTROL_REG_B 0xA4
447 #define DSP_PORT_CONTROL_REG_C 0xA6
448
449 #define REV_A_CODE_MEMORY_BEGIN 0x0000
450 #define REV_A_CODE_MEMORY_END 0x0FFF
451 #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
452 #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
453
454 #define REV_B_CODE_MEMORY_BEGIN 0x0000
455 #define REV_B_CODE_MEMORY_END 0x0BFF
456 #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
457 #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
458
459 #define REV_A_DATA_MEMORY_BEGIN 0x1000
460 #define REV_A_DATA_MEMORY_END 0x2FFF
461 #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
462 #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
463
464 #define REV_B_DATA_MEMORY_BEGIN 0x1000
465 #define REV_B_DATA_MEMORY_END 0x2BFF
466 #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
467 #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
468
469
470 #define NUM_UNITS_KERNEL_CODE 16
471 #define NUM_UNITS_KERNEL_DATA 2
472
473 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
474 #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
475
476 /*
477 * Kernel data layout
478 */
479
480 #define DP_SHIFT_COUNT 7
481
482 #define KDATA_BASE_ADDR 0x1000
483 #define KDATA_BASE_ADDR2 0x1080
484
485 #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
486 #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
487 #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
488 #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
489 #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
490 #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
491 #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
492 #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
493 #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
494
495 #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
496 #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
497
498 #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
499 #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
500 #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
501 #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
502 #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
503 #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
504 #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
505 #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
506 #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
507 #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
508
509 #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
510 #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
511
512 #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
513 #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
514
515 #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
516 #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
517
518 #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
519 #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
520 #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
521
522 #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
523 #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
524 #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
525 #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
526 #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
527
528 #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
529 #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
530 #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
531
532 #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
533 #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
534 #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
535
536 #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
537 #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
538 #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
539 #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
540 #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
541 #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
542 #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
543 #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
544 #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
545 #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
546
547 #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
548 #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
549 #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
550
551 #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
552 #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
553
554 #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
555 #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
556 #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
557
558 #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
559 #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
560 #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
561 #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
562 #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
563 #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
564
565 #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
566 #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
567 #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
568 #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
569 #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
570 #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
571
572 #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
573 #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
574 #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
575 #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
576 #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
577 #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
578
579 #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
580 #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
581 #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
582 #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
583
584 #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
585 #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
586
587 #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
588 #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
589
590 #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
591 #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
592 #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
593 #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
594 #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
595
596 #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
597 #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
598
599 #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
600 #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
601 #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
602
603 #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
604 #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
605
606 #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
607
608 #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
609 #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
610 #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
611 #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
612 #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
613 #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
614 #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
615 #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
616 #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
617 #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
618 #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
619 #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
620
621 #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
622 #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
623 #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
624 #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
625
626 #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
627 #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
628
629 #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
630 #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
631 #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
632 #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
633
634 #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
635 #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
636 #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
637 #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
638 #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
639
640 /*
641 * second 'segment' (?) reserved for mixer
642 * buffers..
643 */
644
645 #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
646 #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
647 #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
648 #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
649 #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
650 #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
651 #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
652 #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
653 #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
654 #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
655 #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
656 #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
657 #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
658 #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
659 #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
660 #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
661
662 #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
663 #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
664 #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
665 #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
666 #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
667 #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
668 #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
669 #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
670 #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
671 #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
672 #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
673
674 #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
675 #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
676 #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
677 #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
678 #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
679 #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
680
681 #define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
682 #define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
683 #define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
684 #define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
685
686 /*
687 * client data area offsets
688 */
689 #define CDATA_INSTANCE_READY 0x00
690
691 #define CDATA_HOST_SRC_ADDRL 0x01
692 #define CDATA_HOST_SRC_ADDRH 0x02
693 #define CDATA_HOST_SRC_END_PLUS_1L 0x03
694 #define CDATA_HOST_SRC_END_PLUS_1H 0x04
695 #define CDATA_HOST_SRC_CURRENTL 0x05
696 #define CDATA_HOST_SRC_CURRENTH 0x06
697
698 #define CDATA_IN_BUF_CONNECT 0x07
699 #define CDATA_OUT_BUF_CONNECT 0x08
700
701 #define CDATA_IN_BUF_BEGIN 0x09
702 #define CDATA_IN_BUF_END_PLUS_1 0x0A
703 #define CDATA_IN_BUF_HEAD 0x0B
704 #define CDATA_IN_BUF_TAIL 0x0C
705 #define CDATA_OUT_BUF_BEGIN 0x0D
706 #define CDATA_OUT_BUF_END_PLUS_1 0x0E
707 #define CDATA_OUT_BUF_HEAD 0x0F
708 #define CDATA_OUT_BUF_TAIL 0x10
709
710 #define CDATA_DMA_CONTROL 0x11
711 #define CDATA_RESERVED 0x12
712
713 #define CDATA_FREQUENCY 0x13
714 #define CDATA_LEFT_VOLUME 0x14
715 #define CDATA_RIGHT_VOLUME 0x15
716 #define CDATA_LEFT_SUR_VOL 0x16
717 #define CDATA_RIGHT_SUR_VOL 0x17
718
719 #define CDATA_HEADER_LEN 0x18
720
721 #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
722 #define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
723 #define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
724 #define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
725 #define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
726 #define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
727 #define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
728 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
729
730 #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
731 #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
732 #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
733 #define MINISRC_BIQUAD_STAGE 2
734 #define MINISRC_COEF_LOC 0x175
735
736 #define DMACONTROL_BLOCK_MASK 0x000F
737 #define DMAC_BLOCK0_SELECTOR 0x0000
738 #define DMAC_BLOCK1_SELECTOR 0x0001
739 #define DMAC_BLOCK2_SELECTOR 0x0002
740 #define DMAC_BLOCK3_SELECTOR 0x0003
741 #define DMAC_BLOCK4_SELECTOR 0x0004
742 #define DMAC_BLOCK5_SELECTOR 0x0005
743 #define DMAC_BLOCK6_SELECTOR 0x0006
744 #define DMAC_BLOCK7_SELECTOR 0x0007
745 #define DMAC_BLOCK8_SELECTOR 0x0008
746 #define DMAC_BLOCK9_SELECTOR 0x0009
747 #define DMAC_BLOCKA_SELECTOR 0x000A
748 #define DMAC_BLOCKB_SELECTOR 0x000B
749 #define DMAC_BLOCKC_SELECTOR 0x000C
750 #define DMAC_BLOCKD_SELECTOR 0x000D
751 #define DMAC_BLOCKE_SELECTOR 0x000E
752 #define DMAC_BLOCKF_SELECTOR 0x000F
753 #define DMACONTROL_PAGE_MASK 0x00F0
754 #define DMAC_PAGE0_SELECTOR 0x0030
755 #define DMAC_PAGE1_SELECTOR 0x0020
756 #define DMAC_PAGE2_SELECTOR 0x0010
757 #define DMAC_PAGE3_SELECTOR 0x0000
758 #define DMACONTROL_AUTOREPEAT 0x1000
759 #define DMACONTROL_STOPPED 0x2000
760 #define DMACONTROL_DIRECTION 0x0100
761
762 /*
763 * an arbitrary volume we set the internal
764 * volume settings to so that the ac97 volume
765 * range is a little less insane. 0x7fff is
766 * max.
767 */
768 #define ARB_VOLUME ( 0x6800 )
769
770 /*
771 */
772
773 struct m3_list {
774 int curlen;
775 int mem_addr;
776 int max;
777 };
778
779 struct m3_dma {
780
781 int number;
782 struct snd_pcm_substream *substream;
783
784 struct assp_instance {
785 unsigned short code, data;
786 } inst;
787
788 int running;
789 int opened;
790
791 unsigned long buffer_addr;
792 int dma_size;
793 int period_size;
794 unsigned int hwptr;
795 int count;
796
797 int index[3];
798 struct m3_list *index_list[3];
799
800 int in_lists;
801
802 struct list_head list;
803
804 };
805
806 struct snd_m3 {
807
808 struct snd_card *card;
809
810 unsigned long iobase;
811
812 int irq;
813 unsigned int allegro_flag : 1;
814
815 struct snd_ac97 *ac97;
816
817 struct snd_pcm *pcm;
818
819 struct pci_dev *pci;
820
821 int dacs_active;
822 int timer_users;
823
824 struct m3_list msrc_list;
825 struct m3_list mixer_list;
826 struct m3_list adc1_list;
827 struct m3_list dma_list;
828
829 /* for storing reset state..*/
830 u8 reset_state;
831
832 int external_amp;
833 int amp_gpio; /* gpio pin # for external amp, -1 = default */
834 unsigned int hv_config; /* hardware-volume config bits */
835 unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION
836 (e.g. for IrDA on Dell Inspirons) */
837 unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */
838
839 /* midi */
840 struct snd_rawmidi *rmidi;
841
842 /* pcm streams */
843 int num_substreams;
844 struct m3_dma *substreams;
845
846 spinlock_t reg_lock;
847
848 #ifdef CONFIG_SND_MAESTRO3_INPUT
849 struct input_dev *input_dev;
850 char phys[64]; /* physical device path */
851 #else
852 spinlock_t ac97_lock;
853 struct snd_kcontrol *master_switch;
854 struct snd_kcontrol *master_volume;
855 struct tasklet_struct hwvol_tq;
856 #endif
857
858 unsigned int in_suspend;
859
860 #ifdef CONFIG_PM
861 u16 *suspend_mem;
862 #endif
863
864 const struct firmware *assp_kernel_image;
865 const struct firmware *assp_minisrc_image;
866 };
867
868 /*
869 * pci ids
870 */
871 static DEFINE_PCI_DEVICE_TABLE(snd_m3_ids) = {
872 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
873 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
874 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
875 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
876 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
877 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
878 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
879 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
880 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
881 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
882 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
883 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
884 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
885 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
886 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
887 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
888 {0,},
889 };
890
891 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
892
893 static struct snd_pci_quirk m3_amp_quirk_list[] __devinitdata = {
894 SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c", 0x0c),
895 SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
896 SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
897 SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
898 SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
899 { } /* END */
900 };
901
902 static struct snd_pci_quirk m3_irda_quirk_list[] __devinitdata = {
903 SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
904 SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
905 SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
906 { } /* END */
907 };
908
909 /* hardware volume quirks */
910 static struct snd_pci_quirk m3_hv_quirk_list[] __devinitdata = {
911 /* Allegro chips */
912 SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
913 SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
914 SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
915 SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
916 SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
917 SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
918 SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
919 SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
920 SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
921 SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
922 SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
923 SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
924 SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
925 SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
926 SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
927 SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
928 SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
929 SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
930 SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
931 SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
932 SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
933 SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
934 SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
935 SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
936 SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
937 SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
938 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
939 SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
940 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
941 SND_PCI_QUIRK(0x107B, 0x340A, NULL,
942 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
943 SND_PCI_QUIRK(0x107B, 0x3450, NULL,
944 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
945 SND_PCI_QUIRK(0x109F, 0x3134, NULL,
946 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
947 SND_PCI_QUIRK(0x109F, 0x3161, NULL,
948 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
949 SND_PCI_QUIRK(0x144D, 0x3280, NULL,
950 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
951 SND_PCI_QUIRK(0x144D, 0x3281, NULL,
952 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
953 SND_PCI_QUIRK(0x144D, 0xC002, NULL,
954 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
955 SND_PCI_QUIRK(0x144D, 0xC003, NULL,
956 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
957 SND_PCI_QUIRK(0x1509, 0x1740, NULL,
958 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
959 SND_PCI_QUIRK(0x1610, 0x0010, NULL,
960 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
961 SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
962 SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
963 SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
964 SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
965 SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
966 /* Maestro3 chips */
967 SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
968 SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
969 SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
970 SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
971 SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
972 SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
973 SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
974 SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
975 SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
976 SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
977 SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
978 SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
979 SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
980 SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
981 SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
982 SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
983 SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
984 { } /* END */
985 };
986
987 /* HP Omnibook quirks */
988 static struct snd_pci_quirk m3_omnibook_quirk_list[] __devinitdata = {
989 SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
990 SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
991 { } /* END */
992 };
993
994 /*
995 * lowlevel functions
996 */
997
998 static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
999 {
1000 outw(value, chip->iobase + reg);
1001 }
1002
1003 static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
1004 {
1005 return inw(chip->iobase + reg);
1006 }
1007
1008 static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
1009 {
1010 outb(value, chip->iobase + reg);
1011 }
1012
1013 static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
1014 {
1015 return inb(chip->iobase + reg);
1016 }
1017
1018 /*
1019 * access 16bit words to the code or data regions of the dsp's memory.
1020 * index addresses 16bit words.
1021 */
1022 static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
1023 {
1024 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1025 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1026 return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1027 }
1028
1029 static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
1030 {
1031 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1032 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1033 snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1034 }
1035
1036 static void snd_m3_assp_halt(struct snd_m3 *chip)
1037 {
1038 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1039 msleep(10);
1040 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1041 }
1042
1043 static void snd_m3_assp_continue(struct snd_m3 *chip)
1044 {
1045 snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1046 }
1047
1048
1049 /*
1050 * This makes me sad. the maestro3 has lists
1051 * internally that must be packed.. 0 terminates,
1052 * apparently, or maybe all unused entries have
1053 * to be 0, the lists have static lengths set
1054 * by the binary code images.
1055 */
1056
1057 static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
1058 {
1059 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1060 list->mem_addr + list->curlen,
1061 val);
1062 return list->curlen++;
1063 }
1064
1065 static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
1066 {
1067 u16 val;
1068 int lastindex = list->curlen - 1;
1069
1070 if (index != lastindex) {
1071 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1072 list->mem_addr + lastindex);
1073 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1074 list->mem_addr + index,
1075 val);
1076 }
1077
1078 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1079 list->mem_addr + lastindex,
1080 0);
1081
1082 list->curlen--;
1083 }
1084
1085 static void snd_m3_inc_timer_users(struct snd_m3 *chip)
1086 {
1087 chip->timer_users++;
1088 if (chip->timer_users != 1)
1089 return;
1090
1091 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1092 KDATA_TIMER_COUNT_RELOAD,
1093 240);
1094
1095 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1096 KDATA_TIMER_COUNT_CURRENT,
1097 240);
1098
1099 snd_m3_outw(chip,
1100 snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1101 HOST_INT_CTRL);
1102 }
1103
1104 static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1105 {
1106 chip->timer_users--;
1107 if (chip->timer_users > 0)
1108 return;
1109
1110 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1111 KDATA_TIMER_COUNT_RELOAD,
1112 0);
1113
1114 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1115 KDATA_TIMER_COUNT_CURRENT,
1116 0);
1117
1118 snd_m3_outw(chip,
1119 snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1120 HOST_INT_CTRL);
1121 }
1122
1123 /*
1124 * start/stop
1125 */
1126
1127 /* spinlock held! */
1128 static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1129 struct snd_pcm_substream *subs)
1130 {
1131 if (! s || ! subs)
1132 return -EINVAL;
1133
1134 snd_m3_inc_timer_users(chip);
1135 switch (subs->stream) {
1136 case SNDRV_PCM_STREAM_PLAYBACK:
1137 chip->dacs_active++;
1138 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1139 s->inst.data + CDATA_INSTANCE_READY, 1);
1140 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1141 KDATA_MIXER_TASK_NUMBER,
1142 chip->dacs_active);
1143 break;
1144 case SNDRV_PCM_STREAM_CAPTURE:
1145 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1146 KDATA_ADC1_REQUEST, 1);
1147 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1148 s->inst.data + CDATA_INSTANCE_READY, 1);
1149 break;
1150 }
1151 return 0;
1152 }
1153
1154 /* spinlock held! */
1155 static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1156 struct snd_pcm_substream *subs)
1157 {
1158 if (! s || ! subs)
1159 return -EINVAL;
1160
1161 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1162 s->inst.data + CDATA_INSTANCE_READY, 0);
1163 snd_m3_dec_timer_users(chip);
1164 switch (subs->stream) {
1165 case SNDRV_PCM_STREAM_PLAYBACK:
1166 chip->dacs_active--;
1167 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1168 KDATA_MIXER_TASK_NUMBER,
1169 chip->dacs_active);
1170 break;
1171 case SNDRV_PCM_STREAM_CAPTURE:
1172 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1173 KDATA_ADC1_REQUEST, 0);
1174 break;
1175 }
1176 return 0;
1177 }
1178
1179 static int
1180 snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1181 {
1182 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1183 struct m3_dma *s = subs->runtime->private_data;
1184 int err = -EINVAL;
1185
1186 if (snd_BUG_ON(!s))
1187 return -ENXIO;
1188
1189 spin_lock(&chip->reg_lock);
1190 switch (cmd) {
1191 case SNDRV_PCM_TRIGGER_START:
1192 case SNDRV_PCM_TRIGGER_RESUME:
1193 if (s->running)
1194 err = -EBUSY;
1195 else {
1196 s->running = 1;
1197 err = snd_m3_pcm_start(chip, s, subs);
1198 }
1199 break;
1200 case SNDRV_PCM_TRIGGER_STOP:
1201 case SNDRV_PCM_TRIGGER_SUSPEND:
1202 if (! s->running)
1203 err = 0; /* should return error? */
1204 else {
1205 s->running = 0;
1206 err = snd_m3_pcm_stop(chip, s, subs);
1207 }
1208 break;
1209 }
1210 spin_unlock(&chip->reg_lock);
1211 return err;
1212 }
1213
1214 /*
1215 * setup
1216 */
1217 static void
1218 snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1219 {
1220 int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1221 struct snd_pcm_runtime *runtime = subs->runtime;
1222
1223 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1224 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1225 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1226 } else {
1227 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1228 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1229 }
1230 dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1231 dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1232
1233 s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1234 s->period_size = frames_to_bytes(runtime, runtime->period_size);
1235 s->hwptr = 0;
1236 s->count = 0;
1237
1238 #define LO(x) ((x) & 0xffff)
1239 #define HI(x) LO((x) >> 16)
1240
1241 /* host dma buffer pointers */
1242 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1243 s->inst.data + CDATA_HOST_SRC_ADDRL,
1244 LO(s->buffer_addr));
1245
1246 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1247 s->inst.data + CDATA_HOST_SRC_ADDRH,
1248 HI(s->buffer_addr));
1249
1250 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1251 s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1252 LO(s->buffer_addr + s->dma_size));
1253
1254 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1255 s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1256 HI(s->buffer_addr + s->dma_size));
1257
1258 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1259 s->inst.data + CDATA_HOST_SRC_CURRENTL,
1260 LO(s->buffer_addr));
1261
1262 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1263 s->inst.data + CDATA_HOST_SRC_CURRENTH,
1264 HI(s->buffer_addr));
1265 #undef LO
1266 #undef HI
1267
1268 /* dsp buffers */
1269
1270 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1271 s->inst.data + CDATA_IN_BUF_BEGIN,
1272 dsp_in_buffer);
1273
1274 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1275 s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1276 dsp_in_buffer + (dsp_in_size / 2));
1277
1278 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1279 s->inst.data + CDATA_IN_BUF_HEAD,
1280 dsp_in_buffer);
1281
1282 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1283 s->inst.data + CDATA_IN_BUF_TAIL,
1284 dsp_in_buffer);
1285
1286 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1287 s->inst.data + CDATA_OUT_BUF_BEGIN,
1288 dsp_out_buffer);
1289
1290 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1291 s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1292 dsp_out_buffer + (dsp_out_size / 2));
1293
1294 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1295 s->inst.data + CDATA_OUT_BUF_HEAD,
1296 dsp_out_buffer);
1297
1298 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1299 s->inst.data + CDATA_OUT_BUF_TAIL,
1300 dsp_out_buffer);
1301 }
1302
1303 static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1304 struct snd_pcm_runtime *runtime)
1305 {
1306 u32 freq;
1307
1308 /*
1309 * put us in the lists if we're not already there
1310 */
1311 if (! s->in_lists) {
1312 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1313 s->inst.data >> DP_SHIFT_COUNT);
1314 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1315 s->inst.data >> DP_SHIFT_COUNT);
1316 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1317 s->inst.data >> DP_SHIFT_COUNT);
1318 s->in_lists = 1;
1319 }
1320
1321 /* write to 'mono' word */
1322 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1323 s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1324 runtime->channels == 2 ? 0 : 1);
1325 /* write to '8bit' word */
1326 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1327 s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1328 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1329
1330 /* set up dac/adc rate */
1331 freq = ((runtime->rate << 15) + 24000 ) / 48000;
1332 if (freq)
1333 freq--;
1334
1335 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1336 s->inst.data + CDATA_FREQUENCY,
1337 freq);
1338 }
1339
1340
1341 static const struct play_vals {
1342 u16 addr, val;
1343 } pv[] = {
1344 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1345 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1346 {SRC3_DIRECTION_OFFSET, 0} ,
1347 /* +1, +2 are stereo/16 bit */
1348 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1349 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1350 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1351 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1352 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1353 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1354 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1355 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1356 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1357 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1358 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1359 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1360 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1361 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1362 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1363 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1364 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1365 };
1366
1367
1368 /* the mode passed should be already shifted and masked */
1369 static void
1370 snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1371 struct snd_pcm_substream *subs)
1372 {
1373 unsigned int i;
1374
1375 /*
1376 * some per client initializers
1377 */
1378
1379 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1380 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1381 s->inst.data + 40 + 8);
1382
1383 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1384 s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1385 s->inst.code + MINISRC_COEF_LOC);
1386
1387 /* enable or disable low pass filter? */
1388 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1389 s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1390 subs->runtime->rate > 45000 ? 0xff : 0);
1391
1392 /* tell it which way dma is going? */
1393 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1394 s->inst.data + CDATA_DMA_CONTROL,
1395 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1396
1397 /*
1398 * set an armload of static initializers
1399 */
1400 for (i = 0; i < ARRAY_SIZE(pv); i++)
1401 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1402 s->inst.data + pv[i].addr, pv[i].val);
1403 }
1404
1405 /*
1406 * Native record driver
1407 */
1408 static const struct rec_vals {
1409 u16 addr, val;
1410 } rv[] = {
1411 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1412 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1413 {SRC3_DIRECTION_OFFSET, 1} ,
1414 /* +1, +2 are stereo/16 bit */
1415 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1416 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1417 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1418 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1419 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1420 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1421 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1422 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1423 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1424 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1425 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1426 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1427 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1428 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1429 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1430 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1431 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1432 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1433 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1434 };
1435
1436 static void
1437 snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1438 {
1439 unsigned int i;
1440
1441 /*
1442 * some per client initializers
1443 */
1444
1445 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1446 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1447 s->inst.data + 40 + 8);
1448
1449 /* tell it which way dma is going? */
1450 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1451 s->inst.data + CDATA_DMA_CONTROL,
1452 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1453 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1454
1455 /*
1456 * set an armload of static initializers
1457 */
1458 for (i = 0; i < ARRAY_SIZE(rv); i++)
1459 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1460 s->inst.data + rv[i].addr, rv[i].val);
1461 }
1462
1463 static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1464 struct snd_pcm_hw_params *hw_params)
1465 {
1466 struct m3_dma *s = substream->runtime->private_data;
1467 int err;
1468
1469 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1470 return err;
1471 /* set buffer address */
1472 s->buffer_addr = substream->runtime->dma_addr;
1473 if (s->buffer_addr & 0x3) {
1474 snd_printk(KERN_ERR "oh my, not aligned\n");
1475 s->buffer_addr = s->buffer_addr & ~0x3;
1476 }
1477 return 0;
1478 }
1479
1480 static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1481 {
1482 struct m3_dma *s;
1483
1484 if (substream->runtime->private_data == NULL)
1485 return 0;
1486 s = substream->runtime->private_data;
1487 snd_pcm_lib_free_pages(substream);
1488 s->buffer_addr = 0;
1489 return 0;
1490 }
1491
1492 static int
1493 snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1494 {
1495 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1496 struct snd_pcm_runtime *runtime = subs->runtime;
1497 struct m3_dma *s = runtime->private_data;
1498
1499 if (snd_BUG_ON(!s))
1500 return -ENXIO;
1501
1502 if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1503 runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1504 return -EINVAL;
1505 if (runtime->rate > 48000 ||
1506 runtime->rate < 8000)
1507 return -EINVAL;
1508
1509 spin_lock_irq(&chip->reg_lock);
1510
1511 snd_m3_pcm_setup1(chip, s, subs);
1512
1513 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1514 snd_m3_playback_setup(chip, s, subs);
1515 else
1516 snd_m3_capture_setup(chip, s, subs);
1517
1518 snd_m3_pcm_setup2(chip, s, runtime);
1519
1520 spin_unlock_irq(&chip->reg_lock);
1521
1522 return 0;
1523 }
1524
1525 /*
1526 * get current pointer
1527 */
1528 static unsigned int
1529 snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1530 {
1531 u16 hi = 0, lo = 0;
1532 int retry = 10;
1533 u32 addr;
1534
1535 /*
1536 * try and get a valid answer
1537 */
1538 while (retry--) {
1539 hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1540 s->inst.data + CDATA_HOST_SRC_CURRENTH);
1541
1542 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1543 s->inst.data + CDATA_HOST_SRC_CURRENTL);
1544
1545 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1546 s->inst.data + CDATA_HOST_SRC_CURRENTH))
1547 break;
1548 }
1549 addr = lo | ((u32)hi<<16);
1550 return (unsigned int)(addr - s->buffer_addr);
1551 }
1552
1553 static snd_pcm_uframes_t
1554 snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1555 {
1556 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1557 unsigned int ptr;
1558 struct m3_dma *s = subs->runtime->private_data;
1559
1560 if (snd_BUG_ON(!s))
1561 return 0;
1562
1563 spin_lock(&chip->reg_lock);
1564 ptr = snd_m3_get_pointer(chip, s, subs);
1565 spin_unlock(&chip->reg_lock);
1566 return bytes_to_frames(subs->runtime, ptr);
1567 }
1568
1569
1570 /* update pointer */
1571 /* spinlock held! */
1572 static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1573 {
1574 struct snd_pcm_substream *subs = s->substream;
1575 unsigned int hwptr;
1576 int diff;
1577
1578 if (! s->running)
1579 return;
1580
1581 hwptr = snd_m3_get_pointer(chip, s, subs);
1582
1583 /* try to avoid expensive modulo divisions */
1584 if (hwptr >= s->dma_size)
1585 hwptr %= s->dma_size;
1586
1587 diff = s->dma_size + hwptr - s->hwptr;
1588 if (diff >= s->dma_size)
1589 diff %= s->dma_size;
1590
1591 s->hwptr = hwptr;
1592 s->count += diff;
1593
1594 if (s->count >= (signed)s->period_size) {
1595
1596 if (s->count < 2 * (signed)s->period_size)
1597 s->count -= (signed)s->period_size;
1598 else
1599 s->count %= s->period_size;
1600
1601 spin_unlock(&chip->reg_lock);
1602 snd_pcm_period_elapsed(subs);
1603 spin_lock(&chip->reg_lock);
1604 }
1605 }
1606
1607 /* The m3's hardware volume works by incrementing / decrementing 2 counters
1608 (without wrap around) in response to volume button presses and then
1609 generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7
1610 of a byte wide register. The meaning of bits 0 and 4 is unknown. */
1611 static void snd_m3_update_hw_volume(unsigned long private_data)
1612 {
1613 struct snd_m3 *chip = (struct snd_m3 *) private_data;
1614 int x, val;
1615 #ifndef CONFIG_SND_MAESTRO3_INPUT
1616 unsigned long flags;
1617 #endif
1618
1619 /* Figure out which volume control button was pushed,
1620 based on differences from the default register
1621 values. */
1622 x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1623
1624 /* Reset the volume counters to 4. Tests on the allegro integrated
1625 into a Compaq N600C laptop, have revealed that:
1626 1) Writing any value will result in the 2 counters being reset to
1627 4 so writing 0x88 is not strictly necessary
1628 2) Writing to any of the 4 involved registers will reset all 4
1629 of them (and reading them always returns the same value for all
1630 of them)
1631 It could be that a maestro deviates from this, so leave the code
1632 as is. */
1633 outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1634 outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1635 outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1636 outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1637
1638 /* Ignore spurious HV interrupts during suspend / resume, this avoids
1639 mistaking them for a mute button press. */
1640 if (chip->in_suspend)
1641 return;
1642
1643 #ifndef CONFIG_SND_MAESTRO3_INPUT
1644 if (!chip->master_switch || !chip->master_volume)
1645 return;
1646
1647 spin_lock_irqsave(&chip->ac97_lock, flags);
1648
1649 val = chip->ac97->regs[AC97_MASTER_VOL];
1650 switch (x) {
1651 case 0x88:
1652 /* The counters have not changed, yet we've received a HV
1653 interrupt. According to tests run by various people this
1654 happens when pressing the mute button. */
1655 val ^= 0x8000;
1656 chip->ac97->regs[AC97_MASTER_VOL] = val;
1657 outw(val, chip->iobase + CODEC_DATA);
1658 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1659 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1660 &chip->master_switch->id);
1661 break;
1662 case 0xaa:
1663 /* counters increased by 1 -> volume up */
1664 if ((val & 0x7f) > 0)
1665 val--;
1666 if ((val & 0x7f00) > 0)
1667 val -= 0x0100;
1668 chip->ac97->regs[AC97_MASTER_VOL] = val;
1669 outw(val, chip->iobase + CODEC_DATA);
1670 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1671 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1672 &chip->master_volume->id);
1673 break;
1674 case 0x66:
1675 /* counters decreased by 1 -> volume down */
1676 if ((val & 0x7f) < 0x1f)
1677 val++;
1678 if ((val & 0x7f00) < 0x1f00)
1679 val += 0x0100;
1680 chip->ac97->regs[AC97_MASTER_VOL] = val;
1681 outw(val, chip->iobase + CODEC_DATA);
1682 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1683 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1684 &chip->master_volume->id);
1685 break;
1686 }
1687 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1688 #else
1689 if (!chip->input_dev)
1690 return;
1691
1692 val = 0;
1693 switch (x) {
1694 case 0x88:
1695 /* The counters have not changed, yet we've received a HV
1696 interrupt. According to tests run by various people this
1697 happens when pressing the mute button. */
1698 val = KEY_MUTE;
1699 break;
1700 case 0xaa:
1701 /* counters increased by 1 -> volume up */
1702 val = KEY_VOLUMEUP;
1703 break;
1704 case 0x66:
1705 /* counters decreased by 1 -> volume down */
1706 val = KEY_VOLUMEDOWN;
1707 break;
1708 }
1709
1710 if (val) {
1711 input_report_key(chip->input_dev, val, 1);
1712 input_sync(chip->input_dev);
1713 input_report_key(chip->input_dev, val, 0);
1714 input_sync(chip->input_dev);
1715 }
1716 #endif
1717 }
1718
1719 static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
1720 {
1721 struct snd_m3 *chip = dev_id;
1722 u8 status;
1723 int i;
1724
1725 status = inb(chip->iobase + HOST_INT_STATUS);
1726
1727 if (status == 0xff)
1728 return IRQ_NONE;
1729
1730 if (status & HV_INT_PENDING)
1731 #ifdef CONFIG_SND_MAESTRO3_INPUT
1732 snd_m3_update_hw_volume((unsigned long)chip);
1733 #else
1734 tasklet_schedule(&chip->hwvol_tq);
1735 #endif
1736
1737 /*
1738 * ack an assp int if its running
1739 * and has an int pending
1740 */
1741 if (status & ASSP_INT_PENDING) {
1742 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1743 if (!(ctl & STOP_ASSP_CLOCK)) {
1744 ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1745 if (ctl & DSP2HOST_REQ_TIMER) {
1746 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1747 /* update adc/dac info if it was a timer int */
1748 spin_lock(&chip->reg_lock);
1749 for (i = 0; i < chip->num_substreams; i++) {
1750 struct m3_dma *s = &chip->substreams[i];
1751 if (s->running)
1752 snd_m3_update_ptr(chip, s);
1753 }
1754 spin_unlock(&chip->reg_lock);
1755 }
1756 }
1757 }
1758
1759
1760 /* ack ints */
1761 outb(status, chip->iobase + HOST_INT_STATUS);
1762
1763 return IRQ_HANDLED;
1764 }
1765
1766
1767 /*
1768 */
1769
1770 static struct snd_pcm_hardware snd_m3_playback =
1771 {
1772 .info = (SNDRV_PCM_INFO_MMAP |
1773 SNDRV_PCM_INFO_INTERLEAVED |
1774 SNDRV_PCM_INFO_MMAP_VALID |
1775 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1776 /*SNDRV_PCM_INFO_PAUSE |*/
1777 SNDRV_PCM_INFO_RESUME),
1778 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1779 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1780 .rate_min = 8000,
1781 .rate_max = 48000,
1782 .channels_min = 1,
1783 .channels_max = 2,
1784 .buffer_bytes_max = (512*1024),
1785 .period_bytes_min = 64,
1786 .period_bytes_max = (512*1024),
1787 .periods_min = 1,
1788 .periods_max = 1024,
1789 };
1790
1791 static struct snd_pcm_hardware snd_m3_capture =
1792 {
1793 .info = (SNDRV_PCM_INFO_MMAP |
1794 SNDRV_PCM_INFO_INTERLEAVED |
1795 SNDRV_PCM_INFO_MMAP_VALID |
1796 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1797 /*SNDRV_PCM_INFO_PAUSE |*/
1798 SNDRV_PCM_INFO_RESUME),
1799 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1800 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1801 .rate_min = 8000,
1802 .rate_max = 48000,
1803 .channels_min = 1,
1804 .channels_max = 2,
1805 .buffer_bytes_max = (512*1024),
1806 .period_bytes_min = 64,
1807 .period_bytes_max = (512*1024),
1808 .periods_min = 1,
1809 .periods_max = 1024,
1810 };
1811
1812
1813 /*
1814 */
1815
1816 static int
1817 snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1818 {
1819 int i;
1820 struct m3_dma *s;
1821
1822 spin_lock_irq(&chip->reg_lock);
1823 for (i = 0; i < chip->num_substreams; i++) {
1824 s = &chip->substreams[i];
1825 if (! s->opened)
1826 goto __found;
1827 }
1828 spin_unlock_irq(&chip->reg_lock);
1829 return -ENOMEM;
1830 __found:
1831 s->opened = 1;
1832 s->running = 0;
1833 spin_unlock_irq(&chip->reg_lock);
1834
1835 subs->runtime->private_data = s;
1836 s->substream = subs;
1837
1838 /* set list owners */
1839 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1840 s->index_list[0] = &chip->mixer_list;
1841 } else
1842 s->index_list[0] = &chip->adc1_list;
1843 s->index_list[1] = &chip->msrc_list;
1844 s->index_list[2] = &chip->dma_list;
1845
1846 return 0;
1847 }
1848
1849 static void
1850 snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1851 {
1852 struct m3_dma *s = subs->runtime->private_data;
1853
1854 if (s == NULL)
1855 return; /* not opened properly */
1856
1857 spin_lock_irq(&chip->reg_lock);
1858 if (s->substream && s->running)
1859 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1860 if (s->in_lists) {
1861 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1862 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1863 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1864 s->in_lists = 0;
1865 }
1866 s->running = 0;
1867 s->opened = 0;
1868 spin_unlock_irq(&chip->reg_lock);
1869 }
1870
1871 static int
1872 snd_m3_playback_open(struct snd_pcm_substream *subs)
1873 {
1874 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1875 struct snd_pcm_runtime *runtime = subs->runtime;
1876 int err;
1877
1878 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1879 return err;
1880
1881 runtime->hw = snd_m3_playback;
1882
1883 return 0;
1884 }
1885
1886 static int
1887 snd_m3_playback_close(struct snd_pcm_substream *subs)
1888 {
1889 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1890
1891 snd_m3_substream_close(chip, subs);
1892 return 0;
1893 }
1894
1895 static int
1896 snd_m3_capture_open(struct snd_pcm_substream *subs)
1897 {
1898 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1899 struct snd_pcm_runtime *runtime = subs->runtime;
1900 int err;
1901
1902 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1903 return err;
1904
1905 runtime->hw = snd_m3_capture;
1906
1907 return 0;
1908 }
1909
1910 static int
1911 snd_m3_capture_close(struct snd_pcm_substream *subs)
1912 {
1913 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1914
1915 snd_m3_substream_close(chip, subs);
1916 return 0;
1917 }
1918
1919 /*
1920 * create pcm instance
1921 */
1922
1923 static struct snd_pcm_ops snd_m3_playback_ops = {
1924 .open = snd_m3_playback_open,
1925 .close = snd_m3_playback_close,
1926 .ioctl = snd_pcm_lib_ioctl,
1927 .hw_params = snd_m3_pcm_hw_params,
1928 .hw_free = snd_m3_pcm_hw_free,
1929 .prepare = snd_m3_pcm_prepare,
1930 .trigger = snd_m3_pcm_trigger,
1931 .pointer = snd_m3_pcm_pointer,
1932 };
1933
1934 static struct snd_pcm_ops snd_m3_capture_ops = {
1935 .open = snd_m3_capture_open,
1936 .close = snd_m3_capture_close,
1937 .ioctl = snd_pcm_lib_ioctl,
1938 .hw_params = snd_m3_pcm_hw_params,
1939 .hw_free = snd_m3_pcm_hw_free,
1940 .prepare = snd_m3_pcm_prepare,
1941 .trigger = snd_m3_pcm_trigger,
1942 .pointer = snd_m3_pcm_pointer,
1943 };
1944
1945 static int __devinit
1946 snd_m3_pcm(struct snd_m3 * chip, int device)
1947 {
1948 struct snd_pcm *pcm;
1949 int err;
1950
1951 err = snd_pcm_new(chip->card, chip->card->driver, device,
1952 MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1953 if (err < 0)
1954 return err;
1955
1956 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1957 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1958
1959 pcm->private_data = chip;
1960 pcm->info_flags = 0;
1961 strcpy(pcm->name, chip->card->driver);
1962 chip->pcm = pcm;
1963
1964 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1965 snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1966
1967 return 0;
1968 }
1969
1970
1971 /*
1972 * ac97 interface
1973 */
1974
1975 /*
1976 * Wait for the ac97 serial bus to be free.
1977 * return nonzero if the bus is still busy.
1978 */
1979 static int snd_m3_ac97_wait(struct snd_m3 *chip)
1980 {
1981 int i = 10000;
1982
1983 do {
1984 if (! (snd_m3_inb(chip, 0x30) & 1))
1985 return 0;
1986 cpu_relax();
1987 } while (i-- > 0);
1988
1989 snd_printk(KERN_ERR "ac97 serial bus busy\n");
1990 return 1;
1991 }
1992
1993 static unsigned short
1994 snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1995 {
1996 struct snd_m3 *chip = ac97->private_data;
1997 #ifndef CONFIG_SND_MAESTRO3_INPUT
1998 unsigned long flags;
1999 #endif
2000 unsigned short data = 0xffff;
2001
2002 if (snd_m3_ac97_wait(chip))
2003 goto fail;
2004 #ifndef CONFIG_SND_MAESTRO3_INPUT
2005 spin_lock_irqsave(&chip->ac97_lock, flags);
2006 #endif
2007 snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
2008 if (snd_m3_ac97_wait(chip))
2009 goto fail_unlock;
2010 data = snd_m3_inw(chip, CODEC_DATA);
2011 fail_unlock:
2012 #ifndef CONFIG_SND_MAESTRO3_INPUT
2013 spin_unlock_irqrestore(&chip->ac97_lock, flags);
2014 #endif
2015 fail:
2016 return data;
2017 }
2018
2019 static void
2020 snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
2021 {
2022 struct snd_m3 *chip = ac97->private_data;
2023 #ifndef CONFIG_SND_MAESTRO3_INPUT
2024 unsigned long flags;
2025 #endif
2026
2027 if (snd_m3_ac97_wait(chip))
2028 return;
2029 #ifndef CONFIG_SND_MAESTRO3_INPUT
2030 spin_lock_irqsave(&chip->ac97_lock, flags);
2031 #endif
2032 snd_m3_outw(chip, val, CODEC_DATA);
2033 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
2034 #ifndef CONFIG_SND_MAESTRO3_INPUT
2035 spin_unlock_irqrestore(&chip->ac97_lock, flags);
2036 #endif
2037 }
2038
2039
2040 static void snd_m3_remote_codec_config(int io, int isremote)
2041 {
2042 isremote = isremote ? 1 : 0;
2043
2044 outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
2045 io + RING_BUS_CTRL_B);
2046 outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
2047 io + SDO_OUT_DEST_CTRL);
2048 outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
2049 io + SDO_IN_DEST_CTRL);
2050 }
2051
2052 /*
2053 * hack, returns non zero on err
2054 */
2055 static int snd_m3_try_read_vendor(struct snd_m3 *chip)
2056 {
2057 u16 ret;
2058
2059 if (snd_m3_ac97_wait(chip))
2060 return 1;
2061
2062 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
2063
2064 if (snd_m3_ac97_wait(chip))
2065 return 1;
2066
2067 ret = snd_m3_inw(chip, 0x32);
2068
2069 return (ret == 0) || (ret == 0xffff);
2070 }
2071
2072 static void snd_m3_ac97_reset(struct snd_m3 *chip)
2073 {
2074 u16 dir;
2075 int delay1 = 0, delay2 = 0, i;
2076 int io = chip->iobase;
2077
2078 if (chip->allegro_flag) {
2079 /*
2080 * the onboard codec on the allegro seems
2081 * to want to wait a very long time before
2082 * coming back to life
2083 */
2084 delay1 = 50;
2085 delay2 = 800;
2086 } else {
2087 /* maestro3 */
2088 delay1 = 20;
2089 delay2 = 500;
2090 }
2091
2092 for (i = 0; i < 5; i++) {
2093 dir = inw(io + GPIO_DIRECTION);
2094 if (!chip->irda_workaround)
2095 dir |= 0x10; /* assuming pci bus master? */
2096
2097 snd_m3_remote_codec_config(io, 0);
2098
2099 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2100 udelay(20);
2101
2102 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2103 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2104 outw(0, io + GPIO_DATA);
2105 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2106
2107 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2108
2109 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2110 udelay(5);
2111 /* ok, bring back the ac-link */
2112 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2113 outw(~0, io + GPIO_MASK);
2114
2115 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2116
2117 if (! snd_m3_try_read_vendor(chip))
2118 break;
2119
2120 delay1 += 10;
2121 delay2 += 100;
2122
2123 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
2124 delay1, delay2);
2125 }
2126
2127 }
2128
2129 static int __devinit snd_m3_mixer(struct snd_m3 *chip)
2130 {
2131 struct snd_ac97_bus *pbus;
2132 struct snd_ac97_template ac97;
2133 #ifndef CONFIG_SND_MAESTRO3_INPUT
2134 struct snd_ctl_elem_id elem_id;
2135 #endif
2136 int err;
2137 static struct snd_ac97_bus_ops ops = {
2138 .write = snd_m3_ac97_write,
2139 .read = snd_m3_ac97_read,
2140 };
2141
2142 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2143 return err;
2144
2145 memset(&ac97, 0, sizeof(ac97));
2146 ac97.private_data = chip;
2147 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2148 return err;
2149
2150 /* seems ac97 PCM needs initialization.. hack hack.. */
2151 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2152 schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2153 snd_ac97_write(chip->ac97, AC97_PCM, 0);
2154
2155 #ifndef CONFIG_SND_MAESTRO3_INPUT
2156 memset(&elem_id, 0, sizeof(elem_id));
2157 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2158 strcpy(elem_id.name, "Master Playback Switch");
2159 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2160 memset(&elem_id, 0, sizeof(elem_id));
2161 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2162 strcpy(elem_id.name, "Master Playback Volume");
2163 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
2164 #endif
2165
2166 return 0;
2167 }
2168
2169
2170 /*
2171 * initialize ASSP
2172 */
2173
2174 #define MINISRC_LPF_LEN 10
2175 static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2176 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2177 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2178 };
2179
2180 static void snd_m3_assp_init(struct snd_m3 *chip)
2181 {
2182 unsigned int i;
2183 const u16 *data;
2184
2185 /* zero kernel data */
2186 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2187 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2188 KDATA_BASE_ADDR + i, 0);
2189
2190 /* zero mixer data? */
2191 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2192 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2193 KDATA_BASE_ADDR2 + i, 0);
2194
2195 /* init dma pointer */
2196 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2197 KDATA_CURRENT_DMA,
2198 KDATA_DMA_XFER0);
2199
2200 /* write kernel into code memory.. */
2201 data = (const u16 *)chip->assp_kernel_image->data;
2202 for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
2203 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2204 REV_B_CODE_MEMORY_BEGIN + i,
2205 le16_to_cpu(data[i]));
2206 }
2207
2208 /*
2209 * We only have this one client and we know that 0x400
2210 * is free in our kernel's mem map, so lets just
2211 * drop it there. It seems that the minisrc doesn't
2212 * need vectors, so we won't bother with them..
2213 */
2214 data = (const u16 *)chip->assp_minisrc_image->data;
2215 for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
2216 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2217 0x400 + i, le16_to_cpu(data[i]));
2218 }
2219
2220 /*
2221 * write the coefficients for the low pass filter?
2222 */
2223 for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2224 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2225 0x400 + MINISRC_COEF_LOC + i,
2226 minisrc_lpf[i]);
2227 }
2228
2229 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2230 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2231 0x8000);
2232
2233 /*
2234 * the minisrc is the only thing on
2235 * our task list..
2236 */
2237 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2238 KDATA_TASK0,
2239 0x400);
2240
2241 /*
2242 * init the mixer number..
2243 */
2244
2245 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2246 KDATA_MIXER_TASK_NUMBER,0);
2247
2248 /*
2249 * EXTREME KERNEL MASTER VOLUME
2250 */
2251 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2252 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2253 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2254 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2255
2256 chip->mixer_list.curlen = 0;
2257 chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2258 chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2259 chip->adc1_list.curlen = 0;
2260 chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2261 chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2262 chip->dma_list.curlen = 0;
2263 chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2264 chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2265 chip->msrc_list.curlen = 0;
2266 chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2267 chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2268 }
2269
2270
2271 static int __devinit snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2272 {
2273 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2274 MINISRC_IN_BUFFER_SIZE / 2 +
2275 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2276 int address, i;
2277
2278 /*
2279 * the revb memory map has 0x1100 through 0x1c00
2280 * free.
2281 */
2282
2283 /*
2284 * align instance address to 256 bytes so that its
2285 * shifted list address is aligned.
2286 * list address = (mem address >> 1) >> 7;
2287 */
2288 data_bytes = ALIGN(data_bytes, 256);
2289 address = 0x1100 + ((data_bytes/2) * index);
2290
2291 if ((address + (data_bytes/2)) >= 0x1c00) {
2292 snd_printk(KERN_ERR "no memory for %d bytes at ind %d (addr 0x%x)\n",
2293 data_bytes, index, address);
2294 return -ENOMEM;
2295 }
2296
2297 s->number = index;
2298 s->inst.code = 0x400;
2299 s->inst.data = address;
2300
2301 for (i = data_bytes / 2; i > 0; address++, i--) {
2302 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2303 address, 0);
2304 }
2305
2306 return 0;
2307 }
2308
2309
2310 /*
2311 * this works for the reference board, have to find
2312 * out about others
2313 *
2314 * this needs more magic for 4 speaker, but..
2315 */
2316 static void
2317 snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2318 {
2319 int io = chip->iobase;
2320 u16 gpo, polarity;
2321
2322 if (! chip->external_amp)
2323 return;
2324
2325 polarity = enable ? 0 : 1;
2326 polarity = polarity << chip->amp_gpio;
2327 gpo = 1 << chip->amp_gpio;
2328
2329 outw(~gpo, io + GPIO_MASK);
2330
2331 outw(inw(io + GPIO_DIRECTION) | gpo,
2332 io + GPIO_DIRECTION);
2333
2334 outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2335 io + GPIO_DATA);
2336
2337 outw(0xffff, io + GPIO_MASK);
2338 }
2339
2340 static void
2341 snd_m3_hv_init(struct snd_m3 *chip)
2342 {
2343 unsigned long io = chip->iobase;
2344 u16 val = GPI_VOL_DOWN | GPI_VOL_UP;
2345
2346 if (!chip->is_omnibook)
2347 return;
2348
2349 /*
2350 * Volume buttons on some HP OmniBook laptops
2351 * require some GPIO magic to work correctly.
2352 */
2353 outw(0xffff, io + GPIO_MASK);
2354 outw(0x0000, io + GPIO_DATA);
2355
2356 outw(~val, io + GPIO_MASK);
2357 outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION);
2358 outw(val, io + GPIO_MASK);
2359
2360 outw(0xffff, io + GPIO_MASK);
2361 }
2362
2363 static int
2364 snd_m3_chip_init(struct snd_m3 *chip)
2365 {
2366 struct pci_dev *pcidev = chip->pci;
2367 unsigned long io = chip->iobase;
2368 u32 n;
2369 u16 w;
2370 u8 t; /* makes as much sense as 'n', no? */
2371
2372 pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2373 w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2374 MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2375 DISABLE_LEGACY);
2376 pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2377
2378 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2379 n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2380 n |= chip->hv_config;
2381 /* For some reason we must always use reduced debounce. */
2382 n |= REDUCED_DEBOUNCE;
2383 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2384 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2385
2386 outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2387 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2388 n &= ~INT_CLK_SELECT;
2389 if (!chip->allegro_flag) {
2390 n &= ~INT_CLK_MULT_ENABLE;
2391 n |= INT_CLK_SRC_NOT_PCI;
2392 }
2393 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2394 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2395
2396 if (chip->allegro_flag) {
2397 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2398 n |= IN_CLK_12MHZ_SELECT;
2399 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2400 }
2401
2402 t = inb(chip->iobase + ASSP_CONTROL_A);
2403 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2404 t |= ASSP_CLK_49MHZ_SELECT;
2405 t |= ASSP_0_WS_ENABLE;
2406 outb(t, chip->iobase + ASSP_CONTROL_A);
2407
2408 snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2409 outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2410
2411 outb(0x00, io + HARDWARE_VOL_CTRL);
2412 outb(0x88, io + SHADOW_MIX_REG_VOICE);
2413 outb(0x88, io + HW_VOL_COUNTER_VOICE);
2414 outb(0x88, io + SHADOW_MIX_REG_MASTER);
2415 outb(0x88, io + HW_VOL_COUNTER_MASTER);
2416
2417 return 0;
2418 }
2419
2420 static void
2421 snd_m3_enable_ints(struct snd_m3 *chip)
2422 {
2423 unsigned long io = chip->iobase;
2424 unsigned short val;
2425
2426 /* TODO: MPU401 not supported yet */
2427 val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2428 if (chip->hv_config & HV_CTRL_ENABLE)
2429 val |= HV_INT_ENABLE;
2430 outb(val, chip->iobase + HOST_INT_STATUS);
2431 outw(val, io + HOST_INT_CTRL);
2432 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2433 io + ASSP_CONTROL_C);
2434 }
2435
2436
2437 /*
2438 */
2439
2440 static int snd_m3_free(struct snd_m3 *chip)
2441 {
2442 struct m3_dma *s;
2443 int i;
2444
2445 #ifdef CONFIG_SND_MAESTRO3_INPUT
2446 if (chip->input_dev)
2447 input_unregister_device(chip->input_dev);
2448 #endif
2449
2450 if (chip->substreams) {
2451 spin_lock_irq(&chip->reg_lock);
2452 for (i = 0; i < chip->num_substreams; i++) {
2453 s = &chip->substreams[i];
2454 /* check surviving pcms; this should not happen though.. */
2455 if (s->substream && s->running)
2456 snd_m3_pcm_stop(chip, s, s->substream);
2457 }
2458 spin_unlock_irq(&chip->reg_lock);
2459 kfree(chip->substreams);
2460 }
2461 if (chip->iobase) {
2462 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2463 }
2464
2465 #ifdef CONFIG_PM
2466 vfree(chip->suspend_mem);
2467 #endif
2468
2469 if (chip->irq >= 0)
2470 free_irq(chip->irq, chip);
2471
2472 if (chip->iobase)
2473 pci_release_regions(chip->pci);
2474
2475 release_firmware(chip->assp_kernel_image);
2476 release_firmware(chip->assp_minisrc_image);
2477
2478 pci_disable_device(chip->pci);
2479 kfree(chip);
2480 return 0;
2481 }
2482
2483
2484 /*
2485 * APM support
2486 */
2487 #ifdef CONFIG_PM
2488 static int m3_suspend(struct pci_dev *pci, pm_message_t state)
2489 {
2490 struct snd_card *card = pci_get_drvdata(pci);
2491 struct snd_m3 *chip = card->private_data;
2492 int i, dsp_index;
2493
2494 if (chip->suspend_mem == NULL)
2495 return 0;
2496
2497 chip->in_suspend = 1;
2498 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2499 snd_pcm_suspend_all(chip->pcm);
2500 snd_ac97_suspend(chip->ac97);
2501
2502 msleep(10); /* give the assp a chance to idle.. */
2503
2504 snd_m3_assp_halt(chip);
2505
2506 /* save dsp image */
2507 dsp_index = 0;
2508 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2509 chip->suspend_mem[dsp_index++] =
2510 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2511 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2512 chip->suspend_mem[dsp_index++] =
2513 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2514
2515 pci_disable_device(pci);
2516 pci_save_state(pci);
2517 pci_set_power_state(pci, pci_choose_state(pci, state));
2518 return 0;
2519 }
2520
2521 static int m3_resume(struct pci_dev *pci)
2522 {
2523 struct snd_card *card = pci_get_drvdata(pci);
2524 struct snd_m3 *chip = card->private_data;
2525 int i, dsp_index;
2526
2527 if (chip->suspend_mem == NULL)
2528 return 0;
2529
2530 pci_set_power_state(pci, PCI_D0);
2531 pci_restore_state(pci);
2532 if (pci_enable_device(pci) < 0) {
2533 printk(KERN_ERR "maestor3: pci_enable_device failed, "
2534 "disabling device\n");
2535 snd_card_disconnect(card);
2536 return -EIO;
2537 }
2538 pci_set_master(pci);
2539
2540 /* first lets just bring everything back. .*/
2541 snd_m3_outw(chip, 0, 0x54);
2542 snd_m3_outw(chip, 0, 0x56);
2543
2544 snd_m3_chip_init(chip);
2545 snd_m3_assp_halt(chip);
2546 snd_m3_ac97_reset(chip);
2547
2548 /* restore dsp image */
2549 dsp_index = 0;
2550 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2551 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2552 chip->suspend_mem[dsp_index++]);
2553 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2554 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2555 chip->suspend_mem[dsp_index++]);
2556
2557 /* tell the dma engine to restart itself */
2558 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2559 KDATA_DMA_ACTIVE, 0);
2560
2561 /* restore ac97 registers */
2562 snd_ac97_resume(chip->ac97);
2563
2564 snd_m3_assp_continue(chip);
2565 snd_m3_enable_ints(chip);
2566 snd_m3_amp_enable(chip, 1);
2567
2568 snd_m3_hv_init(chip);
2569
2570 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2571 chip->in_suspend = 0;
2572 return 0;
2573 }
2574 #endif /* CONFIG_PM */
2575
2576 #ifdef CONFIG_SND_MAESTRO3_INPUT
2577 static int __devinit snd_m3_input_register(struct snd_m3 *chip)
2578 {
2579 struct input_dev *input_dev;
2580 int err;
2581
2582 input_dev = input_allocate_device();
2583 if (!input_dev)
2584 return -ENOMEM;
2585
2586 snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0",
2587 pci_name(chip->pci));
2588
2589 input_dev->name = chip->card->driver;
2590 input_dev->phys = chip->phys;
2591 input_dev->id.bustype = BUS_PCI;
2592 input_dev->id.vendor = chip->pci->vendor;
2593 input_dev->id.product = chip->pci->device;
2594 input_dev->dev.parent = &chip->pci->dev;
2595
2596 __set_bit(EV_KEY, input_dev->evbit);
2597 __set_bit(KEY_MUTE, input_dev->keybit);
2598 __set_bit(KEY_VOLUMEDOWN, input_dev->keybit);
2599 __set_bit(KEY_VOLUMEUP, input_dev->keybit);
2600
2601 err = input_register_device(input_dev);
2602 if (err) {
2603 input_free_device(input_dev);
2604 return err;
2605 }
2606
2607 chip->input_dev = input_dev;
2608 return 0;
2609 }
2610 #endif /* CONFIG_INPUT */
2611
2612 /*
2613 */
2614
2615 static int snd_m3_dev_free(struct snd_device *device)
2616 {
2617 struct snd_m3 *chip = device->device_data;
2618 return snd_m3_free(chip);
2619 }
2620
2621 static int __devinit
2622 snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2623 int enable_amp,
2624 int amp_gpio,
2625 struct snd_m3 **chip_ret)
2626 {
2627 struct snd_m3 *chip;
2628 int i, err;
2629 const struct snd_pci_quirk *quirk;
2630 static struct snd_device_ops ops = {
2631 .dev_free = snd_m3_dev_free,
2632 };
2633
2634 *chip_ret = NULL;
2635
2636 if (pci_enable_device(pci))
2637 return -EIO;
2638
2639 /* check, if we can restrict PCI DMA transfers to 28 bits */
2640 if (pci_set_dma_mask(pci, DMA_BIT_MASK(28)) < 0 ||
2641 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(28)) < 0) {
2642 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2643 pci_disable_device(pci);
2644 return -ENXIO;
2645 }
2646
2647 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2648 if (chip == NULL) {
2649 pci_disable_device(pci);
2650 return -ENOMEM;
2651 }
2652
2653 spin_lock_init(&chip->reg_lock);
2654 #ifndef CONFIG_SND_MAESTRO3_INPUT
2655 spin_lock_init(&chip->ac97_lock);
2656 #endif
2657
2658 switch (pci->device) {
2659 case PCI_DEVICE_ID_ESS_ALLEGRO:
2660 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2661 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2662 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2663 chip->allegro_flag = 1;
2664 break;
2665 }
2666
2667 chip->card = card;
2668 chip->pci = pci;
2669 chip->irq = -1;
2670
2671 chip->external_amp = enable_amp;
2672 if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2673 chip->amp_gpio = amp_gpio;
2674 else {
2675 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2676 if (quirk) {
2677 snd_printdd(KERN_INFO "maestro3: set amp-gpio "
2678 "for '%s'\n", quirk->name);
2679 chip->amp_gpio = quirk->value;
2680 } else if (chip->allegro_flag)
2681 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2682 else /* presumably this is for all 'maestro3's.. */
2683 chip->amp_gpio = GPO_EXT_AMP_M3;
2684 }
2685
2686 quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2687 if (quirk) {
2688 snd_printdd(KERN_INFO "maestro3: enabled irda workaround "
2689 "for '%s'\n", quirk->name);
2690 chip->irda_workaround = 1;
2691 }
2692 quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2693 if (quirk)
2694 chip->hv_config = quirk->value;
2695 if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2696 chip->is_omnibook = 1;
2697
2698 chip->num_substreams = NR_DSPS;
2699 chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2700 GFP_KERNEL);
2701 if (chip->substreams == NULL) {
2702 kfree(chip);
2703 pci_disable_device(pci);
2704 return -ENOMEM;
2705 }
2706
2707 err = request_firmware(&chip->assp_kernel_image,
2708 "ess/maestro3_assp_kernel.fw", &pci->dev);
2709 if (err < 0) {
2710 snd_m3_free(chip);
2711 return err;
2712 }
2713
2714 err = request_firmware(&chip->assp_minisrc_image,
2715 "ess/maestro3_assp_minisrc.fw", &pci->dev);
2716 if (err < 0) {
2717 snd_m3_free(chip);
2718 return err;
2719 }
2720
2721 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2722 snd_m3_free(chip);
2723 return err;
2724 }
2725 chip->iobase = pci_resource_start(pci, 0);
2726
2727 /* just to be sure */
2728 pci_set_master(pci);
2729
2730 snd_m3_chip_init(chip);
2731 snd_m3_assp_halt(chip);
2732
2733 snd_m3_ac97_reset(chip);
2734
2735 snd_m3_amp_enable(chip, 1);
2736
2737 snd_m3_hv_init(chip);
2738
2739 #ifndef CONFIG_SND_MAESTRO3_INPUT
2740 tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
2741 #endif
2742
2743 if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
2744 card->driver, chip)) {
2745 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2746 snd_m3_free(chip);
2747 return -ENOMEM;
2748 }
2749 chip->irq = pci->irq;
2750
2751 #ifdef CONFIG_PM
2752 chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2753 if (chip->suspend_mem == NULL)
2754 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2755 #endif
2756
2757 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2758 snd_m3_free(chip);
2759 return err;
2760 }
2761
2762 if ((err = snd_m3_mixer(chip)) < 0)
2763 return err;
2764
2765 for (i = 0; i < chip->num_substreams; i++) {
2766 struct m3_dma *s = &chip->substreams[i];
2767 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2768 return err;
2769 }
2770
2771 if ((err = snd_m3_pcm(chip, 0)) < 0)
2772 return err;
2773
2774 #ifdef CONFIG_SND_MAESTRO3_INPUT
2775 if (chip->hv_config & HV_CTRL_ENABLE) {
2776 err = snd_m3_input_register(chip);
2777 if (err)
2778 snd_printk(KERN_WARNING "Input device registration "
2779 "failed with error %i", err);
2780 }
2781 #endif
2782
2783 snd_m3_enable_ints(chip);
2784 snd_m3_assp_continue(chip);
2785
2786 snd_card_set_dev(card, &pci->dev);
2787
2788 *chip_ret = chip;
2789
2790 return 0;
2791 }
2792
2793 /*
2794 */
2795 static int __devinit
2796 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2797 {
2798 static int dev;
2799 struct snd_card *card;
2800 struct snd_m3 *chip;
2801 int err;
2802
2803 /* don't pick up modems */
2804 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2805 return -ENODEV;
2806
2807 if (dev >= SNDRV_CARDS)
2808 return -ENODEV;
2809 if (!enable[dev]) {
2810 dev++;
2811 return -ENOENT;
2812 }
2813
2814 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2815 if (err < 0)
2816 return err;
2817
2818 switch (pci->device) {
2819 case PCI_DEVICE_ID_ESS_ALLEGRO:
2820 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2821 strcpy(card->driver, "Allegro");
2822 break;
2823 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2824 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2825 strcpy(card->driver, "Canyon3D-2");
2826 break;
2827 default:
2828 strcpy(card->driver, "Maestro3");
2829 break;
2830 }
2831
2832 if ((err = snd_m3_create(card, pci,
2833 external_amp[dev],
2834 amp_gpio[dev],
2835 &chip)) < 0) {
2836 snd_card_free(card);
2837 return err;
2838 }
2839 card->private_data = chip;
2840
2841 sprintf(card->shortname, "ESS %s PCI", card->driver);
2842 sprintf(card->longname, "%s at 0x%lx, irq %d",
2843 card->shortname, chip->iobase, chip->irq);
2844
2845 if ((err = snd_card_register(card)) < 0) {
2846 snd_card_free(card);
2847 return err;
2848 }
2849
2850
2851 pci_set_drvdata(pci, card);
2852 dev++;
2853 return 0;
2854 }
2855
2856 static void __devexit snd_m3_remove(struct pci_dev *pci)
2857 {
2858 snd_card_free(pci_get_drvdata(pci));
2859 pci_set_drvdata(pci, NULL);
2860 }
2861
2862 static struct pci_driver driver = {
2863 .name = "Maestro3",
2864 .id_table = snd_m3_ids,
2865 .probe = snd_m3_probe,
2866 .remove = __devexit_p(snd_m3_remove),
2867 #ifdef CONFIG_PM
2868 .suspend = m3_suspend,
2869 .resume = m3_resume,
2870 #endif
2871 };
2872
2873 static int __init alsa_card_m3_init(void)
2874 {
2875 return pci_register_driver(&driver);
2876 }
2877
2878 static void __exit alsa_card_m3_exit(void)
2879 {
2880 pci_unregister_driver(&driver);
2881 }
2882
2883 module_init(alsa_card_m3_init)
2884 module_exit(alsa_card_m3_exit)
Tomato firmware and modifications.