2 * Universal Interface for Intel High Definition Audio Codec
4 * HD audio interface patch for NVIDIA HDMI codecs
6 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
7 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
10 * This driver is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This driver is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <sound/core.h>
29 #include "hda_codec.h"
30 #include "hda_local.h"
32 #define MAX_HDMI_CVTS 1
33 #define MAX_HDMI_PINS 1
35 #include "patch_hdmi.c"
37 static char *nvhdmi_pcm_names
[MAX_HDMI_CVTS
] = {
41 /* define below to restrict the supported rates and formats */
42 /* #define LIMITED_RATE_FMT_SUPPORT */
45 HDA_CODEC_NVIDIA_MCP7X
,
46 HDA_CODEC_NVIDIA_MCP89
,
47 HDA_CODEC_NVIDIA_GT21X
,
51 #define Nv_VERB_SET_Channel_Allocation 0xF79
52 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
53 #define Nv_VERB_SET_Audio_Protection_On 0xF98
54 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
56 #define nvhdmi_master_con_nid_7x 0x04
57 #define nvhdmi_master_pin_nid_7x 0x05
59 #define nvhdmi_master_con_nid_89 0x04
60 #define nvhdmi_master_pin_nid_89 0x05
62 static hda_nid_t nvhdmi_con_nids_7x
[4] = {
63 /*front, rear, clfe, rear_surr */
67 static struct hda_verb nvhdmi_basic_init_7x
[] = {
68 /* set audio protect on */
69 { 0x1, Nv_VERB_SET_Audio_Protection_On
, 0x1},
70 /* enable digital output on pin widget */
71 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
72 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
73 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
74 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
75 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
79 #ifdef LIMITED_RATE_FMT_SUPPORT
80 /* support only the safe format and rate */
81 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
82 #define SUPPORTED_MAXBPS 16
83 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
85 /* support all rates and formats */
86 #define SUPPORTED_RATES \
87 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
88 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
89 SNDRV_PCM_RATE_192000)
90 #define SUPPORTED_MAXBPS 24
91 #define SUPPORTED_FORMATS \
92 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
98 static int nvhdmi_build_controls(struct hda_codec
*codec
)
100 struct hdmi_spec
*spec
= codec
->spec
;
104 if ((spec
->codec_type
== HDA_CODEC_NVIDIA_MCP89
)
105 || (spec
->codec_type
== HDA_CODEC_NVIDIA_GT21X
)) {
106 for (i
= 0; i
< codec
->num_pcms
; i
++) {
107 err
= snd_hda_create_spdif_out_ctls(codec
,
113 err
= snd_hda_create_spdif_out_ctls(codec
,
114 spec
->multiout
.dig_out_nid
);
122 static int nvhdmi_init(struct hda_codec
*codec
)
124 struct hdmi_spec
*spec
= codec
->spec
;
126 if ((spec
->codec_type
== HDA_CODEC_NVIDIA_MCP89
)
127 || (spec
->codec_type
== HDA_CODEC_NVIDIA_GT21X
)) {
128 for (i
= 0; spec
->pin
[i
]; i
++) {
129 hdmi_enable_output(codec
, spec
->pin
[i
]);
130 snd_hda_codec_write(codec
, spec
->pin
[i
], 0,
131 AC_VERB_SET_UNSOLICITED_ENABLE
,
132 AC_USRSP_EN
| spec
->pin
[i
]);
135 snd_hda_sequence_write(codec
, nvhdmi_basic_init_7x
);
140 static void nvhdmi_free(struct hda_codec
*codec
)
142 struct hdmi_spec
*spec
= codec
->spec
;
145 if ((spec
->codec_type
== HDA_CODEC_NVIDIA_MCP89
)
146 || (spec
->codec_type
== HDA_CODEC_NVIDIA_GT21X
)) {
147 for (i
= 0; i
< spec
->num_pins
; i
++)
148 snd_hda_eld_proc_free(codec
, &spec
->sink_eld
[i
]);
157 static int nvhdmi_dig_playback_pcm_open(struct hda_pcm_stream
*hinfo
,
158 struct hda_codec
*codec
,
159 struct snd_pcm_substream
*substream
)
161 struct hdmi_spec
*spec
= codec
->spec
;
162 return snd_hda_multi_out_dig_open(codec
, &spec
->multiout
);
165 static int nvhdmi_dig_playback_pcm_close_8ch_7x(struct hda_pcm_stream
*hinfo
,
166 struct hda_codec
*codec
,
167 struct snd_pcm_substream
*substream
)
169 struct hdmi_spec
*spec
= codec
->spec
;
172 snd_hda_codec_write(codec
, nvhdmi_master_con_nid_7x
,
173 0, AC_VERB_SET_CHANNEL_STREAMID
, 0);
174 for (i
= 0; i
< 4; i
++) {
175 /* set the stream id */
176 snd_hda_codec_write(codec
, nvhdmi_con_nids_7x
[i
], 0,
177 AC_VERB_SET_CHANNEL_STREAMID
, 0);
178 /* set the stream format */
179 snd_hda_codec_write(codec
, nvhdmi_con_nids_7x
[i
], 0,
180 AC_VERB_SET_STREAM_FORMAT
, 0);
183 return snd_hda_multi_out_dig_close(codec
, &spec
->multiout
);
186 static int nvhdmi_dig_playback_pcm_close_2ch(struct hda_pcm_stream
*hinfo
,
187 struct hda_codec
*codec
,
188 struct snd_pcm_substream
*substream
)
190 struct hdmi_spec
*spec
= codec
->spec
;
191 return snd_hda_multi_out_dig_close(codec
, &spec
->multiout
);
194 static int nvhdmi_dig_playback_pcm_prepare_8ch_89(struct hda_pcm_stream
*hinfo
,
195 struct hda_codec
*codec
,
196 unsigned int stream_tag
,
198 struct snd_pcm_substream
*substream
)
200 hdmi_set_channel_count(codec
, hinfo
->nid
,
201 substream
->runtime
->channels
);
203 hdmi_setup_audio_infoframe(codec
, hinfo
->nid
, substream
);
205 return hdmi_setup_stream(codec
, hinfo
->nid
, stream_tag
, format
);
208 static int nvhdmi_dig_playback_pcm_prepare_8ch(struct hda_pcm_stream
*hinfo
,
209 struct hda_codec
*codec
,
210 unsigned int stream_tag
,
212 struct snd_pcm_substream
*substream
)
215 unsigned int dataDCC1
, dataDCC2
, chan
, chanmask
, channel_id
;
218 mutex_lock(&codec
->spdif_mutex
);
220 chs
= substream
->runtime
->channels
;
221 chan
= chs
? (chs
- 1) : 1;
239 dataDCC1
= AC_DIG1_ENABLE
| AC_DIG1_COPYRIGHT
;
242 /* set the Audio InforFrame Channel Allocation */
243 snd_hda_codec_write(codec
, 0x1, 0,
244 Nv_VERB_SET_Channel_Allocation
, chanmask
);
246 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
247 if (codec
->spdif_status_reset
&& (codec
->spdif_ctls
& AC_DIG1_ENABLE
))
248 snd_hda_codec_write(codec
,
249 nvhdmi_master_con_nid_7x
,
251 AC_VERB_SET_DIGI_CONVERT_1
,
252 codec
->spdif_ctls
& ~AC_DIG1_ENABLE
& 0xff);
254 /* set the stream id */
255 snd_hda_codec_write(codec
, nvhdmi_master_con_nid_7x
, 0,
256 AC_VERB_SET_CHANNEL_STREAMID
, (stream_tag
<< 4) | 0x0);
258 /* set the stream format */
259 snd_hda_codec_write(codec
, nvhdmi_master_con_nid_7x
, 0,
260 AC_VERB_SET_STREAM_FORMAT
, format
);
262 /* turn on again (if needed) */
263 /* enable and set the channel status audio/data flag */
264 if (codec
->spdif_status_reset
&& (codec
->spdif_ctls
& AC_DIG1_ENABLE
)) {
265 snd_hda_codec_write(codec
,
266 nvhdmi_master_con_nid_7x
,
268 AC_VERB_SET_DIGI_CONVERT_1
,
269 codec
->spdif_ctls
& 0xff);
270 snd_hda_codec_write(codec
,
271 nvhdmi_master_con_nid_7x
,
273 AC_VERB_SET_DIGI_CONVERT_2
, dataDCC2
);
276 for (i
= 0; i
< 4; i
++) {
282 /* turn off SPDIF once;
283 *otherwise the IEC958 bits won't be updated
285 if (codec
->spdif_status_reset
&&
286 (codec
->spdif_ctls
& AC_DIG1_ENABLE
))
287 snd_hda_codec_write(codec
,
288 nvhdmi_con_nids_7x
[i
],
290 AC_VERB_SET_DIGI_CONVERT_1
,
291 codec
->spdif_ctls
& ~AC_DIG1_ENABLE
& 0xff);
292 /* set the stream id */
293 snd_hda_codec_write(codec
,
294 nvhdmi_con_nids_7x
[i
],
296 AC_VERB_SET_CHANNEL_STREAMID
,
297 (stream_tag
<< 4) | channel_id
);
298 /* set the stream format */
299 snd_hda_codec_write(codec
,
300 nvhdmi_con_nids_7x
[i
],
302 AC_VERB_SET_STREAM_FORMAT
,
304 /* turn on again (if needed) */
305 /* enable and set the channel status audio/data flag */
306 if (codec
->spdif_status_reset
&&
307 (codec
->spdif_ctls
& AC_DIG1_ENABLE
)) {
308 snd_hda_codec_write(codec
,
309 nvhdmi_con_nids_7x
[i
],
311 AC_VERB_SET_DIGI_CONVERT_1
,
312 codec
->spdif_ctls
& 0xff);
313 snd_hda_codec_write(codec
,
314 nvhdmi_con_nids_7x
[i
],
316 AC_VERB_SET_DIGI_CONVERT_2
, dataDCC2
);
320 /* set the Audio Info Frame Checksum */
321 snd_hda_codec_write(codec
, 0x1, 0,
322 Nv_VERB_SET_Info_Frame_Checksum
,
323 (0x71 - chan
- chanmask
));
325 mutex_unlock(&codec
->spdif_mutex
);
329 static int nvhdmi_dig_playback_pcm_prepare_2ch(struct hda_pcm_stream
*hinfo
,
330 struct hda_codec
*codec
,
331 unsigned int stream_tag
,
333 struct snd_pcm_substream
*substream
)
335 struct hdmi_spec
*spec
= codec
->spec
;
336 return snd_hda_multi_out_dig_prepare(codec
, &spec
->multiout
, stream_tag
,
340 static struct hda_pcm_stream nvhdmi_pcm_digital_playback_8ch_89
= {
344 .open
= hdmi_pcm_open
,
345 .prepare
= nvhdmi_dig_playback_pcm_prepare_8ch_89
,
349 static struct hda_pcm_stream nvhdmi_pcm_digital_playback_8ch_7x
= {
353 .nid
= nvhdmi_master_con_nid_7x
,
354 .rates
= SUPPORTED_RATES
,
355 .maxbps
= SUPPORTED_MAXBPS
,
356 .formats
= SUPPORTED_FORMATS
,
358 .open
= nvhdmi_dig_playback_pcm_open
,
359 .close
= nvhdmi_dig_playback_pcm_close_8ch_7x
,
360 .prepare
= nvhdmi_dig_playback_pcm_prepare_8ch
364 static struct hda_pcm_stream nvhdmi_pcm_digital_playback_2ch
= {
368 .nid
= nvhdmi_master_con_nid_7x
,
369 .rates
= SUPPORTED_RATES
,
370 .maxbps
= SUPPORTED_MAXBPS
,
371 .formats
= SUPPORTED_FORMATS
,
373 .open
= nvhdmi_dig_playback_pcm_open
,
374 .close
= nvhdmi_dig_playback_pcm_close_2ch
,
375 .prepare
= nvhdmi_dig_playback_pcm_prepare_2ch
379 static int nvhdmi_build_pcms_8ch_89(struct hda_codec
*codec
)
381 struct hdmi_spec
*spec
= codec
->spec
;
382 struct hda_pcm
*info
= spec
->pcm_rec
;
385 codec
->num_pcms
= spec
->num_cvts
;
386 codec
->pcm_info
= info
;
388 for (i
= 0; i
< codec
->num_pcms
; i
++, info
++) {
391 chans
= get_wcaps(codec
, spec
->cvt
[i
]);
392 chans
= get_wcaps_channels(chans
);
394 info
->name
= nvhdmi_pcm_names
[i
];
395 info
->pcm_type
= HDA_PCM_TYPE_HDMI
;
396 info
->stream
[SNDRV_PCM_STREAM_PLAYBACK
]
397 = nvhdmi_pcm_digital_playback_8ch_89
;
398 info
->stream
[SNDRV_PCM_STREAM_PLAYBACK
].nid
= spec
->cvt
[i
];
399 info
->stream
[SNDRV_PCM_STREAM_PLAYBACK
].channels_max
= chans
;
405 static int nvhdmi_build_pcms_8ch_7x(struct hda_codec
*codec
)
407 struct hdmi_spec
*spec
= codec
->spec
;
408 struct hda_pcm
*info
= spec
->pcm_rec
;
411 codec
->pcm_info
= info
;
413 info
->name
= "NVIDIA HDMI";
414 info
->pcm_type
= HDA_PCM_TYPE_HDMI
;
415 info
->stream
[SNDRV_PCM_STREAM_PLAYBACK
]
416 = nvhdmi_pcm_digital_playback_8ch_7x
;
421 static int nvhdmi_build_pcms_2ch(struct hda_codec
*codec
)
423 struct hdmi_spec
*spec
= codec
->spec
;
424 struct hda_pcm
*info
= spec
->pcm_rec
;
427 codec
->pcm_info
= info
;
429 info
->name
= "NVIDIA HDMI";
430 info
->pcm_type
= HDA_PCM_TYPE_HDMI
;
431 info
->stream
[SNDRV_PCM_STREAM_PLAYBACK
]
432 = nvhdmi_pcm_digital_playback_2ch
;
437 static struct hda_codec_ops nvhdmi_patch_ops_8ch_89
= {
438 .build_controls
= nvhdmi_build_controls
,
439 .build_pcms
= nvhdmi_build_pcms_8ch_89
,
442 .unsol_event
= hdmi_unsol_event
,
445 static struct hda_codec_ops nvhdmi_patch_ops_8ch_7x
= {
446 .build_controls
= nvhdmi_build_controls
,
447 .build_pcms
= nvhdmi_build_pcms_8ch_7x
,
452 static struct hda_codec_ops nvhdmi_patch_ops_2ch
= {
453 .build_controls
= nvhdmi_build_controls
,
454 .build_pcms
= nvhdmi_build_pcms_2ch
,
459 static int patch_nvhdmi_8ch_89(struct hda_codec
*codec
)
461 struct hdmi_spec
*spec
;
464 spec
= kzalloc(sizeof(*spec
), GFP_KERNEL
);
469 spec
->codec_type
= HDA_CODEC_NVIDIA_MCP89
;
470 spec
->old_pin_detect
= 1;
472 if (hdmi_parse_codec(codec
) < 0) {
477 codec
->patch_ops
= nvhdmi_patch_ops_8ch_89
;
479 for (i
= 0; i
< spec
->num_pins
; i
++)
480 snd_hda_eld_proc_new(codec
, &spec
->sink_eld
[i
], i
);
482 init_channel_allocations();
487 static int patch_nvhdmi_8ch_7x(struct hda_codec
*codec
)
489 struct hdmi_spec
*spec
;
491 spec
= kzalloc(sizeof(*spec
), GFP_KERNEL
);
497 spec
->multiout
.num_dacs
= 0; /* no analog */
498 spec
->multiout
.max_channels
= 8;
499 spec
->multiout
.dig_out_nid
= nvhdmi_master_con_nid_7x
;
500 spec
->codec_type
= HDA_CODEC_NVIDIA_MCP7X
;
501 spec
->old_pin_detect
= 1;
503 codec
->patch_ops
= nvhdmi_patch_ops_8ch_7x
;
508 static int patch_nvhdmi_2ch(struct hda_codec
*codec
)
510 struct hdmi_spec
*spec
;
512 spec
= kzalloc(sizeof(*spec
), GFP_KERNEL
);
518 spec
->multiout
.num_dacs
= 0; /* no analog */
519 spec
->multiout
.max_channels
= 2;
520 spec
->multiout
.dig_out_nid
= nvhdmi_master_con_nid_7x
;
521 spec
->codec_type
= HDA_CODEC_NVIDIA_MCP7X
;
522 spec
->old_pin_detect
= 1;
524 codec
->patch_ops
= nvhdmi_patch_ops_2ch
;
532 static struct hda_codec_preset snd_hda_preset_nvhdmi
[] = {
533 { .id
= 0x10de0002, .name
= "MCP77/78 HDMI", .patch
= patch_nvhdmi_8ch_7x
},
534 { .id
= 0x10de0003, .name
= "MCP77/78 HDMI", .patch
= patch_nvhdmi_8ch_7x
},
535 { .id
= 0x10de0005, .name
= "MCP77/78 HDMI", .patch
= patch_nvhdmi_8ch_7x
},
536 { .id
= 0x10de0006, .name
= "MCP77/78 HDMI", .patch
= patch_nvhdmi_8ch_7x
},
537 { .id
= 0x10de0007, .name
= "MCP79/7A HDMI", .patch
= patch_nvhdmi_8ch_7x
},
538 { .id
= 0x10de000a, .name
= "GPU 0a HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
539 { .id
= 0x10de000b, .name
= "GPU 0b HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
540 { .id
= 0x10de000c, .name
= "MCP89 HDMI", .patch
= patch_nvhdmi_8ch_89
},
541 { .id
= 0x10de000d, .name
= "GPU 0d HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
542 { .id
= 0x10de0010, .name
= "GPU 10 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
543 { .id
= 0x10de0011, .name
= "GPU 11 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
544 { .id
= 0x10de0012, .name
= "GPU 12 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
545 { .id
= 0x10de0013, .name
= "GPU 13 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
546 { .id
= 0x10de0014, .name
= "GPU 14 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
547 { .id
= 0x10de0018, .name
= "GPU 18 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
548 { .id
= 0x10de0019, .name
= "GPU 19 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
549 { .id
= 0x10de001a, .name
= "GPU 1a HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
550 { .id
= 0x10de001b, .name
= "GPU 1b HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
551 { .id
= 0x10de001c, .name
= "GPU 1c HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
552 { .id
= 0x10de0040, .name
= "GPU 40 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
553 { .id
= 0x10de0041, .name
= "GPU 41 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
554 { .id
= 0x10de0042, .name
= "GPU 42 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
555 { .id
= 0x10de0043, .name
= "GPU 43 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
556 { .id
= 0x10de0044, .name
= "GPU 44 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
557 { .id
= 0x10de0067, .name
= "MCP67 HDMI", .patch
= patch_nvhdmi_2ch
},
558 { .id
= 0x10de8001, .name
= "MCP73 HDMI", .patch
= patch_nvhdmi_2ch
},
562 MODULE_ALIAS("snd-hda-codec-id:10de0002");
563 MODULE_ALIAS("snd-hda-codec-id:10de0003");
564 MODULE_ALIAS("snd-hda-codec-id:10de0005");
565 MODULE_ALIAS("snd-hda-codec-id:10de0006");
566 MODULE_ALIAS("snd-hda-codec-id:10de0007");
567 MODULE_ALIAS("snd-hda-codec-id:10de000a");
568 MODULE_ALIAS("snd-hda-codec-id:10de000b");
569 MODULE_ALIAS("snd-hda-codec-id:10de000c");
570 MODULE_ALIAS("snd-hda-codec-id:10de000d");
571 MODULE_ALIAS("snd-hda-codec-id:10de0010");
572 MODULE_ALIAS("snd-hda-codec-id:10de0011");
573 MODULE_ALIAS("snd-hda-codec-id:10de0012");
574 MODULE_ALIAS("snd-hda-codec-id:10de0013");
575 MODULE_ALIAS("snd-hda-codec-id:10de0014");
576 MODULE_ALIAS("snd-hda-codec-id:10de0018");
577 MODULE_ALIAS("snd-hda-codec-id:10de0019");
578 MODULE_ALIAS("snd-hda-codec-id:10de001a");
579 MODULE_ALIAS("snd-hda-codec-id:10de001b");
580 MODULE_ALIAS("snd-hda-codec-id:10de001c");
581 MODULE_ALIAS("snd-hda-codec-id:10de0040");
582 MODULE_ALIAS("snd-hda-codec-id:10de0041");
583 MODULE_ALIAS("snd-hda-codec-id:10de0042");
584 MODULE_ALIAS("snd-hda-codec-id:10de0043");
585 MODULE_ALIAS("snd-hda-codec-id:10de0044");
586 MODULE_ALIAS("snd-hda-codec-id:10de0067");
587 MODULE_ALIAS("snd-hda-codec-id:10de8001");
589 MODULE_LICENSE("GPL");
590 MODULE_DESCRIPTION("NVIDIA HDMI HD-audio codec");
592 static struct hda_codec_preset_list nvhdmi_list
= {
593 .preset
= snd_hda_preset_nvhdmi
,
594 .owner
= THIS_MODULE
,
597 static int __init
patch_nvhdmi_init(void)
599 return snd_hda_add_codec_preset(&nvhdmi_list
);
602 static void __exit
patch_nvhdmi_exit(void)
604 snd_hda_delete_codec_preset(&nvhdmi_list
);
607 module_init(patch_nvhdmi_init
)
608 module_exit(patch_nvhdmi_exit
)