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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / include / linux / pci.h
blobdb4311d498475cf939f879ca79cf7b3e011ec1e8
1 /*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/pci_regs.h> /* The pci register defines */
21
22 /*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41 #ifdef __KERNEL__
42
43 #include <linux/mod_devicetable.h>
44
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <asm/atomic.h>
53 #include <linux/device.h>
54 #include <linux/io.h>
55 #include <linux/irqreturn.h>
56
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
59
60 /* pci_slot represents a physical slot */
61 struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67 };
68
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
70 {
71 return kobject_name(&slot->kobj);
72 }
73
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78 };
79
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
85
86 /*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89 enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
97 /* device specific resources */
98 #ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101 #endif
102
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE
115 };
116
117 typedef int __bitwise pci_power_t;
118
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
126
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
129
130 static inline const char *pci_power_name(pci_power_t state)
131 {
132 return pci_power_names[1 + (int) state];
133 }
134
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_BUS_WAIT 50
138
139 /** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
142 */
143 typedef unsigned int __bitwise pci_channel_state_t;
144
145 enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
148
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
151
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
154 };
155
156 typedef unsigned int __bitwise pcie_reset_state_t;
157
158 enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
161
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
164
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
167 };
168
169 typedef unsigned short __bitwise pci_dev_flags_t;
170 enum pci_dev_flags {
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
172 * generation too.
173 */
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
177 };
178
179 enum pci_irq_reroute_variant {
180 INTEL_IRQ_REROUTE_VARIANT = 1,
181 MAX_IRQ_REROUTE_VARIANTS = 3
182 };
183
184 typedef unsigned short __bitwise pci_bus_flags_t;
185 enum pci_bus_flags {
186 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
187 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
188 };
189
190 /* Based on the PCI Hotplug Spec, but some values are made up by us */
191 enum pci_bus_speed {
192 PCI_SPEED_33MHz = 0x00,
193 PCI_SPEED_66MHz = 0x01,
194 PCI_SPEED_66MHz_PCIX = 0x02,
195 PCI_SPEED_100MHz_PCIX = 0x03,
196 PCI_SPEED_133MHz_PCIX = 0x04,
197 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
198 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
199 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
200 PCI_SPEED_66MHz_PCIX_266 = 0x09,
201 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
202 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
203 AGP_UNKNOWN = 0x0c,
204 AGP_1X = 0x0d,
205 AGP_2X = 0x0e,
206 AGP_4X = 0x0f,
207 AGP_8X = 0x10,
208 PCI_SPEED_66MHz_PCIX_533 = 0x11,
209 PCI_SPEED_100MHz_PCIX_533 = 0x12,
210 PCI_SPEED_133MHz_PCIX_533 = 0x13,
211 PCIE_SPEED_2_5GT = 0x14,
212 PCIE_SPEED_5_0GT = 0x15,
213 PCIE_SPEED_8_0GT = 0x16,
214 PCI_SPEED_UNKNOWN = 0xff,
215 };
216
217 struct pci_cap_saved_state {
218 struct hlist_node next;
219 char cap_nr;
220 u32 data[0];
221 };
222
223 struct pcie_link_state;
224 struct pci_vpd;
225 struct pci_sriov;
226 struct pci_ats;
227
228 /*
229 * The pci_dev structure is used to describe PCI devices.
230 */
231 struct pci_dev {
232 struct list_head bus_list; /* node in per-bus list */
233 struct pci_bus *bus; /* bus this device is on */
234 struct pci_bus *subordinate; /* bus this device bridges to */
235
236 void *sysdata; /* hook for sys-specific extension */
237 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
238 struct pci_slot *slot; /* Physical slot this device is in */
239
240 unsigned int devfn; /* encoded device & function index */
241 unsigned short vendor;
242 unsigned short device;
243 unsigned short subsystem_vendor;
244 unsigned short subsystem_device;
245 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
246 u8 revision; /* PCI revision, low byte of class word */
247 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
248 u8 pcie_cap; /* PCI-E capability offset */
249 u8 pcie_type; /* PCI-E device/port type */
250 u8 rom_base_reg; /* which config register controls the ROM */
251 u8 pin; /* which interrupt pin this device uses */
252
253 struct pci_driver *driver; /* which driver has allocated this device */
254 u64 dma_mask; /* Mask of the bits of bus address this
255 device implements. Normally this is
256 0xffffffff. You only need to change
257 this if your device has broken DMA
258 or supports 64-bit transfers. */
259
260 struct device_dma_parameters dma_parms;
261
262 pci_power_t current_state; /* Current operating state. In ACPI-speak,
263 this is D0-D3, D0 being fully functional,
264 and D3 being off. */
265 int pm_cap; /* PM capability offset in the
266 configuration space */
267 unsigned int pme_support:5; /* Bitmask of states from which PME#
268 can be generated */
269 unsigned int pme_interrupt:1;
270 unsigned int d1_support:1; /* Low power state D1 is supported */
271 unsigned int d2_support:1; /* Low power state D2 is supported */
272 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
273 unsigned int mmio_always_on:1; /* disallow turning off io/mem
274 decoding during bar sizing */
275 unsigned int wakeup_prepared:1;
276 unsigned int d3_delay; /* D3->D0 transition time in ms */
277
278 #ifdef CONFIG_PCIEASPM
279 struct pcie_link_state *link_state; /* ASPM link state. */
280 #endif
281
282 pci_channel_state_t error_state; /* current connectivity state */
283 struct device dev; /* Generic device interface */
284
285 int cfg_size; /* Size of configuration space */
286
287 /*
288 * Instead of touching interrupt line and base address registers
289 * directly, use the values stored here. They might be different!
290 */
291 unsigned int irq;
292 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
293 resource_size_t fw_addr[DEVICE_COUNT_RESOURCE]; /* FW-assigned addr */
294
295 /* These fields are used by common fixups */
296 unsigned int transparent:1; /* Transparent PCI bridge */
297 unsigned int multifunction:1;/* Part of multi-function device */
298 /* keep track of device state */
299 unsigned int is_added:1;
300 unsigned int is_busmaster:1; /* device is busmaster */
301 unsigned int no_msi:1; /* device may not use msi */
302 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
303 unsigned int broken_parity_status:1; /* Device generates false positive parity */
304 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
305 unsigned int msi_enabled:1;
306 unsigned int msix_enabled:1;
307 unsigned int ari_enabled:1; /* ARI forwarding */
308 unsigned int is_managed:1;
309 unsigned int is_pcie:1; /* Obsolete. Will be removed.
310 Use pci_is_pcie() instead */
311 unsigned int needs_freset:1; /* Dev requires fundamental reset */
312 unsigned int state_saved:1;
313 unsigned int is_physfn:1;
314 unsigned int is_virtfn:1;
315 unsigned int reset_fn:1;
316 unsigned int is_hotplug_bridge:1;
317 unsigned int __aer_firmware_first_valid:1;
318 unsigned int __aer_firmware_first:1;
319 pci_dev_flags_t dev_flags;
320 atomic_t enable_cnt; /* pci_enable_device has been called */
321
322 u32 saved_config_space[16]; /* config space saved at suspend time */
323 struct hlist_head saved_cap_space;
324 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
325 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
326 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
327 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
328 #ifdef CONFIG_PCI_MSI
329 struct list_head msi_list;
330 #endif
331 struct pci_vpd *vpd;
332 #ifdef CONFIG_PCI_IOV
333 union {
334 struct pci_sriov *sriov; /* SR-IOV capability related */
335 struct pci_dev *physfn; /* the PF this VF is associated with */
336 };
337 struct pci_ats *ats; /* Address Translation Service */
338 #endif
339 };
340
341 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
342 {
343 #ifdef CONFIG_PCI_IOV
344 if (dev->is_virtfn)
345 dev = dev->physfn;
346 #endif
347
348 return dev;
349 }
350
351 extern struct pci_dev *alloc_pci_dev(void);
352
353 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
354 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
355 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
356
357 static inline int pci_channel_offline(struct pci_dev *pdev)
358 {
359 return (pdev->error_state != pci_channel_io_normal);
360 }
361
362 static inline struct pci_cap_saved_state *pci_find_saved_cap(
363 struct pci_dev *pci_dev, char cap)
364 {
365 struct pci_cap_saved_state *tmp;
366 struct hlist_node *pos;
367
368 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
369 if (tmp->cap_nr == cap)
370 return tmp;
371 }
372 return NULL;
373 }
374
375 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
376 struct pci_cap_saved_state *new_cap)
377 {
378 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
379 }
380
381 /*
382 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
383 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
384 * buses below host bridges or subtractive decode bridges) go in the list.
385 * Use pci_bus_for_each_resource() to iterate through all the resources.
386 */
387
388 /*
389 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
390 * and there's no way to program the bridge with the details of the window.
391 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
392 * decode bit set, because they are explicit and can be programmed with _SRS.
393 */
394 #define PCI_SUBTRACTIVE_DECODE 0x1
395
396 struct pci_bus_resource {
397 struct list_head list;
398 struct resource *res;
399 unsigned int flags;
400 };
401
402 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
403
404 struct pci_bus {
405 struct list_head node; /* node in list of buses */
406 struct pci_bus *parent; /* parent bus this bridge is on */
407 struct list_head children; /* list of child buses */
408 struct list_head devices; /* list of devices on this bus */
409 struct pci_dev *self; /* bridge device as seen by parent */
410 struct list_head slots; /* list of slots on this bus */
411 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
412 struct list_head resources; /* address space routed to this bus */
413
414 struct pci_ops *ops; /* configuration access functions */
415 void *sysdata; /* hook for sys-specific extension */
416 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
417
418 unsigned char number; /* bus number */
419 unsigned char primary; /* number of primary bridge */
420 unsigned char secondary; /* number of secondary bridge */
421 unsigned char subordinate; /* max number of subordinate buses */
422 unsigned char max_bus_speed; /* enum pci_bus_speed */
423 unsigned char cur_bus_speed; /* enum pci_bus_speed */
424
425 char name[48];
426
427 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
428 pci_bus_flags_t bus_flags; /* Inherited by child busses */
429 struct device *bridge;
430 struct device dev;
431 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
432 struct bin_attribute *legacy_mem; /* legacy mem */
433 unsigned int is_added:1;
434 };
435
436 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
437 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
438
439 /*
440 * Returns true if the pci bus is root (behind host-pci bridge),
441 * false otherwise
442 */
443 static inline bool pci_is_root_bus(struct pci_bus *pbus)
444 {
445 return !(pbus->parent);
446 }
447
448 #ifdef CONFIG_PCI_MSI
449 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
450 {
451 return pci_dev->msi_enabled || pci_dev->msix_enabled;
452 }
453 #else
454 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
455 #endif
456
457 /*
458 * Error values that may be returned by PCI functions.
459 */
460 #define PCIBIOS_SUCCESSFUL 0x00
461 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
462 #define PCIBIOS_BAD_VENDOR_ID 0x83
463 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
464 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
465 #define PCIBIOS_SET_FAILED 0x88
466 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
467
468 /* Low-level architecture-dependent routines */
469
470 struct pci_ops {
471 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
472 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
473 };
474
475 /*
476 * ACPI needs to be able to access PCI config space before we've done a
477 * PCI bus scan and created pci_bus structures.
478 */
479 extern int raw_pci_read(unsigned int domain, unsigned int bus,
480 unsigned int devfn, int reg, int len, u32 *val);
481 extern int raw_pci_write(unsigned int domain, unsigned int bus,
482 unsigned int devfn, int reg, int len, u32 val);
483
484 struct pci_bus_region {
485 resource_size_t start;
486 resource_size_t end;
487 };
488
489 struct pci_dynids {
490 spinlock_t lock; /* protects list, index */
491 struct list_head list; /* for IDs added at runtime */
492 };
493
494 /* ---------------------------------------------------------------- */
495 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
496 * a set of callbacks in struct pci_error_handlers, then that device driver
497 * will be notified of PCI bus errors, and will be driven to recovery
498 * when an error occurs.
499 */
500
501 typedef unsigned int __bitwise pci_ers_result_t;
502
503 enum pci_ers_result {
504 /* no result/none/not supported in device driver */
505 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
506
507 /* Device driver can recover without slot reset */
508 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
509
510 /* Device driver wants slot to be reset. */
511 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
512
513 /* Device has completely failed, is unrecoverable */
514 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
515
516 /* Device driver is fully recovered and operational */
517 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
518 };
519
520 /* PCI bus error event callbacks */
521 struct pci_error_handlers {
522 /* PCI bus error detected on this device */
523 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
524 enum pci_channel_state error);
525
526 /* MMIO has been re-enabled, but not DMA */
527 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
528
529 /* PCI Express link has been reset */
530 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
531
532 /* PCI slot has been reset */
533 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
534
535 /* Device driver may resume normal operations */
536 void (*resume)(struct pci_dev *dev);
537 };
538
539 /* ---------------------------------------------------------------- */
540
541 struct module;
542 struct pci_driver {
543 struct list_head node;
544 char *name;
545 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
546 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
547 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
548 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
549 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
550 int (*resume_early) (struct pci_dev *dev);
551 int (*resume) (struct pci_dev *dev); /* Device woken up */
552 void (*shutdown) (struct pci_dev *dev);
553 struct pci_error_handlers *err_handler;
554 struct device_driver driver;
555 struct pci_dynids dynids;
556 };
557
558 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
559
560 /**
561 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
562 * @_table: device table name
563 *
564 * This macro is used to create a struct pci_device_id array (a device table)
565 * in a generic manner.
566 */
567 #define DEFINE_PCI_DEVICE_TABLE(_table) \
568 const struct pci_device_id _table[] __devinitconst
569
570 /**
571 * PCI_DEVICE - macro used to describe a specific pci device
572 * @vend: the 16 bit PCI Vendor ID
573 * @dev: the 16 bit PCI Device ID
574 *
575 * This macro is used to create a struct pci_device_id that matches a
576 * specific device. The subvendor and subdevice fields will be set to
577 * PCI_ANY_ID.
578 */
579 #define PCI_DEVICE(vend,dev) \
580 .vendor = (vend), .device = (dev), \
581 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
582
583 /**
584 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
585 * @dev_class: the class, subclass, prog-if triple for this device
586 * @dev_class_mask: the class mask for this device
587 *
588 * This macro is used to create a struct pci_device_id that matches a
589 * specific PCI class. The vendor, device, subvendor, and subdevice
590 * fields will be set to PCI_ANY_ID.
591 */
592 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
593 .class = (dev_class), .class_mask = (dev_class_mask), \
594 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
595 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
596
597 /**
598 * PCI_VDEVICE - macro used to describe a specific pci device in short form
599 * @vendor: the vendor name
600 * @device: the 16 bit PCI Device ID
601 *
602 * This macro is used to create a struct pci_device_id that matches a
603 * specific PCI device. The subvendor, and subdevice fields will be set
604 * to PCI_ANY_ID. The macro allows the next field to follow as the device
605 * private data.
606 */
607
608 #define PCI_VDEVICE(vendor, device) \
609 PCI_VENDOR_ID_##vendor, (device), \
610 PCI_ANY_ID, PCI_ANY_ID, 0, 0
611
612 /* these external functions are only available when PCI support is enabled */
613 #ifdef CONFIG_PCI
614
615 extern struct bus_type pci_bus_type;
616
617 /* Do NOT directly access these two variables, unless you are arch specific pci
618 * code, or pci core code. */
619 extern struct list_head pci_root_buses; /* list of all known PCI buses */
620 /* Some device drivers need know if pci is initiated */
621 extern int no_pci_devices(void);
622
623 void pcibios_fixup_bus(struct pci_bus *);
624 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
625 char *pcibios_setup(char *str);
626
627 /* Used only when drivers/pci/setup.c is used */
628 resource_size_t pcibios_align_resource(void *, const struct resource *,
629 resource_size_t,
630 resource_size_t);
631 void pcibios_update_irq(struct pci_dev *, int irq);
632
633 /* Weak but can be overriden by arch */
634 void pci_fixup_cardbus(struct pci_bus *);
635
636 /* Generic PCI functions used internally */
637
638 void pcibios_scan_specific_bus(int busn);
639 extern struct pci_bus *pci_find_bus(int domain, int busnr);
640 void pci_bus_add_devices(const struct pci_bus *bus);
641 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
642 struct pci_ops *ops, void *sysdata);
643 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
644 void *sysdata)
645 {
646 struct pci_bus *root_bus;
647 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
648 if (root_bus)
649 pci_bus_add_devices(root_bus);
650 return root_bus;
651 }
652 struct pci_bus *pci_create_bus(struct device *parent, int bus,
653 struct pci_ops *ops, void *sysdata);
654 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
655 int busnr);
656 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
657 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
658 const char *name,
659 struct hotplug_slot *hotplug);
660 void pci_destroy_slot(struct pci_slot *slot);
661 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
662 int pci_scan_slot(struct pci_bus *bus, int devfn);
663 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
664 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
665 unsigned int pci_scan_child_bus(struct pci_bus *bus);
666 int __must_check pci_bus_add_device(struct pci_dev *dev);
667 void pci_read_bridge_bases(struct pci_bus *child);
668 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
669 struct resource *res);
670 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
671 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
672 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
673 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
674 extern void pci_dev_put(struct pci_dev *dev);
675 extern void pci_remove_bus(struct pci_bus *b);
676 extern void pci_remove_bus_device(struct pci_dev *dev);
677 extern void pci_stop_bus_device(struct pci_dev *dev);
678 void pci_setup_cardbus(struct pci_bus *bus);
679 extern void pci_sort_breadthfirst(void);
680 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
681 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
682 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
683
684 /* Generic PCI functions exported to card drivers */
685
686 enum pci_lost_interrupt_reason {
687 PCI_LOST_IRQ_NO_INFORMATION = 0,
688 PCI_LOST_IRQ_DISABLE_MSI,
689 PCI_LOST_IRQ_DISABLE_MSIX,
690 PCI_LOST_IRQ_DISABLE_ACPI,
691 };
692 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
693 int pci_find_capability(struct pci_dev *dev, int cap);
694 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
695 int pci_find_ext_capability(struct pci_dev *dev, int cap);
696 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
697 int cap);
698 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
699 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
700 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
701
702 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
703 struct pci_dev *from);
704 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
705 unsigned int ss_vendor, unsigned int ss_device,
706 struct pci_dev *from);
707 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
708 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
709 unsigned int devfn);
710 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
711 unsigned int devfn)
712 {
713 return pci_get_domain_bus_and_slot(0, bus, devfn);
714 }
715 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
716 int pci_dev_present(const struct pci_device_id *ids);
717
718 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
719 int where, u8 *val);
720 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
721 int where, u16 *val);
722 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
723 int where, u32 *val);
724 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
725 int where, u8 val);
726 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
727 int where, u16 val);
728 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
729 int where, u32 val);
730 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
731
732 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
733 {
734 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
735 }
736 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
737 {
738 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
739 }
740 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
741 u32 *val)
742 {
743 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
744 }
745 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
746 {
747 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
748 }
749 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
750 {
751 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
752 }
753 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
754 u32 val)
755 {
756 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
757 }
758
759 int __must_check pci_enable_device(struct pci_dev *dev);
760 int __must_check pci_enable_device_io(struct pci_dev *dev);
761 int __must_check pci_enable_device_mem(struct pci_dev *dev);
762 int __must_check pci_reenable_device(struct pci_dev *);
763 int __must_check pcim_enable_device(struct pci_dev *pdev);
764 void pcim_pin_device(struct pci_dev *pdev);
765
766 static inline int pci_is_enabled(struct pci_dev *pdev)
767 {
768 return (atomic_read(&pdev->enable_cnt) > 0);
769 }
770
771 static inline int pci_is_managed(struct pci_dev *pdev)
772 {
773 return pdev->is_managed;
774 }
775
776 void pci_disable_device(struct pci_dev *dev);
777 void pci_set_master(struct pci_dev *dev);
778 void pci_clear_master(struct pci_dev *dev);
779 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
780 int pci_set_cacheline_size(struct pci_dev *dev);
781 #define HAVE_PCI_SET_MWI
782 int __must_check pci_set_mwi(struct pci_dev *dev);
783 int pci_try_set_mwi(struct pci_dev *dev);
784 void pci_clear_mwi(struct pci_dev *dev);
785 void pci_intx(struct pci_dev *dev, int enable);
786 void pci_msi_off(struct pci_dev *dev);
787 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
788 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
789 int pcix_get_max_mmrbc(struct pci_dev *dev);
790 int pcix_get_mmrbc(struct pci_dev *dev);
791 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
792 int pcie_get_readrq(struct pci_dev *dev);
793 int pcie_set_readrq(struct pci_dev *dev, int rq);
794 int __pci_reset_function(struct pci_dev *dev);
795 int pci_reset_function(struct pci_dev *dev);
796 void pci_update_resource(struct pci_dev *dev, int resno);
797 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
798 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
799
800 /* ROM control related routines */
801 int pci_enable_rom(struct pci_dev *pdev);
802 void pci_disable_rom(struct pci_dev *pdev);
803 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
804 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
805 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
806
807 /* Power management related routines */
808 int pci_save_state(struct pci_dev *dev);
809 int pci_restore_state(struct pci_dev *dev);
810 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
811 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
812 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
813 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
814 void pci_pme_active(struct pci_dev *dev, bool enable);
815 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
816 bool runtime, bool enable);
817 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
818 pci_power_t pci_target_state(struct pci_dev *dev);
819 int pci_prepare_to_sleep(struct pci_dev *dev);
820 int pci_back_from_sleep(struct pci_dev *dev);
821 bool pci_dev_run_wake(struct pci_dev *dev);
822
823 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
824 bool enable)
825 {
826 return __pci_enable_wake(dev, state, false, enable);
827 }
828
829 /* For use by arch with custom probe code */
830 void set_pcie_port_type(struct pci_dev *pdev);
831 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
832
833 /* Functions for PCI Hotplug drivers to use */
834 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
835 #ifdef CONFIG_HOTPLUG
836 unsigned int pci_rescan_bus(struct pci_bus *bus);
837 #endif
838
839 /* Vital product data routines */
840 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
841 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
842 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
843
844 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
845 void pci_bus_assign_resources(const struct pci_bus *bus);
846 void pci_bus_size_bridges(struct pci_bus *bus);
847 int pci_claim_resource(struct pci_dev *, int);
848 void pci_assign_unassigned_resources(void);
849 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
850 void pdev_enable_device(struct pci_dev *);
851 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
852 int pci_enable_resources(struct pci_dev *, int mask);
853 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
854 int (*)(struct pci_dev *, u8, u8));
855 #define HAVE_PCI_REQ_REGIONS 2
856 int __must_check pci_request_regions(struct pci_dev *, const char *);
857 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
858 void pci_release_regions(struct pci_dev *);
859 int __must_check pci_request_region(struct pci_dev *, int, const char *);
860 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
861 void pci_release_region(struct pci_dev *, int);
862 int pci_request_selected_regions(struct pci_dev *, int, const char *);
863 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
864 void pci_release_selected_regions(struct pci_dev *, int);
865
866 /* drivers/pci/bus.c */
867 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
868 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
869 void pci_bus_remove_resources(struct pci_bus *bus);
870
871 #define pci_bus_for_each_resource(bus, res, i) \
872 for (i = 0; \
873 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
874 i++)
875
876 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
877 struct resource *res, resource_size_t size,
878 resource_size_t align, resource_size_t min,
879 unsigned int type_mask,
880 resource_size_t (*alignf)(void *,
881 const struct resource *,
882 resource_size_t,
883 resource_size_t),
884 void *alignf_data);
885 void pci_enable_bridges(struct pci_bus *bus);
886
887 /* Proper probing supporting hot-pluggable devices */
888 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
889 const char *mod_name);
890
891 /*
892 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
893 */
894 #define pci_register_driver(driver) \
895 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
896
897 void pci_unregister_driver(struct pci_driver *dev);
898 void pci_remove_behind_bridge(struct pci_dev *dev);
899 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
900 int pci_add_dynid(struct pci_driver *drv,
901 unsigned int vendor, unsigned int device,
902 unsigned int subvendor, unsigned int subdevice,
903 unsigned int class, unsigned int class_mask,
904 unsigned long driver_data);
905 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
906 struct pci_dev *dev);
907 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
908 int pass);
909
910 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
911 void *userdata);
912 int pci_cfg_space_size_ext(struct pci_dev *dev);
913 int pci_cfg_space_size(struct pci_dev *dev);
914 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
915
916 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
917 unsigned int command_bits, bool change_bridge);
918 /* kmem_cache style wrapper around pci_alloc_consistent() */
919
920 #include <linux/pci-dma.h>
921 #include <linux/dmapool.h>
922
923 #define pci_pool dma_pool
924 #define pci_pool_create(name, pdev, size, align, allocation) \
925 dma_pool_create(name, &pdev->dev, size, align, allocation)
926 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
927 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
928 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
929
930 enum pci_dma_burst_strategy {
931 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
932 strategy_parameter is N/A */
933 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
934 byte boundaries */
935 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
936 strategy_parameter byte boundaries */
937 };
938
939 struct msix_entry {
940 u32 vector; /* kernel uses to write allocated vector */
941 u16 entry; /* driver uses to specify entry, OS writes */
942 };
943
944
945 #ifndef CONFIG_PCI_MSI
946 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
947 {
948 return -1;
949 }
950
951 static inline void pci_msi_shutdown(struct pci_dev *dev)
952 { }
953 static inline void pci_disable_msi(struct pci_dev *dev)
954 { }
955
956 static inline int pci_msix_table_size(struct pci_dev *dev)
957 {
958 return 0;
959 }
960 static inline int pci_enable_msix(struct pci_dev *dev,
961 struct msix_entry *entries, int nvec)
962 {
963 return -1;
964 }
965
966 static inline void pci_msix_shutdown(struct pci_dev *dev)
967 { }
968 static inline void pci_disable_msix(struct pci_dev *dev)
969 { }
970
971 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
972 { }
973
974 static inline void pci_restore_msi_state(struct pci_dev *dev)
975 { }
976 static inline int pci_msi_enabled(void)
977 {
978 return 0;
979 }
980 #else
981 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
982 extern void pci_msi_shutdown(struct pci_dev *dev);
983 extern void pci_disable_msi(struct pci_dev *dev);
984 extern int pci_msix_table_size(struct pci_dev *dev);
985 extern int pci_enable_msix(struct pci_dev *dev,
986 struct msix_entry *entries, int nvec);
987 extern void pci_msix_shutdown(struct pci_dev *dev);
988 extern void pci_disable_msix(struct pci_dev *dev);
989 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
990 extern void pci_restore_msi_state(struct pci_dev *dev);
991 extern int pci_msi_enabled(void);
992 #endif
993
994 #ifndef CONFIG_PCIEASPM
995 static inline int pcie_aspm_enabled(void)
996 {
997 return 0;
998 }
999 #else
1000 extern int pcie_aspm_enabled(void);
1001 #endif
1002
1003 #ifndef CONFIG_PCIE_ECRC
1004 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1005 {
1006 return;
1007 }
1008 static inline void pcie_ecrc_get_policy(char *str) {};
1009 #else
1010 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1011 extern void pcie_ecrc_get_policy(char *str);
1012 #endif
1013
1014 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1015
1016 #ifdef CONFIG_HT_IRQ
1017 /* The functions a driver should call */
1018 int ht_create_irq(struct pci_dev *dev, int idx);
1019 void ht_destroy_irq(unsigned int irq);
1020 #endif /* CONFIG_HT_IRQ */
1021
1022 extern void pci_block_user_cfg_access(struct pci_dev *dev);
1023 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
1024
1025 /*
1026 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1027 * a PCI domain is defined to be a set of PCI busses which share
1028 * configuration space.
1029 */
1030 #ifdef CONFIG_PCI_DOMAINS
1031 extern int pci_domains_supported;
1032 #else
1033 enum { pci_domains_supported = 0 };
1034 static inline int pci_domain_nr(struct pci_bus *bus)
1035 {
1036 return 0;
1037 }
1038
1039 static inline int pci_proc_domain(struct pci_bus *bus)
1040 {
1041 return 0;
1042 }
1043 #endif /* CONFIG_PCI_DOMAINS */
1044
1045 /* some architectures require additional setup to direct VGA traffic */
1046 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1047 unsigned int command_bits, bool change_bridge);
1048 extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1049
1050 #else /* CONFIG_PCI is not enabled */
1051
1052 /*
1053 * If the system does not have PCI, clearly these return errors. Define
1054 * these as simple inline functions to avoid hair in drivers.
1055 */
1056
1057 #define _PCI_NOP(o, s, t) \
1058 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1059 int where, t val) \
1060 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1061
1062 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1063 _PCI_NOP(o, word, u16 x) \
1064 _PCI_NOP(o, dword, u32 x)
1065 _PCI_NOP_ALL(read, *)
1066 _PCI_NOP_ALL(write,)
1067
1068 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1069 unsigned int device,
1070 struct pci_dev *from)
1071 {
1072 return NULL;
1073 }
1074
1075 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1076 unsigned int device,
1077 unsigned int ss_vendor,
1078 unsigned int ss_device,
1079 struct pci_dev *from)
1080 {
1081 return NULL;
1082 }
1083
1084 static inline struct pci_dev *pci_get_class(unsigned int class,
1085 struct pci_dev *from)
1086 {
1087 return NULL;
1088 }
1089
1090 #define pci_dev_present(ids) (0)
1091 #define no_pci_devices() (1)
1092 #define pci_dev_put(dev) do { } while (0)
1093
1094 static inline void pci_set_master(struct pci_dev *dev)
1095 { }
1096
1097 static inline int pci_enable_device(struct pci_dev *dev)
1098 {
1099 return -EIO;
1100 }
1101
1102 static inline void pci_disable_device(struct pci_dev *dev)
1103 { }
1104
1105 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1106 {
1107 return -EIO;
1108 }
1109
1110 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1111 {
1112 return -EIO;
1113 }
1114
1115 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1116 unsigned int size)
1117 {
1118 return -EIO;
1119 }
1120
1121 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1122 unsigned long mask)
1123 {
1124 return -EIO;
1125 }
1126
1127 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1128 {
1129 return -EBUSY;
1130 }
1131
1132 static inline int __pci_register_driver(struct pci_driver *drv,
1133 struct module *owner)
1134 {
1135 return 0;
1136 }
1137
1138 static inline int pci_register_driver(struct pci_driver *drv)
1139 {
1140 return 0;
1141 }
1142
1143 static inline void pci_unregister_driver(struct pci_driver *drv)
1144 { }
1145
1146 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1147 {
1148 return 0;
1149 }
1150
1151 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1152 int cap)
1153 {
1154 return 0;
1155 }
1156
1157 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1158 {
1159 return 0;
1160 }
1161
1162 /* Power management related routines */
1163 static inline int pci_save_state(struct pci_dev *dev)
1164 {
1165 return 0;
1166 }
1167
1168 static inline int pci_restore_state(struct pci_dev *dev)
1169 {
1170 return 0;
1171 }
1172
1173 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1174 {
1175 return 0;
1176 }
1177
1178 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1179 pm_message_t state)
1180 {
1181 return PCI_D0;
1182 }
1183
1184 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1185 int enable)
1186 {
1187 return 0;
1188 }
1189
1190 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1191 {
1192 return -EIO;
1193 }
1194
1195 static inline void pci_release_regions(struct pci_dev *dev)
1196 { }
1197
1198 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1199
1200 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
1201 { }
1202
1203 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
1204 { }
1205
1206 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1207 { return NULL; }
1208
1209 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1210 unsigned int devfn)
1211 { return NULL; }
1212
1213 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1214 unsigned int devfn)
1215 { return NULL; }
1216
1217 static inline int pci_domain_nr(struct pci_bus *bus)
1218 { return 0; }
1219
1220 #define dev_is_pci(d) (false)
1221 #define dev_is_pf(d) (false)
1222 #define dev_num_vf(d) (0)
1223 #endif /* CONFIG_PCI */
1224
1225 /* Include architecture-dependent settings and functions */
1226
1227 #include <asm/pci.h>
1228
1229 #ifndef PCIBIOS_MAX_MEM_32
1230 #define PCIBIOS_MAX_MEM_32 (-1)
1231 #endif
1232
1233 /* these helpers provide future and backwards compatibility
1234 * for accessing popular PCI BAR info */
1235 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1236 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1237 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1238 #define pci_resource_len(dev,bar) \
1239 ((pci_resource_start((dev), (bar)) == 0 && \
1240 pci_resource_end((dev), (bar)) == \
1241 pci_resource_start((dev), (bar))) ? 0 : \
1242 \
1243 (pci_resource_end((dev), (bar)) - \
1244 pci_resource_start((dev), (bar)) + 1))
1245
1246 /* Similar to the helpers above, these manipulate per-pci_dev
1247 * driver-specific data. They are really just a wrapper around
1248 * the generic device structure functions of these calls.
1249 */
1250 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1251 {
1252 return dev_get_drvdata(&pdev->dev);
1253 }
1254
1255 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1256 {
1257 dev_set_drvdata(&pdev->dev, data);
1258 }
1259
1260 /* If you want to know what to call your pci_dev, ask this function.
1261 * Again, it's a wrapper around the generic device.
1262 */
1263 static inline const char *pci_name(const struct pci_dev *pdev)
1264 {
1265 return dev_name(&pdev->dev);
1266 }
1267
1268
1269 /* Some archs don't want to expose struct resource to userland as-is
1270 * in sysfs and /proc
1271 */
1272 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1273 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1274 const struct resource *rsrc, resource_size_t *start,
1275 resource_size_t *end)
1276 {
1277 *start = rsrc->start;
1278 *end = rsrc->end;
1279 }
1280 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1281
1282
1283
1284 struct pci_fixup {
1285 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1286 void (*hook)(struct pci_dev *dev);
1287 };
1288
1289 enum pci_fixup_pass {
1290 pci_fixup_early, /* Before probing BARs */
1291 pci_fixup_header, /* After reading configuration header */
1292 pci_fixup_final, /* Final phase of device fixups */
1293 pci_fixup_enable, /* pci_enable_device() time */
1294 pci_fixup_resume, /* pci_device_resume() */
1295 pci_fixup_suspend, /* pci_device_suspend */
1296 pci_fixup_resume_early, /* pci_device_resume_early() */
1297 };
1298
1299 /* Anonymous variables would be nice... */
1300 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1301 static const struct pci_fixup __pci_fixup_##name __used \
1302 __attribute__((__section__(#section))) = { vendor, device, hook };
1303 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1304 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1305 vendor##device##hook, vendor, device, hook)
1306 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1307 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1308 vendor##device##hook, vendor, device, hook)
1309 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1310 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1311 vendor##device##hook, vendor, device, hook)
1312 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1313 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1314 vendor##device##hook, vendor, device, hook)
1315 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1316 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1317 resume##vendor##device##hook, vendor, device, hook)
1318 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1319 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1320 resume_early##vendor##device##hook, vendor, device, hook)
1321 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1322 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1323 suspend##vendor##device##hook, vendor, device, hook)
1324
1325 #ifdef CONFIG_PCI_QUIRKS
1326 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1327 #else
1328 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1329 struct pci_dev *dev) {}
1330 #endif
1331
1332 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1333 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1334 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1335 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1336 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1337 const char *name);
1338 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1339
1340 extern int pci_pci_problems;
1341 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1342 #define PCIPCI_TRITON 2
1343 #define PCIPCI_NATOMA 4
1344 #define PCIPCI_VIAETBF 8
1345 #define PCIPCI_VSFX 16
1346 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1347 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1348
1349 extern unsigned long pci_cardbus_io_size;
1350 extern unsigned long pci_cardbus_mem_size;
1351 extern u8 __devinitdata pci_dfl_cache_line_size;
1352 extern u8 pci_cache_line_size;
1353
1354 extern unsigned long pci_hotplug_io_size;
1355 extern unsigned long pci_hotplug_mem_size;
1356
1357 int pcibios_add_platform_entries(struct pci_dev *dev);
1358 void pcibios_disable_device(struct pci_dev *dev);
1359 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1360 enum pcie_reset_state state);
1361
1362 #ifdef CONFIG_PCI_MMCONFIG
1363 extern void __init pci_mmcfg_early_init(void);
1364 extern void __init pci_mmcfg_late_init(void);
1365 #else
1366 static inline void pci_mmcfg_early_init(void) { }
1367 static inline void pci_mmcfg_late_init(void) { }
1368 #endif
1369
1370 int pci_ext_cfg_avail(struct pci_dev *dev);
1371
1372 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1373
1374 #ifdef CONFIG_PCI_IOV
1375 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1376 extern void pci_disable_sriov(struct pci_dev *dev);
1377 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1378 extern int pci_num_vf(struct pci_dev *dev);
1379 #else
1380 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1381 {
1382 return -ENODEV;
1383 }
1384 static inline void pci_disable_sriov(struct pci_dev *dev)
1385 {
1386 }
1387 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1388 {
1389 return IRQ_NONE;
1390 }
1391 static inline int pci_num_vf(struct pci_dev *dev)
1392 {
1393 return 0;
1394 }
1395 #endif
1396
1397 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1398 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1399 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1400 #endif
1401
1402 /**
1403 * pci_pcie_cap - get the saved PCIe capability offset
1404 * @dev: PCI device
1405 *
1406 * PCIe capability offset is calculated at PCI device initialization
1407 * time and saved in the data structure. This function returns saved
1408 * PCIe capability offset. Using this instead of pci_find_capability()
1409 * reduces unnecessary search in the PCI configuration space. If you
1410 * need to calculate PCIe capability offset from raw device for some
1411 * reasons, please use pci_find_capability() instead.
1412 */
1413 static inline int pci_pcie_cap(struct pci_dev *dev)
1414 {
1415 return dev->pcie_cap;
1416 }
1417
1418 /**
1419 * pci_is_pcie - check if the PCI device is PCI Express capable
1420 * @dev: PCI device
1421 *
1422 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1423 */
1424 static inline bool pci_is_pcie(struct pci_dev *dev)
1425 {
1426 return !!pci_pcie_cap(dev);
1427 }
1428
1429 void pci_request_acs(void);
1430
1431
1432 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1433 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1434
1435 /* Large Resource Data Type Tag Item Names */
1436 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1437 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1438 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1439
1440 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1441 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1442 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1443
1444 /* Small Resource Data Type Tag Item Names */
1445 #define PCI_VPD_STIN_END 0x78 /* End */
1446
1447 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1448
1449 #define PCI_VPD_SRDT_TIN_MASK 0x78
1450 #define PCI_VPD_SRDT_LEN_MASK 0x07
1451
1452 #define PCI_VPD_LRDT_TAG_SIZE 3
1453 #define PCI_VPD_SRDT_TAG_SIZE 1
1454
1455 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1456
1457 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1458 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1459 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1460
1461 /**
1462 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1463 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1464 *
1465 * Returns the extracted Large Resource Data Type length.
1466 */
1467 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1468 {
1469 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1470 }
1471
1472 /**
1473 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1474 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1475 *
1476 * Returns the extracted Small Resource Data Type length.
1477 */
1478 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1479 {
1480 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1481 }
1482
1483 /**
1484 * pci_vpd_info_field_size - Extracts the information field length
1485 * @lrdt: Pointer to the beginning of an information field header
1486 *
1487 * Returns the extracted information field length.
1488 */
1489 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1490 {
1491 return info_field[2];
1492 }
1493
1494 /**
1495 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1496 * @buf: Pointer to buffered vpd data
1497 * @off: The offset into the buffer at which to begin the search
1498 * @len: The length of the vpd buffer
1499 * @rdt: The Resource Data Type to search for
1500 *
1501 * Returns the index where the Resource Data Type was found or
1502 * -ENOENT otherwise.
1503 */
1504 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1505
1506 /**
1507 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1508 * @buf: Pointer to buffered vpd data
1509 * @off: The offset into the buffer at which to begin the search
1510 * @len: The length of the buffer area, relative to off, in which to search
1511 * @kw: The keyword to search for
1512 *
1513 * Returns the index where the information field keyword was found or
1514 * -ENOENT otherwise.
1515 */
1516 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1517 unsigned int len, const char *kw);
1518
1519 #endif /* __KERNEL__ */
1520 #endif /* LINUX_PCI_H */
Tomato firmware and modifications.