release/src-rt-6.x.4708/linux/linux-2.6.36/include/linux/fsl-diu-fb.h

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  *  Freescale DIU Frame Buffer device driver
   5  *
   6  *  Authors: Hongjun Chen <hong-jun.chen@freescale.com>
   7  *           Paul Widmer <paul.widmer@freescale.com>
   8  *           Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
   9  *           York Sun <yorksun@freescale.com>
  10  *
  11  *   Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  *
  18  */
  19
  20 #ifndef __FSL_DIU_FB_H__
  21 #define __FSL_DIU_FB_H__
  22
  23 /* Arbitrary threshold to determine the allocation method
  24  * See mpc8610fb_set_par(), map_video_memory(), and unmap_video_memory()
  25  */
  26 #define MEM_ALLOC_THRESHOLD (1024*768*4+32)
  27 /* Minimum value that the pixel clock can be set to in pico seconds
  28  * This is determined by platform clock/3 where the minimum platform
  29  * clock is 533MHz. This gives 5629 pico seconds.
  30  */
  31 #define MIN_PIX_CLK 5629
  32 #define MAX_PIX_CLK 96096
  33
  34 #include <linux/types.h>
  35
  36 struct mfb_alpha {
  37         int enable;
  38         int alpha;
  39 };
  40
  41 struct mfb_chroma_key {
  42         int enable;
  43         __u8  red_max;
  44         __u8  green_max;
  45         __u8  blue_max;
  46         __u8  red_min;
  47         __u8  green_min;
  48         __u8  blue_min;
  49 };
  50
  51 struct aoi_display_offset {
  52         int x_aoi_d;
  53         int y_aoi_d;
  54 };
  55
  56 #define MFB_SET_CHROMA_KEY      _IOW('M', 1, struct mfb_chroma_key)
  57 #define MFB_WAIT_FOR_VSYNC      _IOW('F', 0x20, u_int32_t)
  58 #define MFB_SET_BRIGHTNESS      _IOW('M', 3, __u8)
  59
  60 #define MFB_SET_ALPHA           0x80014d00
  61 #define MFB_GET_ALPHA           0x40014d00
  62 #define MFB_SET_AOID            0x80084d04
  63 #define MFB_GET_AOID            0x40084d04
  64 #define MFB_SET_PIXFMT          0x80014d08
  65 #define MFB_GET_PIXFMT          0x40014d08
  66
  67 #define FBIOGET_GWINFO          0x46E0
  68 #define FBIOPUT_GWINFO          0x46E1
  69
  70 #ifdef __KERNEL__
  71 #include <linux/spinlock.h>
  72
  73 /*
  74  * These are the fields of area descriptor(in DDR memory) for every plane
  75  */
  76 struct diu_ad {
  77         /* Word 0(32-bit) in DDR memory */
  78 /*      __u16 comp; */
  79 /*      __u16 pixel_s:2; */
  80 /*      __u16 pallete:1; */
  81 /*      __u16 red_c:2; */
  82 /*      __u16 green_c:2; */
  83 /*      __u16 blue_c:2; */
  84 /*      __u16 alpha_c:3; */
  85 /*      __u16 byte_f:1; */
  86 /*      __u16 res0:3; */
  87
  88         __be32 pix_fmt; /* hard coding pixel format */
  89
  90         /* Word 1(32-bit) in DDR memory */
  91         __le32 addr;
  92
  93         /* Word 2(32-bit) in DDR memory */
  94 /*      __u32 delta_xs:11; */
  95 /*      __u32 res1:1; */
  96 /*      __u32 delta_ys:11; */
  97 /*      __u32 res2:1; */
  98 /*      __u32 g_alpha:8; */
  99         __le32 src_size_g_alpha;
 100
 101         /* Word 3(32-bit) in DDR memory */
 102 /*      __u32 delta_xi:11; */
 103 /*      __u32 res3:5; */
 104 /*      __u32 delta_yi:11; */
 105 /*      __u32 res4:3; */
 106 /*      __u32 flip:2; */
 107         __le32 aoi_size;
 108
 109         /* Word 4(32-bit) in DDR memory */
 110         /*__u32 offset_xi:11;
 111         __u32 res5:5;
 112         __u32 offset_yi:11;
 113         __u32 res6:5;
 114         */
 115         __le32 offset_xyi;
 116
 117         /* Word 5(32-bit) in DDR memory */
 118         /*__u32 offset_xd:11;
 119         __u32 res7:5;
 120         __u32 offset_yd:11;
 121         __u32 res8:5; */
 122         __le32 offset_xyd;
 123
 124
 125         /* Word 6(32-bit) in DDR memory */
 126         __u8 ckmax_r;
 127         __u8 ckmax_g;
 128         __u8 ckmax_b;
 129         __u8 res9;
 130
 131         /* Word 7(32-bit) in DDR memory */
 132         __u8 ckmin_r;
 133         __u8 ckmin_g;
 134         __u8 ckmin_b;
 135         __u8 res10;
 136 /*      __u32 res10:8; */
 137
 138         /* Word 8(32-bit) in DDR memory */
 139         __le32 next_ad;
 140
 141         /* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
 142         __u32 paddr;
 143 } __attribute__ ((packed));
 144
 145 /* DIU register map */
 146 struct diu {
 147         __be32 desc[3];
 148         __be32 gamma;
 149         __be32 pallete;
 150         __be32 cursor;
 151         __be32 curs_pos;
 152         __be32 diu_mode;
 153         __be32 bgnd;
 154         __be32 bgnd_wb;
 155         __be32 disp_size;
 156         __be32 wb_size;
 157         __be32 wb_mem_addr;
 158         __be32 hsyn_para;
 159         __be32 vsyn_para;
 160         __be32 syn_pol;
 161         __be32 thresholds;
 162         __be32 int_status;
 163         __be32 int_mask;
 164         __be32 colorbar[8];
 165         __be32 filling;
 166         __be32 plut;
 167 } __attribute__ ((packed));
 168
 169 struct diu_hw {
 170         struct diu *diu_reg;
 171         spinlock_t reg_lock;
 172
 173         __u32 mode;             /* DIU operation mode */
 174 };
 175
 176 struct diu_addr {
 177         __u8 __iomem *vaddr;    /* Virtual address */
 178         dma_addr_t paddr;       /* Physical address */
 179         __u32      offset;
 180 };
 181
 182 struct diu_pool {
 183         struct diu_addr ad;
 184         struct diu_addr gamma;
 185         struct diu_addr pallete;
 186         struct diu_addr cursor;
 187 };
 188
 189 #define FSL_DIU_BASE_OFFSET     0x2C000 /* Offset of DIU */
 190 #define INT_LCDC                64      /* DIU interrupt number */
 191
 192 #define FSL_AOI_NUM     6       /* 5 AOIs and one dummy AOI */
 193                                 /* 1 for plane 0, 2 for plane 1&2 each */
 194
 195 /* Minimum X and Y resolutions */
 196 #define MIN_XRES        64
 197 #define MIN_YRES        64
 198
 199 /* HW cursor parameters */
 200 #define MAX_CURS                32
 201
 202 /* Modes of operation of DIU */
 203 #define MFB_MODE0       0       /* DIU off */
 204 #define MFB_MODE1       1       /* All three planes output to display */
 205 #define MFB_MODE2       2       /* Plane 1 to display, planes 2+3 written back*/
 206 #define MFB_MODE3       3       /* All three planes written back to memory */
 207 #define MFB_MODE4       4       /* Color bar generation */
 208
 209 /* INT_STATUS/INT_MASK field descriptions */
 210 #define INT_VSYNC       0x01    /* Vsync interrupt  */
 211 #define INT_VSYNC_WB    0x02    /* Vsync interrupt for write back operation */
 212 #define INT_UNDRUN      0x04    /* Under run exception interrupt */
 213 #define INT_PARERR      0x08    /* Display parameters error interrupt */
 214 #define INT_LS_BF_VS    0x10    /* Lines before vsync. interrupt */
 215
 216 /* Panels'operation modes */
 217 #define MFB_TYPE_OUTPUT 0       /* Panel output to display */
 218 #define MFB_TYPE_OFF    1       /* Panel off */
 219 #define MFB_TYPE_WB     2       /* Panel written back to memory */
 220 #define MFB_TYPE_TEST   3       /* Panel generate color bar */
 221
 222 #endif /* __KERNEL__ */
 223 #endif /* __FSL_DIU_FB_H__ */