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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / video / sh_mobile_hdmi.c
blob2749ffe8a0dccdc2596f4f8d1df9653cd1c7ba16
1 /*
2 * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
3 * for SLISHDMI13T and SLIPHDMIT IP cores
4 *
5 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/clk.h>
13 #include <linux/console.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/slab.h>
23 #include <linux/types.h>
24 #include <linux/workqueue.h>
25
26 #include <video/sh_mobile_hdmi.h>
27 #include <video/sh_mobile_lcdc.h>
28
29 #define HDMI_SYSTEM_CTRL 0x00 /* System control */
30 #define HDMI_L_R_DATA_SWAP_CTRL_RPKT 0x01 /* L/R data swap control,
31 bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
32 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8 0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
33 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0 0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
34 #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS 0x04 /* SPDIF audio sampling frequency,
35 bits 19..16 of Internal CTS */
36 #define HDMI_INTERNAL_CTS_15_8 0x05 /* bits 15..8 of Internal CTS */
37 #define HDMI_INTERNAL_CTS_7_0 0x06 /* bits 7..0 of Internal CTS */
38 #define HDMI_EXTERNAL_CTS_19_16 0x07 /* External CTS */
39 #define HDMI_EXTERNAL_CTS_15_8 0x08 /* External CTS */
40 #define HDMI_EXTERNAL_CTS_7_0 0x09 /* External CTS */
41 #define HDMI_AUDIO_SETTING_1 0x0A /* Audio setting.1 */
42 #define HDMI_AUDIO_SETTING_2 0x0B /* Audio setting.2 */
43 #define HDMI_I2S_AUDIO_SET 0x0C /* I2S audio setting */
44 #define HDMI_DSD_AUDIO_SET 0x0D /* DSD audio setting */
45 #define HDMI_DEBUG_MONITOR_1 0x0E /* Debug monitor.1 */
46 #define HDMI_DEBUG_MONITOR_2 0x0F /* Debug monitor.2 */
47 #define HDMI_I2S_INPUT_PIN_SWAP 0x10 /* I2S input pin swap */
48 #define HDMI_AUDIO_STATUS_BITS_SETTING_1 0x11 /* Audio status bits setting.1 */
49 #define HDMI_AUDIO_STATUS_BITS_SETTING_2 0x12 /* Audio status bits setting.2 */
50 #define HDMI_CATEGORY_CODE 0x13 /* Category code */
51 #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN 0x14 /* Source number/Audio word length */
52 #define HDMI_AUDIO_VIDEO_SETTING_1 0x15 /* Audio/Video setting.1 */
53 #define HDMI_VIDEO_SETTING_1 0x16 /* Video setting.1 */
54 #define HDMI_DEEP_COLOR_MODES 0x17 /* Deep Color Modes */
55
56 /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
57 #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS 0x18
58
59 #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS 0x30 /* External video parameter settings */
60 #define HDMI_EXTERNAL_H_TOTAL_7_0 0x31 /* External horizontal total (LSB) */
61 #define HDMI_EXTERNAL_H_TOTAL_11_8 0x32 /* External horizontal total (MSB) */
62 #define HDMI_EXTERNAL_H_BLANK_7_0 0x33 /* External horizontal blank (LSB) */
63 #define HDMI_EXTERNAL_H_BLANK_9_8 0x34 /* External horizontal blank (MSB) */
64 #define HDMI_EXTERNAL_H_DELAY_7_0 0x35 /* External horizontal delay (LSB) */
65 #define HDMI_EXTERNAL_H_DELAY_9_8 0x36 /* External horizontal delay (MSB) */
66 #define HDMI_EXTERNAL_H_DURATION_7_0 0x37 /* External horizontal duration (LSB) */
67 #define HDMI_EXTERNAL_H_DURATION_9_8 0x38 /* External horizontal duration (MSB) */
68 #define HDMI_EXTERNAL_V_TOTAL_7_0 0x39 /* External vertical total (LSB) */
69 #define HDMI_EXTERNAL_V_TOTAL_9_8 0x3A /* External vertical total (MSB) */
70 #define HDMI_AUDIO_VIDEO_SETTING_2 0x3B /* Audio/Video setting.2 */
71 #define HDMI_EXTERNAL_V_BLANK 0x3D /* External vertical blank */
72 #define HDMI_EXTERNAL_V_DELAY 0x3E /* External vertical delay */
73 #define HDMI_EXTERNAL_V_DURATION 0x3F /* External vertical duration */
74 #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL 0x40 /* Control packet manual send control */
75 #define HDMI_CTRL_PKT_AUTO_SEND 0x41 /* Control packet auto send with VSYNC control */
76 #define HDMI_AUTO_CHECKSUM_OPTION 0x42 /* Auto checksum option */
77 #define HDMI_VIDEO_SETTING_2 0x45 /* Video setting.2 */
78 #define HDMI_OUTPUT_OPTION 0x46 /* Output option */
79 #define HDMI_SLIPHDMIT_PARAM_OPTION 0x51 /* SLIPHDMIT parameter option */
80 #define HDMI_HSYNC_PMENT_AT_EMB_7_0 0x52 /* HSYNC placement at embedded sync (LSB) */
81 #define HDMI_HSYNC_PMENT_AT_EMB_15_8 0x53 /* HSYNC placement at embedded sync (MSB) */
82 #define HDMI_VSYNC_PMENT_AT_EMB_7_0 0x54 /* VSYNC placement at embedded sync (LSB) */
83 #define HDMI_VSYNC_PMENT_AT_EMB_14_8 0x55 /* VSYNC placement at embedded sync (MSB) */
84 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1 0x56 /* SLIPHDMIT parameter settings.1 */
85 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2 0x57 /* SLIPHDMIT parameter settings.2 */
86 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3 0x58 /* SLIPHDMIT parameter settings.3 */
87 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5 0x59 /* SLIPHDMIT parameter settings.5 */
88 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6 0x5A /* SLIPHDMIT parameter settings.6 */
89 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7 0x5B /* SLIPHDMIT parameter settings.7 */
90 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8 0x5C /* SLIPHDMIT parameter settings.8 */
91 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9 0x5D /* SLIPHDMIT parameter settings.9 */
92 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10 0x5E /* SLIPHDMIT parameter settings.10 */
93 #define HDMI_CTRL_PKT_BUF_INDEX 0x5F /* Control packet buffer index */
94 #define HDMI_CTRL_PKT_BUF_ACCESS_HB0 0x60 /* Control packet data buffer access window - HB0 */
95 #define HDMI_CTRL_PKT_BUF_ACCESS_HB1 0x61 /* Control packet data buffer access window - HB1 */
96 #define HDMI_CTRL_PKT_BUF_ACCESS_HB2 0x62 /* Control packet data buffer access window - HB2 */
97 #define HDMI_CTRL_PKT_BUF_ACCESS_PB0 0x63 /* Control packet data buffer access window - PB0 */
98 #define HDMI_CTRL_PKT_BUF_ACCESS_PB1 0x64 /* Control packet data buffer access window - PB1 */
99 #define HDMI_CTRL_PKT_BUF_ACCESS_PB2 0x65 /* Control packet data buffer access window - PB2 */
100 #define HDMI_CTRL_PKT_BUF_ACCESS_PB3 0x66 /* Control packet data buffer access window - PB3 */
101 #define HDMI_CTRL_PKT_BUF_ACCESS_PB4 0x67 /* Control packet data buffer access window - PB4 */
102 #define HDMI_CTRL_PKT_BUF_ACCESS_PB5 0x68 /* Control packet data buffer access window - PB5 */
103 #define HDMI_CTRL_PKT_BUF_ACCESS_PB6 0x69 /* Control packet data buffer access window - PB6 */
104 #define HDMI_CTRL_PKT_BUF_ACCESS_PB7 0x6A /* Control packet data buffer access window - PB7 */
105 #define HDMI_CTRL_PKT_BUF_ACCESS_PB8 0x6B /* Control packet data buffer access window - PB8 */
106 #define HDMI_CTRL_PKT_BUF_ACCESS_PB9 0x6C /* Control packet data buffer access window - PB9 */
107 #define HDMI_CTRL_PKT_BUF_ACCESS_PB10 0x6D /* Control packet data buffer access window - PB10 */
108 #define HDMI_CTRL_PKT_BUF_ACCESS_PB11 0x6E /* Control packet data buffer access window - PB11 */
109 #define HDMI_CTRL_PKT_BUF_ACCESS_PB12 0x6F /* Control packet data buffer access window - PB12 */
110 #define HDMI_CTRL_PKT_BUF_ACCESS_PB13 0x70 /* Control packet data buffer access window - PB13 */
111 #define HDMI_CTRL_PKT_BUF_ACCESS_PB14 0x71 /* Control packet data buffer access window - PB14 */
112 #define HDMI_CTRL_PKT_BUF_ACCESS_PB15 0x72 /* Control packet data buffer access window - PB15 */
113 #define HDMI_CTRL_PKT_BUF_ACCESS_PB16 0x73 /* Control packet data buffer access window - PB16 */
114 #define HDMI_CTRL_PKT_BUF_ACCESS_PB17 0x74 /* Control packet data buffer access window - PB17 */
115 #define HDMI_CTRL_PKT_BUF_ACCESS_PB18 0x75 /* Control packet data buffer access window - PB18 */
116 #define HDMI_CTRL_PKT_BUF_ACCESS_PB19 0x76 /* Control packet data buffer access window - PB19 */
117 #define HDMI_CTRL_PKT_BUF_ACCESS_PB20 0x77 /* Control packet data buffer access window - PB20 */
118 #define HDMI_CTRL_PKT_BUF_ACCESS_PB21 0x78 /* Control packet data buffer access window - PB21 */
119 #define HDMI_CTRL_PKT_BUF_ACCESS_PB22 0x79 /* Control packet data buffer access window - PB22 */
120 #define HDMI_CTRL_PKT_BUF_ACCESS_PB23 0x7A /* Control packet data buffer access window - PB23 */
121 #define HDMI_CTRL_PKT_BUF_ACCESS_PB24 0x7B /* Control packet data buffer access window - PB24 */
122 #define HDMI_CTRL_PKT_BUF_ACCESS_PB25 0x7C /* Control packet data buffer access window - PB25 */
123 #define HDMI_CTRL_PKT_BUF_ACCESS_PB26 0x7D /* Control packet data buffer access window - PB26 */
124 #define HDMI_CTRL_PKT_BUF_ACCESS_PB27 0x7E /* Control packet data buffer access window - PB27 */
125 #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW 0x80 /* EDID/KSV FIFO access window */
126 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0 0x81 /* DDC bus access frequency control (LSB) */
127 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8 0x82 /* DDC bus access frequency control (MSB) */
128 #define HDMI_INTERRUPT_MASK_1 0x92 /* Interrupt mask.1 */
129 #define HDMI_INTERRUPT_MASK_2 0x93 /* Interrupt mask.2 */
130 #define HDMI_INTERRUPT_STATUS_1 0x94 /* Interrupt status.1 */
131 #define HDMI_INTERRUPT_STATUS_2 0x95 /* Interrupt status.2 */
132 #define HDMI_INTERRUPT_MASK_3 0x96 /* Interrupt mask.3 */
133 #define HDMI_INTERRUPT_MASK_4 0x97 /* Interrupt mask.4 */
134 #define HDMI_INTERRUPT_STATUS_3 0x98 /* Interrupt status.3 */
135 #define HDMI_INTERRUPT_STATUS_4 0x99 /* Interrupt status.4 */
136 #define HDMI_SOFTWARE_HDCP_CONTROL_1 0x9A /* Software HDCP control.1 */
137 #define HDMI_FRAME_COUNTER 0x9C /* Frame counter */
138 #define HDMI_FRAME_COUNTER_FOR_RI_CHECK 0x9D /* Frame counter for Ri check */
139 #define HDMI_HDCP_CONTROL 0xAF /* HDCP control */
140 #define HDMI_RI_FRAME_COUNT_REGISTER 0xB2 /* Ri frame count register */
141 #define HDMI_DDC_BUS_CONTROL 0xB7 /* DDC bus control */
142 #define HDMI_HDCP_STATUS 0xB8 /* HDCP status */
143 #define HDMI_SHA0 0xB9 /* sha0 */
144 #define HDMI_SHA1 0xBA /* sha1 */
145 #define HDMI_SHA2 0xBB /* sha2 */
146 #define HDMI_SHA3 0xBC /* sha3 */
147 #define HDMI_SHA4 0xBD /* sha4 */
148 #define HDMI_BCAPS_READ 0xBE /* BCAPS read / debug */
149 #define HDMI_AKSV_BKSV_7_0_MONITOR 0xBF /* AKSV/BKSV[7:0] monitor */
150 #define HDMI_AKSV_BKSV_15_8_MONITOR 0xC0 /* AKSV/BKSV[15:8] monitor */
151 #define HDMI_AKSV_BKSV_23_16_MONITOR 0xC1 /* AKSV/BKSV[23:16] monitor */
152 #define HDMI_AKSV_BKSV_31_24_MONITOR 0xC2 /* AKSV/BKSV[31:24] monitor */
153 #define HDMI_AKSV_BKSV_39_32_MONITOR 0xC3 /* AKSV/BKSV[39:32] monitor */
154 #define HDMI_EDID_SEGMENT_POINTER 0xC4 /* EDID segment pointer */
155 #define HDMI_EDID_WORD_ADDRESS 0xC5 /* EDID word address */
156 #define HDMI_EDID_DATA_FIFO_ADDRESS 0xC6 /* EDID data FIFO address */
157 #define HDMI_NUM_OF_HDMI_DEVICES 0xC7 /* Number of HDMI devices */
158 #define HDMI_HDCP_ERROR_CODE 0xC8 /* HDCP error code */
159 #define HDMI_100MS_TIMER_SET 0xC9 /* 100ms timer setting */
160 #define HDMI_5SEC_TIMER_SET 0xCA /* 5sec timer setting */
161 #define HDMI_RI_READ_COUNT 0xCB /* Ri read count */
162 #define HDMI_AN_SEED 0xCC /* An seed */
163 #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED 0xCD /* Maximum number of receivers allowed */
164 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1 0xCE /* HDCP memory access control.1 */
165 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2 0xCF /* HDCP memory access control.2 */
166 #define HDMI_HDCP_CONTROL_2 0xD0 /* HDCP Control 2 */
167 #define HDMI_HDCP_KEY_MEMORY_CONTROL 0xD2 /* HDCP Key Memory Control */
168 #define HDMI_COLOR_SPACE_CONV_CONFIG_1 0xD3 /* Color space conversion configuration.1 */
169 #define HDMI_VIDEO_SETTING_3 0xD4 /* Video setting.3 */
170 #define HDMI_RI_7_0 0xD5 /* Ri[7:0] */
171 #define HDMI_RI_15_8 0xD6 /* Ri[15:8] */
172 #define HDMI_PJ 0xD7 /* Pj */
173 #define HDMI_SHA_RD 0xD8 /* sha_rd */
174 #define HDMI_RI_7_0_SAVED 0xD9 /* Ri[7:0] saved */
175 #define HDMI_RI_15_8_SAVED 0xDA /* Ri[15:8] saved */
176 #define HDMI_PJ_SAVED 0xDB /* Pj saved */
177 #define HDMI_NUM_OF_DEVICES 0xDC /* Number of devices */
178 #define HDMI_HOT_PLUG_MSENS_STATUS 0xDF /* Hot plug/MSENS status */
179 #define HDMI_BCAPS_WRITE 0xE0 /* bcaps */
180 #define HDMI_BSTAT_7_0 0xE1 /* bstat[7:0] */
181 #define HDMI_BSTAT_15_8 0xE2 /* bstat[15:8] */
182 #define HDMI_BKSV_7_0 0xE3 /* bksv[7:0] */
183 #define HDMI_BKSV_15_8 0xE4 /* bksv[15:8] */
184 #define HDMI_BKSV_23_16 0xE5 /* bksv[23:16] */
185 #define HDMI_BKSV_31_24 0xE6 /* bksv[31:24] */
186 #define HDMI_BKSV_39_32 0xE7 /* bksv[39:32] */
187 #define HDMI_AN_7_0 0xE8 /* An[7:0] */
188 #define HDMI_AN_15_8 0xE9 /* An [15:8] */
189 #define HDMI_AN_23_16 0xEA /* An [23:16] */
190 #define HDMI_AN_31_24 0xEB /* An [31:24] */
191 #define HDMI_AN_39_32 0xEC /* An [39:32] */
192 #define HDMI_AN_47_40 0xED /* An [47:40] */
193 #define HDMI_AN_55_48 0xEE /* An [55:48] */
194 #define HDMI_AN_63_56 0xEF /* An [63:56] */
195 #define HDMI_PRODUCT_ID 0xF0 /* Product ID */
196 #define HDMI_REVISION_ID 0xF1 /* Revision ID */
197 #define HDMI_TEST_MODE 0xFE /* Test mode */
198
199 enum hotplug_state {
200 HDMI_HOTPLUG_DISCONNECTED,
201 HDMI_HOTPLUG_CONNECTED,
202 HDMI_HOTPLUG_EDID_DONE,
203 };
204
205 struct sh_hdmi {
206 void __iomem *base;
207 enum hotplug_state hp_state;
208 struct clk *hdmi_clk;
209 struct device *dev;
210 struct fb_info *info;
211 struct delayed_work edid_work;
212 struct fb_var_screeninfo var;
213 };
214
215 static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
216 {
217 iowrite8(data, hdmi->base + reg);
218 }
219
220 static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
221 {
222 return ioread8(hdmi->base + reg);
223 }
224
225 /* External video parameter settings */
226 static void hdmi_external_video_param(struct sh_hdmi *hdmi)
227 {
228 struct fb_var_screeninfo *var = &hdmi->var;
229 u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
230 u8 sync = 0;
231
232 htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
233
234 hdelay = var->hsync_len + var->left_margin;
235 hblank = var->right_margin + hdelay;
236
237 /*
238 * Vertical timing looks a bit different in Figure 18,
239 * but let's try the same first by setting offset = 0
240 */
241 vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
242
243 vdelay = var->vsync_len + var->upper_margin;
244 vblank = var->lower_margin + vdelay;
245 voffset = min(var->upper_margin / 2, 6U);
246
247 /*
248 * [3]: VSYNC polarity: Positive
249 * [2]: HSYNC polarity: Positive
250 * [1]: Interlace/Progressive: Progressive
251 * [0]: External video settings enable: used.
252 */
253 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
254 sync |= 4;
255 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
256 sync |= 8;
257
258 pr_debug("H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
259 htotal, hblank, hdelay, var->hsync_len,
260 vtotal, vblank, vdelay, var->vsync_len, sync);
261
262 hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
263
264 hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
265 hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
266
267 hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
268 hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
269
270 hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
271 hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
272
273 hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
274 hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
275
276 hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
277 hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
278
279 hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
280
281 hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
282
283 hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
284
285 /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for manual mode */
286 }
287
288 /**
289 * sh_hdmi_video_config()
290 */
291 static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
292 {
293 /*
294 * [7:4]: Audio sampling frequency: 48kHz
295 * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
296 * [0]: Internal/External DE select: internal
297 */
298 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
299
300 /*
301 * [7:6]: Video output format: RGB 4:4:4
302 * [5:4]: Input video data width: 8 bit
303 * [3:1]: EAV/SAV location: channel 1
304 * [0]: Video input color space: RGB
305 */
306 hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
307
308 /*
309 * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
310 * left at 0 by default, this configures 24bpp and sets the Color Depth
311 * (CD) field in the General Control Packet
312 */
313 hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
314 }
315
316 /**
317 * sh_hdmi_audio_config()
318 */
319 static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
320 {
321 /*
322 * [7:4] L/R data swap control
323 * [3:0] appropriate N[19:16]
324 */
325 hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
326 /* appropriate N[15:8] */
327 hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
328 /* appropriate N[7:0] */
329 hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
330
331 /* [7:4] 48 kHz SPDIF not used */
332 hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
333
334 /*
335 * [6:5] set required down sampling rate if required
336 * [4:3] set required audio source
337 */
338 hdmi_write(hdmi, 0x00, HDMI_AUDIO_SETTING_1);
339
340 /* [3:0] set sending channel number for channel status */
341 hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
342
343 /*
344 * [5:2] set valid I2S source input pin
345 * [1:0] set input I2S source mode
346 */
347 hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
348
349 /* [7:4] set valid DSD source input pin */
350 hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
351
352 /* [7:0] set appropriate I2S input pin swap settings if required */
353 hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
354
355 /*
356 * [7] set validity bit for channel status
357 * [3:0] set original sample frequency for channel status
358 */
359 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
360
361 /*
362 * [7] set value for channel status
363 * [6] set value for channel status
364 * [5] set copyright bit for channel status
365 * [4:2] set additional information for channel status
366 * [1:0] set clock accuracy for channel status
367 */
368 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
369
370 /* [7:0] set category code for channel status */
371 hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
372
373 /*
374 * [7:4] set source number for channel status
375 * [3:0] set word length for channel status
376 */
377 hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
378
379 /* [7:4] set sample frequency for channel status */
380 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
381 }
382
383 /**
384 * sh_hdmi_phy_config()
385 */
386 static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
387 {
388 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
389 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
390 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
391 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
392 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
393 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
394 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
395 hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
396 hdmi_write(hdmi, 0x0E, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
397 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
398 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
399 }
400
401 /**
402 * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
403 */
404 static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
405 {
406 /* AVI InfoFrame */
407 hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
408
409 /* Packet Type = 0x82 */
410 hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
411
412 /* Version = 0x02 */
413 hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
414
415 /* Length = 13 (0x0D) */
416 hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
417
418 /* N. A. Checksum */
419 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
420
421 /*
422 * Y = RGB
423 * A0 = No Data
424 * B = Bar Data not valid
425 * S = No Data
426 */
427 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
428
429 /*
430 * C = No Data
431 * M = 16:9 Picture Aspect Ratio
432 * R = Same as picture aspect ratio
433 */
434 hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
435
436 /*
437 * ITC = No Data
438 * EC = xvYCC601
439 * Q = Default (depends on video format)
440 * SC = No Known non_uniform Scaling
441 */
442 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
443
444 /*
445 * VIC = 1280 x 720p: ignored if external config is used
446 * Send 2 for 720 x 480p, 16 for 1080p
447 */
448 hdmi_write(hdmi, 4, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
449
450 /* PR = No Repetition */
451 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
452
453 /* Line Number of End of Top Bar (lower 8 bits) */
454 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
455
456 /* Line Number of End of Top Bar (upper 8 bits) */
457 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
458
459 /* Line Number of Start of Bottom Bar (lower 8 bits) */
460 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
461
462 /* Line Number of Start of Bottom Bar (upper 8 bits) */
463 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
464
465 /* Pixel Number of End of Left Bar (lower 8 bits) */
466 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
467
468 /* Pixel Number of End of Left Bar (upper 8 bits) */
469 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
470
471 /* Pixel Number of Start of Right Bar (lower 8 bits) */
472 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
473
474 /* Pixel Number of Start of Right Bar (upper 8 bits) */
475 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
476 }
477
478 /**
479 * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
480 */
481 static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
482 {
483 /* Audio InfoFrame */
484 hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
485
486 /* Packet Type = 0x84 */
487 hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
488
489 /* Version Number = 0x01 */
490 hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
491
492 /* 0 Length = 10 (0x0A) */
493 hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
494
495 /* n. a. Checksum */
496 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
497
498 /* Audio Channel Count = Refer to Stream Header */
499 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
500
501 /* Refer to Stream Header */
502 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
503
504 /* Format depends on coding type (i.e. CT0...CT3) */
505 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
506
507 /* Speaker Channel Allocation = Front Right + Front Left */
508 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
509
510 /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
511 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
512
513 /* Reserved (0) */
514 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
515 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
516 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
517 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
518 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
519 }
520
521 /**
522 * sh_hdmi_gamut_metadata_setup() - Gamut Metadata Packet of CONTROL PACKET
523 */
524 static void sh_hdmi_gamut_metadata_setup(struct sh_hdmi *hdmi)
525 {
526 int i;
527
528 /* Gamut Metadata Packet */
529 hdmi_write(hdmi, 0x04, HDMI_CTRL_PKT_BUF_INDEX);
530
531 /* Packet Type = 0x0A */
532 hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
533 /* Gamut Packet is not used, so default value */
534 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
535 /* Gamut Packet is not used, so default value */
536 hdmi_write(hdmi, 0x10, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
537
538 /* GBD bytes 0 through 27 */
539 for (i = 0; i <= 27; i++)
540 /* HDMI_CTRL_PKT_BUF_ACCESS_PB0_63H - PB27_7EH */
541 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
542 }
543
544 /**
545 * sh_hdmi_acp_setup() - Audio Content Protection Packet (ACP)
546 */
547 static void sh_hdmi_acp_setup(struct sh_hdmi *hdmi)
548 {
549 int i;
550
551 /* Audio Content Protection Packet (ACP) */
552 hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_INDEX);
553
554 /* Packet Type = 0x04 */
555 hdmi_write(hdmi, 0x04, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
556 /* ACP_Type */
557 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
558 /* Reserved (0) */
559 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
560
561 /* GBD bytes 0 through 27 */
562 for (i = 0; i <= 27; i++)
563 /* HDMI_CTRL_PKT_BUF_ACCESS_PB0 - PB27 */
564 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
565 }
566
567 /**
568 * sh_hdmi_isrc1_setup() - ISRC1 Packet
569 */
570 static void sh_hdmi_isrc1_setup(struct sh_hdmi *hdmi)
571 {
572 int i;
573
574 /* ISRC1 Packet */
575 hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_INDEX);
576
577 /* Packet Type = 0x05 */
578 hdmi_write(hdmi, 0x05, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
579 /* ISRC_Cont, ISRC_Valid, Reserved (0), ISRC_Status */
580 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
581 /* Reserved (0) */
582 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
583
584 /* PB0 UPC_EAN_ISRC_0-15 */
585 /* Bytes PB16-PB27 shall be set to a value of 0. */
586 for (i = 0; i <= 27; i++)
587 /* HDMI_CTRL_PKT_BUF_ACCESS_PB0 - PB27 */
588 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
589 }
590
591 /**
592 * sh_hdmi_isrc2_setup() - ISRC2 Packet
593 */
594 static void sh_hdmi_isrc2_setup(struct sh_hdmi *hdmi)
595 {
596 int i;
597
598 /* ISRC2 Packet */
599 hdmi_write(hdmi, 0x03, HDMI_CTRL_PKT_BUF_INDEX);
600
601 /* HB0 Packet Type = 0x06 */
602 hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
603 /* Reserved (0) */
604 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
605 /* Reserved (0) */
606 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
607
608 /* PB0 UPC_EAN_ISRC_16-31 */
609 /* Bytes PB16-PB27 shall be set to a value of 0. */
610 for (i = 0; i <= 27; i++)
611 /* HDMI_CTRL_PKT_BUF_ACCESS_PB0 - PB27 */
612 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
613 }
614
615 /**
616 * sh_hdmi_configure() - Initialise HDMI for output
617 */
618 static void sh_hdmi_configure(struct sh_hdmi *hdmi)
619 {
620 /* Configure video format */
621 sh_hdmi_video_config(hdmi);
622
623 /* Configure audio format */
624 sh_hdmi_audio_config(hdmi);
625
626 /* Configure PHY */
627 sh_hdmi_phy_config(hdmi);
628
629 /* Auxiliary Video Information (AVI) InfoFrame */
630 sh_hdmi_avi_infoframe_setup(hdmi);
631
632 /* Audio InfoFrame */
633 sh_hdmi_audio_infoframe_setup(hdmi);
634
635 /* Gamut Metadata packet */
636 sh_hdmi_gamut_metadata_setup(hdmi);
637
638 /* Audio Content Protection (ACP) Packet */
639 sh_hdmi_acp_setup(hdmi);
640
641 /* ISRC1 Packet */
642 sh_hdmi_isrc1_setup(hdmi);
643
644 /* ISRC2 Packet */
645 sh_hdmi_isrc2_setup(hdmi);
646
647 /*
648 * Control packet auto send with VSYNC control: auto send
649 * General control, Gamut metadata, ISRC, and ACP packets
650 */
651 hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
652
653 msleep(10);
654
655 /* PS mode b->d, reset PLLA and PLLB */
656 hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
657
658 udelay(10);
659
660 hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
661 }
662
663 static void sh_hdmi_read_edid(struct sh_hdmi *hdmi)
664 {
665 struct fb_var_screeninfo *var = &hdmi->var;
666 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
667 struct fb_videomode *lcd_cfg = &pdata->lcd_chan->lcd_cfg;
668 unsigned long height = var->height, width = var->width;
669 int i;
670 u8 edid[128];
671
672 /* Read EDID */
673 pr_debug("Read back EDID code:");
674 for (i = 0; i < 128; i++) {
675 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
676 #ifdef DEBUG
677 if ((i % 16) == 0) {
678 printk(KERN_CONT "\n");
679 printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
680 } else {
681 printk(KERN_CONT " %02X", edid[i]);
682 }
683 #endif
684 }
685 #ifdef DEBUG
686 printk(KERN_CONT "\n");
687 #endif
688 fb_parse_edid(edid, var);
689 pr_debug("%u-%u-%u-%u x %u-%u-%u-%u @ %lu kHz monitor detected\n",
690 var->left_margin, var->xres, var->right_margin, var->hsync_len,
691 var->upper_margin, var->yres, var->lower_margin, var->vsync_len,
692 PICOS2KHZ(var->pixclock));
693
694 var->width = width;
695 var->xres = lcd_cfg->xres;
696 var->xres_virtual = lcd_cfg->xres;
697 var->left_margin = lcd_cfg->left_margin;
698 var->right_margin = lcd_cfg->right_margin;
699 var->hsync_len = lcd_cfg->hsync_len;
700 var->height = height;
701 var->yres = lcd_cfg->yres;
702 var->yres_virtual = lcd_cfg->yres * 2;
703 var->upper_margin = lcd_cfg->upper_margin;
704 var->lower_margin = lcd_cfg->lower_margin;
705 var->vsync_len = lcd_cfg->vsync_len;
706 var->sync = lcd_cfg->sync;
707 var->pixclock = lcd_cfg->pixclock;
708
709 hdmi_external_video_param(hdmi);
710 }
711
712 static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
713 {
714 struct sh_hdmi *hdmi = dev_id;
715 u8 status1, status2, mask1, mask2;
716
717 /* mode_b and PLLA and PLLB reset */
718 hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
719
720 /* How long shall reset be held? */
721 udelay(10);
722
723 /* mode_b and PLLA and PLLB reset release */
724 hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
725
726 status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
727 status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
728
729 mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
730 mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
731
732 /* Correct would be to ack only set bits, but the datasheet requires 0xff */
733 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
734 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
735
736 if (printk_ratelimit())
737 pr_debug("IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
738 irq, status1, mask1, status2, mask2);
739
740 if (!((status1 & mask1) | (status2 & mask2))) {
741 return IRQ_NONE;
742 } else if (status1 & 0xc0) {
743 u8 msens;
744
745 /* Datasheet specifies 10ms... */
746 udelay(500);
747
748 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
749 pr_debug("MSENS 0x%x\n", msens);
750 /* Check, if hot plug & MSENS pin status are both high */
751 if ((msens & 0xC0) == 0xC0) {
752 /* Display plug in */
753 hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
754
755 /* Set EDID word address */
756 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
757 /* Set EDID segment pointer */
758 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
759 /* Enable EDID interrupt */
760 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
761 } else if (!(status1 & 0x80)) {
762 /* Display unplug, beware multiple interrupts */
763 if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED)
764 schedule_delayed_work(&hdmi->edid_work, 0);
765
766 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
767 /* display_off will switch back to mode_a */
768 }
769 } else if (status1 & 2) {
770 /* EDID error interrupt: retry */
771 /* Set EDID word address */
772 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
773 /* Set EDID segment pointer */
774 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
775 } else if (status1 & 4) {
776 /* Disable EDID interrupt */
777 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
778 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
779 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
780 }
781
782 return IRQ_HANDLED;
783 }
784
785 static void hdmi_display_on(void *arg, struct fb_info *info)
786 {
787 struct sh_hdmi *hdmi = arg;
788 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
789
790 if (info->var.xres != 1280 || info->var.yres != 720) {
791 dev_warn(info->device, "Unsupported framebuffer geometry %ux%u\n",
792 info->var.xres, info->var.yres);
793 return;
794 }
795
796 pr_debug("%s(%p): state %x\n", __func__, pdata->lcd_dev, info->state);
797 hdmi->info = info;
798 switch (hdmi->hp_state) {
799 case HDMI_HOTPLUG_EDID_DONE:
800 /* PS mode d->e. All functions are active */
801 hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
802 pr_debug("HDMI running\n");
803 break;
804 case HDMI_HOTPLUG_DISCONNECTED:
805 info->state = FBINFO_STATE_SUSPENDED;
806 default:
807 hdmi->var = info->var;
808 }
809 }
810
811 static void hdmi_display_off(void *arg)
812 {
813 struct sh_hdmi *hdmi = arg;
814 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
815
816 pr_debug("%s(%p)\n", __func__, pdata->lcd_dev);
817 /* PS mode e->a */
818 hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
819 }
820
821 /* Hotplug interrupt occurred, read EDID */
822 static void edid_work_fn(struct work_struct *work)
823 {
824 struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
825 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
826
827 pr_debug("%s(%p): begin, hotplug status %d\n", __func__,
828 pdata->lcd_dev, hdmi->hp_state);
829
830 if (!pdata->lcd_dev)
831 return;
832
833 if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) {
834 pm_runtime_get_sync(hdmi->dev);
835 /* A device has been plugged in */
836 sh_hdmi_read_edid(hdmi);
837 msleep(10);
838 sh_hdmi_configure(hdmi);
839 /* Switched to another (d) power-save mode */
840 msleep(10);
841
842 if (!hdmi->info)
843 return;
844
845 acquire_console_sem();
846
847 /* HDMI plug in */
848 hdmi->info->var = hdmi->var;
849 if (hdmi->info->state != FBINFO_STATE_RUNNING)
850 fb_set_suspend(hdmi->info, 0);
851 else
852 hdmi_display_on(hdmi, hdmi->info);
853
854 release_console_sem();
855 } else {
856 if (!hdmi->info)
857 return;
858
859 acquire_console_sem();
860
861 /* HDMI disconnect */
862 fb_set_suspend(hdmi->info, 1);
863
864 release_console_sem();
865 pm_runtime_put(hdmi->dev);
866 }
867
868 pr_debug("%s(%p): end\n", __func__, pdata->lcd_dev);
869 }
870
871 static int __init sh_hdmi_probe(struct platform_device *pdev)
872 {
873 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
874 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
875 int irq = platform_get_irq(pdev, 0), ret;
876 struct sh_hdmi *hdmi;
877 long rate;
878
879 if (!res || !pdata || irq < 0)
880 return -ENODEV;
881
882 hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
883 if (!hdmi) {
884 dev_err(&pdev->dev, "Cannot allocate device data\n");
885 return -ENOMEM;
886 }
887
888 hdmi->dev = &pdev->dev;
889
890 hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
891 if (IS_ERR(hdmi->hdmi_clk)) {
892 ret = PTR_ERR(hdmi->hdmi_clk);
893 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
894 goto egetclk;
895 }
896
897 rate = PICOS2KHZ(pdata->lcd_chan->lcd_cfg.pixclock) * 1000;
898
899 rate = clk_round_rate(hdmi->hdmi_clk, rate);
900 if (rate < 0) {
901 ret = rate;
902 dev_err(&pdev->dev, "Cannot get suitable rate: %ld\n", rate);
903 goto erate;
904 }
905
906 ret = clk_set_rate(hdmi->hdmi_clk, rate);
907 if (ret < 0) {
908 dev_err(&pdev->dev, "Cannot set rate %ld: %d\n", rate, ret);
909 goto erate;
910 }
911
912 pr_debug("HDMI set frequency %lu\n", rate);
913
914 ret = clk_enable(hdmi->hdmi_clk);
915 if (ret < 0) {
916 dev_err(&pdev->dev, "Cannot enable clock: %d\n", ret);
917 goto eclkenable;
918 }
919
920 dev_info(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
921
922 if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
923 dev_err(&pdev->dev, "HDMI register region already claimed\n");
924 ret = -EBUSY;
925 goto ereqreg;
926 }
927
928 hdmi->base = ioremap(res->start, resource_size(res));
929 if (!hdmi->base) {
930 dev_err(&pdev->dev, "HDMI register region already claimed\n");
931 ret = -ENOMEM;
932 goto emap;
933 }
934
935 platform_set_drvdata(pdev, hdmi);
936
937 /* Product and revision IDs are 0 in sh-mobile version */
938 dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
939 hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
940
941 /* Set up LCDC callbacks */
942 pdata->lcd_chan->board_cfg.board_data = hdmi;
943 pdata->lcd_chan->board_cfg.display_on = hdmi_display_on;
944 pdata->lcd_chan->board_cfg.display_off = hdmi_display_off;
945
946 INIT_DELAYED_WORK(&hdmi->edid_work, edid_work_fn);
947
948 pm_runtime_enable(&pdev->dev);
949 pm_runtime_resume(&pdev->dev);
950
951 ret = request_irq(irq, sh_hdmi_hotplug, 0,
952 dev_name(&pdev->dev), hdmi);
953 if (ret < 0) {
954 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
955 goto ereqirq;
956 }
957
958 return 0;
959
960 ereqirq:
961 pm_runtime_disable(&pdev->dev);
962 iounmap(hdmi->base);
963 emap:
964 release_mem_region(res->start, resource_size(res));
965 ereqreg:
966 clk_disable(hdmi->hdmi_clk);
967 eclkenable:
968 erate:
969 clk_put(hdmi->hdmi_clk);
970 egetclk:
971 kfree(hdmi);
972
973 return ret;
974 }
975
976 static int __exit sh_hdmi_remove(struct platform_device *pdev)
977 {
978 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
979 struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
980 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
981 int irq = platform_get_irq(pdev, 0);
982
983 pdata->lcd_chan->board_cfg.display_on = NULL;
984 pdata->lcd_chan->board_cfg.display_off = NULL;
985 pdata->lcd_chan->board_cfg.board_data = NULL;
986
987 free_irq(irq, hdmi);
988 pm_runtime_disable(&pdev->dev);
989 cancel_delayed_work_sync(&hdmi->edid_work);
990 clk_disable(hdmi->hdmi_clk);
991 clk_put(hdmi->hdmi_clk);
992 iounmap(hdmi->base);
993 release_mem_region(res->start, resource_size(res));
994 kfree(hdmi);
995
996 return 0;
997 }
998
999 static struct platform_driver sh_hdmi_driver = {
1000 .remove = __exit_p(sh_hdmi_remove),
1001 .driver = {
1002 .name = "sh-mobile-hdmi",
1003 },
1004 };
1005
1006 static int __init sh_hdmi_init(void)
1007 {
1008 return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
1009 }
1010 module_init(sh_hdmi_init);
1011
1012 static void __exit sh_hdmi_exit(void)
1013 {
1014 platform_driver_unregister(&sh_hdmi_driver);
1015 }
1016 module_exit(sh_hdmi_exit);
1017
1018 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1019 MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1020 MODULE_LICENSE("GPL v2");
Tomato firmware and modifications.