release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/usb/gadget/amd5536udc.c

   1 /*
   2  * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
   3  *
   4  * Copyright (C) 2005-2007 AMD (http://www.amd.com)
   5  * Author: Thomas Dahlmann
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 /*
  23  * The AMD5536 UDC is part of the x86 southbridge AMD Geode CS5536.
  24  * It is a USB Highspeed DMA capable USB device controller. Beside ep0 it
  25  * provides 4 IN and 4 OUT endpoints (bulk or interrupt type).
  26  *
  27  * Make sure that UDC is assigned to port 4 by BIOS settings (port can also
  28  * be used as host port) and UOC bits PAD_EN and APU are set (should be done
  29  * by BIOS init).
  30  *
  31  * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
  32  * work without updating NET_IP_ALIGN. Or PIO mode (module param "use_dma=0")
  33  * can be used with gadget ether.
  34  */
  35
  36 /* debug control */
  37 /* #define UDC_VERBOSE */
  38
  39 /* Driver strings */
  40 #define UDC_MOD_DESCRIPTION             "AMD 5536 UDC - USB Device Controller"
  41 #define UDC_DRIVER_VERSION_STRING       "01.00.0206 - $Revision: #3 $"
  42
  43 /* system */
  44 #include <linux/module.h>
  45 #include <linux/pci.h>
  46 #include <linux/kernel.h>
  47 #include <linux/delay.h>
  48 #include <linux/ioport.h>
  49 #include <linux/sched.h>
  50 #include <linux/slab.h>
  51 #include <linux/errno.h>
  52 #include <linux/init.h>
  53 #include <linux/timer.h>
  54 #include <linux/list.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/ioctl.h>
  57 #include <linux/fs.h>
  58 #include <linux/dmapool.h>
  59 #include <linux/moduleparam.h>
  60 #include <linux/device.h>
  61 #include <linux/io.h>
  62 #include <linux/irq.h>
  63
  64 #include <asm/byteorder.h>
  65 #include <asm/system.h>
  66 #include <asm/unaligned.h>
  67
  68 /* gadget stack */
  69 #include <linux/usb/ch9.h>
  70 #include <linux/usb/gadget.h>
  71
  72 /* udc specific */
  73 #include "amd5536udc.h"
  74
  75
  76 static void udc_tasklet_disconnect(unsigned long);
  77 static void empty_req_queue(struct udc_ep *);
  78 static int udc_probe(struct udc *dev);
  79 static void udc_basic_init(struct udc *dev);
  80 static void udc_setup_endpoints(struct udc *dev);
  81 static void udc_soft_reset(struct udc *dev);
  82 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep);
  83 static void udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq);
  84 static int udc_free_dma_chain(struct udc *dev, struct udc_request *req);
  85 static int udc_create_dma_chain(struct udc_ep *ep, struct udc_request *req,
  86                                 unsigned long buf_len, gfp_t gfp_flags);
  87 static int udc_remote_wakeup(struct udc *dev);
  88 static int udc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
  89 static void udc_pci_remove(struct pci_dev *pdev);
  90
  91 /* description */
  92 static const char mod_desc[] = UDC_MOD_DESCRIPTION;
  93 static const char name[] = "amd5536udc";
  94
  95 /* structure to hold endpoint function pointers */
  96 static const struct usb_ep_ops udc_ep_ops;
  97
  98 /* received setup data */
  99 static union udc_setup_data setup_data;
 100
 101 /* pointer to device object */
 102 static struct udc *udc;
 103
 104 /* irq spin lock for soft reset */
 105 static DEFINE_SPINLOCK(udc_irq_spinlock);
 106 /* stall spin lock */
 107 static DEFINE_SPINLOCK(udc_stall_spinlock);
 108
 109 /*
 110 * slave mode: pending bytes in rx fifo after nyet,
 111 * used if EPIN irq came but no req was available
 112 */
 113 static unsigned int udc_rxfifo_pending;
 114
 115 /* count soft resets after suspend to avoid loop */
 116 static int soft_reset_occured;
 117 static int soft_reset_after_usbreset_occured;
 118
 119 /* timer */
 120 static struct timer_list udc_timer;
 121 static int stop_timer;
 122
 123 /* set_rde -- Is used to control enabling of RX DMA. Problem is
 124  * that UDC has only one bit (RDE) to enable/disable RX DMA for
 125  * all OUT endpoints. So we have to handle race conditions like
 126  * when OUT data reaches the fifo but no request was queued yet.
 127  * This cannot be solved by letting the RX DMA disabled until a
 128  * request gets queued because there may be other OUT packets
 129  * in the FIFO (important for not blocking control traffic).
 130  * The value of set_rde controls the correspondig timer.
 131  *
 132  * set_rde -1 == not used, means it is alloed to be set to 0 or 1
 133  * set_rde  0 == do not touch RDE, do no start the RDE timer
 134  * set_rde  1 == timer function will look whether FIFO has data
 135  * set_rde  2 == set by timer function to enable RX DMA on next call
 136  */
 137 static int set_rde = -1;
 138
 139 static DECLARE_COMPLETION(on_exit);
 140 static struct timer_list udc_pollstall_timer;
 141 static int stop_pollstall_timer;
 142 static DECLARE_COMPLETION(on_pollstall_exit);
 143
 144 /* tasklet for usb disconnect */
 145 static DECLARE_TASKLET(disconnect_tasklet, udc_tasklet_disconnect,
 146                 (unsigned long) &udc);
 147
 148
 149 /* endpoint names used for print */
 150 static const char ep0_string[] = "ep0in";
 151 static const char *ep_string[] = {
 152         ep0_string,
 153         "ep1in-int", "ep2in-bulk", "ep3in-bulk", "ep4in-bulk", "ep5in-bulk",
 154         "ep6in-bulk", "ep7in-bulk", "ep8in-bulk", "ep9in-bulk", "ep10in-bulk",
 155         "ep11in-bulk", "ep12in-bulk", "ep13in-bulk", "ep14in-bulk",
 156         "ep15in-bulk", "ep0out", "ep1out-bulk", "ep2out-bulk", "ep3out-bulk",
 157         "ep4out-bulk", "ep5out-bulk", "ep6out-bulk", "ep7out-bulk",
 158         "ep8out-bulk", "ep9out-bulk", "ep10out-bulk", "ep11out-bulk",
 159         "ep12out-bulk", "ep13out-bulk", "ep14out-bulk", "ep15out-bulk"
 160 };
 161
 162 /* DMA usage flag */
 163 static int use_dma = 1;
 164 /* packet per buffer dma */
 165 static int use_dma_ppb = 1;
 166 /* with per descr. update */
 167 static int use_dma_ppb_du;
 168 /* buffer fill mode */
 169 static int use_dma_bufferfill_mode;
 170 /* full speed only mode */
 171 static int use_fullspeed;
 172 /* tx buffer size for high speed */
 173 static unsigned long hs_tx_buf = UDC_EPIN_BUFF_SIZE;
 174
 175 /* module parameters */
 176 module_param(use_dma, bool, S_IRUGO);
 177 MODULE_PARM_DESC(use_dma, "true for DMA");
 178 module_param(use_dma_ppb, bool, S_IRUGO);
 179 MODULE_PARM_DESC(use_dma_ppb, "true for DMA in packet per buffer mode");
 180 module_param(use_dma_ppb_du, bool, S_IRUGO);
 181 MODULE_PARM_DESC(use_dma_ppb_du,
 182         "true for DMA in packet per buffer mode with descriptor update");
 183 module_param(use_fullspeed, bool, S_IRUGO);
 184 MODULE_PARM_DESC(use_fullspeed, "true for fullspeed only");
 185
 186 /*---------------------------------------------------------------------------*/
 187 /* Prints UDC device registers and endpoint irq registers */
 188 static void print_regs(struct udc *dev)
 189 {
 190         DBG(dev, "------- Device registers -------\n");
 191         DBG(dev, "dev config     = %08x\n", readl(&dev->regs->cfg));
 192         DBG(dev, "dev control    = %08x\n", readl(&dev->regs->ctl));
 193         DBG(dev, "dev status     = %08x\n", readl(&dev->regs->sts));
 194         DBG(dev, "\n");
 195         DBG(dev, "dev int's      = %08x\n", readl(&dev->regs->irqsts));
 196         DBG(dev, "dev intmask    = %08x\n", readl(&dev->regs->irqmsk));
 197         DBG(dev, "\n");
 198         DBG(dev, "dev ep int's   = %08x\n", readl(&dev->regs->ep_irqsts));
 199         DBG(dev, "dev ep intmask = %08x\n", readl(&dev->regs->ep_irqmsk));
 200         DBG(dev, "\n");
 201         DBG(dev, "USE DMA        = %d\n", use_dma);
 202         if (use_dma && use_dma_ppb && !use_dma_ppb_du) {
 203                 DBG(dev, "DMA mode       = PPBNDU (packet per buffer "
 204                         "WITHOUT desc. update)\n");
 205                 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBNDU");
 206         } else if (use_dma && use_dma_ppb_du && use_dma_ppb_du) {
 207                 DBG(dev, "DMA mode       = PPBDU (packet per buffer "
 208                         "WITH desc. update)\n");
 209                 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBDU");
 210         }
 211         if (use_dma && use_dma_bufferfill_mode) {
 212                 DBG(dev, "DMA mode       = BF (buffer fill mode)\n");
 213                 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "BF");
 214         }
 215         if (!use_dma) {
 216                 dev_info(&dev->pdev->dev, "FIFO mode\n");
 217         }
 218         DBG(dev, "-------------------------------------------------------\n");
 219 }
 220
 221 /* Masks unused interrupts */
 222 static int udc_mask_unused_interrupts(struct udc *dev)
 223 {
 224         u32 tmp;
 225
 226         /* mask all dev interrupts */
 227         tmp =   AMD_BIT(UDC_DEVINT_SVC) |
 228                 AMD_BIT(UDC_DEVINT_ENUM) |
 229                 AMD_BIT(UDC_DEVINT_US) |
 230                 AMD_BIT(UDC_DEVINT_UR) |
 231                 AMD_BIT(UDC_DEVINT_ES) |
 232                 AMD_BIT(UDC_DEVINT_SI) |
 233                 AMD_BIT(UDC_DEVINT_SOF)|
 234                 AMD_BIT(UDC_DEVINT_SC);
 235         writel(tmp, &dev->regs->irqmsk);
 236
 237         /* mask all ep interrupts */
 238         writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk);
 239
 240         return 0;
 241 }
 242
 243 /* Enables endpoint 0 interrupts */
 244 static int udc_enable_ep0_interrupts(struct udc *dev)
 245 {
 246         u32 tmp;
 247
 248         DBG(dev, "udc_enable_ep0_interrupts()\n");
 249
 250         /* read irq mask */
 251         tmp = readl(&dev->regs->ep_irqmsk);
 252         /* enable ep0 irq's */
 253         tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0)
 254                 & AMD_UNMASK_BIT(UDC_EPINT_OUT_EP0);
 255         writel(tmp, &dev->regs->ep_irqmsk);
 256
 257         return 0;
 258 }
 259
 260 /* Enables device interrupts for SET_INTF and SET_CONFIG */
 261 static int udc_enable_dev_setup_interrupts(struct udc *dev)
 262 {
 263         u32 tmp;
 264
 265         DBG(dev, "enable device interrupts for setup data\n");
 266
 267         /* read irq mask */
 268         tmp = readl(&dev->regs->irqmsk);
 269
 270         /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
 271         tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI)
 272                 & AMD_UNMASK_BIT(UDC_DEVINT_SC)
 273                 & AMD_UNMASK_BIT(UDC_DEVINT_UR)
 274                 & AMD_UNMASK_BIT(UDC_DEVINT_SVC)
 275                 & AMD_UNMASK_BIT(UDC_DEVINT_ENUM);
 276         writel(tmp, &dev->regs->irqmsk);
 277
 278         return 0;
 279 }
 280
 281 /* Calculates fifo start of endpoint based on preceeding endpoints */
 282 static int udc_set_txfifo_addr(struct udc_ep *ep)
 283 {
 284         struct udc      *dev;
 285         u32 tmp;
 286         int i;
 287
 288         if (!ep || !(ep->in))
 289                 return -EINVAL;
 290
 291         dev = ep->dev;
 292         ep->txfifo = dev->txfifo;
 293
 294         /* traverse ep's */
 295         for (i = 0; i < ep->num; i++) {
 296                 if (dev->ep[i].regs) {
 297                         /* read fifo size */
 298                         tmp = readl(&dev->ep[i].regs->bufin_framenum);
 299                         tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE);
 300                         ep->txfifo += tmp;
 301                 }
 302         }
 303         return 0;
 304 }
 305
 306 /* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
 307 static u32 cnak_pending;
 308
 309 static void UDC_QUEUE_CNAK(struct udc_ep *ep, unsigned num)
 310 {
 311         if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) {
 312                 DBG(ep->dev, "NAK could not be cleared for ep%d\n", num);
 313                 cnak_pending |= 1 << (num);
 314                 ep->naking = 1;
 315         } else
 316                 cnak_pending = cnak_pending & (~(1 << (num)));
 317 }
 318
 319
 320 /* Enables endpoint, is called by gadget driver */
 321 static int
 322 udc_ep_enable(struct usb_ep *usbep, const struct usb_endpoint_descriptor *desc)
 323 {
 324         struct udc_ep           *ep;
 325         struct udc              *dev;
 326         u32                     tmp;
 327         unsigned long           iflags;
 328         u8 udc_csr_epix;
 329         unsigned                maxpacket;
 330
 331         if (!usbep
 332                         || usbep->name == ep0_string
 333                         || !desc
 334                         || desc->bDescriptorType != USB_DT_ENDPOINT)
 335                 return -EINVAL;
 336
 337         ep = container_of(usbep, struct udc_ep, ep);
 338         dev = ep->dev;
 339
 340         DBG(dev, "udc_ep_enable() ep %d\n", ep->num);
 341
 342         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
 343                 return -ESHUTDOWN;
 344
 345         spin_lock_irqsave(&dev->lock, iflags);
 346         ep->desc = desc;
 347
 348         ep->halted = 0;
 349
 350         /* set traffic type */
 351         tmp = readl(&dev->ep[ep->num].regs->ctl);
 352         tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET);
 353         writel(tmp, &dev->ep[ep->num].regs->ctl);
 354
 355         /* set max packet size */
 356         maxpacket = le16_to_cpu(desc->wMaxPacketSize);
 357         tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt);
 358         tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE);
 359         ep->ep.maxpacket = maxpacket;
 360         writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt);
 361
 362         /* IN ep */
 363         if (ep->in) {
 364
 365                 /* ep ix in UDC CSR register space */
 366                 udc_csr_epix = ep->num;
 367
 368                 /* set buffer size (tx fifo entries) */
 369                 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum);
 370                 /* double buffering: fifo size = 2 x max packet size */
 371                 tmp = AMD_ADDBITS(
 372                                 tmp,
 373                                 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
 374                                           / UDC_DWORD_BYTES,
 375                                 UDC_EPIN_BUFF_SIZE);
 376                 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum);
 377
 378                 /* calc. tx fifo base addr */
 379                 udc_set_txfifo_addr(ep);
 380
 381                 /* flush fifo */
 382                 tmp = readl(&ep->regs->ctl);
 383                 tmp |= AMD_BIT(UDC_EPCTL_F);
 384                 writel(tmp, &ep->regs->ctl);
 385
 386         /* OUT ep */
 387         } else {
 388                 /* ep ix in UDC CSR register space */
 389                 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
 390
 391                 /* set max packet size UDC CSR  */
 392                 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
 393                 tmp = AMD_ADDBITS(tmp, maxpacket,
 394                                         UDC_CSR_NE_MAX_PKT);
 395                 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
 396
 397                 if (use_dma && !ep->in) {
 398                         /* alloc and init BNA dummy request */
 399                         ep->bna_dummy_req = udc_alloc_bna_dummy(ep);
 400                         ep->bna_occurred = 0;
 401                 }
 402
 403                 if (ep->num != UDC_EP0OUT_IX)
 404                         dev->data_ep_enabled = 1;
 405         }
 406
 407         /* set ep values */
 408         tmp = readl(&dev->csr->ne[udc_csr_epix]);
 409         /* max packet */
 410         tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT);
 411         /* ep number */
 412         tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM);
 413         /* ep direction */
 414         tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR);
 415         /* ep type */
 416         tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE);
 417         /* ep config */
 418         tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG);
 419         /* ep interface */
 420         tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF);
 421         /* ep alt */
 422         tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT);
 423         /* write reg */
 424         writel(tmp, &dev->csr->ne[udc_csr_epix]);
 425
 426         /* enable ep irq */
 427         tmp = readl(&dev->regs->ep_irqmsk);
 428         tmp &= AMD_UNMASK_BIT(ep->num);
 429         writel(tmp, &dev->regs->ep_irqmsk);
 430
 431         /*
 432          * clear NAK by writing CNAK
 433          * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
 434          */
 435         if (!use_dma || ep->in) {
 436                 tmp = readl(&ep->regs->ctl);
 437                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
 438                 writel(tmp, &ep->regs->ctl);
 439                 ep->naking = 0;
 440                 UDC_QUEUE_CNAK(ep, ep->num);
 441         }
 442         tmp = desc->bEndpointAddress;
 443         DBG(dev, "%s enabled\n", usbep->name);
 444
 445         spin_unlock_irqrestore(&dev->lock, iflags);
 446         return 0;
 447 }
 448
 449 /* Resets endpoint */
 450 static void ep_init(struct udc_regs __iomem *regs, struct udc_ep *ep)
 451 {
 452         u32             tmp;
 453
 454         VDBG(ep->dev, "ep-%d reset\n", ep->num);
 455         ep->desc = NULL;
 456         ep->ep.ops = &udc_ep_ops;
 457         INIT_LIST_HEAD(&ep->queue);
 458
 459         ep->ep.maxpacket = (u16) ~0;
 460         /* set NAK */
 461         tmp = readl(&ep->regs->ctl);
 462         tmp |= AMD_BIT(UDC_EPCTL_SNAK);
 463         writel(tmp, &ep->regs->ctl);
 464         ep->naking = 1;
 465
 466         /* disable interrupt */
 467         tmp = readl(&regs->ep_irqmsk);
 468         tmp |= AMD_BIT(ep->num);
 469         writel(tmp, &regs->ep_irqmsk);
 470
 471         if (ep->in) {
 472                 /* unset P and IN bit of potential former DMA */
 473                 tmp = readl(&ep->regs->ctl);
 474                 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P);
 475                 writel(tmp, &ep->regs->ctl);
 476
 477                 tmp = readl(&ep->regs->sts);
 478                 tmp |= AMD_BIT(UDC_EPSTS_IN);
 479                 writel(tmp, &ep->regs->sts);
 480
 481                 /* flush the fifo */
 482                 tmp = readl(&ep->regs->ctl);
 483                 tmp |= AMD_BIT(UDC_EPCTL_F);
 484                 writel(tmp, &ep->regs->ctl);
 485
 486         }
 487         /* reset desc pointer */
 488         writel(0, &ep->regs->desptr);
 489 }
 490
 491 /* Disables endpoint, is called by gadget driver */
 492 static int udc_ep_disable(struct usb_ep *usbep)
 493 {
 494         struct udc_ep   *ep = NULL;
 495         unsigned long   iflags;
 496
 497         if (!usbep)
 498                 return -EINVAL;
 499
 500         ep = container_of(usbep, struct udc_ep, ep);
 501         if (usbep->name == ep0_string || !ep->desc)
 502                 return -EINVAL;
 503
 504         DBG(ep->dev, "Disable ep-%d\n", ep->num);
 505
 506         spin_lock_irqsave(&ep->dev->lock, iflags);
 507         udc_free_request(&ep->ep, &ep->bna_dummy_req->req);
 508         empty_req_queue(ep);
 509         ep_init(ep->dev->regs, ep);
 510         spin_unlock_irqrestore(&ep->dev->lock, iflags);
 511
 512         return 0;
 513 }
 514
 515 /* Allocates request packet, called by gadget driver */
 516 static struct usb_request *
 517 udc_alloc_request(struct usb_ep *usbep, gfp_t gfp)
 518 {
 519         struct udc_request      *req;
 520         struct udc_data_dma     *dma_desc;
 521         struct udc_ep   *ep;
 522
 523         if (!usbep)
 524                 return NULL;
 525
 526         ep = container_of(usbep, struct udc_ep, ep);
 527
 528         VDBG(ep->dev, "udc_alloc_req(): ep%d\n", ep->num);
 529         req = kzalloc(sizeof(struct udc_request), gfp);
 530         if (!req)
 531                 return NULL;
 532
 533         req->req.dma = DMA_DONT_USE;
 534         INIT_LIST_HEAD(&req->queue);
 535
 536         if (ep->dma) {
 537                 /* ep0 in requests are allocated from data pool here */
 538                 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
 539                                                 &req->td_phys);
 540                 if (!dma_desc) {
 541                         kfree(req);
 542                         return NULL;
 543                 }
 544
 545                 VDBG(ep->dev, "udc_alloc_req: req = %p dma_desc = %p, "
 546                                 "td_phys = %lx\n",
 547                                 req, dma_desc,
 548                                 (unsigned long)req->td_phys);
 549                 /* prevent from using desc. - set HOST BUSY */
 550                 dma_desc->status = AMD_ADDBITS(dma_desc->status,
 551                                                 UDC_DMA_STP_STS_BS_HOST_BUSY,
 552                                                 UDC_DMA_STP_STS_BS);
 553                 dma_desc->bufptr = cpu_to_le32(DMA_DONT_USE);
 554                 req->td_data = dma_desc;
 555                 req->td_data_last = NULL;
 556                 req->chain_len = 1;
 557         }
 558
 559         return &req->req;
 560 }
 561
 562 /* Frees request packet, called by gadget driver */
 563 static void
 564 udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq)
 565 {
 566         struct udc_ep   *ep;
 567         struct udc_request      *req;
 568
 569         if (!usbep || !usbreq)
 570                 return;
 571
 572         ep = container_of(usbep, struct udc_ep, ep);
 573         req = container_of(usbreq, struct udc_request, req);
 574         VDBG(ep->dev, "free_req req=%p\n", req);
 575         BUG_ON(!list_empty(&req->queue));
 576         if (req->td_data) {
 577                 VDBG(ep->dev, "req->td_data=%p\n", req->td_data);
 578
 579                 /* free dma chain if created */
 580                 if (req->chain_len > 1) {
 581                         udc_free_dma_chain(ep->dev, req);
 582                 }
 583
 584                 pci_pool_free(ep->dev->data_requests, req->td_data,
 585                                                         req->td_phys);
 586         }
 587         kfree(req);
 588 }
 589
 590 /* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
 591 static void udc_init_bna_dummy(struct udc_request *req)
 592 {
 593         if (req) {
 594                 /* set last bit */
 595                 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
 596                 /* set next pointer to itself */
 597                 req->td_data->next = req->td_phys;
 598                 /* set HOST BUSY */
 599                 req->td_data->status
 600                         = AMD_ADDBITS(req->td_data->status,
 601                                         UDC_DMA_STP_STS_BS_DMA_DONE,
 602                                         UDC_DMA_STP_STS_BS);
 603 #ifdef UDC_VERBOSE
 604                 pr_debug("bna desc = %p, sts = %08x\n",
 605                         req->td_data, req->td_data->status);
 606 #endif
 607         }
 608 }
 609
 610 /* Allocate BNA dummy descriptor */
 611 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep)
 612 {
 613         struct udc_request *req = NULL;
 614         struct usb_request *_req = NULL;
 615
 616         /* alloc the dummy request */
 617         _req = udc_alloc_request(&ep->ep, GFP_ATOMIC);
 618         if (_req) {
 619                 req = container_of(_req, struct udc_request, req);
 620                 ep->bna_dummy_req = req;
 621                 udc_init_bna_dummy(req);
 622         }
 623         return req;
 624 }
 625
 626 /* Write data to TX fifo for IN packets */
 627 static void
 628 udc_txfifo_write(struct udc_ep *ep, struct usb_request *req)
 629 {
 630         u8                      *req_buf;
 631         u32                     *buf;
 632         int                     i, j;
 633         unsigned                bytes = 0;
 634         unsigned                remaining = 0;
 635
 636         if (!req || !ep)
 637                 return;
 638
 639         req_buf = req->buf + req->actual;
 640         prefetch(req_buf);
 641         remaining = req->length - req->actual;
 642
 643         buf = (u32 *) req_buf;
 644
 645         bytes = ep->ep.maxpacket;
 646         if (bytes > remaining)
 647                 bytes = remaining;
 648
 649         /* dwords first */
 650         for (i = 0; i < bytes / UDC_DWORD_BYTES; i++) {
 651                 writel(*(buf + i), ep->txfifo);
 652         }
 653
 654         /* remaining bytes must be written by byte access */
 655         for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
 656                 writeb((u8)(*(buf + i) >> (j << UDC_BITS_PER_BYTE_SHIFT)),
 657                                                         ep->txfifo);
 658         }
 659
 660         /* dummy write confirm */
 661         writel(0, &ep->regs->confirm);
 662 }
 663
 664 /* Read dwords from RX fifo for OUT transfers */
 665 static int udc_rxfifo_read_dwords(struct udc *dev, u32 *buf, int dwords)
 666 {
 667         int i;
 668
 669         VDBG(dev, "udc_read_dwords(): %d dwords\n", dwords);
 670
 671         for (i = 0; i < dwords; i++) {
 672                 *(buf + i) = readl(dev->rxfifo);
 673         }
 674         return 0;
 675 }
 676
 677 /* Read bytes from RX fifo for OUT transfers */
 678 static int udc_rxfifo_read_bytes(struct udc *dev, u8 *buf, int bytes)
 679 {
 680         int i, j;
 681         u32 tmp;
 682
 683         VDBG(dev, "udc_read_bytes(): %d bytes\n", bytes);
 684
 685         /* dwords first */
 686         for (i = 0; i < bytes / UDC_DWORD_BYTES; i++) {
 687                 *((u32 *)(buf + (i<<2))) = readl(dev->rxfifo);
 688         }
 689
 690         /* remaining bytes must be read by byte access */
 691         if (bytes % UDC_DWORD_BYTES) {
 692                 tmp = readl(dev->rxfifo);
 693                 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
 694                         *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK);
 695                         tmp = tmp >> UDC_BITS_PER_BYTE;
 696                 }
 697         }
 698
 699         return 0;
 700 }
 701
 702 /* Read data from RX fifo for OUT transfers */
 703 static int
 704 udc_rxfifo_read(struct udc_ep *ep, struct udc_request *req)
 705 {
 706         u8 *buf;
 707         unsigned buf_space;
 708         unsigned bytes = 0;
 709         unsigned finished = 0;
 710
 711         /* received number bytes */
 712         bytes = readl(&ep->regs->sts);
 713         bytes = AMD_GETBITS(bytes, UDC_EPSTS_RX_PKT_SIZE);
 714
 715         buf_space = req->req.length - req->req.actual;
 716         buf = req->req.buf + req->req.actual;
 717         if (bytes > buf_space) {
 718                 if ((buf_space % ep->ep.maxpacket) != 0) {
 719                         DBG(ep->dev,
 720                                 "%s: rx %d bytes, rx-buf space = %d bytesn\n",
 721                                 ep->ep.name, bytes, buf_space);
 722                         req->req.status = -EOVERFLOW;
 723                 }
 724                 bytes = buf_space;
 725         }
 726         req->req.actual += bytes;
 727
 728         /* last packet ? */
 729         if (((bytes % ep->ep.maxpacket) != 0) || (!bytes)
 730                 || ((req->req.actual == req->req.length) && !req->req.zero))
 731                 finished = 1;
 732
 733         /* read rx fifo bytes */
 734         VDBG(ep->dev, "ep %s: rxfifo read %d bytes\n", ep->ep.name, bytes);
 735         udc_rxfifo_read_bytes(ep->dev, buf, bytes);
 736
 737         return finished;
 738 }
 739
 740 /* create/re-init a DMA descriptor or a DMA descriptor chain */
 741 static int prep_dma(struct udc_ep *ep, struct udc_request *req, gfp_t gfp)
 742 {
 743         int     retval = 0;
 744         u32     tmp;
 745
 746         VDBG(ep->dev, "prep_dma\n");
 747         VDBG(ep->dev, "prep_dma ep%d req->td_data=%p\n",
 748                         ep->num, req->td_data);
 749
 750         /* set buffer pointer */
 751         req->td_data->bufptr = req->req.dma;
 752
 753         /* set last bit */
 754         req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
 755
 756         /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
 757         if (use_dma_ppb) {
 758
 759                 retval = udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
 760                 if (retval != 0) {
 761                         if (retval == -ENOMEM)
 762                                 DBG(ep->dev, "Out of DMA memory\n");
 763                         return retval;
 764                 }
 765                 if (ep->in) {
 766                         if (req->req.length == ep->ep.maxpacket) {
 767                                 /* write tx bytes */
 768                                 req->td_data->status =
 769                                         AMD_ADDBITS(req->td_data->status,
 770                                                 ep->ep.maxpacket,
 771                                                 UDC_DMA_IN_STS_TXBYTES);
 772
 773                         }
 774                 }
 775
 776         }
 777
 778         if (ep->in) {
 779                 VDBG(ep->dev, "IN: use_dma_ppb=%d req->req.len=%d "
 780                                 "maxpacket=%d ep%d\n",
 781                                 use_dma_ppb, req->req.length,
 782                                 ep->ep.maxpacket, ep->num);
 783                 /*
 784                  * if bytes < max packet then tx bytes must
 785                  * be written in packet per buffer mode
 786                  */
 787                 if (!use_dma_ppb || req->req.length < ep->ep.maxpacket
 788                                 || ep->num == UDC_EP0OUT_IX
 789                                 || ep->num == UDC_EP0IN_IX) {
 790                         /* write tx bytes */
 791                         req->td_data->status =
 792                                 AMD_ADDBITS(req->td_data->status,
 793                                                 req->req.length,
 794                                                 UDC_DMA_IN_STS_TXBYTES);
 795                         /* reset frame num */
 796                         req->td_data->status =
 797                                 AMD_ADDBITS(req->td_data->status,
 798                                                 0,
 799                                                 UDC_DMA_IN_STS_FRAMENUM);
 800                 }
 801                 /* set HOST BUSY */
 802                 req->td_data->status =
 803                         AMD_ADDBITS(req->td_data->status,
 804                                 UDC_DMA_STP_STS_BS_HOST_BUSY,
 805                                 UDC_DMA_STP_STS_BS);
 806         } else {
 807                 VDBG(ep->dev, "OUT set host ready\n");
 808                 /* set HOST READY */
 809                 req->td_data->status =
 810                         AMD_ADDBITS(req->td_data->status,
 811                                 UDC_DMA_STP_STS_BS_HOST_READY,
 812                                 UDC_DMA_STP_STS_BS);
 813
 814
 815                         /* clear NAK by writing CNAK */
 816                         if (ep->naking) {
 817                                 tmp = readl(&ep->regs->ctl);
 818                                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
 819                                 writel(tmp, &ep->regs->ctl);
 820                                 ep->naking = 0;
 821                                 UDC_QUEUE_CNAK(ep, ep->num);
 822                         }
 823
 824         }
 825
 826         return retval;
 827 }
 828
 829 /* Completes request packet ... caller MUST hold lock */
 830 static void
 831 complete_req(struct udc_ep *ep, struct udc_request *req, int sts)
 832 __releases(ep->dev->lock)
 833 __acquires(ep->dev->lock)
 834 {
 835         struct udc              *dev;
 836         unsigned                halted;
 837
 838         VDBG(ep->dev, "complete_req(): ep%d\n", ep->num);
 839
 840         dev = ep->dev;
 841         /* unmap DMA */
 842         if (req->dma_mapping) {
 843                 if (ep->in)
 844                         pci_unmap_single(dev->pdev,
 845                                         req->req.dma,
 846                                         req->req.length,
 847                                         PCI_DMA_TODEVICE);
 848                 else
 849                         pci_unmap_single(dev->pdev,
 850                                         req->req.dma,
 851                                         req->req.length,
 852                                         PCI_DMA_FROMDEVICE);
 853                 req->dma_mapping = 0;
 854                 req->req.dma = DMA_DONT_USE;
 855         }
 856
 857         halted = ep->halted;
 858         ep->halted = 1;
 859
 860         /* set new status if pending */
 861         if (req->req.status == -EINPROGRESS)
 862                 req->req.status = sts;
 863
 864         /* remove from ep queue */
 865         list_del_init(&req->queue);
 866
 867         VDBG(ep->dev, "req %p => complete %d bytes at %s with sts %d\n",
 868                 &req->req, req->req.length, ep->ep.name, sts);
 869
 870         spin_unlock(&dev->lock);
 871         req->req.complete(&ep->ep, &req->req);
 872         spin_lock(&dev->lock);
 873         ep->halted = halted;
 874 }
 875
 876 /* frees pci pool descriptors of a DMA chain */
 877 static int udc_free_dma_chain(struct udc *dev, struct udc_request *req)
 878 {
 879
 880         int ret_val = 0;
 881         struct udc_data_dma     *td;
 882         struct udc_data_dma     *td_last = NULL;
 883         unsigned int i;
 884
 885         DBG(dev, "free chain req = %p\n", req);
 886
 887         /* do not free first desc., will be done by free for request */
 888         td_last = req->td_data;
 889         td = phys_to_virt(td_last->next);
 890
 891         for (i = 1; i < req->chain_len; i++) {
 892
 893                 pci_pool_free(dev->data_requests, td,
 894                                 (dma_addr_t) td_last->next);
 895                 td_last = td;
 896                 td = phys_to_virt(td_last->next);
 897         }
 898
 899         return ret_val;
 900 }
 901
 902 /* Iterates to the end of a DMA chain and returns last descriptor */
 903 static struct udc_data_dma *udc_get_last_dma_desc(struct udc_request *req)
 904 {
 905         struct udc_data_dma     *td;
 906
 907         td = req->td_data;
 908         while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
 909                 td = phys_to_virt(td->next);
 910         }
 911
 912         return td;
 913
 914 }
 915
 916 /* Iterates to the end of a DMA chain and counts bytes received */
 917 static u32 udc_get_ppbdu_rxbytes(struct udc_request *req)
 918 {
 919         struct udc_data_dma     *td;
 920         u32 count;
 921
 922         td = req->td_data;
 923         /* received number bytes */
 924         count = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_RXBYTES);
 925
 926         while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
 927                 td = phys_to_virt(td->next);
 928                 /* received number bytes */
 929                 if (td) {
 930                         count += AMD_GETBITS(td->status,
 931                                 UDC_DMA_OUT_STS_RXBYTES);
 932                 }
 933         }
 934
 935         return count;
 936
 937 }
 938
 939 /* Creates or re-inits a DMA chain */
 940 static int udc_create_dma_chain(
 941         struct udc_ep *ep,
 942         struct udc_request *req,
 943         unsigned long buf_len, gfp_t gfp_flags
 944 )
 945 {
 946         unsigned long bytes = req->req.length;
 947         unsigned int i;
 948         dma_addr_t dma_addr;
 949         struct udc_data_dma     *td = NULL;
 950         struct udc_data_dma     *last = NULL;
 951         unsigned long txbytes;
 952         unsigned create_new_chain = 0;
 953         unsigned len;
 954
 955         VDBG(ep->dev, "udc_create_dma_chain: bytes=%ld buf_len=%ld\n",
 956                         bytes, buf_len);
 957         dma_addr = DMA_DONT_USE;
 958
 959         /* unset L bit in first desc for OUT */
 960         if (!ep->in) {
 961                 req->td_data->status &= AMD_CLEAR_BIT(UDC_DMA_IN_STS_L);
 962         }
 963
 964         /* alloc only new desc's if not already available */
 965         len = req->req.length / ep->ep.maxpacket;
 966         if (req->req.length % ep->ep.maxpacket) {
 967                 len++;
 968         }
 969
 970         if (len > req->chain_len) {
 971                 /* shorter chain already allocated before */
 972                 if (req->chain_len > 1) {
 973                         udc_free_dma_chain(ep->dev, req);
 974                 }
 975                 req->chain_len = len;
 976                 create_new_chain = 1;
 977         }
 978
 979         td = req->td_data;
 980         /* gen. required number of descriptors and buffers */
 981         for (i = buf_len; i < bytes; i += buf_len) {
 982                 /* create or determine next desc. */
 983                 if (create_new_chain) {
 984
 985                         td = pci_pool_alloc(ep->dev->data_requests,
 986                                         gfp_flags, &dma_addr);
 987                         if (!td)
 988                                 return -ENOMEM;
 989
 990                         td->status = 0;
 991                 } else if (i == buf_len) {
 992                         /* first td */
 993                         td = (struct udc_data_dma *) phys_to_virt(
 994                                                 req->td_data->next);
 995                         td->status = 0;
 996                 } else {
 997                         td = (struct udc_data_dma *) phys_to_virt(last->next);
 998                         td->status = 0;
 999                 }
1000
1001
1002                 if (td)
1003                         td->bufptr = req->req.dma + i; /* assign buffer */
1004                 else
1005                         break;
1006
1007                 /* short packet ? */
1008                 if ((bytes - i) >= buf_len) {
1009                         txbytes = buf_len;
1010                 } else {
1011                         /* short packet */
1012                         txbytes = bytes - i;
1013                 }
1014
1015                 /* link td and assign tx bytes */
1016                 if (i == buf_len) {
1017                         if (create_new_chain) {
1018                                 req->td_data->next = dma_addr;
1019                         } else {
1020                                 /* req->td_data->next = virt_to_phys(td); */
1021                         }
1022                         /* write tx bytes */
1023                         if (ep->in) {
1024                                 /* first desc */
1025                                 req->td_data->status =
1026                                         AMD_ADDBITS(req->td_data->status,
1027                                                         ep->ep.maxpacket,
1028                                                         UDC_DMA_IN_STS_TXBYTES);
1029                                 /* second desc */
1030                                 td->status = AMD_ADDBITS(td->status,
1031                                                         txbytes,
1032                                                         UDC_DMA_IN_STS_TXBYTES);
1033                         }
1034                 } else {
1035                         if (create_new_chain) {
1036                                 last->next = dma_addr;
1037                         } else {
1038                                 /* last->next = virt_to_phys(td); */
1039                         }
1040                         if (ep->in) {
1041                                 /* write tx bytes */
1042                                 td->status = AMD_ADDBITS(td->status,
1043                                                         txbytes,
1044                                                         UDC_DMA_IN_STS_TXBYTES);
1045                         }
1046                 }
1047                 last = td;
1048         }
1049         /* set last bit */
1050         if (td) {
1051                 td->status |= AMD_BIT(UDC_DMA_IN_STS_L);
1052                 /* last desc. points to itself */
1053                 req->td_data_last = td;
1054         }
1055
1056         return 0;
1057 }
1058
1059 /* Enabling RX DMA */
1060 static void udc_set_rde(struct udc *dev)
1061 {
1062         u32 tmp;
1063
1064         VDBG(dev, "udc_set_rde()\n");
1065         /* stop RDE timer */
1066         if (timer_pending(&udc_timer)) {
1067                 set_rde = 0;
1068                 mod_timer(&udc_timer, jiffies - 1);
1069         }
1070         /* set RDE */
1071         tmp = readl(&dev->regs->ctl);
1072         tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1073         writel(tmp, &dev->regs->ctl);
1074 }
1075
1076 /* Queues a request packet, called by gadget driver */
1077 static int
1078 udc_queue(struct usb_ep *usbep, struct usb_request *usbreq, gfp_t gfp)
1079 {
1080         int                     retval = 0;
1081         u8                      open_rxfifo = 0;
1082         unsigned long           iflags;
1083         struct udc_ep           *ep;
1084         struct udc_request      *req;
1085         struct udc              *dev;
1086         u32                     tmp;
1087
1088         /* check the inputs */
1089         req = container_of(usbreq, struct udc_request, req);
1090
1091         if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf
1092                         || !list_empty(&req->queue))
1093                 return -EINVAL;
1094
1095         ep = container_of(usbep, struct udc_ep, ep);
1096         if (!ep->desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1097                 return -EINVAL;
1098
1099         VDBG(ep->dev, "udc_queue(): ep%d-in=%d\n", ep->num, ep->in);
1100         dev = ep->dev;
1101
1102         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
1103                 return -ESHUTDOWN;
1104
1105         /* map dma (usually done before) */
1106         if (ep->dma && usbreq->length != 0
1107                         && (usbreq->dma == DMA_DONT_USE || usbreq->dma == 0)) {
1108                 VDBG(dev, "DMA map req %p\n", req);
1109                 if (ep->in)
1110                         usbreq->dma = pci_map_single(dev->pdev,
1111                                                 usbreq->buf,
1112                                                 usbreq->length,
1113                                                 PCI_DMA_TODEVICE);
1114                 else
1115                         usbreq->dma = pci_map_single(dev->pdev,
1116                                                 usbreq->buf,
1117                                                 usbreq->length,
1118                                                 PCI_DMA_FROMDEVICE);
1119                 req->dma_mapping = 1;
1120         }
1121
1122         VDBG(dev, "%s queue req %p, len %d req->td_data=%p buf %p\n",
1123                         usbep->name, usbreq, usbreq->length,
1124                         req->td_data, usbreq->buf);
1125
1126         spin_lock_irqsave(&dev->lock, iflags);
1127         usbreq->actual = 0;
1128         usbreq->status = -EINPROGRESS;
1129         req->dma_done = 0;
1130
1131         /* on empty queue just do first transfer */
1132         if (list_empty(&ep->queue)) {
1133                 /* zlp */
1134                 if (usbreq->length == 0) {
1135                         /* IN zlp's are handled by hardware */
1136                         complete_req(ep, req, 0);
1137                         VDBG(dev, "%s: zlp\n", ep->ep.name);
1138                         /*
1139                          * if set_config or set_intf is waiting for ack by zlp
1140                          * then set CSR_DONE
1141                          */
1142                         if (dev->set_cfg_not_acked) {
1143                                 tmp = readl(&dev->regs->ctl);
1144                                 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE);
1145                                 writel(tmp, &dev->regs->ctl);
1146                                 dev->set_cfg_not_acked = 0;
1147                         }
1148                         /* setup command is ACK'ed now by zlp */
1149                         if (dev->waiting_zlp_ack_ep0in) {
1150                                 /* clear NAK by writing CNAK in EP0_IN */
1151                                 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1152                                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1153                                 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1154                                 dev->ep[UDC_EP0IN_IX].naking = 0;
1155                                 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX],
1156                                                         UDC_EP0IN_IX);
1157                                 dev->waiting_zlp_ack_ep0in = 0;
1158                         }
1159                         goto finished;
1160                 }
1161                 if (ep->dma) {
1162                         retval = prep_dma(ep, req, gfp);
1163                         if (retval != 0)
1164                                 goto finished;
1165                         /* write desc pointer to enable DMA */
1166                         if (ep->in) {
1167                                 /* set HOST READY */
1168                                 req->td_data->status =
1169                                         AMD_ADDBITS(req->td_data->status,
1170                                                 UDC_DMA_IN_STS_BS_HOST_READY,
1171                                                 UDC_DMA_IN_STS_BS);
1172                         }
1173
1174                         /* disabled rx dma while descriptor update */
1175                         if (!ep->in) {
1176                                 /* stop RDE timer */
1177                                 if (timer_pending(&udc_timer)) {
1178                                         set_rde = 0;
1179                                         mod_timer(&udc_timer, jiffies - 1);
1180                                 }
1181                                 /* clear RDE */
1182                                 tmp = readl(&dev->regs->ctl);
1183                                 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1184                                 writel(tmp, &dev->regs->ctl);
1185                                 open_rxfifo = 1;
1186
1187                                 /*
1188                                  * if BNA occurred then let BNA dummy desc.
1189                                  * point to current desc.
1190                                  */
1191                                 if (ep->bna_occurred) {
1192                                         VDBG(dev, "copy to BNA dummy desc.\n");
1193                                         memcpy(ep->bna_dummy_req->td_data,
1194                                                 req->td_data,
1195                                                 sizeof(struct udc_data_dma));
1196                                 }
1197                         }
1198                         /* write desc pointer */
1199                         writel(req->td_phys, &ep->regs->desptr);
1200
1201                         /* clear NAK by writing CNAK */
1202                         if (ep->naking) {
1203                                 tmp = readl(&ep->regs->ctl);
1204                                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1205                                 writel(tmp, &ep->regs->ctl);
1206                                 ep->naking = 0;
1207                                 UDC_QUEUE_CNAK(ep, ep->num);
1208                         }
1209
1210                         if (ep->in) {
1211                                 /* enable ep irq */
1212                                 tmp = readl(&dev->regs->ep_irqmsk);
1213                                 tmp &= AMD_UNMASK_BIT(ep->num);
1214                                 writel(tmp, &dev->regs->ep_irqmsk);
1215                         }
1216                 } else if (ep->in) {
1217                                 /* enable ep irq */
1218                                 tmp = readl(&dev->regs->ep_irqmsk);
1219                                 tmp &= AMD_UNMASK_BIT(ep->num);
1220                                 writel(tmp, &dev->regs->ep_irqmsk);
1221                         }
1222
1223         } else if (ep->dma) {
1224
1225                 /*
1226                  * prep_dma not used for OUT ep's, this is not possible
1227                  * for PPB modes, because of chain creation reasons
1228                  */
1229                 if (ep->in) {
1230                         retval = prep_dma(ep, req, gfp);
1231                         if (retval != 0)
1232                                 goto finished;
1233                 }
1234         }
1235         VDBG(dev, "list_add\n");
1236         /* add request to ep queue */
1237         if (req) {
1238
1239                 list_add_tail(&req->queue, &ep->queue);
1240
1241                 /* open rxfifo if out data queued */
1242                 if (open_rxfifo) {
1243                         /* enable DMA */
1244                         req->dma_going = 1;
1245                         udc_set_rde(dev);
1246                         if (ep->num != UDC_EP0OUT_IX)
1247                                 dev->data_ep_queued = 1;
1248                 }
1249                 /* stop OUT naking */
1250                 if (!ep->in) {
1251                         if (!use_dma && udc_rxfifo_pending) {
1252                                 DBG(dev, "udc_queue(): pending bytes in "
1253                                         "rxfifo after nyet\n");
1254                                 /*
1255                                  * read pending bytes afer nyet:
1256                                  * referring to isr
1257                                  */
1258                                 if (udc_rxfifo_read(ep, req)) {
1259                                         /* finish */
1260                                         complete_req(ep, req, 0);
1261                                 }
1262                                 udc_rxfifo_pending = 0;
1263
1264                         }
1265                 }
1266         }
1267
1268 finished:
1269         spin_unlock_irqrestore(&dev->lock, iflags);
1270         return retval;
1271 }
1272
1273 /* Empty request queue of an endpoint; caller holds spinlock */
1274 static void empty_req_queue(struct udc_ep *ep)
1275 {
1276         struct udc_request      *req;
1277
1278         ep->halted = 1;
1279         while (!list_empty(&ep->queue)) {
1280                 req = list_entry(ep->queue.next,
1281                         struct udc_request,
1282                         queue);
1283                 complete_req(ep, req, -ESHUTDOWN);
1284         }
1285 }
1286
1287 /* Dequeues a request packet, called by gadget driver */
1288 static int udc_dequeue(struct usb_ep *usbep, struct usb_request *usbreq)
1289 {
1290         struct udc_ep           *ep;
1291         struct udc_request      *req;
1292         unsigned                halted;
1293         unsigned long           iflags;
1294
1295         ep = container_of(usbep, struct udc_ep, ep);
1296         if (!usbep || !usbreq || (!ep->desc && (ep->num != 0
1297                                 && ep->num != UDC_EP0OUT_IX)))
1298                 return -EINVAL;
1299
1300         req = container_of(usbreq, struct udc_request, req);
1301
1302         spin_lock_irqsave(&ep->dev->lock, iflags);
1303         halted = ep->halted;
1304         ep->halted = 1;
1305         /* request in processing or next one */
1306         if (ep->queue.next == &req->queue) {
1307                 if (ep->dma && req->dma_going) {
1308                         if (ep->in)
1309                                 ep->cancel_transfer = 1;
1310                         else {
1311                                 u32 tmp;
1312                                 u32 dma_sts;
1313                                 /* stop potential receive DMA */
1314                                 tmp = readl(&udc->regs->ctl);
1315                                 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE),
1316                                                         &udc->regs->ctl);
1317                                 /*
1318                                  * Cancel transfer later in ISR
1319                                  * if descriptor was touched.
1320                                  */
1321                                 dma_sts = AMD_GETBITS(req->td_data->status,
1322                                                         UDC_DMA_OUT_STS_BS);
1323                                 if (dma_sts != UDC_DMA_OUT_STS_BS_HOST_READY)
1324                                         ep->cancel_transfer = 1;
1325                                 else {
1326                                         udc_init_bna_dummy(ep->req);
1327                                         writel(ep->bna_dummy_req->td_phys,
1328                                                 &ep->regs->desptr);
1329                                 }
1330                                 writel(tmp, &udc->regs->ctl);
1331                         }
1332                 }
1333         }
1334         complete_req(ep, req, -ECONNRESET);
1335         ep->halted = halted;
1336
1337         spin_unlock_irqrestore(&ep->dev->lock, iflags);
1338         return 0;
1339 }
1340
1341 /* Halt or clear halt of endpoint */
1342 static int
1343 udc_set_halt(struct usb_ep *usbep, int halt)
1344 {
1345         struct udc_ep   *ep;
1346         u32 tmp;
1347         unsigned long iflags;
1348         int retval = 0;
1349
1350         if (!usbep)
1351                 return -EINVAL;
1352
1353         pr_debug("set_halt %s: halt=%d\n", usbep->name, halt);
1354
1355         ep = container_of(usbep, struct udc_ep, ep);
1356         if (!ep->desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1357                 return -EINVAL;
1358         if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN)
1359                 return -ESHUTDOWN;
1360
1361         spin_lock_irqsave(&udc_stall_spinlock, iflags);
1362         /* halt or clear halt */
1363         if (halt) {
1364                 if (ep->num == 0)
1365                         ep->dev->stall_ep0in = 1;
1366                 else {
1367                         /*
1368                          * set STALL
1369                          * rxfifo empty not taken into acount
1370                          */
1371                         tmp = readl(&ep->regs->ctl);
1372                         tmp |= AMD_BIT(UDC_EPCTL_S);
1373                         writel(tmp, &ep->regs->ctl);
1374                         ep->halted = 1;
1375
1376                         /* setup poll timer */
1377                         if (!timer_pending(&udc_pollstall_timer)) {
1378                                 udc_pollstall_timer.expires = jiffies +
1379                                         HZ * UDC_POLLSTALL_TIMER_USECONDS
1380                                         / (1000 * 1000);
1381                                 if (!stop_pollstall_timer) {
1382                                         DBG(ep->dev, "start polltimer\n");
1383                                         add_timer(&udc_pollstall_timer);
1384                                 }
1385                         }
1386                 }
1387         } else {
1388                 /* ep is halted by set_halt() before */
1389                 if (ep->halted) {
1390                         tmp = readl(&ep->regs->ctl);
1391                         /* clear stall bit */
1392                         tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
1393                         /* clear NAK by writing CNAK */
1394                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1395                         writel(tmp, &ep->regs->ctl);
1396                         ep->halted = 0;
1397                         UDC_QUEUE_CNAK(ep, ep->num);
1398                 }
1399         }
1400         spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1401         return retval;
1402 }
1403
1404 /* gadget interface */
1405 static const struct usb_ep_ops udc_ep_ops = {
1406         .enable         = udc_ep_enable,
1407         .disable        = udc_ep_disable,
1408
1409         .alloc_request  = udc_alloc_request,
1410         .free_request   = udc_free_request,
1411
1412         .queue          = udc_queue,
1413         .dequeue        = udc_dequeue,
1414
1415         .set_halt       = udc_set_halt,
1416         /* fifo ops not implemented */
1417 };
1418
1419 /*-------------------------------------------------------------------------*/
1420
1421 /* Get frame counter (not implemented) */
1422 static int udc_get_frame(struct usb_gadget *gadget)
1423 {
1424         return -EOPNOTSUPP;
1425 }
1426
1427 /* Remote wakeup gadget interface */
1428 static int udc_wakeup(struct usb_gadget *gadget)
1429 {
1430         struct udc              *dev;
1431
1432         if (!gadget)
1433                 return -EINVAL;
1434         dev = container_of(gadget, struct udc, gadget);
1435         udc_remote_wakeup(dev);
1436
1437         return 0;
1438 }
1439
1440 /* gadget operations */
1441 static const struct usb_gadget_ops udc_ops = {
1442         .wakeup         = udc_wakeup,
1443         .get_frame      = udc_get_frame,
1444 };
1445
1446 /* Setups endpoint parameters, adds endpoints to linked list */
1447 static void make_ep_lists(struct udc *dev)
1448 {
1449         /* make gadget ep lists */
1450         INIT_LIST_HEAD(&dev->gadget.ep_list);
1451         list_add_tail(&dev->ep[UDC_EPIN_STATUS_IX].ep.ep_list,
1452                                                 &dev->gadget.ep_list);
1453         list_add_tail(&dev->ep[UDC_EPIN_IX].ep.ep_list,
1454                                                 &dev->gadget.ep_list);
1455         list_add_tail(&dev->ep[UDC_EPOUT_IX].ep.ep_list,
1456                                                 &dev->gadget.ep_list);
1457
1458         /* fifo config */
1459         dev->ep[UDC_EPIN_STATUS_IX].fifo_depth = UDC_EPIN_SMALLINT_BUFF_SIZE;
1460         if (dev->gadget.speed == USB_SPEED_FULL)
1461                 dev->ep[UDC_EPIN_IX].fifo_depth = UDC_FS_EPIN_BUFF_SIZE;
1462         else if (dev->gadget.speed == USB_SPEED_HIGH)
1463                 dev->ep[UDC_EPIN_IX].fifo_depth = hs_tx_buf;
1464         dev->ep[UDC_EPOUT_IX].fifo_depth = UDC_RXFIFO_SIZE;
1465 }
1466
1467 /* init registers at driver load time */
1468 static int startup_registers(struct udc *dev)
1469 {
1470         u32 tmp;
1471
1472         /* init controller by soft reset */
1473         udc_soft_reset(dev);
1474
1475         /* mask not needed interrupts */
1476         udc_mask_unused_interrupts(dev);
1477
1478         /* put into initial config */
1479         udc_basic_init(dev);
1480         /* link up all endpoints */
1481         udc_setup_endpoints(dev);
1482
1483         /* program speed */
1484         tmp = readl(&dev->regs->cfg);
1485         if (use_fullspeed) {
1486                 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1487         } else {
1488                 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD);
1489         }
1490         writel(tmp, &dev->regs->cfg);
1491
1492         return 0;
1493 }
1494
1495 /* Inits UDC context */
1496 static void udc_basic_init(struct udc *dev)
1497 {
1498         u32     tmp;
1499
1500         DBG(dev, "udc_basic_init()\n");
1501
1502         dev->gadget.speed = USB_SPEED_UNKNOWN;
1503
1504         /* stop RDE timer */
1505         if (timer_pending(&udc_timer)) {
1506                 set_rde = 0;
1507                 mod_timer(&udc_timer, jiffies - 1);
1508         }
1509         /* stop poll stall timer */
1510         if (timer_pending(&udc_pollstall_timer)) {
1511                 mod_timer(&udc_pollstall_timer, jiffies - 1);
1512         }
1513         /* disable DMA */
1514         tmp = readl(&dev->regs->ctl);
1515         tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1516         tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE);
1517         writel(tmp, &dev->regs->ctl);
1518
1519         /* enable dynamic CSR programming */
1520         tmp = readl(&dev->regs->cfg);
1521         tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG);
1522         /* set self powered */
1523         tmp |= AMD_BIT(UDC_DEVCFG_SP);
1524         /* set remote wakeupable */
1525         tmp |= AMD_BIT(UDC_DEVCFG_RWKP);
1526         writel(tmp, &dev->regs->cfg);
1527
1528         make_ep_lists(dev);
1529
1530         dev->data_ep_enabled = 0;
1531         dev->data_ep_queued = 0;
1532 }
1533
1534 /* Sets initial endpoint parameters */
1535 static void udc_setup_endpoints(struct udc *dev)
1536 {
1537         struct udc_ep   *ep;
1538         u32     tmp;
1539         u32     reg;
1540
1541         DBG(dev, "udc_setup_endpoints()\n");
1542
1543         /* read enum speed */
1544         tmp = readl(&dev->regs->sts);
1545         tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED);
1546         if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH) {
1547                 dev->gadget.speed = USB_SPEED_HIGH;
1548         } else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL) {
1549                 dev->gadget.speed = USB_SPEED_FULL;
1550         }
1551
1552         /* set basic ep parameters */
1553         for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1554                 ep = &dev->ep[tmp];
1555                 ep->dev = dev;
1556                 ep->ep.name = ep_string[tmp];
1557                 ep->num = tmp;
1558                 /* txfifo size is calculated at enable time */
1559                 ep->txfifo = dev->txfifo;
1560
1561                 /* fifo size */
1562                 if (tmp < UDC_EPIN_NUM) {
1563                         ep->fifo_depth = UDC_TXFIFO_SIZE;
1564                         ep->in = 1;
1565                 } else {
1566                         ep->fifo_depth = UDC_RXFIFO_SIZE;
1567                         ep->in = 0;
1568
1569                 }
1570                 ep->regs = &dev->ep_regs[tmp];
1571                 /*
1572                  * ep will be reset only if ep was not enabled before to avoid
1573                  * disabling ep interrupts when ENUM interrupt occurs but ep is
1574                  * not enabled by gadget driver
1575                  */
1576                 if (!ep->desc) {
1577                         ep_init(dev->regs, ep);
1578                 }
1579
1580                 if (use_dma) {
1581                         /*
1582                          * ep->dma is not really used, just to indicate that
1583                          * DMA is active: remove this
1584                          * dma regs = dev control regs
1585                          */
1586                         ep->dma = &dev->regs->ctl;
1587
1588                         /* nak OUT endpoints until enable - not for ep0 */
1589                         if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX
1590                                                 && tmp > UDC_EPIN_NUM) {
1591                                 /* set NAK */
1592                                 reg = readl(&dev->ep[tmp].regs->ctl);
1593                                 reg |= AMD_BIT(UDC_EPCTL_SNAK);
1594                                 writel(reg, &dev->ep[tmp].regs->ctl);
1595                                 dev->ep[tmp].naking = 1;
1596
1597                         }
1598                 }
1599         }
1600         /* EP0 max packet */
1601         if (dev->gadget.speed == USB_SPEED_FULL) {
1602                 dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_FS_EP0IN_MAX_PKT_SIZE;
1603                 dev->ep[UDC_EP0OUT_IX].ep.maxpacket =
1604                                                 UDC_FS_EP0OUT_MAX_PKT_SIZE;
1605         } else if (dev->gadget.speed == USB_SPEED_HIGH) {
1606                 dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
1607                 dev->ep[UDC_EP0OUT_IX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
1608         }
1609
1610         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
1611         dev->ep[UDC_EP0IN_IX].halted = 0;
1612         INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1613
1614         /* init cfg/alt/int */
1615         dev->cur_config = 0;
1616         dev->cur_intf = 0;
1617         dev->cur_alt = 0;
1618 }
1619
1620 /* Bringup after Connect event, initial bringup to be ready for ep0 events */
1621 static void usb_connect(struct udc *dev)
1622 {
1623
1624         dev_info(&dev->pdev->dev, "USB Connect\n");
1625
1626         dev->connected = 1;
1627
1628         /* put into initial config */
1629         udc_basic_init(dev);
1630
1631         /* enable device setup interrupts */
1632         udc_enable_dev_setup_interrupts(dev);
1633 }
1634
1635 /*
1636  * Calls gadget with disconnect event and resets the UDC and makes
1637  * initial bringup to be ready for ep0 events
1638  */
1639 static void usb_disconnect(struct udc *dev)
1640 {
1641
1642         dev_info(&dev->pdev->dev, "USB Disconnect\n");
1643
1644         dev->connected = 0;
1645
1646         /* mask interrupts */
1647         udc_mask_unused_interrupts(dev);
1648
1649         /* REVISIT there doesn't seem to be a point to having this
1650          * talk to a tasklet ... do it directly, we already hold
1651          * the spinlock needed to process the disconnect.
1652          */
1653
1654         tasklet_schedule(&disconnect_tasklet);
1655 }
1656
1657 /* Tasklet for disconnect to be outside of interrupt context */
1658 static void udc_tasklet_disconnect(unsigned long par)
1659 {
1660         struct udc *dev = (struct udc *)(*((struct udc **) par));
1661         u32 tmp;
1662
1663         DBG(dev, "Tasklet disconnect\n");
1664         spin_lock_irq(&dev->lock);
1665
1666         if (dev->driver) {
1667                 spin_unlock(&dev->lock);
1668                 dev->driver->disconnect(&dev->gadget);
1669                 spin_lock(&dev->lock);
1670
1671                 /* empty queues */
1672                 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1673                         empty_req_queue(&dev->ep[tmp]);
1674                 }
1675
1676         }
1677
1678         /* disable ep0 */
1679         ep_init(dev->regs,
1680                         &dev->ep[UDC_EP0IN_IX]);
1681
1682
1683         if (!soft_reset_occured) {
1684                 /* init controller by soft reset */
1685                 udc_soft_reset(dev);
1686                 soft_reset_occured++;
1687         }
1688
1689         /* re-enable dev interrupts */
1690         udc_enable_dev_setup_interrupts(dev);
1691         /* back to full speed ? */
1692         if (use_fullspeed) {
1693                 tmp = readl(&dev->regs->cfg);
1694                 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1695                 writel(tmp, &dev->regs->cfg);
1696         }
1697
1698         spin_unlock_irq(&dev->lock);
1699 }
1700
1701 /* Reset the UDC core */
1702 static void udc_soft_reset(struct udc *dev)
1703 {
1704         unsigned long   flags;
1705
1706         DBG(dev, "Soft reset\n");
1707         /*
1708          * reset possible waiting interrupts, because int.
1709          * status is lost after soft reset,
1710          * ep int. status reset
1711          */
1712         writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts);
1713         /* device int. status reset */
1714         writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts);
1715
1716         spin_lock_irqsave(&udc_irq_spinlock, flags);
1717         writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
1718         readl(&dev->regs->cfg);
1719         spin_unlock_irqrestore(&udc_irq_spinlock, flags);
1720
1721 }
1722
1723 /* RDE timer callback to set RDE bit */
1724 static void udc_timer_function(unsigned long v)
1725 {
1726         u32 tmp;
1727
1728         spin_lock_irq(&udc_irq_spinlock);
1729
1730         if (set_rde > 0) {
1731                 /*
1732                  * open the fifo if fifo was filled on last timer call
1733                  * conditionally
1734                  */
1735                 if (set_rde > 1) {
1736                         /* set RDE to receive setup data */
1737                         tmp = readl(&udc->regs->ctl);
1738                         tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1739                         writel(tmp, &udc->regs->ctl);
1740                         set_rde = -1;
1741                 } else if (readl(&udc->regs->sts)
1742                                 & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
1743                         /*
1744                          * if fifo empty setup polling, do not just
1745                          * open the fifo
1746                          */
1747                         udc_timer.expires = jiffies + HZ/UDC_RDE_TIMER_DIV;
1748                         if (!stop_timer) {
1749                                 add_timer(&udc_timer);
1750                         }
1751                 } else {
1752                         /*
1753                          * fifo contains data now, setup timer for opening
1754                          * the fifo when timer expires to be able to receive
1755                          * setup packets, when data packets gets queued by
1756                          * gadget layer then timer will forced to expire with
1757                          * set_rde=0 (RDE is set in udc_queue())
1758                          */
1759                         set_rde++;
1760                         /* debug: lhadmot_timer_start = 221070 */
1761                         udc_timer.expires = jiffies + HZ*UDC_RDE_TIMER_SECONDS;
1762                         if (!stop_timer) {
1763                                 add_timer(&udc_timer);
1764                         }
1765                 }
1766
1767         } else
1768                 set_rde = -1; /* RDE was set by udc_queue() */
1769         spin_unlock_irq(&udc_irq_spinlock);
1770         if (stop_timer)
1771                 complete(&on_exit);
1772
1773 }
1774
1775 /* Handle halt state, used in stall poll timer */
1776 static void udc_handle_halt_state(struct udc_ep *ep)
1777 {
1778         u32 tmp;
1779         /* set stall as long not halted */
1780         if (ep->halted == 1) {
1781                 tmp = readl(&ep->regs->ctl);
1782                 /* STALL cleared ? */
1783                 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) {
1784
1785                         /* clear NAK by writing CNAK */
1786                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1787                         writel(tmp, &ep->regs->ctl);
1788                         ep->halted = 0;
1789                         UDC_QUEUE_CNAK(ep, ep->num);
1790                 }
1791         }
1792 }
1793
1794 /* Stall timer callback to poll S bit and set it again after */
1795 static void udc_pollstall_timer_function(unsigned long v)
1796 {
1797         struct udc_ep *ep;
1798         int halted = 0;
1799
1800         spin_lock_irq(&udc_stall_spinlock);
1801         /*
1802          * only one IN and OUT endpoints are handled
1803          * IN poll stall
1804          */
1805         ep = &udc->ep[UDC_EPIN_IX];
1806         udc_handle_halt_state(ep);
1807         if (ep->halted)
1808                 halted = 1;
1809         /* OUT poll stall */
1810         ep = &udc->ep[UDC_EPOUT_IX];
1811         udc_handle_halt_state(ep);
1812         if (ep->halted)
1813                 halted = 1;
1814
1815         /* setup timer again when still halted */
1816         if (!stop_pollstall_timer && halted) {
1817                 udc_pollstall_timer.expires = jiffies +
1818                                         HZ * UDC_POLLSTALL_TIMER_USECONDS
1819                                         / (1000 * 1000);
1820                 add_timer(&udc_pollstall_timer);
1821         }
1822         spin_unlock_irq(&udc_stall_spinlock);
1823
1824         if (stop_pollstall_timer)
1825                 complete(&on_pollstall_exit);
1826 }
1827
1828 /* Inits endpoint 0 so that SETUP packets are processed */
1829 static void activate_control_endpoints(struct udc *dev)
1830 {
1831         u32 tmp;
1832
1833         DBG(dev, "activate_control_endpoints\n");
1834
1835         /* flush fifo */
1836         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1837         tmp |= AMD_BIT(UDC_EPCTL_F);
1838         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1839
1840         /* set ep0 directions */
1841         dev->ep[UDC_EP0IN_IX].in = 1;
1842         dev->ep[UDC_EP0OUT_IX].in = 0;
1843
1844         /* set buffer size (tx fifo entries) of EP0_IN */
1845         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1846         if (dev->gadget.speed == USB_SPEED_FULL)
1847                 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE,
1848                                         UDC_EPIN_BUFF_SIZE);
1849         else if (dev->gadget.speed == USB_SPEED_HIGH)
1850                 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE,
1851                                         UDC_EPIN_BUFF_SIZE);
1852         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1853
1854         /* set max packet size of EP0_IN */
1855         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1856         if (dev->gadget.speed == USB_SPEED_FULL)
1857                 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE,
1858                                         UDC_EP_MAX_PKT_SIZE);
1859         else if (dev->gadget.speed == USB_SPEED_HIGH)
1860                 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE,
1861                                 UDC_EP_MAX_PKT_SIZE);
1862         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1863
1864         /* set max packet size of EP0_OUT */
1865         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1866         if (dev->gadget.speed == USB_SPEED_FULL)
1867                 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1868                                         UDC_EP_MAX_PKT_SIZE);
1869         else if (dev->gadget.speed == USB_SPEED_HIGH)
1870                 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1871                                         UDC_EP_MAX_PKT_SIZE);
1872         writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1873
1874         /* set max packet size of EP0 in UDC CSR */
1875         tmp = readl(&dev->csr->ne[0]);
1876         if (dev->gadget.speed == USB_SPEED_FULL)
1877                 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1878                                         UDC_CSR_NE_MAX_PKT);
1879         else if (dev->gadget.speed == USB_SPEED_HIGH)
1880                 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1881                                         UDC_CSR_NE_MAX_PKT);
1882         writel(tmp, &dev->csr->ne[0]);
1883
1884         if (use_dma) {
1885                 dev->ep[UDC_EP0OUT_IX].td->status |=
1886                         AMD_BIT(UDC_DMA_OUT_STS_L);
1887                 /* write dma desc address */
1888                 writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma,
1889                         &dev->ep[UDC_EP0OUT_IX].regs->subptr);
1890                 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
1891                         &dev->ep[UDC_EP0OUT_IX].regs->desptr);
1892                 /* stop RDE timer */
1893                 if (timer_pending(&udc_timer)) {
1894                         set_rde = 0;
1895                         mod_timer(&udc_timer, jiffies - 1);
1896                 }
1897                 /* stop pollstall timer */
1898                 if (timer_pending(&udc_pollstall_timer)) {
1899                         mod_timer(&udc_pollstall_timer, jiffies - 1);
1900                 }
1901                 /* enable DMA */
1902                 tmp = readl(&dev->regs->ctl);
1903                 tmp |= AMD_BIT(UDC_DEVCTL_MODE)
1904                                 | AMD_BIT(UDC_DEVCTL_RDE)
1905                                 | AMD_BIT(UDC_DEVCTL_TDE);
1906                 if (use_dma_bufferfill_mode) {
1907                         tmp |= AMD_BIT(UDC_DEVCTL_BF);
1908                 } else if (use_dma_ppb_du) {
1909                         tmp |= AMD_BIT(UDC_DEVCTL_DU);
1910                 }
1911                 writel(tmp, &dev->regs->ctl);
1912         }
1913
1914         /* clear NAK by writing CNAK for EP0IN */
1915         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1916         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1917         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1918         dev->ep[UDC_EP0IN_IX].naking = 0;
1919         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
1920
1921         /* clear NAK by writing CNAK for EP0OUT */
1922         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
1923         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1924         writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
1925         dev->ep[UDC_EP0OUT_IX].naking = 0;
1926         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
1927 }
1928
1929 /* Make endpoint 0 ready for control traffic */
1930 static int setup_ep0(struct udc *dev)
1931 {
1932         activate_control_endpoints(dev);
1933         /* enable ep0 interrupts */
1934         udc_enable_ep0_interrupts(dev);
1935         /* enable device setup interrupts */
1936         udc_enable_dev_setup_interrupts(dev);
1937
1938         return 0;
1939 }
1940
1941 /* Called by gadget driver to register itself */
1942 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1943 {
1944         struct udc              *dev = udc;
1945         int                     retval;
1946         u32 tmp;
1947
1948         if (!driver || !driver->bind || !driver->setup
1949                         || driver->speed != USB_SPEED_HIGH)
1950                 return -EINVAL;
1951         if (!dev)
1952                 return -ENODEV;
1953         if (dev->driver)
1954                 return -EBUSY;
1955
1956         driver->driver.bus = NULL;
1957         dev->driver = driver;
1958         dev->gadget.dev.driver = &driver->driver;
1959
1960         retval = driver->bind(&dev->gadget);
1961
1962         /* Some gadget drivers use both ep0 directions.
1963          * NOTE: to gadget driver, ep0 is just one endpoint...
1964          */
1965         dev->ep[UDC_EP0OUT_IX].ep.driver_data =
1966                 dev->ep[UDC_EP0IN_IX].ep.driver_data;
1967
1968         if (retval) {
1969                 DBG(dev, "binding to %s returning %d\n",
1970                                 driver->driver.name, retval);
1971                 dev->driver = NULL;
1972                 dev->gadget.dev.driver = NULL;
1973                 return retval;
1974         }
1975
1976         /* get ready for ep0 traffic */
1977         setup_ep0(dev);
1978
1979         /* clear SD */
1980         tmp = readl(&dev->regs->ctl);
1981         tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD);
1982         writel(tmp, &dev->regs->ctl);
1983
1984         usb_connect(dev);
1985
1986         return 0;
1987 }
1988 EXPORT_SYMBOL(usb_gadget_register_driver);
1989
1990 /* shutdown requests and disconnect from gadget */
1991 static void
1992 shutdown(struct udc *dev, struct usb_gadget_driver *driver)
1993 __releases(dev->lock)
1994 __acquires(dev->lock)
1995 {
1996         int tmp;
1997
1998         if (dev->gadget.speed != USB_SPEED_UNKNOWN) {
1999                 spin_unlock(&dev->lock);
2000                 driver->disconnect(&dev->gadget);
2001                 spin_lock(&dev->lock);
2002         }
2003
2004         /* empty queues and init hardware */
2005         udc_basic_init(dev);
2006         for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
2007                 empty_req_queue(&dev->ep[tmp]);
2008
2009         udc_setup_endpoints(dev);
2010 }
2011
2012 /* Called by gadget driver to unregister itself */
2013 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2014 {
2015         struct udc      *dev = udc;
2016         unsigned long   flags;
2017         u32 tmp;
2018
2019         if (!dev)
2020                 return -ENODEV;
2021         if (!driver || driver != dev->driver || !driver->unbind)
2022                 return -EINVAL;
2023
2024         spin_lock_irqsave(&dev->lock, flags);
2025         udc_mask_unused_interrupts(dev);
2026         shutdown(dev, driver);
2027         spin_unlock_irqrestore(&dev->lock, flags);
2028
2029         driver->unbind(&dev->gadget);
2030         dev->gadget.dev.driver = NULL;
2031         dev->driver = NULL;
2032
2033         /* set SD */
2034         tmp = readl(&dev->regs->ctl);
2035         tmp |= AMD_BIT(UDC_DEVCTL_SD);
2036         writel(tmp, &dev->regs->ctl);
2037
2038
2039         DBG(dev, "%s: unregistered\n", driver->driver.name);
2040
2041         return 0;
2042 }
2043 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2044
2045
2046 /* Clear pending NAK bits */
2047 static void udc_process_cnak_queue(struct udc *dev)
2048 {
2049         u32 tmp;
2050         u32 reg;
2051
2052         /* check epin's */
2053         DBG(dev, "CNAK pending queue processing\n");
2054         for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) {
2055                 if (cnak_pending & (1 << tmp)) {
2056                         DBG(dev, "CNAK pending for ep%d\n", tmp);
2057                         /* clear NAK by writing CNAK */
2058                         reg = readl(&dev->ep[tmp].regs->ctl);
2059                         reg |= AMD_BIT(UDC_EPCTL_CNAK);
2060                         writel(reg, &dev->ep[tmp].regs->ctl);
2061                         dev->ep[tmp].naking = 0;
2062                         UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num);
2063                 }
2064         }
2065         /* ...  and ep0out */
2066         if (cnak_pending & (1 << UDC_EP0OUT_IX)) {
2067                 DBG(dev, "CNAK pending for ep%d\n", UDC_EP0OUT_IX);
2068                 /* clear NAK by writing CNAK */
2069                 reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2070                 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2071                 writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2072                 dev->ep[UDC_EP0OUT_IX].naking = 0;
2073                 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX],
2074                                 dev->ep[UDC_EP0OUT_IX].num);
2075         }
2076 }
2077
2078 /* Enabling RX DMA after setup packet */
2079 static void udc_ep0_set_rde(struct udc *dev)
2080 {
2081         if (use_dma) {
2082                 /*
2083                  * only enable RXDMA when no data endpoint enabled
2084                  * or data is queued
2085                  */
2086                 if (!dev->data_ep_enabled || dev->data_ep_queued) {
2087                         udc_set_rde(dev);
2088                 } else {
2089                         /*
2090                          * setup timer for enabling RDE (to not enable
2091                          * RXFIFO DMA for data endpoints to early)
2092                          */
2093                         if (set_rde != 0 && !timer_pending(&udc_timer)) {
2094                                 udc_timer.expires =
2095                                         jiffies + HZ/UDC_RDE_TIMER_DIV;
2096                                 set_rde = 1;
2097                                 if (!stop_timer) {
2098                                         add_timer(&udc_timer);
2099                                 }
2100                         }
2101                 }
2102         }
2103 }
2104
2105
2106 /* Interrupt handler for data OUT traffic */
2107 static irqreturn_t udc_data_out_isr(struct udc *dev, int ep_ix)
2108 {
2109         irqreturn_t             ret_val = IRQ_NONE;
2110         u32                     tmp;
2111         struct udc_ep           *ep;
2112         struct udc_request      *req;
2113         unsigned int            count;
2114         struct udc_data_dma     *td = NULL;
2115         unsigned                dma_done;
2116
2117         VDBG(dev, "ep%d irq\n", ep_ix);
2118         ep = &dev->ep[ep_ix];
2119
2120         tmp = readl(&ep->regs->sts);
2121         if (use_dma) {
2122                 /* BNA event ? */
2123                 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2124                         DBG(dev, "BNA ep%dout occured - DESPTR = %x \n",
2125                                         ep->num, readl(&ep->regs->desptr));
2126                         /* clear BNA */
2127                         writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts);
2128                         if (!ep->cancel_transfer)
2129                                 ep->bna_occurred = 1;
2130                         else
2131                                 ep->cancel_transfer = 0;
2132                         ret_val = IRQ_HANDLED;
2133                         goto finished;
2134                 }
2135         }
2136         /* HE event ? */
2137         if (tmp & AMD_BIT(UDC_EPSTS_HE)) {
2138                 dev_err(&dev->pdev->dev, "HE ep%dout occured\n", ep->num);
2139
2140                 /* clear HE */
2141                 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2142                 ret_val = IRQ_HANDLED;
2143                 goto finished;
2144         }
2145
2146         if (!list_empty(&ep->queue)) {
2147
2148                 /* next request */
2149                 req = list_entry(ep->queue.next,
2150                         struct udc_request, queue);
2151         } else {
2152                 req = NULL;
2153                 udc_rxfifo_pending = 1;
2154         }
2155         VDBG(dev, "req = %p\n", req);
2156         /* fifo mode */
2157         if (!use_dma) {
2158
2159                 /* read fifo */
2160                 if (req && udc_rxfifo_read(ep, req)) {
2161                         ret_val = IRQ_HANDLED;
2162
2163                         /* finish */
2164                         complete_req(ep, req, 0);
2165                         /* next request */
2166                         if (!list_empty(&ep->queue) && !ep->halted) {
2167                                 req = list_entry(ep->queue.next,
2168                                         struct udc_request, queue);
2169                         } else
2170                                 req = NULL;
2171                 }
2172
2173         /* DMA */
2174         } else if (!ep->cancel_transfer && req != NULL) {
2175                 ret_val = IRQ_HANDLED;
2176
2177                 /* check for DMA done */
2178                 if (!use_dma_ppb) {
2179                         dma_done = AMD_GETBITS(req->td_data->status,
2180                                                 UDC_DMA_OUT_STS_BS);
2181                 /* packet per buffer mode - rx bytes */
2182                 } else {
2183                         /*
2184                          * if BNA occurred then recover desc. from
2185                          * BNA dummy desc.
2186                          */
2187                         if (ep->bna_occurred) {
2188                                 VDBG(dev, "Recover desc. from BNA dummy\n");
2189                                 memcpy(req->td_data, ep->bna_dummy_req->td_data,
2190                                                 sizeof(struct udc_data_dma));
2191                                 ep->bna_occurred = 0;
2192                                 udc_init_bna_dummy(ep->req);
2193                         }
2194                         td = udc_get_last_dma_desc(req);
2195                         dma_done = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_BS);
2196                 }
2197                 if (dma_done == UDC_DMA_OUT_STS_BS_DMA_DONE) {
2198                         /* buffer fill mode - rx bytes */
2199                         if (!use_dma_ppb) {
2200                                 /* received number bytes */
2201                                 count = AMD_GETBITS(req->td_data->status,
2202                                                 UDC_DMA_OUT_STS_RXBYTES);
2203                                 VDBG(dev, "rx bytes=%u\n", count);
2204                         /* packet per buffer mode - rx bytes */
2205                         } else {
2206                                 VDBG(dev, "req->td_data=%p\n", req->td_data);
2207                                 VDBG(dev, "last desc = %p\n", td);
2208                                 /* received number bytes */
2209                                 if (use_dma_ppb_du) {
2210                                         /* every desc. counts bytes */
2211                                         count = udc_get_ppbdu_rxbytes(req);
2212                                 } else {
2213                                         /* last desc. counts bytes */
2214                                         count = AMD_GETBITS(td->status,
2215                                                 UDC_DMA_OUT_STS_RXBYTES);
2216                                         if (!count && req->req.length
2217                                                 == UDC_DMA_MAXPACKET) {
2218                                                 /*
2219                                                  * on 64k packets the RXBYTES
2220                                                  * field is zero
2221                                                  */
2222                                                 count = UDC_DMA_MAXPACKET;
2223                                         }
2224                                 }
2225                                 VDBG(dev, "last desc rx bytes=%u\n", count);
2226                         }
2227
2228                         tmp = req->req.length - req->req.actual;
2229                         if (count > tmp) {
2230                                 if ((tmp % ep->ep.maxpacket) != 0) {
2231                                         DBG(dev, "%s: rx %db, space=%db\n",
2232                                                 ep->ep.name, count, tmp);
2233                                         req->req.status = -EOVERFLOW;
2234                                 }
2235                                 count = tmp;
2236                         }
2237                         req->req.actual += count;
2238                         req->dma_going = 0;
2239                         /* complete request */
2240                         complete_req(ep, req, 0);
2241
2242                         /* next request */
2243                         if (!list_empty(&ep->queue) && !ep->halted) {
2244                                 req = list_entry(ep->queue.next,
2245                                         struct udc_request,
2246                                         queue);
2247                                 /*
2248                                  * DMA may be already started by udc_queue()
2249                                  * called by gadget drivers completion
2250                                  * routine. This happens when queue
2251                                  * holds one request only.
2252                                  */
2253                                 if (req->dma_going == 0) {
2254                                         /* next dma */
2255                                         if (prep_dma(ep, req, GFP_ATOMIC) != 0)
2256                                                 goto finished;
2257                                         /* write desc pointer */
2258                                         writel(req->td_phys,
2259                                                 &ep->regs->desptr);
2260                                         req->dma_going = 1;
2261                                         /* enable DMA */
2262                                         udc_set_rde(dev);
2263                                 }
2264                         } else {
2265                                 /*
2266                                  * implant BNA dummy descriptor to allow
2267                                  * RXFIFO opening by RDE
2268                                  */
2269                                 if (ep->bna_dummy_req) {
2270                                         /* write desc pointer */
2271                                         writel(ep->bna_dummy_req->td_phys,
2272                                                 &ep->regs->desptr);
2273                                         ep->bna_occurred = 0;
2274                                 }
2275
2276                                 /*
2277                                  * schedule timer for setting RDE if queue
2278                                  * remains empty to allow ep0 packets pass
2279                                  * through
2280                                  */
2281                                 if (set_rde != 0
2282                                                 && !timer_pending(&udc_timer)) {
2283                                         udc_timer.expires =
2284                                                 jiffies
2285                                                 + HZ*UDC_RDE_TIMER_SECONDS;
2286                                         set_rde = 1;
2287                                         if (!stop_timer) {
2288                                                 add_timer(&udc_timer);
2289                                         }
2290                                 }
2291                                 if (ep->num != UDC_EP0OUT_IX)
2292                                         dev->data_ep_queued = 0;
2293                         }
2294
2295                 } else {
2296                         /*
2297                         * RX DMA must be reenabled for each desc in PPBDU mode
2298                         * and must be enabled for PPBNDU mode in case of BNA
2299                         */
2300                         udc_set_rde(dev);
2301                 }
2302
2303         } else if (ep->cancel_transfer) {
2304                 ret_val = IRQ_HANDLED;
2305                 ep->cancel_transfer = 0;
2306         }
2307
2308         /* check pending CNAKS */
2309         if (cnak_pending) {
2310                 /* CNAk processing when rxfifo empty only */
2311                 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
2312                         udc_process_cnak_queue(dev);
2313                 }
2314         }
2315
2316         /* clear OUT bits in ep status */
2317         writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts);
2318 finished:
2319         return ret_val;
2320 }
2321
2322 /* Interrupt handler for data IN traffic */
2323 static irqreturn_t udc_data_in_isr(struct udc *dev, int ep_ix)
2324 {
2325         irqreturn_t ret_val = IRQ_NONE;
2326         u32 tmp;
2327         u32 epsts;
2328         struct udc_ep *ep;
2329         struct udc_request *req;
2330         struct udc_data_dma *td;
2331         unsigned dma_done;
2332         unsigned len;
2333
2334         ep = &dev->ep[ep_ix];
2335
2336         epsts = readl(&ep->regs->sts);
2337         if (use_dma) {
2338                 /* BNA ? */
2339                 if (epsts & AMD_BIT(UDC_EPSTS_BNA)) {
2340                         dev_err(&dev->pdev->dev,
2341                                 "BNA ep%din occured - DESPTR = %08lx \n",
2342                                 ep->num,
2343                                 (unsigned long) readl(&ep->regs->desptr));
2344
2345                         /* clear BNA */
2346                         writel(epsts, &ep->regs->sts);
2347                         ret_val = IRQ_HANDLED;
2348                         goto finished;
2349                 }
2350         }
2351         /* HE event ? */
2352         if (epsts & AMD_BIT(UDC_EPSTS_HE)) {
2353                 dev_err(&dev->pdev->dev,
2354                         "HE ep%dn occured - DESPTR = %08lx \n",
2355                         ep->num, (unsigned long) readl(&ep->regs->desptr));
2356
2357                 /* clear HE */
2358                 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2359                 ret_val = IRQ_HANDLED;
2360                 goto finished;
2361         }
2362
2363         /* DMA completion */
2364         if (epsts & AMD_BIT(UDC_EPSTS_TDC)) {
2365                 VDBG(dev, "TDC set- completion\n");
2366                 ret_val = IRQ_HANDLED;
2367                 if (!ep->cancel_transfer && !list_empty(&ep->queue)) {
2368                         req = list_entry(ep->queue.next,
2369                                         struct udc_request, queue);
2370                         /*
2371                          * length bytes transfered
2372                          * check dma done of last desc. in PPBDU mode
2373                          */
2374                         if (use_dma_ppb_du) {
2375                                 td = udc_get_last_dma_desc(req);
2376                                 if (td) {
2377                                         dma_done =
2378                                                 AMD_GETBITS(td->status,
2379                                                 UDC_DMA_IN_STS_BS);
2380                                         /* don't care DMA done */
2381                                         req->req.actual = req->req.length;
2382                                 }
2383                         } else {
2384                                 /* assume all bytes transferred */
2385                                 req->req.actual = req->req.length;
2386                         }
2387
2388                         if (req->req.actual == req->req.length) {
2389                                 /* complete req */
2390                                 complete_req(ep, req, 0);
2391                                 req->dma_going = 0;
2392                                 /* further request available ? */
2393                                 if (list_empty(&ep->queue)) {
2394                                         /* disable interrupt */
2395                                         tmp = readl(&dev->regs->ep_irqmsk);
2396                                         tmp |= AMD_BIT(ep->num);
2397                                         writel(tmp, &dev->regs->ep_irqmsk);
2398                                 }
2399                         }
2400                 }
2401                 ep->cancel_transfer = 0;
2402
2403         }
2404         /*
2405          * status reg has IN bit set and TDC not set (if TDC was handled,
2406          * IN must not be handled (UDC defect) ?
2407          */
2408         if ((epsts & AMD_BIT(UDC_EPSTS_IN))
2409                         && !(epsts & AMD_BIT(UDC_EPSTS_TDC))) {
2410                 ret_val = IRQ_HANDLED;
2411                 if (!list_empty(&ep->queue)) {
2412                         /* next request */
2413                         req = list_entry(ep->queue.next,
2414                                         struct udc_request, queue);
2415                         /* FIFO mode */
2416                         if (!use_dma) {
2417                                 /* write fifo */
2418                                 udc_txfifo_write(ep, &req->req);
2419                                 len = req->req.length - req->req.actual;
2420                                                 if (len > ep->ep.maxpacket)
2421                                                         len = ep->ep.maxpacket;
2422                                                 req->req.actual += len;
2423                                 if (req->req.actual == req->req.length
2424                                         || (len != ep->ep.maxpacket)) {
2425                                         /* complete req */
2426                                         complete_req(ep, req, 0);
2427                                 }
2428                         /* DMA */
2429                         } else if (req && !req->dma_going) {
2430                                 VDBG(dev, "IN DMA : req=%p req->td_data=%p\n",
2431                                         req, req->td_data);
2432                                 if (req->td_data) {
2433
2434                                         req->dma_going = 1;
2435
2436                                         /*
2437                                          * unset L bit of first desc.
2438                                          * for chain
2439                                          */
2440                                         if (use_dma_ppb && req->req.length >
2441                                                         ep->ep.maxpacket) {
2442                                                 req->td_data->status &=
2443                                                         AMD_CLEAR_BIT(
2444                                                         UDC_DMA_IN_STS_L);
2445                                         }
2446
2447                                         /* write desc pointer */
2448                                         writel(req->td_phys, &ep->regs->desptr);
2449
2450                                         /* set HOST READY */
2451                                         req->td_data->status =
2452                                                 AMD_ADDBITS(
2453                                                 req->td_data->status,
2454                                                 UDC_DMA_IN_STS_BS_HOST_READY,
2455                                                 UDC_DMA_IN_STS_BS);
2456
2457                                         /* set poll demand bit */
2458                                         tmp = readl(&ep->regs->ctl);
2459                                         tmp |= AMD_BIT(UDC_EPCTL_P);
2460                                         writel(tmp, &ep->regs->ctl);
2461                                 }
2462                         }
2463
2464                 } else if (!use_dma && ep->in) {
2465                         /* disable interrupt */
2466                         tmp = readl(
2467                                 &dev->regs->ep_irqmsk);
2468                         tmp |= AMD_BIT(ep->num);
2469                         writel(tmp,
2470                                 &dev->regs->ep_irqmsk);
2471                 }
2472         }
2473         /* clear status bits */
2474         writel(epsts, &ep->regs->sts);
2475
2476 finished:
2477         return ret_val;
2478
2479 }
2480
2481 /* Interrupt handler for Control OUT traffic */
2482 static irqreturn_t udc_control_out_isr(struct udc *dev)
2483 __releases(dev->lock)
2484 __acquires(dev->lock)
2485 {
2486         irqreturn_t ret_val = IRQ_NONE;
2487         u32 tmp;
2488         int setup_supported;
2489         u32 count;
2490         int set = 0;
2491         struct udc_ep   *ep;
2492         struct udc_ep   *ep_tmp;
2493
2494         ep = &dev->ep[UDC_EP0OUT_IX];
2495
2496         /* clear irq */
2497         writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts);
2498
2499         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2500         /* check BNA and clear if set */
2501         if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2502                 VDBG(dev, "ep0: BNA set\n");
2503                 writel(AMD_BIT(UDC_EPSTS_BNA),
2504                         &dev->ep[UDC_EP0OUT_IX].regs->sts);
2505                 ep->bna_occurred = 1;
2506                 ret_val = IRQ_HANDLED;
2507                 goto finished;
2508         }
2509
2510         /* type of data: SETUP or DATA 0 bytes */
2511         tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT);
2512         VDBG(dev, "data_typ = %x\n", tmp);
2513
2514         /* setup data */
2515         if (tmp == UDC_EPSTS_OUT_SETUP) {
2516                 ret_val = IRQ_HANDLED;
2517
2518                 ep->dev->stall_ep0in = 0;
2519                 dev->waiting_zlp_ack_ep0in = 0;
2520
2521                 /* set NAK for EP0_IN */
2522                 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2523                 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
2524                 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2525                 dev->ep[UDC_EP0IN_IX].naking = 1;
2526                 /* get setup data */
2527                 if (use_dma) {
2528
2529                         /* clear OUT bits in ep status */
2530                         writel(UDC_EPSTS_OUT_CLEAR,
2531                                 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2532
2533                         setup_data.data[0] =
2534                                 dev->ep[UDC_EP0OUT_IX].td_stp->data12;
2535                         setup_data.data[1] =
2536                                 dev->ep[UDC_EP0OUT_IX].td_stp->data34;
2537                         /* set HOST READY */
2538                         dev->ep[UDC_EP0OUT_IX].td_stp->status =
2539                                         UDC_DMA_STP_STS_BS_HOST_READY;
2540                 } else {
2541                         /* read fifo */
2542                         udc_rxfifo_read_dwords(dev, setup_data.data, 2);
2543                 }
2544
2545                 /* determine direction of control data */
2546                 if ((setup_data.request.bRequestType & USB_DIR_IN) != 0) {
2547                         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
2548                         /* enable RDE */
2549                         udc_ep0_set_rde(dev);
2550                         set = 0;
2551                 } else {
2552                         dev->gadget.ep0 = &dev->ep[UDC_EP0OUT_IX].ep;
2553                         /*
2554                          * implant BNA dummy descriptor to allow RXFIFO opening
2555                          * by RDE
2556                          */
2557                         if (ep->bna_dummy_req) {
2558                                 /* write desc pointer */
2559                                 writel(ep->bna_dummy_req->td_phys,
2560                                         &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2561                                 ep->bna_occurred = 0;
2562                         }
2563
2564                         set = 1;
2565                         dev->ep[UDC_EP0OUT_IX].naking = 1;
2566                         /*
2567                          * setup timer for enabling RDE (to not enable
2568                          * RXFIFO DMA for data to early)
2569                          */
2570                         set_rde = 1;
2571                         if (!timer_pending(&udc_timer)) {
2572                                 udc_timer.expires = jiffies +
2573                                                         HZ/UDC_RDE_TIMER_DIV;
2574                                 if (!stop_timer) {
2575                                         add_timer(&udc_timer);
2576                                 }
2577                         }
2578                 }
2579
2580                 /*
2581                  * mass storage reset must be processed here because
2582                  * next packet may be a CLEAR_FEATURE HALT which would not
2583                  * clear the stall bit when no STALL handshake was received
2584                  * before (autostall can cause this)
2585                  */
2586                 if (setup_data.data[0] == UDC_MSCRES_DWORD0
2587                                 && setup_data.data[1] == UDC_MSCRES_DWORD1) {
2588                         DBG(dev, "MSC Reset\n");
2589                         /*
2590                          * clear stall bits
2591                          * only one IN and OUT endpoints are handled
2592                          */
2593                         ep_tmp = &udc->ep[UDC_EPIN_IX];
2594                         udc_set_halt(&ep_tmp->ep, 0);
2595                         ep_tmp = &udc->ep[UDC_EPOUT_IX];
2596                         udc_set_halt(&ep_tmp->ep, 0);
2597                 }
2598
2599                 /* call gadget with setup data received */
2600                 spin_unlock(&dev->lock);
2601                 setup_supported = dev->driver->setup(&dev->gadget,
2602                                                 &setup_data.request);
2603                 spin_lock(&dev->lock);
2604
2605                 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2606                 /* ep0 in returns data (not zlp) on IN phase */
2607                 if (setup_supported >= 0 && setup_supported <
2608                                 UDC_EP0IN_MAXPACKET) {
2609                         /* clear NAK by writing CNAK in EP0_IN */
2610                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2611                         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2612                         dev->ep[UDC_EP0IN_IX].naking = 0;
2613                         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
2614
2615                 /* if unsupported request then stall */
2616                 } else if (setup_supported < 0) {
2617                         tmp |= AMD_BIT(UDC_EPCTL_S);
2618                         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2619                 } else
2620                         dev->waiting_zlp_ack_ep0in = 1;
2621
2622
2623                 /* clear NAK by writing CNAK in EP0_OUT */
2624                 if (!set) {
2625                         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2626                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2627                         writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2628                         dev->ep[UDC_EP0OUT_IX].naking = 0;
2629                         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
2630                 }
2631
2632                 if (!use_dma) {
2633                         /* clear OUT bits in ep status */
2634                         writel(UDC_EPSTS_OUT_CLEAR,
2635                                 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2636                 }
2637
2638         /* data packet 0 bytes */
2639         } else if (tmp == UDC_EPSTS_OUT_DATA) {
2640                 /* clear OUT bits in ep status */
2641                 writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts);
2642
2643                 /* get setup data: only 0 packet */
2644                 if (use_dma) {
2645                         /* no req if 0 packet, just reactivate */
2646                         if (list_empty(&dev->ep[UDC_EP0OUT_IX].queue)) {
2647                                 VDBG(dev, "ZLP\n");
2648
2649                                 /* set HOST READY */
2650                                 dev->ep[UDC_EP0OUT_IX].td->status =
2651                                         AMD_ADDBITS(
2652                                         dev->ep[UDC_EP0OUT_IX].td->status,
2653                                         UDC_DMA_OUT_STS_BS_HOST_READY,
2654                                         UDC_DMA_OUT_STS_BS);
2655                                 /* enable RDE */
2656                                 udc_ep0_set_rde(dev);
2657                                 ret_val = IRQ_HANDLED;
2658
2659                         } else {
2660                                 /* control write */
2661                                 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2662                                 /* re-program desc. pointer for possible ZLPs */
2663                                 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
2664                                         &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2665                                 /* enable RDE */
2666                                 udc_ep0_set_rde(dev);
2667                         }
2668                 } else {
2669
2670                         /* received number bytes */
2671                         count = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2672                         count = AMD_GETBITS(count, UDC_EPSTS_RX_PKT_SIZE);
2673                         /* out data for fifo mode not working */
2674                         count = 0;
2675
2676                         /* 0 packet or real data ? */
2677                         if (count != 0) {
2678                                 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2679                         } else {
2680                                 /* dummy read confirm */
2681                                 readl(&dev->ep[UDC_EP0OUT_IX].regs->confirm);
2682                                 ret_val = IRQ_HANDLED;
2683                         }
2684                 }
2685         }
2686
2687         /* check pending CNAKS */
2688         if (cnak_pending) {
2689                 /* CNAk processing when rxfifo empty only */
2690                 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
2691                         udc_process_cnak_queue(dev);
2692                 }
2693         }
2694
2695 finished:
2696         return ret_val;
2697 }
2698
2699 /* Interrupt handler for Control IN traffic */
2700 static irqreturn_t udc_control_in_isr(struct udc *dev)
2701 {
2702         irqreturn_t ret_val = IRQ_NONE;
2703         u32 tmp;
2704         struct udc_ep *ep;
2705         struct udc_request *req;
2706         unsigned len;
2707
2708         ep = &dev->ep[UDC_EP0IN_IX];
2709
2710         /* clear irq */
2711         writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts);
2712
2713         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts);
2714         /* DMA completion */
2715         if (tmp & AMD_BIT(UDC_EPSTS_TDC)) {
2716                 VDBG(dev, "isr: TDC clear \n");
2717                 ret_val = IRQ_HANDLED;
2718
2719                 /* clear TDC bit */
2720                 writel(AMD_BIT(UDC_EPSTS_TDC),
2721                                 &dev->ep[UDC_EP0IN_IX].regs->sts);
2722
2723         /* status reg has IN bit set ? */
2724         } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) {
2725                 ret_val = IRQ_HANDLED;
2726
2727                 if (ep->dma) {
2728                         /* clear IN bit */
2729                         writel(AMD_BIT(UDC_EPSTS_IN),
2730                                 &dev->ep[UDC_EP0IN_IX].regs->sts);
2731                 }
2732                 if (dev->stall_ep0in) {
2733                         DBG(dev, "stall ep0in\n");
2734                         /* halt ep0in */
2735                         tmp = readl(&ep->regs->ctl);
2736                         tmp |= AMD_BIT(UDC_EPCTL_S);
2737                         writel(tmp, &ep->regs->ctl);
2738                 } else {
2739                         if (!list_empty(&ep->queue)) {
2740                                 /* next request */
2741                                 req = list_entry(ep->queue.next,
2742                                                 struct udc_request, queue);
2743
2744                                 if (ep->dma) {
2745                                         /* write desc pointer */
2746                                         writel(req->td_phys, &ep->regs->desptr);
2747                                         /* set HOST READY */
2748                                         req->td_data->status =
2749                                                 AMD_ADDBITS(
2750                                                 req->td_data->status,
2751                                                 UDC_DMA_STP_STS_BS_HOST_READY,
2752                                                 UDC_DMA_STP_STS_BS);
2753
2754                                         /* set poll demand bit */
2755                                         tmp =
2756                                         readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2757                                         tmp |= AMD_BIT(UDC_EPCTL_P);
2758                                         writel(tmp,
2759                                         &dev->ep[UDC_EP0IN_IX].regs->ctl);
2760
2761                                         /* all bytes will be transferred */
2762                                         req->req.actual = req->req.length;
2763
2764                                         /* complete req */
2765                                         complete_req(ep, req, 0);
2766
2767                                 } else {
2768                                         /* write fifo */
2769                                         udc_txfifo_write(ep, &req->req);
2770
2771                                         /* lengh bytes transfered */
2772                                         len = req->req.length - req->req.actual;
2773                                         if (len > ep->ep.maxpacket)
2774                                                 len = ep->ep.maxpacket;
2775
2776                                         req->req.actual += len;
2777                                         if (req->req.actual == req->req.length
2778                                                 || (len != ep->ep.maxpacket)) {
2779                                                 /* complete req */
2780                                                 complete_req(ep, req, 0);
2781                                         }
2782                                 }
2783
2784                         }
2785                 }
2786                 ep->halted = 0;
2787                 dev->stall_ep0in = 0;
2788                 if (!ep->dma) {
2789                         /* clear IN bit */
2790                         writel(AMD_BIT(UDC_EPSTS_IN),
2791                                 &dev->ep[UDC_EP0IN_IX].regs->sts);
2792                 }
2793         }
2794
2795         return ret_val;
2796 }
2797
2798
2799 /* Interrupt handler for global device events */
2800 static irqreturn_t udc_dev_isr(struct udc *dev, u32 dev_irq)
2801 __releases(dev->lock)
2802 __acquires(dev->lock)
2803 {
2804         irqreturn_t ret_val = IRQ_NONE;
2805         u32 tmp;
2806         u32 cfg;
2807         struct udc_ep *ep;
2808         u16 i;
2809         u8 udc_csr_epix;
2810
2811         /* SET_CONFIG irq ? */
2812         if (dev_irq & AMD_BIT(UDC_DEVINT_SC)) {
2813                 ret_val = IRQ_HANDLED;
2814
2815                 /* read config value */
2816                 tmp = readl(&dev->regs->sts);
2817                 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG);
2818                 DBG(dev, "SET_CONFIG interrupt: config=%d\n", cfg);
2819                 dev->cur_config = cfg;
2820                 dev->set_cfg_not_acked = 1;
2821
2822                 /* make usb request for gadget driver */
2823                 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2824                 setup_data.request.bRequest = USB_REQ_SET_CONFIGURATION;
2825                 setup_data.request.wValue = cpu_to_le16(dev->cur_config);
2826
2827                 /* programm the NE registers */
2828                 for (i = 0; i < UDC_EP_NUM; i++) {
2829                         ep = &dev->ep[i];
2830                         if (ep->in) {
2831
2832                                 /* ep ix in UDC CSR register space */
2833                                 udc_csr_epix = ep->num;
2834
2835
2836                         /* OUT ep */
2837                         } else {
2838                                 /* ep ix in UDC CSR register space */
2839                                 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2840                         }
2841
2842                         tmp = readl(&dev->csr->ne[udc_csr_epix]);
2843                         /* ep cfg */
2844                         tmp = AMD_ADDBITS(tmp, ep->dev->cur_config,
2845                                                 UDC_CSR_NE_CFG);
2846                         /* write reg */
2847                         writel(tmp, &dev->csr->ne[udc_csr_epix]);
2848
2849                         /* clear stall bits */
2850                         ep->halted = 0;
2851                         tmp = readl(&ep->regs->ctl);
2852                         tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2853                         writel(tmp, &ep->regs->ctl);
2854                 }
2855                 /* call gadget zero with setup data received */
2856                 spin_unlock(&dev->lock);
2857                 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2858                 spin_lock(&dev->lock);
2859
2860         } /* SET_INTERFACE ? */
2861         if (dev_irq & AMD_BIT(UDC_DEVINT_SI)) {
2862                 ret_val = IRQ_HANDLED;
2863
2864                 dev->set_cfg_not_acked = 1;
2865                 /* read interface and alt setting values */
2866                 tmp = readl(&dev->regs->sts);
2867                 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT);
2868                 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF);
2869
2870                 /* make usb request for gadget driver */
2871                 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2872                 setup_data.request.bRequest = USB_REQ_SET_INTERFACE;
2873                 setup_data.request.bRequestType = USB_RECIP_INTERFACE;
2874                 setup_data.request.wValue = cpu_to_le16(dev->cur_alt);
2875                 setup_data.request.wIndex = cpu_to_le16(dev->cur_intf);
2876
2877                 DBG(dev, "SET_INTERFACE interrupt: alt=%d intf=%d\n",
2878                                 dev->cur_alt, dev->cur_intf);
2879
2880                 /* programm the NE registers */
2881                 for (i = 0; i < UDC_EP_NUM; i++) {
2882                         ep = &dev->ep[i];
2883                         if (ep->in) {
2884
2885                                 /* ep ix in UDC CSR register space */
2886                                 udc_csr_epix = ep->num;
2887
2888
2889                         /* OUT ep */
2890                         } else {
2891                                 /* ep ix in UDC CSR register space */
2892                                 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2893                         }
2894
2895                         /* UDC CSR reg */
2896                         /* set ep values */
2897                         tmp = readl(&dev->csr->ne[udc_csr_epix]);
2898                         /* ep interface */
2899                         tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf,
2900                                                 UDC_CSR_NE_INTF);
2901                         /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2902                         /* ep alt */
2903                         tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt,
2904                                                 UDC_CSR_NE_ALT);
2905                         /* write reg */
2906                         writel(tmp, &dev->csr->ne[udc_csr_epix]);
2907
2908                         /* clear stall bits */
2909                         ep->halted = 0;
2910                         tmp = readl(&ep->regs->ctl);
2911                         tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2912                         writel(tmp, &ep->regs->ctl);
2913                 }
2914
2915                 /* call gadget zero with setup data received */
2916                 spin_unlock(&dev->lock);
2917                 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2918                 spin_lock(&dev->lock);
2919
2920         } /* USB reset */
2921         if (dev_irq & AMD_BIT(UDC_DEVINT_UR)) {
2922                 DBG(dev, "USB Reset interrupt\n");
2923                 ret_val = IRQ_HANDLED;
2924
2925                 /* allow soft reset when suspend occurs */
2926                 soft_reset_occured = 0;
2927
2928                 dev->waiting_zlp_ack_ep0in = 0;
2929                 dev->set_cfg_not_acked = 0;
2930
2931                 /* mask not needed interrupts */
2932                 udc_mask_unused_interrupts(dev);
2933
2934                 /* call gadget to resume and reset configs etc. */
2935                 spin_unlock(&dev->lock);
2936                 if (dev->sys_suspended && dev->driver->resume) {
2937                         dev->driver->resume(&dev->gadget);
2938                         dev->sys_suspended = 0;
2939                 }
2940                 dev->driver->disconnect(&dev->gadget);
2941                 spin_lock(&dev->lock);
2942
2943                 /* disable ep0 to empty req queue */
2944                 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2945                 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2946
2947                 /* soft reset when rxfifo not empty */
2948                 tmp = readl(&dev->regs->sts);
2949                 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2950                                 && !soft_reset_after_usbreset_occured) {
2951                         udc_soft_reset(dev);
2952                         soft_reset_after_usbreset_occured++;
2953                 }
2954
2955                 /*
2956                  * DMA reset to kill potential old DMA hw hang,
2957                  * POLL bit is already reset by ep_init() through
2958                  * disconnect()
2959                  */
2960                 DBG(dev, "DMA machine reset\n");
2961                 tmp = readl(&dev->regs->cfg);
2962                 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg);
2963                 writel(tmp, &dev->regs->cfg);
2964
2965                 /* put into initial config */
2966                 udc_basic_init(dev);
2967
2968                 /* enable device setup interrupts */
2969                 udc_enable_dev_setup_interrupts(dev);
2970
2971                 /* enable suspend interrupt */
2972                 tmp = readl(&dev->regs->irqmsk);
2973                 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US);
2974                 writel(tmp, &dev->regs->irqmsk);
2975
2976         } /* USB suspend */
2977         if (dev_irq & AMD_BIT(UDC_DEVINT_US)) {
2978                 DBG(dev, "USB Suspend interrupt\n");
2979                 ret_val = IRQ_HANDLED;
2980                 if (dev->driver->suspend) {
2981                         spin_unlock(&dev->lock);
2982                         dev->sys_suspended = 1;
2983                         dev->driver->suspend(&dev->gadget);
2984                         spin_lock(&dev->lock);
2985                 }
2986         } /* new speed ? */
2987         if (dev_irq & AMD_BIT(UDC_DEVINT_ENUM)) {
2988                 DBG(dev, "ENUM interrupt\n");
2989                 ret_val = IRQ_HANDLED;
2990                 soft_reset_after_usbreset_occured = 0;
2991
2992                 /* disable ep0 to empty req queue */
2993                 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2994                 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2995
2996                 /* link up all endpoints */
2997                 udc_setup_endpoints(dev);
2998                 if (dev->gadget.speed == USB_SPEED_HIGH) {
2999                         dev_info(&dev->pdev->dev, "Connect: speed = %s\n",
3000                                 "high");
3001                 } else if (dev->gadget.speed == USB_SPEED_FULL) {
3002                         dev_info(&dev->pdev->dev, "Connect: speed = %s\n",
3003                                 "full");
3004                 }
3005
3006                 /* init ep 0 */
3007                 activate_control_endpoints(dev);
3008
3009                 /* enable ep0 interrupts */
3010                 udc_enable_ep0_interrupts(dev);
3011         }
3012         /* session valid change interrupt */
3013         if (dev_irq & AMD_BIT(UDC_DEVINT_SVC)) {
3014                 DBG(dev, "USB SVC interrupt\n");
3015                 ret_val = IRQ_HANDLED;
3016
3017                 /* check that session is not valid to detect disconnect */
3018                 tmp = readl(&dev->regs->sts);
3019                 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) {
3020                         /* disable suspend interrupt */
3021                         tmp = readl(&dev->regs->irqmsk);
3022                         tmp |= AMD_BIT(UDC_DEVINT_US);
3023                         writel(tmp, &dev->regs->irqmsk);
3024                         DBG(dev, "USB Disconnect (session valid low)\n");
3025                         /* cleanup on disconnect */
3026                         usb_disconnect(udc);
3027                 }
3028
3029         }
3030
3031         return ret_val;
3032 }
3033
3034 /* Interrupt Service Routine, see Linux Kernel Doc for parameters */
3035 static irqreturn_t udc_irq(int irq, void *pdev)
3036 {
3037         struct udc *dev = pdev;
3038         u32 reg;
3039         u16 i;
3040         u32 ep_irq;
3041         irqreturn_t ret_val = IRQ_NONE;
3042
3043         spin_lock(&dev->lock);
3044
3045         /* check for ep irq */
3046         reg = readl(&dev->regs->ep_irqsts);
3047         if (reg) {
3048                 if (reg & AMD_BIT(UDC_EPINT_OUT_EP0))
3049                         ret_val |= udc_control_out_isr(dev);
3050                 if (reg & AMD_BIT(UDC_EPINT_IN_EP0))
3051                         ret_val |= udc_control_in_isr(dev);
3052
3053                 /*
3054                  * data endpoint
3055                  * iterate ep's
3056                  */
3057                 for (i = 1; i < UDC_EP_NUM; i++) {
3058                         ep_irq = 1 << i;
3059                         if (!(reg & ep_irq) || i == UDC_EPINT_OUT_EP0)
3060                                 continue;
3061
3062                         /* clear irq status */
3063                         writel(ep_irq, &dev->regs->ep_irqsts);
3064
3065                         /* irq for out ep ? */
3066                         if (i > UDC_EPIN_NUM)
3067                                 ret_val |= udc_data_out_isr(dev, i);
3068                         else
3069                                 ret_val |= udc_data_in_isr(dev, i);
3070                 }
3071
3072         }
3073
3074
3075         /* check for dev irq */
3076         reg = readl(&dev->regs->irqsts);
3077         if (reg) {
3078                 /* clear irq */
3079                 writel(reg, &dev->regs->irqsts);
3080                 ret_val |= udc_dev_isr(dev, reg);
3081         }
3082
3083
3084         spin_unlock(&dev->lock);
3085         return ret_val;
3086 }
3087
3088 /* Tears down device */
3089 static void gadget_release(struct device *pdev)
3090 {
3091         struct amd5536udc *dev = dev_get_drvdata(pdev);
3092         kfree(dev);
3093 }
3094
3095 /* Cleanup on device remove */
3096 static void udc_remove(struct udc *dev)
3097 {
3098         /* remove timer */
3099         stop_timer++;
3100         if (timer_pending(&udc_timer))
3101                 wait_for_completion(&on_exit);
3102         if (udc_timer.data)
3103                 del_timer_sync(&udc_timer);
3104         /* remove pollstall timer */
3105         stop_pollstall_timer++;
3106         if (timer_pending(&udc_pollstall_timer))
3107                 wait_for_completion(&on_pollstall_exit);
3108         if (udc_pollstall_timer.data)
3109                 del_timer_sync(&udc_pollstall_timer);
3110         udc = NULL;
3111 }
3112
3113 /* Reset all pci context */
3114 static void udc_pci_remove(struct pci_dev *pdev)
3115 {
3116         struct udc              *dev;
3117
3118         dev = pci_get_drvdata(pdev);
3119
3120         /* gadget driver must not be registered */
3121         BUG_ON(dev->driver != NULL);
3122
3123         /* dma pool cleanup */
3124         if (dev->data_requests)
3125                 pci_pool_destroy(dev->data_requests);
3126
3127         if (dev->stp_requests) {
3128                 /* cleanup DMA desc's for ep0in */
3129                 pci_pool_free(dev->stp_requests,
3130                         dev->ep[UDC_EP0OUT_IX].td_stp,
3131                         dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3132                 pci_pool_free(dev->stp_requests,
3133                         dev->ep[UDC_EP0OUT_IX].td,
3134                         dev->ep[UDC_EP0OUT_IX].td_phys);
3135
3136                 pci_pool_destroy(dev->stp_requests);
3137         }
3138
3139         /* reset controller */
3140         writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
3141         if (dev->irq_registered)
3142                 free_irq(pdev->irq, dev);
3143         if (dev->regs)
3144                 iounmap(dev->regs);
3145         if (dev->mem_region)
3146                 release_mem_region(pci_resource_start(pdev, 0),
3147                                 pci_resource_len(pdev, 0));
3148         if (dev->active)
3149                 pci_disable_device(pdev);
3150
3151         device_unregister(&dev->gadget.dev);
3152         pci_set_drvdata(pdev, NULL);
3153
3154         udc_remove(dev);
3155 }
3156
3157 /* create dma pools on init */
3158 static int init_dma_pools(struct udc *dev)
3159 {
3160         struct udc_stp_dma      *td_stp;
3161         struct udc_data_dma     *td_data;
3162         int retval;
3163
3164         /* consistent DMA mode setting ? */
3165         if (use_dma_ppb) {
3166                 use_dma_bufferfill_mode = 0;
3167         } else {
3168                 use_dma_ppb_du = 0;
3169                 use_dma_bufferfill_mode = 1;
3170         }
3171
3172         /* DMA setup */
3173         dev->data_requests = dma_pool_create("data_requests", NULL,
3174                 sizeof(struct udc_data_dma), 0, 0);
3175         if (!dev->data_requests) {
3176                 DBG(dev, "can't get request data pool\n");
3177                 retval = -ENOMEM;
3178                 goto finished;
3179         }
3180
3181         /* EP0 in dma regs = dev control regs */
3182         dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;
3183
3184         /* dma desc for setup data */
3185         dev->stp_requests = dma_pool_create("setup requests", NULL,
3186                 sizeof(struct udc_stp_dma), 0, 0);
3187         if (!dev->stp_requests) {
3188                 DBG(dev, "can't get stp request pool\n");
3189                 retval = -ENOMEM;
3190                 goto finished;
3191         }
3192         /* setup */
3193         td_stp = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3194                                 &dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3195         if (td_stp == NULL) {
3196                 retval = -ENOMEM;
3197                 goto finished;
3198         }
3199         dev->ep[UDC_EP0OUT_IX].td_stp = td_stp;
3200
3201         /* data: 0 packets !? */
3202         td_data = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3203                                 &dev->ep[UDC_EP0OUT_IX].td_phys);
3204         if (td_data == NULL) {
3205                 retval = -ENOMEM;
3206                 goto finished;
3207         }
3208         dev->ep[UDC_EP0OUT_IX].td = td_data;
3209         return 0;
3210
3211 finished:
3212         return retval;
3213 }
3214
3215 /* Called by pci bus driver to init pci context */
3216 static int udc_pci_probe(
3217         struct pci_dev *pdev,
3218         const struct pci_device_id *id
3219 )
3220 {
3221         struct udc              *dev;
3222         unsigned long           resource;
3223         unsigned long           len;
3224         int                     retval = 0;
3225
3226         /* one udc only */
3227         if (udc) {
3228                 dev_dbg(&pdev->dev, "already probed\n");
3229                 return -EBUSY;
3230         }
3231
3232         /* init */
3233         dev = kzalloc(sizeof(struct udc), GFP_KERNEL);
3234         if (!dev) {
3235                 retval = -ENOMEM;
3236                 goto finished;
3237         }
3238
3239         /* pci setup */
3240         if (pci_enable_device(pdev) < 0) {
3241                 kfree(dev);
3242                 dev = NULL;
3243                 retval = -ENODEV;
3244                 goto finished;
3245         }
3246         dev->active = 1;
3247
3248         /* PCI resource allocation */
3249         resource = pci_resource_start(pdev, 0);
3250         len = pci_resource_len(pdev, 0);
3251
3252         if (!request_mem_region(resource, len, name)) {
3253                 dev_dbg(&pdev->dev, "pci device used already\n");
3254                 kfree(dev);
3255                 dev = NULL;
3256                 retval = -EBUSY;
3257                 goto finished;
3258         }
3259         dev->mem_region = 1;
3260
3261         dev->virt_addr = ioremap_nocache(resource, len);
3262         if (dev->virt_addr == NULL) {
3263                 dev_dbg(&pdev->dev, "start address cannot be mapped\n");
3264                 kfree(dev);
3265                 dev = NULL;
3266                 retval = -EFAULT;
3267                 goto finished;
3268         }
3269
3270         if (!pdev->irq) {
3271                 dev_err(&dev->pdev->dev, "irq not set\n");
3272                 kfree(dev);
3273                 dev = NULL;
3274                 retval = -ENODEV;
3275                 goto finished;
3276         }
3277
3278         spin_lock_init(&dev->lock);
3279         /* udc csr registers base */
3280         dev->csr = dev->virt_addr + UDC_CSR_ADDR;
3281         /* dev registers base */
3282         dev->regs = dev->virt_addr + UDC_DEVCFG_ADDR;
3283         /* ep registers base */
3284         dev->ep_regs = dev->virt_addr + UDC_EPREGS_ADDR;
3285         /* fifo's base */
3286         dev->rxfifo = (u32 __iomem *)(dev->virt_addr + UDC_RXFIFO_ADDR);
3287         dev->txfifo = (u32 __iomem *)(dev->virt_addr + UDC_TXFIFO_ADDR);
3288
3289         if (request_irq(pdev->irq, udc_irq, IRQF_SHARED, name, dev) != 0) {
3290                 dev_dbg(&dev->pdev->dev, "request_irq(%d) fail\n", pdev->irq);
3291                 kfree(dev);
3292                 dev = NULL;
3293                 retval = -EBUSY;
3294                 goto finished;
3295         }
3296         dev->irq_registered = 1;
3297
3298         pci_set_drvdata(pdev, dev);
3299
3300         /* chip revision for Hs AMD5536 */
3301         dev->chiprev = pdev->revision;
3302
3303         pci_set_master(pdev);
3304         pci_try_set_mwi(pdev);
3305
3306         /* init dma pools */
3307         if (use_dma) {
3308                 retval = init_dma_pools(dev);
3309                 if (retval != 0)
3310                         goto finished;
3311         }
3312
3313         dev->phys_addr = resource;
3314         dev->irq = pdev->irq;
3315         dev->pdev = pdev;
3316         dev->gadget.dev.parent = &pdev->dev;
3317         dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
3318
3319         /* general probing */
3320         if (udc_probe(dev) == 0)
3321                 return 0;
3322
3323 finished:
3324         if (dev)
3325                 udc_pci_remove(pdev);
3326         return retval;
3327 }
3328
3329 /* general probe */
3330 static int udc_probe(struct udc *dev)
3331 {
3332         char            tmp[128];
3333         u32             reg;
3334         int             retval;
3335
3336         /* mark timer as not initialized */
3337         udc_timer.data = 0;
3338         udc_pollstall_timer.data = 0;
3339
3340         /* device struct setup */
3341         dev->gadget.ops = &udc_ops;
3342
3343         dev_set_name(&dev->gadget.dev, "gadget");
3344         dev->gadget.dev.release = gadget_release;
3345         dev->gadget.name = name;
3346         dev->gadget.name = name;
3347         dev->gadget.is_dualspeed = 1;
3348
3349         /* init registers, interrupts, ... */
3350         startup_registers(dev);
3351
3352         dev_info(&dev->pdev->dev, "%s\n", mod_desc);
3353
3354         snprintf(tmp, sizeof tmp, "%d", dev->irq);
3355         dev_info(&dev->pdev->dev,
3356                 "irq %s, pci mem %08lx, chip rev %02x(Geode5536 %s)\n",
3357                 tmp, dev->phys_addr, dev->chiprev,
3358                 (dev->chiprev == UDC_HSA0_REV) ? "A0" : "B1");
3359         strcpy(tmp, UDC_DRIVER_VERSION_STRING);
3360         if (dev->chiprev == UDC_HSA0_REV) {
3361                 dev_err(&dev->pdev->dev, "chip revision is A0; too old\n");
3362                 retval = -ENODEV;
3363                 goto finished;
3364         }
3365         dev_info(&dev->pdev->dev,
3366                 "driver version: %s(for Geode5536 B1)\n", tmp);
3367         udc = dev;
3368
3369         retval = device_register(&dev->gadget.dev);
3370         if (retval)
3371                 goto finished;
3372
3373         /* timer init */
3374         init_timer(&udc_timer);
3375         udc_timer.function = udc_timer_function;
3376         udc_timer.data = 1;
3377         /* timer pollstall init */
3378         init_timer(&udc_pollstall_timer);
3379         udc_pollstall_timer.function = udc_pollstall_timer_function;
3380         udc_pollstall_timer.data = 1;
3381
3382         /* set SD */
3383         reg = readl(&dev->regs->ctl);
3384         reg |= AMD_BIT(UDC_DEVCTL_SD);
3385         writel(reg, &dev->regs->ctl);
3386
3387         /* print dev register info */
3388         print_regs(dev);
3389
3390         return 0;
3391
3392 finished:
3393         return retval;
3394 }
3395
3396 /* Initiates a remote wakeup */
3397 static int udc_remote_wakeup(struct udc *dev)
3398 {
3399         unsigned long flags;
3400         u32 tmp;
3401
3402         DBG(dev, "UDC initiates remote wakeup\n");
3403
3404         spin_lock_irqsave(&dev->lock, flags);
3405
3406         tmp = readl(&dev->regs->ctl);
3407         tmp |= AMD_BIT(UDC_DEVCTL_RES);
3408         writel(tmp, &dev->regs->ctl);
3409         tmp &= AMD_CLEAR_BIT(UDC_DEVCTL_RES);
3410         writel(tmp, &dev->regs->ctl);
3411
3412         spin_unlock_irqrestore(&dev->lock, flags);
3413         return 0;
3414 }
3415
3416 /* PCI device parameters */
3417 static const struct pci_device_id pci_id[] = {
3418         {
3419                 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x2096),
3420                 .class =        (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3421                 .class_mask =   0xffffffff,
3422         },
3423         {},
3424 };
3425 MODULE_DEVICE_TABLE(pci, pci_id);
3426
3427 /* PCI functions */
3428 static struct pci_driver udc_pci_driver = {
3429         .name =         (char *) name,
3430         .id_table =     pci_id,
3431         .probe =        udc_pci_probe,
3432         .remove =       udc_pci_remove,
3433 };
3434
3435 /* Inits driver */
3436 static int __init init(void)
3437 {
3438         return pci_register_driver(&udc_pci_driver);
3439 }
3440 module_init(init);
3441
3442 /* Cleans driver */
3443 static void __exit cleanup(void)
3444 {
3445         pci_unregister_driver(&udc_pci_driver);
3446 }
3447 module_exit(cleanup);
3448
3449 MODULE_DESCRIPTION(UDC_MOD_DESCRIPTION);
3450 MODULE_AUTHOR("Thomas Dahlmann");
3451 MODULE_LICENSE("GPL");