release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/tidspbridge/include/dspbridge/mbx_sh.h

   1 /*
   2  * mbx_sh.h
   3  *
   4  * DSP-BIOS Bridge driver support functions for TI OMAP processors.
   5  *
   6  * Definitions for shared mailbox cmd/data values.(used on both
   7  * the GPP and DSP sides).
   8  *
   9  * Copyright (C) 2008 Texas Instruments, Inc.
  10  *
  11  * This package is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  *
  15  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  17  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  18  */
  19
  20 /*
  21  *  Bridge usage of OMAP mailbox 1 is determined by the "class" of the
  22  *  mailbox interrupt's cmd value received. The class value are defined
  23  *  as a bit (10 thru 15) being set.
  24  *
  25  *  Note: Only 16 bits of each  is used. Other 16 bit data reg available.
  26  *
  27  *   16 bit Mbx bit defns:
  28  *
  29  * A). Exception/Error handling (Module DEH) : class = 0.
  30  *
  31  *    15         10                  0
  32  *   ---------------------------------
  33  *   |0|0|0|0|0|0|x|x|x|x|x|x|x|x|x|x|
  34  *   ---------------------------------
  35  *   |  (class)  | (module specific) |
  36  *
  37  *
  38  * B: DSP-DMA link driver channels (DDMA) : class = 1.
  39  *
  40  *    15         10                  0
  41  *   ---------------------------------
  42  *   |0|0|0|0|0|1|b|b|b|b|b|c|c|c|c|c|
  43  *   ---------------------------------
  44  *   |  (class)  | (module specific) |
  45  *
  46  *   where b -> buffer index  (32 DDMA buffers/chnl max)
  47  *         c -> channel Id    (32 DDMA chnls max)
  48  *
  49  *
  50  * C: Proc-copy link driver channels (PCPY) : class = 2.
  51  *
  52  *    15         10                  0
  53  *   ---------------------------------
  54  *   |0|0|0|0|1|0|x|x|x|x|x|x|x|x|x|x|
  55  *   ---------------------------------
  56  *   |  (class)  | (module specific) |
  57  *
  58  *
  59  * D: Zero-copy link driver channels (DDZC) : class = 4.
  60  *
  61  *    15         10                  0
  62  *   ---------------------------------
  63  *   |0|0|0|1|0|0|x|x|x|x|x|c|c|c|c|c|
  64  *   ---------------------------------
  65  *   |  (class)  | (module specific) |
  66  *
  67  *   where x -> not used
  68  *         c -> channel Id    (32 ZCPY chnls max)
  69  *
  70  *
  71  * E: Power management : class = 8.
  72  *
  73  *    15         10                  0
  74  *   ---------------------------------
  75  *   |0|0|1|0|0|0|x|x|x|x|x|c|c|c|c|c|
  76
  77  *      0010 00xx xxxc cccc
  78  *      0010 00nn pppp qqqq
  79  *      nn:
  80  *      00 = reserved
  81  *      01 = pwr state change
  82  *      10 = opp pre-change
  83  *      11 = opp post-change
  84  *
  85  *      if nn = pwr state change:
  86  *      pppp = don't care
  87  *      qqqq:
  88  *      0010 = hibernate
  89  *      0010 0001 0000 0010
  90  *      0110 = retention
  91  *      0010 0001 0000 0110
  92  *      others reserved
  93  *
  94  *      if nn = opp pre-change:
  95  *      pppp = current opp
  96  *      qqqq = next opp
  97  *
  98  *      if nn = opp post-change:
  99  *      pppp = prev opp
 100  *      qqqq = current opp
 101  *
 102  *   ---------------------------------
 103  *   |  (class)  | (module specific) |
 104  *
 105  *   where x -> not used
 106  *         c -> Power management command
 107  *
 108  */
 109
 110 #ifndef _MBX_SH_H
 111 #define _MBX_SH_H
 112
 113 #define MBX_CLASS_MSK      0xFC00       /* Class bits are 10 thru 15 */
 114 #define MBX_VALUE_MSK      0x03FF       /* Value is 0 thru 9 */
 115
 116 #define MBX_DEH_CLASS      0x0000       /* DEH owns Mbx INTR */
 117 #define MBX_DDMA_CLASS     0x0400       /* DSP-DMA link drvr chnls owns INTR */
 118 #define MBX_PCPY_CLASS     0x0800       /* PROC-COPY  " */
 119 #define MBX_ZCPY_CLASS     0x1000       /* ZERO-COPY  " */
 120 #define MBX_PM_CLASS       0x2000       /* Power Management */
 121 #define MBX_DBG_CLASS      0x4000       /* For debugging purpose */
 122
 123 /*
 124  * Exception Handler codes
 125  * Magic code used to determine if DSP signaled exception.
 126  */
 127 #define MBX_DEH_BASE        0x0
 128 #define MBX_DEH_USERS_BASE  0x100       /* 256 */
 129 #define MBX_DEH_LIMIT       0x3FF       /* 1023 */
 130 #define MBX_DEH_RESET       0x101       /* DSP RESET (DEH) */
 131 #define MBX_DEH_EMMU        0X103       /*DSP MMU FAULT RECOVERY */
 132
 133 /*
 134  *  Link driver command/status codes.
 135  */
 136 /* DSP-DMA */
 137 #define MBX_DDMA_NUMCHNLBITS 5  /* # chnl Id: # bits available */
 138 #define MBX_DDMA_CHNLSHIFT   0  /* # of bits to shift */
 139 #define MBX_DDMA_CHNLMSK     0x01F      /* bits 0 thru 4 */
 140
 141 #define MBX_DDMA_NUMBUFBITS  5  /* buffer index: # of bits avail */
 142 #define MBX_DDMA_BUFSHIFT    (MBX_DDMA_NUMCHNLBITS + MBX_DDMA_CHNLSHIFT)
 143 #define MBX_DDMA_BUFMSK      0x3E0      /* bits 5 thru 9 */
 144
 145 /* Zero-Copy */
 146 #define MBX_ZCPY_NUMCHNLBITS 5  /* # chnl Id: # bits available */
 147 #define MBX_ZCPY_CHNLSHIFT   0  /* # of bits to shift */
 148 #define MBX_ZCPY_CHNLMSK     0x01F      /* bits 0 thru 4 */
 149
 150 /*  Power Management Commands */
 151 #define MBX_PM_DSPIDLE                  (MBX_PM_CLASS + 0x0)
 152 #define MBX_PM_DSPWAKEUP                (MBX_PM_CLASS + 0x1)
 153 #define MBX_PM_EMERGENCYSLEEP           (MBX_PM_CLASS + 0x2)
 154 #define MBX_PM_SLEEPUNTILRESTART        (MBX_PM_CLASS + 0x3)
 155 #define MBX_PM_DSPGLOBALIDLE_OFF        (MBX_PM_CLASS + 0x4)
 156 #define MBX_PM_DSPGLOBALIDLE_ON         (MBX_PM_CLASS + 0x5)
 157 #define MBX_PM_SETPOINT_PRENOTIFY       (MBX_PM_CLASS + 0x6)
 158 #define MBX_PM_SETPOINT_POSTNOTIFY      (MBX_PM_CLASS + 0x7)
 159 #define MBX_PM_DSPRETN                  (MBX_PM_CLASS + 0x8)
 160 #define MBX_PM_DSPRETENTION        (MBX_PM_CLASS + 0x8)
 161 #define MBX_PM_DSPHIBERNATE        (MBX_PM_CLASS + 0x9)
 162 #define MBX_PM_HIBERNATE_EN        (MBX_PM_CLASS + 0xA)
 163 #define MBX_PM_OPP_REQ                  (MBX_PM_CLASS + 0xB)
 164 #define MBX_PM_OPP_CHG                  (MBX_PM_CLASS + 0xC)
 165
 166 #define MBX_PM_TYPE_MASK 0x0300
 167 #define MBX_PM_TYPE_PWR_CHNG 0x0100
 168 #define MBX_PM_TYPE_OPP_PRECHNG 0x0200
 169 #define MBX_PM_TYPE_OPP_POSTCHNG 0x0300
 170 #define MBX_PM_TYPE_OPP_MASK 0x0300
 171 #define MBX_PM_OPP_PRECHNG (MBX_PM_CLASS | MBX_PM_TYPE_OPP_PRECHNG)
 172 /* DSP to MPU */
 173 #define MBX_PM_OPP_CHNG(OPP) (MBX_PM_CLASS | MBX_PM_TYPE_OPP_PRECHNG | (OPP))
 174 #define MBX_PM_RET (MBX_PM_CLASS | MBX_PM_TYPE_PWR_CHNG | 0x0006)
 175 #define MBX_PM_HIB (MBX_PM_CLASS | MBX_PM_TYPE_PWR_CHNG | 0x0002)
 176 #define MBX_PM_OPP1 0
 177 #define MBX_PM_OPP2 1
 178 #define MBX_PM_OPP3 2
 179 #define MBX_PM_OPP4 3
 180
 181 /* Bridge Debug Commands */
 182 #define MBX_DBG_SYSPRINTF       (MBX_DBG_CLASS + 0x0)
 183
 184 #endif /* _MBX_SH_H */