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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / staging / rtl8192e / r819xE_phy.c
blobba3c6c801b3e319d4bdb95052526461613c65ecc
1 #include "r8192E.h"
2 #include "r8192E_hw.h"
3 #include "r819xE_phyreg.h"
4 #include "r8190_rtl8256.h"
5 #include "r819xE_phy.h"
6 #include "r8192E_dm.h"
7 #ifdef ENABLE_DOT11D
8 #include "ieee80211/dot11d.h"
9 #endif
10 static const u32 RF_CHANNEL_TABLE_ZEBRA[] = {
11 0,
12 0x085c, //2412 1
13 0x08dc, //2417 2
14 0x095c, //2422 3
15 0x09dc, //2427 4
16 0x0a5c, //2432 5
17 0x0adc, //2437 6
18 0x0b5c, //2442 7
19 0x0bdc, //2447 8
20 0x0c5c, //2452 9
21 0x0cdc, //2457 10
22 0x0d5c, //2462 11
23 0x0ddc, //2467 12
24 0x0e5c, //2472 13
25 0x0f72, //2484
26 };
27 #ifdef RTL8190P
28 u32 Rtl8190PciMACPHY_Array[] = {
29 0x03c,0xffff0000,0x00000f0f,
30 0x340,0xffffffff,0x161a1a1a,
31 0x344,0xffffffff,0x12121416,
32 0x348,0x0000ffff,0x00001818,
33 0x12c,0xffffffff,0x04000802,
34 0x318,0x00000fff,0x00000800,
35 };
36 u32 Rtl8190PciMACPHY_Array_PG[] = {
37 0x03c,0xffff0000,0x00000f0f,
38 0x340,0xffffffff,0x0a0c0d0f,
39 0x344,0xffffffff,0x06070809,
40 0x344,0xffffffff,0x06070809,
41 0x348,0x0000ffff,0x00000000,
42 0x12c,0xffffffff,0x04000802,
43 0x318,0x00000fff,0x00000800,
44 };
45
46 u32 Rtl8190PciAGCTAB_Array[AGCTAB_ArrayLength] = {
47 0xc78,0x7d000001,
48 0xc78,0x7d010001,
49 0xc78,0x7d020001,
50 0xc78,0x7d030001,
51 0xc78,0x7c040001,
52 0xc78,0x7b050001,
53 0xc78,0x7a060001,
54 0xc78,0x79070001,
55 0xc78,0x78080001,
56 0xc78,0x77090001,
57 0xc78,0x760a0001,
58 0xc78,0x750b0001,
59 0xc78,0x740c0001,
60 0xc78,0x730d0001,
61 0xc78,0x720e0001,
62 0xc78,0x710f0001,
63 0xc78,0x70100001,
64 0xc78,0x6f110001,
65 0xc78,0x6e120001,
66 0xc78,0x6d130001,
67 0xc78,0x6c140001,
68 0xc78,0x6b150001,
69 0xc78,0x6a160001,
70 0xc78,0x69170001,
71 0xc78,0x68180001,
72 0xc78,0x67190001,
73 0xc78,0x661a0001,
74 0xc78,0x651b0001,
75 0xc78,0x641c0001,
76 0xc78,0x491d0001,
77 0xc78,0x481e0001,
78 0xc78,0x471f0001,
79 0xc78,0x46200001,
80 0xc78,0x45210001,
81 0xc78,0x44220001,
82 0xc78,0x43230001,
83 0xc78,0x28240001,
84 0xc78,0x27250001,
85 0xc78,0x26260001,
86 0xc78,0x25270001,
87 0xc78,0x24280001,
88 0xc78,0x23290001,
89 0xc78,0x222a0001,
90 0xc78,0x212b0001,
91 0xc78,0x202c0001,
92 0xc78,0x0a2d0001,
93 0xc78,0x082e0001,
94 0xc78,0x062f0001,
95 0xc78,0x05300001,
96 0xc78,0x04310001,
97 0xc78,0x03320001,
98 0xc78,0x02330001,
99 0xc78,0x01340001,
100 0xc78,0x00350001,
101 0xc78,0x00360001,
102 0xc78,0x00370001,
103 0xc78,0x00380001,
104 0xc78,0x00390001,
105 0xc78,0x003a0001,
106 0xc78,0x003b0001,
107 0xc78,0x003c0001,
108 0xc78,0x003d0001,
109 0xc78,0x003e0001,
110 0xc78,0x003f0001,
111 0xc78,0x7d400001,
112 0xc78,0x7d410001,
113 0xc78,0x7d420001,
114 0xc78,0x7d430001,
115 0xc78,0x7c440001,
116 0xc78,0x7b450001,
117 0xc78,0x7a460001,
118 0xc78,0x79470001,
119 0xc78,0x78480001,
120 0xc78,0x77490001,
121 0xc78,0x764a0001,
122 0xc78,0x754b0001,
123 0xc78,0x744c0001,
124 0xc78,0x734d0001,
125 0xc78,0x724e0001,
126 0xc78,0x714f0001,
127 0xc78,0x70500001,
128 0xc78,0x6f510001,
129 0xc78,0x6e520001,
130 0xc78,0x6d530001,
131 0xc78,0x6c540001,
132 0xc78,0x6b550001,
133 0xc78,0x6a560001,
134 0xc78,0x69570001,
135 0xc78,0x68580001,
136 0xc78,0x67590001,
137 0xc78,0x665a0001,
138 0xc78,0x655b0001,
139 0xc78,0x645c0001,
140 0xc78,0x495d0001,
141 0xc78,0x485e0001,
142 0xc78,0x475f0001,
143 0xc78,0x46600001,
144 0xc78,0x45610001,
145 0xc78,0x44620001,
146 0xc78,0x43630001,
147 0xc78,0x28640001,
148 0xc78,0x27650001,
149 0xc78,0x26660001,
150 0xc78,0x25670001,
151 0xc78,0x24680001,
152 0xc78,0x23690001,
153 0xc78,0x226a0001,
154 0xc78,0x216b0001,
155 0xc78,0x206c0001,
156 0xc78,0x0a6d0001,
157 0xc78,0x086e0001,
158 0xc78,0x066f0001,
159 0xc78,0x05700001,
160 0xc78,0x04710001,
161 0xc78,0x03720001,
162 0xc78,0x02730001,
163 0xc78,0x01740001,
164 0xc78,0x00750001,
165 0xc78,0x00760001,
166 0xc78,0x00770001,
167 0xc78,0x00780001,
168 0xc78,0x00790001,
169 0xc78,0x007a0001,
170 0xc78,0x007b0001,
171 0xc78,0x007c0001,
172 0xc78,0x007d0001,
173 0xc78,0x007e0001,
174 0xc78,0x007f0001,
175 0xc78,0x3600001e,
176 0xc78,0x3601001e,
177 0xc78,0x3602001e,
178 0xc78,0x3603001e,
179 0xc78,0x3604001e,
180 0xc78,0x3605001e,
181 0xc78,0x3a06001e,
182 0xc78,0x3c07001e,
183 0xc78,0x3e08001e,
184 0xc78,0x4209001e,
185 0xc78,0x430a001e,
186 0xc78,0x450b001e,
187 0xc78,0x470c001e,
188 0xc78,0x480d001e,
189 0xc78,0x490e001e,
190 0xc78,0x4b0f001e,
191 0xc78,0x4c10001e,
192 0xc78,0x4d11001e,
193 0xc78,0x4d12001e,
194 0xc78,0x4e13001e,
195 0xc78,0x4f14001e,
196 0xc78,0x5015001e,
197 0xc78,0x5116001e,
198 0xc78,0x5117001e,
199 0xc78,0x5218001e,
200 0xc78,0x5219001e,
201 0xc78,0x531a001e,
202 0xc78,0x541b001e,
203 0xc78,0x541c001e,
204 0xc78,0x551d001e,
205 0xc78,0x561e001e,
206 0xc78,0x561f001e,
207 0xc78,0x5720001e,
208 0xc78,0x5821001e,
209 0xc78,0x5822001e,
210 0xc78,0x5923001e,
211 0xc78,0x5924001e,
212 0xc78,0x5a25001e,
213 0xc78,0x5b26001e,
214 0xc78,0x5b27001e,
215 0xc78,0x5c28001e,
216 0xc78,0x5c29001e,
217 0xc78,0x5d2a001e,
218 0xc78,0x5d2b001e,
219 0xc78,0x5e2c001e,
220 0xc78,0x5e2d001e,
221 0xc78,0x5f2e001e,
222 0xc78,0x602f001e,
223 0xc78,0x6030001e,
224 0xc78,0x6131001e,
225 0xc78,0x6132001e,
226 0xc78,0x6233001e,
227 0xc78,0x6234001e,
228 0xc78,0x6335001e,
229 0xc78,0x6336001e,
230 0xc78,0x6437001e,
231 0xc78,0x6538001e,
232 0xc78,0x6639001e,
233 0xc78,0x663a001e,
234 0xc78,0x673b001e,
235 0xc78,0x683c001e,
236 0xc78,0x693d001e,
237 0xc78,0x6a3e001e,
238 0xc78,0x6b3f001e,
239 };
240
241 u32 Rtl8190PciPHY_REGArray[PHY_REGArrayLength] = {
242 0x800,0x00050060,
243 0x804,0x00000005,
244 0x808,0x0000fc00,
245 0x80c,0x0000001c,
246 0x810,0x801010aa,
247 0x814,0x000908c0,
248 0x818,0x00000000,
249 0x81c,0x00000000,
250 0x820,0x00000004,
251 0x824,0x00690000,
252 0x828,0x00000004,
253 0x82c,0x00e90000,
254 0x830,0x00000004,
255 0x834,0x00690000,
256 0x838,0x00000004,
257 0x83c,0x00e90000,
258 0x840,0x00000000,
259 0x844,0x00000000,
260 0x848,0x00000000,
261 0x84c,0x00000000,
262 0x850,0x00000000,
263 0x854,0x00000000,
264 0x858,0x65a965a9,
265 0x85c,0x65a965a9,
266 0x860,0x001f0010,
267 0x864,0x007f0010,
268 0x868,0x001f0010,
269 0x86c,0x007f0010,
270 0x870,0x0f100f70,
271 0x874,0x0f100f70,
272 0x878,0x00000000,
273 0x87c,0x00000000,
274 0x880,0x5c385eb8,
275 0x884,0x6357060d,
276 0x888,0x0460c341,
277 0x88c,0x0000ff00,
278 0x890,0x00000000,
279 0x894,0xfffffffe,
280 0x898,0x4c42382f,
281 0x89c,0x00656056,
282 0x8b0,0x00000000,
283 0x8e0,0x00000000,
284 0x8e4,0x00000000,
285 0x900,0x00000000,
286 0x904,0x00000023,
287 0x908,0x00000000,
288 0x90c,0x35541545,
289 0xa00,0x00d0c7d8,
290 0xa04,0xab1f0008,
291 0xa08,0x80cd8300,
292 0xa0c,0x2e62740f,
293 0xa10,0x95009b78,
294 0xa14,0x11145008,
295 0xa18,0x00881117,
296 0xa1c,0x89140fa0,
297 0xa20,0x1a1b0000,
298 0xa24,0x090e1317,
299 0xa28,0x00000204,
300 0xa2c,0x00000000,
301 0xc00,0x00000040,
302 0xc04,0x0000500f,
303 0xc08,0x000000e4,
304 0xc0c,0x6c6c6c6c,
305 0xc10,0x08000000,
306 0xc14,0x40000100,
307 0xc18,0x08000000,
308 0xc1c,0x40000100,
309 0xc20,0x08000000,
310 0xc24,0x40000100,
311 0xc28,0x08000000,
312 0xc2c,0x40000100,
313 0xc30,0x6de9ac44,
314 0xc34,0x164052cd,
315 0xc38,0x00070a14,
316 0xc3c,0x0a969764,
317 0xc40,0x1f7c403f,
318 0xc44,0x000100b7,
319 0xc48,0xec020000,
320 0xc4c,0x00000300,
321 0xc50,0x69543420,
322 0xc54,0x433c0094,
323 0xc58,0x69543420,
324 0xc5c,0x433c0094,
325 0xc60,0x69543420,
326 0xc64,0x433c0094,
327 0xc68,0x69543420,
328 0xc6c,0x433c0094,
329 0xc70,0x2c7f000d,
330 0xc74,0x0186175b,
331 0xc78,0x0000001f,
332 0xc7c,0x00b91612,
333 0xc80,0x40000100,
334 0xc84,0x00000000,
335 0xc88,0x40000100,
336 0xc8c,0x08000000,
337 0xc90,0x40000100,
338 0xc94,0x00000000,
339 0xc98,0x40000100,
340 0xc9c,0x00000000,
341 0xca0,0x00492492,
342 0xca4,0x00000000,
343 0xca8,0x00000000,
344 0xcac,0x00000000,
345 0xcb0,0x00000000,
346 0xcb4,0x00000000,
347 0xcb8,0x00000000,
348 0xcbc,0x00492492,
349 0xcc0,0x00000000,
350 0xcc4,0x00000000,
351 0xcc8,0x00000000,
352 0xccc,0x00000000,
353 0xcd0,0x00000000,
354 0xcd4,0x00000000,
355 0xcd8,0x64b22427,
356 0xcdc,0x00766932,
357 0xce0,0x00222222,
358 0xd00,0x00000740,
359 0xd04,0x0000040f,
360 0xd08,0x0000803f,
361 0xd0c,0x00000001,
362 0xd10,0xa0633333,
363 0xd14,0x33333c63,
364 0xd18,0x6a8f5b6b,
365 0xd1c,0x00000000,
366 0xd20,0x00000000,
367 0xd24,0x00000000,
368 0xd28,0x00000000,
369 0xd2c,0xcc979975,
370 0xd30,0x00000000,
371 0xd34,0x00000000,
372 0xd38,0x00000000,
373 0xd3c,0x00027293,
374 0xd40,0x00000000,
375 0xd44,0x00000000,
376 0xd48,0x00000000,
377 0xd4c,0x00000000,
378 0xd50,0x6437140a,
379 0xd54,0x024dbd02,
380 0xd58,0x00000000,
381 0xd5c,0x14032064,
382 };
383 u32 Rtl8190PciPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = {
384 0x800,0x00050060,
385 0x804,0x00000004,
386 0x808,0x0000fc00,
387 0x80c,0x0000001c,
388 0x810,0x801010aa,
389 0x814,0x000908c0,
390 0x818,0x00000000,
391 0x81c,0x00000000,
392 0x820,0x00000004,
393 0x824,0x00690000,
394 0x828,0x00000004,
395 0x82c,0x00e90000,
396 0x830,0x00000004,
397 0x834,0x00690000,
398 0x838,0x00000004,
399 0x83c,0x00e90000,
400 0x840,0x00000000,
401 0x844,0x00000000,
402 0x848,0x00000000,
403 0x84c,0x00000000,
404 0x850,0x00000000,
405 0x854,0x00000000,
406 0x858,0x65a965a9,
407 0x85c,0x65a965a9,
408 0x860,0x001f0000,
409 0x864,0x007f0000,
410 0x868,0x001f0010,
411 0x86c,0x007f0010,
412 0x870,0x0f100f70,
413 0x874,0x0f100f70,
414 0x878,0x00000000,
415 0x87c,0x00000000,
416 0x880,0x5c385898,
417 0x884,0x6357060d,
418 0x888,0x0460c341,
419 0x88c,0x0000fc00,
420 0x890,0x00000000,
421 0x894,0xfffffffe,
422 0x898,0x4c42382f,
423 0x89c,0x00656056,
424 0x8b0,0x00000000,
425 0x8e0,0x00000000,
426 0x8e4,0x00000000,
427 0x900,0x00000000,
428 0x904,0x00000023,
429 0x908,0x00000000,
430 0x90c,0x34441444,
431 0xa00,0x00d0c7d8,
432 0xa04,0x2b1f0008,
433 0xa08,0x80cd8300,
434 0xa0c,0x2e62740f,
435 0xa10,0x95009b78,
436 0xa14,0x11145008,
437 0xa18,0x00881117,
438 0xa1c,0x89140fa0,
439 0xa20,0x1a1b0000,
440 0xa24,0x090e1317,
441 0xa28,0x00000204,
442 0xa2c,0x00000000,
443 0xc00,0x00000040,
444 0xc04,0x0000500c,
445 0xc08,0x000000e4,
446 0xc0c,0x6c6c6c6c,
447 0xc10,0x08000000,
448 0xc14,0x40000100,
449 0xc18,0x08000000,
450 0xc1c,0x40000100,
451 0xc20,0x08000000,
452 0xc24,0x40000100,
453 0xc28,0x08000000,
454 0xc2c,0x40000100,
455 0xc30,0x6de9ac44,
456 0xc34,0x164052cd,
457 0xc38,0x00070a14,
458 0xc3c,0x0a969764,
459 0xc40,0x1f7c403f,
460 0xc44,0x000100b7,
461 0xc48,0xec020000,
462 0xc4c,0x00000300,
463 0xc50,0x69543420,
464 0xc54,0x433c0094,
465 0xc58,0x69543420,
466 0xc5c,0x433c0094,
467 0xc60,0x69543420,
468 0xc64,0x433c0094,
469 0xc68,0x69543420,
470 0xc6c,0x433c0094,
471 0xc70,0x2c7f000d,
472 0xc74,0x0186175b,
473 0xc78,0x0000001f,
474 0xc7c,0x00b91612,
475 0xc80,0x40000100,
476 0xc84,0x00000000,
477 0xc88,0x40000100,
478 0xc8c,0x08000000,
479 0xc90,0x40000100,
480 0xc94,0x00000000,
481 0xc98,0x40000100,
482 0xc9c,0x00000000,
483 0xca0,0x00492492,
484 0xca4,0x00000000,
485 0xca8,0x00000000,
486 0xcac,0x00000000,
487 0xcb0,0x00000000,
488 0xcb4,0x00000000,
489 0xcb8,0x00000000,
490 0xcbc,0x00492492,
491 0xcc0,0x00000000,
492 0xcc4,0x00000000,
493 0xcc8,0x00000000,
494 0xccc,0x00000000,
495 0xcd0,0x00000000,
496 0xcd4,0x00000000,
497 0xcd8,0x64b22427,
498 0xcdc,0x00766932,
499 0xce0,0x00222222,
500 0xd00,0x00000740,
501 0xd04,0x0000040c,
502 0xd08,0x0000803f,
503 0xd0c,0x00000001,
504 0xd10,0xa0633333,
505 0xd14,0x33333c63,
506 0xd18,0x6a8f5b6b,
507 0xd1c,0x00000000,
508 0xd20,0x00000000,
509 0xd24,0x00000000,
510 0xd28,0x00000000,
511 0xd2c,0xcc979975,
512 0xd30,0x00000000,
513 0xd34,0x00000000,
514 0xd38,0x00000000,
515 0xd3c,0x00027293,
516 0xd40,0x00000000,
517 0xd44,0x00000000,
518 0xd48,0x00000000,
519 0xd4c,0x00000000,
520 0xd50,0x6437140a,
521 0xd54,0x024dbd02,
522 0xd58,0x00000000,
523 0xd5c,0x14032064,
524 };
525
526 u32 Rtl8190PciRadioA_Array[RadioA_ArrayLength] = {
527 0x019,0x00000003,
528 0x000,0x000000bf,
529 0x001,0x00000ee0,
530 0x002,0x0000004c,
531 0x003,0x000007f1,
532 0x004,0x00000975,
533 0x005,0x00000c58,
534 0x006,0x00000ae6,
535 0x007,0x000000ca,
536 0x008,0x00000e1c,
537 0x009,0x000007f0,
538 0x00a,0x000009d0,
539 0x00b,0x000001ba,
540 0x00c,0x00000240,
541 0x00e,0x00000020,
542 0x00f,0x00000990,
543 0x012,0x00000806,
544 0x014,0x000005ab,
545 0x015,0x00000f80,
546 0x016,0x00000020,
547 0x017,0x00000597,
548 0x018,0x0000050a,
549 0x01a,0x00000f80,
550 0x01b,0x00000f5e,
551 0x01c,0x00000008,
552 0x01d,0x00000607,
553 0x01e,0x000006cc,
554 0x01f,0x00000000,
555 0x020,0x000001a5,
556 0x01f,0x00000001,
557 0x020,0x00000165,
558 0x01f,0x00000002,
559 0x020,0x000000c6,
560 0x01f,0x00000003,
561 0x020,0x00000086,
562 0x01f,0x00000004,
563 0x020,0x00000046,
564 0x01f,0x00000005,
565 0x020,0x000001e6,
566 0x01f,0x00000006,
567 0x020,0x000001a6,
568 0x01f,0x00000007,
569 0x020,0x00000166,
570 0x01f,0x00000008,
571 0x020,0x000000c7,
572 0x01f,0x00000009,
573 0x020,0x00000087,
574 0x01f,0x0000000a,
575 0x020,0x000000f7,
576 0x01f,0x0000000b,
577 0x020,0x000000d7,
578 0x01f,0x0000000c,
579 0x020,0x000000b7,
580 0x01f,0x0000000d,
581 0x020,0x00000097,
582 0x01f,0x0000000e,
583 0x020,0x00000077,
584 0x01f,0x0000000f,
585 0x020,0x00000057,
586 0x01f,0x00000010,
587 0x020,0x00000037,
588 0x01f,0x00000011,
589 0x020,0x000000fb,
590 0x01f,0x00000012,
591 0x020,0x000000db,
592 0x01f,0x00000013,
593 0x020,0x000000bb,
594 0x01f,0x00000014,
595 0x020,0x000000ff,
596 0x01f,0x00000015,
597 0x020,0x000000e3,
598 0x01f,0x00000016,
599 0x020,0x000000c3,
600 0x01f,0x00000017,
601 0x020,0x000000a3,
602 0x01f,0x00000018,
603 0x020,0x00000083,
604 0x01f,0x00000019,
605 0x020,0x00000063,
606 0x01f,0x0000001a,
607 0x020,0x00000043,
608 0x01f,0x0000001b,
609 0x020,0x00000023,
610 0x01f,0x0000001c,
611 0x020,0x00000003,
612 0x01f,0x0000001d,
613 0x020,0x000001e3,
614 0x01f,0x0000001e,
615 0x020,0x000001c3,
616 0x01f,0x0000001f,
617 0x020,0x000001a3,
618 0x01f,0x00000020,
619 0x020,0x00000183,
620 0x01f,0x00000021,
621 0x020,0x00000163,
622 0x01f,0x00000022,
623 0x020,0x00000143,
624 0x01f,0x00000023,
625 0x020,0x00000123,
626 0x01f,0x00000024,
627 0x020,0x00000103,
628 0x023,0x00000203,
629 0x024,0x00000200,
630 0x00b,0x000001ba,
631 0x02c,0x000003d7,
632 0x02d,0x00000ff0,
633 0x000,0x00000037,
634 0x004,0x00000160,
635 0x007,0x00000080,
636 0x002,0x0000088d,
637 0x0fe,0x00000000,
638 0x0fe,0x00000000,
639 0x016,0x00000200,
640 0x016,0x00000380,
641 0x016,0x00000020,
642 0x016,0x000001a0,
643 0x000,0x000000bf,
644 0x00d,0x0000001f,
645 0x00d,0x00000c9f,
646 0x002,0x0000004d,
647 0x000,0x00000cbf,
648 0x004,0x00000975,
649 0x007,0x00000700,
650 };
651 u32 Rtl8190PciRadioB_Array[RadioB_ArrayLength] = {
652 0x019,0x00000003,
653 0x000,0x000000bf,
654 0x001,0x000006e0,
655 0x002,0x0000004c,
656 0x003,0x000007f1,
657 0x004,0x00000975,
658 0x005,0x00000c58,
659 0x006,0x00000ae6,
660 0x007,0x000000ca,
661 0x008,0x00000e1c,
662 0x000,0x000000b7,
663 0x00a,0x00000850,
664 0x000,0x000000bf,
665 0x00b,0x000001ba,
666 0x00c,0x00000240,
667 0x00e,0x00000020,
668 0x015,0x00000f80,
669 0x016,0x00000020,
670 0x017,0x00000597,
671 0x018,0x0000050a,
672 0x01a,0x00000e00,
673 0x01b,0x00000f5e,
674 0x01d,0x00000607,
675 0x01e,0x000006cc,
676 0x00b,0x000001ba,
677 0x023,0x00000203,
678 0x024,0x00000200,
679 0x000,0x00000037,
680 0x004,0x00000160,
681 0x016,0x00000200,
682 0x016,0x00000380,
683 0x016,0x00000020,
684 0x016,0x000001a0,
685 0x00d,0x00000ccc,
686 0x000,0x000000bf,
687 0x002,0x0000004d,
688 0x000,0x00000cbf,
689 0x004,0x00000975,
690 0x007,0x00000700,
691 };
692 u32 Rtl8190PciRadioC_Array[RadioC_ArrayLength] = {
693 0x019,0x00000003,
694 0x000,0x000000bf,
695 0x001,0x00000ee0,
696 0x002,0x0000004c,
697 0x003,0x000007f1,
698 0x004,0x00000975,
699 0x005,0x00000c58,
700 0x006,0x00000ae6,
701 0x007,0x000000ca,
702 0x008,0x00000e1c,
703 0x009,0x000007f0,
704 0x00a,0x000009d0,
705 0x00b,0x000001ba,
706 0x00c,0x00000240,
707 0x00e,0x00000020,
708 0x00f,0x00000990,
709 0x012,0x00000806,
710 0x014,0x000005ab,
711 0x015,0x00000f80,
712 0x016,0x00000020,
713 0x017,0x00000597,
714 0x018,0x0000050a,
715 0x01a,0x00000f80,
716 0x01b,0x00000f5e,
717 0x01c,0x00000008,
718 0x01d,0x00000607,
719 0x01e,0x000006cc,
720 0x01f,0x00000000,
721 0x020,0x000001a5,
722 0x01f,0x00000001,
723 0x020,0x00000165,
724 0x01f,0x00000002,
725 0x020,0x000000c6,
726 0x01f,0x00000003,
727 0x020,0x00000086,
728 0x01f,0x00000004,
729 0x020,0x00000046,
730 0x01f,0x00000005,
731 0x020,0x000001e6,
732 0x01f,0x00000006,
733 0x020,0x000001a6,
734 0x01f,0x00000007,
735 0x020,0x00000166,
736 0x01f,0x00000008,
737 0x020,0x000000c7,
738 0x01f,0x00000009,
739 0x020,0x00000087,
740 0x01f,0x0000000a,
741 0x020,0x000000f7,
742 0x01f,0x0000000b,
743 0x020,0x000000d7,
744 0x01f,0x0000000c,
745 0x020,0x000000b7,
746 0x01f,0x0000000d,
747 0x020,0x00000097,
748 0x01f,0x0000000e,
749 0x020,0x00000077,
750 0x01f,0x0000000f,
751 0x020,0x00000057,
752 0x01f,0x00000010,
753 0x020,0x00000037,
754 0x01f,0x00000011,
755 0x020,0x000000fb,
756 0x01f,0x00000012,
757 0x020,0x000000db,
758 0x01f,0x00000013,
759 0x020,0x000000bb,
760 0x01f,0x00000014,
761 0x020,0x000000ff,
762 0x01f,0x00000015,
763 0x020,0x000000e3,
764 0x01f,0x00000016,
765 0x020,0x000000c3,
766 0x01f,0x00000017,
767 0x020,0x000000a3,
768 0x01f,0x00000018,
769 0x020,0x00000083,
770 0x01f,0x00000019,
771 0x020,0x00000063,
772 0x01f,0x0000001a,
773 0x020,0x00000043,
774 0x01f,0x0000001b,
775 0x020,0x00000023,
776 0x01f,0x0000001c,
777 0x020,0x00000003,
778 0x01f,0x0000001d,
779 0x020,0x000001e3,
780 0x01f,0x0000001e,
781 0x020,0x000001c3,
782 0x01f,0x0000001f,
783 0x020,0x000001a3,
784 0x01f,0x00000020,
785 0x020,0x00000183,
786 0x01f,0x00000021,
787 0x020,0x00000163,
788 0x01f,0x00000022,
789 0x020,0x00000143,
790 0x01f,0x00000023,
791 0x020,0x00000123,
792 0x01f,0x00000024,
793 0x020,0x00000103,
794 0x023,0x00000203,
795 0x024,0x00000200,
796 0x00b,0x000001ba,
797 0x02c,0x000003d7,
798 0x02d,0x00000ff0,
799 0x000,0x00000037,
800 0x004,0x00000160,
801 0x007,0x00000080,
802 0x002,0x0000088d,
803 0x0fe,0x00000000,
804 0x0fe,0x00000000,
805 0x016,0x00000200,
806 0x016,0x00000380,
807 0x016,0x00000020,
808 0x016,0x000001a0,
809 0x000,0x000000bf,
810 0x00d,0x0000001f,
811 0x00d,0x00000c9f,
812 0x002,0x0000004d,
813 0x000,0x00000cbf,
814 0x004,0x00000975,
815 0x007,0x00000700,
816 };
817 u32 Rtl8190PciRadioD_Array[RadioD_ArrayLength] = {
818 0x019,0x00000003,
819 0x000,0x000000bf,
820 0x001,0x000006e0,
821 0x002,0x0000004c,
822 0x003,0x000007f1,
823 0x004,0x00000975,
824 0x005,0x00000c58,
825 0x006,0x00000ae6,
826 0x007,0x000000ca,
827 0x008,0x00000e1c,
828 0x000,0x000000b7,
829 0x00a,0x00000850,
830 0x000,0x000000bf,
831 0x00b,0x000001ba,
832 0x00c,0x00000240,
833 0x00e,0x00000020,
834 0x015,0x00000f80,
835 0x016,0x00000020,
836 0x017,0x00000597,
837 0x018,0x0000050a,
838 0x01a,0x00000e00,
839 0x01b,0x00000f5e,
840 0x01d,0x00000607,
841 0x01e,0x000006cc,
842 0x00b,0x000001ba,
843 0x023,0x00000203,
844 0x024,0x00000200,
845 0x000,0x00000037,
846 0x004,0x00000160,
847 0x016,0x00000200,
848 0x016,0x00000380,
849 0x016,0x00000020,
850 0x016,0x000001a0,
851 0x00d,0x00000ccc,
852 0x000,0x000000bf,
853 0x002,0x0000004d,
854 0x000,0x00000cbf,
855 0x004,0x00000975,
856 0x007,0x00000700,
857 };
858 #endif
859 #ifdef RTL8192E
860 static u32 Rtl8192PciEMACPHY_Array[] = {
861 0x03c,0xffff0000,0x00000f0f,
862 0x340,0xffffffff,0x161a1a1a,
863 0x344,0xffffffff,0x12121416,
864 0x348,0x0000ffff,0x00001818,
865 0x12c,0xffffffff,0x04000802,
866 0x318,0x00000fff,0x00000100,
867 };
868 static u32 Rtl8192PciEMACPHY_Array_PG[] = {
869 0x03c,0xffff0000,0x00000f0f,
870 0xe00,0xffffffff,0x06090909,
871 0xe04,0xffffffff,0x00030306,
872 0xe08,0x0000ff00,0x00000000,
873 0xe10,0xffffffff,0x0a0c0d0f,
874 0xe14,0xffffffff,0x06070809,
875 0xe18,0xffffffff,0x0a0c0d0f,
876 0xe1c,0xffffffff,0x06070809,
877 0x12c,0xffffffff,0x04000802,
878 0x318,0x00000fff,0x00000800,
879 };
880 static u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLength] = {
881 0xc78,0x7d000001,
882 0xc78,0x7d010001,
883 0xc78,0x7d020001,
884 0xc78,0x7d030001,
885 0xc78,0x7d040001,
886 0xc78,0x7d050001,
887 0xc78,0x7c060001,
888 0xc78,0x7b070001,
889 0xc78,0x7a080001,
890 0xc78,0x79090001,
891 0xc78,0x780a0001,
892 0xc78,0x770b0001,
893 0xc78,0x760c0001,
894 0xc78,0x750d0001,
895 0xc78,0x740e0001,
896 0xc78,0x730f0001,
897 0xc78,0x72100001,
898 0xc78,0x71110001,
899 0xc78,0x70120001,
900 0xc78,0x6f130001,
901 0xc78,0x6e140001,
902 0xc78,0x6d150001,
903 0xc78,0x6c160001,
904 0xc78,0x6b170001,
905 0xc78,0x6a180001,
906 0xc78,0x69190001,
907 0xc78,0x681a0001,
908 0xc78,0x671b0001,
909 0xc78,0x661c0001,
910 0xc78,0x651d0001,
911 0xc78,0x641e0001,
912 0xc78,0x491f0001,
913 0xc78,0x48200001,
914 0xc78,0x47210001,
915 0xc78,0x46220001,
916 0xc78,0x45230001,
917 0xc78,0x44240001,
918 0xc78,0x43250001,
919 0xc78,0x28260001,
920 0xc78,0x27270001,
921 0xc78,0x26280001,
922 0xc78,0x25290001,
923 0xc78,0x242a0001,
924 0xc78,0x232b0001,
925 0xc78,0x222c0001,
926 0xc78,0x212d0001,
927 0xc78,0x202e0001,
928 0xc78,0x0a2f0001,
929 0xc78,0x08300001,
930 0xc78,0x06310001,
931 0xc78,0x05320001,
932 0xc78,0x04330001,
933 0xc78,0x03340001,
934 0xc78,0x02350001,
935 0xc78,0x01360001,
936 0xc78,0x00370001,
937 0xc78,0x00380001,
938 0xc78,0x00390001,
939 0xc78,0x003a0001,
940 0xc78,0x003b0001,
941 0xc78,0x003c0001,
942 0xc78,0x003d0001,
943 0xc78,0x003e0001,
944 0xc78,0x003f0001,
945 0xc78,0x7d400001,
946 0xc78,0x7d410001,
947 0xc78,0x7d420001,
948 0xc78,0x7d430001,
949 0xc78,0x7d440001,
950 0xc78,0x7d450001,
951 0xc78,0x7c460001,
952 0xc78,0x7b470001,
953 0xc78,0x7a480001,
954 0xc78,0x79490001,
955 0xc78,0x784a0001,
956 0xc78,0x774b0001,
957 0xc78,0x764c0001,
958 0xc78,0x754d0001,
959 0xc78,0x744e0001,
960 0xc78,0x734f0001,
961 0xc78,0x72500001,
962 0xc78,0x71510001,
963 0xc78,0x70520001,
964 0xc78,0x6f530001,
965 0xc78,0x6e540001,
966 0xc78,0x6d550001,
967 0xc78,0x6c560001,
968 0xc78,0x6b570001,
969 0xc78,0x6a580001,
970 0xc78,0x69590001,
971 0xc78,0x685a0001,
972 0xc78,0x675b0001,
973 0xc78,0x665c0001,
974 0xc78,0x655d0001,
975 0xc78,0x645e0001,
976 0xc78,0x495f0001,
977 0xc78,0x48600001,
978 0xc78,0x47610001,
979 0xc78,0x46620001,
980 0xc78,0x45630001,
981 0xc78,0x44640001,
982 0xc78,0x43650001,
983 0xc78,0x28660001,
984 0xc78,0x27670001,
985 0xc78,0x26680001,
986 0xc78,0x25690001,
987 0xc78,0x246a0001,
988 0xc78,0x236b0001,
989 0xc78,0x226c0001,
990 0xc78,0x216d0001,
991 0xc78,0x206e0001,
992 0xc78,0x0a6f0001,
993 0xc78,0x08700001,
994 0xc78,0x06710001,
995 0xc78,0x05720001,
996 0xc78,0x04730001,
997 0xc78,0x03740001,
998 0xc78,0x02750001,
999 0xc78,0x01760001,
1000 0xc78,0x00770001,
1001 0xc78,0x00780001,
1002 0xc78,0x00790001,
1003 0xc78,0x007a0001,
1004 0xc78,0x007b0001,
1005 0xc78,0x007c0001,
1006 0xc78,0x007d0001,
1007 0xc78,0x007e0001,
1008 0xc78,0x007f0001,
1009 0xc78,0x2e00001e,
1010 0xc78,0x2e01001e,
1011 0xc78,0x2e02001e,
1012 0xc78,0x2e03001e,
1013 0xc78,0x2e04001e,
1014 0xc78,0x2e05001e,
1015 0xc78,0x3006001e,
1016 0xc78,0x3407001e,
1017 0xc78,0x3908001e,
1018 0xc78,0x3c09001e,
1019 0xc78,0x3f0a001e,
1020 0xc78,0x420b001e,
1021 0xc78,0x440c001e,
1022 0xc78,0x450d001e,
1023 0xc78,0x460e001e,
1024 0xc78,0x460f001e,
1025 0xc78,0x4710001e,
1026 0xc78,0x4811001e,
1027 0xc78,0x4912001e,
1028 0xc78,0x4a13001e,
1029 0xc78,0x4b14001e,
1030 0xc78,0x4b15001e,
1031 0xc78,0x4c16001e,
1032 0xc78,0x4d17001e,
1033 0xc78,0x4e18001e,
1034 0xc78,0x4f19001e,
1035 0xc78,0x4f1a001e,
1036 0xc78,0x501b001e,
1037 0xc78,0x511c001e,
1038 0xc78,0x521d001e,
1039 0xc78,0x521e001e,
1040 0xc78,0x531f001e,
1041 0xc78,0x5320001e,
1042 0xc78,0x5421001e,
1043 0xc78,0x5522001e,
1044 0xc78,0x5523001e,
1045 0xc78,0x5624001e,
1046 0xc78,0x5725001e,
1047 0xc78,0x5726001e,
1048 0xc78,0x5827001e,
1049 0xc78,0x5828001e,
1050 0xc78,0x5929001e,
1051 0xc78,0x592a001e,
1052 0xc78,0x5a2b001e,
1053 0xc78,0x5b2c001e,
1054 0xc78,0x5c2d001e,
1055 0xc78,0x5c2e001e,
1056 0xc78,0x5d2f001e,
1057 0xc78,0x5e30001e,
1058 0xc78,0x5f31001e,
1059 0xc78,0x6032001e,
1060 0xc78,0x6033001e,
1061 0xc78,0x6134001e,
1062 0xc78,0x6235001e,
1063 0xc78,0x6336001e,
1064 0xc78,0x6437001e,
1065 0xc78,0x6438001e,
1066 0xc78,0x6539001e,
1067 0xc78,0x663a001e,
1068 0xc78,0x673b001e,
1069 0xc78,0x673c001e,
1070 0xc78,0x683d001e,
1071 0xc78,0x693e001e,
1072 0xc78,0x6a3f001e,
1073 };
1074 static u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLength] = {
1075 0x0, };
1076 static u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = {
1077 0x800,0x00000000,
1078 0x804,0x00000001,
1079 0x808,0x0000fc00,
1080 0x80c,0x0000001c,
1081 0x810,0x801010aa,
1082 0x814,0x008514d0,
1083 0x818,0x00000040,
1084 0x81c,0x00000000,
1085 0x820,0x00000004,
1086 0x824,0x00690000,
1087 0x828,0x00000004,
1088 0x82c,0x00e90000,
1089 0x830,0x00000004,
1090 0x834,0x00690000,
1091 0x838,0x00000004,
1092 0x83c,0x00e90000,
1093 0x840,0x00000000,
1094 0x844,0x00000000,
1095 0x848,0x00000000,
1096 0x84c,0x00000000,
1097 0x850,0x00000000,
1098 0x854,0x00000000,
1099 0x858,0x65a965a9,
1100 0x85c,0x65a965a9,
1101 0x860,0x001f0010,
1102 0x864,0x007f0010,
1103 0x868,0x001f0010,
1104 0x86c,0x007f0010,
1105 0x870,0x0f100f70,
1106 0x874,0x0f100f70,
1107 0x878,0x00000000,
1108 0x87c,0x00000000,
1109 0x880,0x6870e36c,
1110 0x884,0xe3573600,
1111 0x888,0x4260c340,
1112 0x88c,0x0000ff00,
1113 0x890,0x00000000,
1114 0x894,0xfffffffe,
1115 0x898,0x4c42382f,
1116 0x89c,0x00656056,
1117 0x8b0,0x00000000,
1118 0x8e0,0x00000000,
1119 0x8e4,0x00000000,
1120 0x900,0x00000000,
1121 0x904,0x00000023,
1122 0x908,0x00000000,
1123 0x90c,0x31121311,
1124 0xa00,0x00d0c7d8,
1125 0xa04,0x811f0008,
1126 0xa08,0x80cd8300,
1127 0xa0c,0x2e62740f,
1128 0xa10,0x95009b78,
1129 0xa14,0x11145008,
1130 0xa18,0x00881117,
1131 0xa1c,0x89140fa0,
1132 0xa20,0x1a1b0000,
1133 0xa24,0x090e1317,
1134 0xa28,0x00000204,
1135 0xa2c,0x00000000,
1136 0xc00,0x00000040,
1137 0xc04,0x00005433,
1138 0xc08,0x000000e4,
1139 0xc0c,0x6c6c6c6c,
1140 0xc10,0x08800000,
1141 0xc14,0x40000100,
1142 0xc18,0x08000000,
1143 0xc1c,0x40000100,
1144 0xc20,0x08000000,
1145 0xc24,0x40000100,
1146 0xc28,0x08000000,
1147 0xc2c,0x40000100,
1148 0xc30,0x6de9ac44,
1149 0xc34,0x465c52cd,
1150 0xc38,0x497f5994,
1151 0xc3c,0x0a969764,
1152 0xc40,0x1f7c403f,
1153 0xc44,0x000100b7,
1154 0xc48,0xec020000,
1155 0xc4c,0x00000300,
1156 0xc50,0x69543420,
1157 0xc54,0x433c0094,
1158 0xc58,0x69543420,
1159 0xc5c,0x433c0094,
1160 0xc60,0x69543420,
1161 0xc64,0x433c0094,
1162 0xc68,0x69543420,
1163 0xc6c,0x433c0094,
1164 0xc70,0x2c7f000d,
1165 0xc74,0x0186175b,
1166 0xc78,0x0000001f,
1167 0xc7c,0x00b91612,
1168 0xc80,0x40000100,
1169 0xc84,0x20000000,
1170 0xc88,0x40000100,
1171 0xc8c,0x20200000,
1172 0xc90,0x40000100,
1173 0xc94,0x00000000,
1174 0xc98,0x40000100,
1175 0xc9c,0x00000000,
1176 0xca0,0x00492492,
1177 0xca4,0x00000000,
1178 0xca8,0x00000000,
1179 0xcac,0x00000000,
1180 0xcb0,0x00000000,
1181 0xcb4,0x00000000,
1182 0xcb8,0x00000000,
1183 0xcbc,0x00492492,
1184 0xcc0,0x00000000,
1185 0xcc4,0x00000000,
1186 0xcc8,0x00000000,
1187 0xccc,0x00000000,
1188 0xcd0,0x00000000,
1189 0xcd4,0x00000000,
1190 0xcd8,0x64b22427,
1191 0xcdc,0x00766932,
1192 0xce0,0x00222222,
1193 0xd00,0x00000750,
1194 0xd04,0x00000403,
1195 0xd08,0x0000907f,
1196 0xd0c,0x00000001,
1197 0xd10,0xa0633333,
1198 0xd14,0x33333c63,
1199 0xd18,0x6a8f5b6b,
1200 0xd1c,0x00000000,
1201 0xd20,0x00000000,
1202 0xd24,0x00000000,
1203 0xd28,0x00000000,
1204 0xd2c,0xcc979975,
1205 0xd30,0x00000000,
1206 0xd34,0x00000000,
1207 0xd38,0x00000000,
1208 0xd3c,0x00027293,
1209 0xd40,0x00000000,
1210 0xd44,0x00000000,
1211 0xd48,0x00000000,
1212 0xd4c,0x00000000,
1213 0xd50,0x6437140a,
1214 0xd54,0x024dbd02,
1215 0xd58,0x00000000,
1216 0xd5c,0x04032064,
1217 0xe00,0x161a1a1a,
1218 0xe04,0x12121416,
1219 0xe08,0x00001800,
1220 0xe0c,0x00000000,
1221 0xe10,0x161a1a1a,
1222 0xe14,0x12121416,
1223 0xe18,0x161a1a1a,
1224 0xe1c,0x12121416,
1225 };
1226 static u32 Rtl8192PciERadioA_Array[RadioA_ArrayLength] = {
1227 0x019,0x00000003,
1228 0x000,0x000000bf,
1229 0x001,0x00000ee0,
1230 0x002,0x0000004c,
1231 0x003,0x000007f1,
1232 0x004,0x00000975,
1233 0x005,0x00000c58,
1234 0x006,0x00000ae6,
1235 0x007,0x000000ca,
1236 0x008,0x00000e1c,
1237 0x009,0x000007f0,
1238 0x00a,0x000009d0,
1239 0x00b,0x000001ba,
1240 0x00c,0x00000240,
1241 0x00e,0x00000020,
1242 0x00f,0x00000990,
1243 0x012,0x00000806,
1244 0x014,0x000005ab,
1245 0x015,0x00000f80,
1246 0x016,0x00000020,
1247 0x017,0x00000597,
1248 0x018,0x0000050a,
1249 0x01a,0x00000f80,
1250 0x01b,0x00000f5e,
1251 0x01c,0x00000008,
1252 0x01d,0x00000607,
1253 0x01e,0x000006cc,
1254 0x01f,0x00000000,
1255 0x020,0x000001a5,
1256 0x01f,0x00000001,
1257 0x020,0x00000165,
1258 0x01f,0x00000002,
1259 0x020,0x000000c6,
1260 0x01f,0x00000003,
1261 0x020,0x00000086,
1262 0x01f,0x00000004,
1263 0x020,0x00000046,
1264 0x01f,0x00000005,
1265 0x020,0x000001e6,
1266 0x01f,0x00000006,
1267 0x020,0x000001a6,
1268 0x01f,0x00000007,
1269 0x020,0x00000166,
1270 0x01f,0x00000008,
1271 0x020,0x000000c7,
1272 0x01f,0x00000009,
1273 0x020,0x00000087,
1274 0x01f,0x0000000a,
1275 0x020,0x000000f7,
1276 0x01f,0x0000000b,
1277 0x020,0x000000d7,
1278 0x01f,0x0000000c,
1279 0x020,0x000000b7,
1280 0x01f,0x0000000d,
1281 0x020,0x00000097,
1282 0x01f,0x0000000e,
1283 0x020,0x00000077,
1284 0x01f,0x0000000f,
1285 0x020,0x00000057,
1286 0x01f,0x00000010,
1287 0x020,0x00000037,
1288 0x01f,0x00000011,
1289 0x020,0x000000fb,
1290 0x01f,0x00000012,
1291 0x020,0x000000db,
1292 0x01f,0x00000013,
1293 0x020,0x000000bb,
1294 0x01f,0x00000014,
1295 0x020,0x000000ff,
1296 0x01f,0x00000015,
1297 0x020,0x000000e3,
1298 0x01f,0x00000016,
1299 0x020,0x000000c3,
1300 0x01f,0x00000017,
1301 0x020,0x000000a3,
1302 0x01f,0x00000018,
1303 0x020,0x00000083,
1304 0x01f,0x00000019,
1305 0x020,0x00000063,
1306 0x01f,0x0000001a,
1307 0x020,0x00000043,
1308 0x01f,0x0000001b,
1309 0x020,0x00000023,
1310 0x01f,0x0000001c,
1311 0x020,0x00000003,
1312 0x01f,0x0000001d,
1313 0x020,0x000001e3,
1314 0x01f,0x0000001e,
1315 0x020,0x000001c3,
1316 0x01f,0x0000001f,
1317 0x020,0x000001a3,
1318 0x01f,0x00000020,
1319 0x020,0x00000183,
1320 0x01f,0x00000021,
1321 0x020,0x00000163,
1322 0x01f,0x00000022,
1323 0x020,0x00000143,
1324 0x01f,0x00000023,
1325 0x020,0x00000123,
1326 0x01f,0x00000024,
1327 0x020,0x00000103,
1328 0x023,0x00000203,
1329 0x024,0x00000100,
1330 0x00b,0x000001ba,
1331 0x02c,0x000003d7,
1332 0x02d,0x00000ff0,
1333 0x000,0x00000037,
1334 0x004,0x00000160,
1335 0x007,0x00000080,
1336 0x002,0x0000088d,
1337 0x0fe,0x00000000,
1338 0x0fe,0x00000000,
1339 0x016,0x00000200,
1340 0x016,0x00000380,
1341 0x016,0x00000020,
1342 0x016,0x000001a0,
1343 0x000,0x000000bf,
1344 0x00d,0x0000001f,
1345 0x00d,0x00000c9f,
1346 0x002,0x0000004d,
1347 0x000,0x00000cbf,
1348 0x004,0x00000975,
1349 0x007,0x00000700,
1350 };
1351 static u32 Rtl8192PciERadioB_Array[RadioB_ArrayLength] = {
1352 0x019,0x00000003,
1353 0x000,0x000000bf,
1354 0x001,0x000006e0,
1355 0x002,0x0000004c,
1356 0x003,0x000007f1,
1357 0x004,0x00000975,
1358 0x005,0x00000c58,
1359 0x006,0x00000ae6,
1360 0x007,0x000000ca,
1361 0x008,0x00000e1c,
1362 0x000,0x000000b7,
1363 0x00a,0x00000850,
1364 0x000,0x000000bf,
1365 0x00b,0x000001ba,
1366 0x00c,0x00000240,
1367 0x00e,0x00000020,
1368 0x015,0x00000f80,
1369 0x016,0x00000020,
1370 0x017,0x00000597,
1371 0x018,0x0000050a,
1372 0x01a,0x00000e00,
1373 0x01b,0x00000f5e,
1374 0x01d,0x00000607,
1375 0x01e,0x000006cc,
1376 0x00b,0x000001ba,
1377 0x023,0x00000203,
1378 0x024,0x00000100,
1379 0x000,0x00000037,
1380 0x004,0x00000160,
1381 0x016,0x00000200,
1382 0x016,0x00000380,
1383 0x016,0x00000020,
1384 0x016,0x000001a0,
1385 0x00d,0x00000ccc,
1386 0x000,0x000000bf,
1387 0x002,0x0000004d,
1388 0x000,0x00000cbf,
1389 0x004,0x00000975,
1390 0x007,0x00000700,
1391 };
1392 static u32 Rtl8192PciERadioC_Array[RadioC_ArrayLength] = {
1393 0x0, };
1394 static u32 Rtl8192PciERadioD_Array[RadioD_ArrayLength] = {
1395 0x0, };
1396 #endif
1397
1398 /*************************Define local function prototype**********************/
1399
1400 static u32 phy_FwRFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset);
1401 static void phy_FwRFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32 Data);
1402 /*************************Define local function prototype**********************/
1403 /******************************************************************************
1404 *function: This function read BB parameters from Header file we gen,
1405 * and do register read/write
1406 * input: u32 dwBitMask //taget bit pos in the addr to be modified
1407 * output: none
1408 * return: u32 return the shift bit bit position of the mask
1409 * ****************************************************************************/
1410 static u32 rtl8192_CalculateBitShift(u32 dwBitMask)
1411 {
1412 u32 i;
1413 for (i=0; i<=31; i++)
1414 {
1415 if (((dwBitMask>>i)&0x1) == 1)
1416 break;
1417 }
1418 return i;
1419 }
1420 /******************************************************************************
1421 *function: This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false.
1422 * input: none
1423 * output: none
1424 * return: 0(illegal, false), 1(legal,true)
1425 * ***************************************************************************/
1426 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
1427 {
1428 u8 ret = 1;
1429 struct r8192_priv *priv = ieee80211_priv(dev);
1430 #ifdef RTL8190P
1431 if(priv->rf_type == RF_2T4R)
1432 {
1433 ret= 1;
1434 }
1435 else if (priv->rf_type == RF_1T2R)
1436 {
1437 if(eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
1438 ret = 0;
1439 else if(eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
1440 ret = 1;
1441 }
1442 #else
1443 #ifdef RTL8192E
1444 if (priv->rf_type == RF_2T4R)
1445 ret = 0;
1446 else if (priv->rf_type == RF_1T2R)
1447 {
1448 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
1449 ret = 1;
1450 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
1451 ret = 0;
1452 }
1453 #endif
1454 #endif
1455 return ret;
1456 }
1457 /******************************************************************************
1458 *function: This function set specific bits to BB register
1459 * input: net_device dev
1460 * u32 dwRegAddr //target addr to be modified
1461 * u32 dwBitMask //taget bit pos in the addr to be modified
1462 * u32 dwData //value to be write
1463 * output: none
1464 * return: none
1465 * notice:
1466 * ****************************************************************************/
1467 void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
1468 {
1469
1470 u32 OriginalValue, BitShift, NewValue;
1471
1472 if(dwBitMask!= bMaskDWord)
1473 {//if not "double word" write
1474 OriginalValue = read_nic_dword(dev, dwRegAddr);
1475 BitShift = rtl8192_CalculateBitShift(dwBitMask);
1476 NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
1477 write_nic_dword(dev, dwRegAddr, NewValue);
1478 }else
1479 write_nic_dword(dev, dwRegAddr, dwData);
1480 return;
1481 }
1482 /******************************************************************************
1483 *function: This function reads specific bits from BB register
1484 * input: net_device dev
1485 * u32 dwRegAddr //target addr to be readback
1486 * u32 dwBitMask //taget bit pos in the addr to be readback
1487 * output: none
1488 * return: u32 Data //the readback register value
1489 * notice:
1490 * ****************************************************************************/
1491 u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask)
1492 {
1493 u32 Ret = 0, OriginalValue, BitShift;
1494
1495 OriginalValue = read_nic_dword(dev, dwRegAddr);
1496 BitShift = rtl8192_CalculateBitShift(dwBitMask);
1497 Ret = (OriginalValue & dwBitMask) >> BitShift;
1498
1499 return (Ret);
1500 }
1501 /******************************************************************************
1502 *function: This function read register from RF chip
1503 * input: net_device dev
1504 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
1505 * u32 Offset //target address to be read
1506 * output: none
1507 * return: u32 readback value
1508 * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information.
1509 * ****************************************************************************/
1510 static u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset)
1511 {
1512 struct r8192_priv *priv = ieee80211_priv(dev);
1513 u32 ret = 0;
1514 u32 NewOffset = 0;
1515 BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath];
1516 //rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
1517 //make sure RF register offset is correct
1518 Offset &= 0x3f;
1519
1520 //switch page for 8256 RF IC
1521 if (priv->rf_chip == RF_8256)
1522 {
1523 #ifdef RTL8190P
1524 //analog to digital off, for protection
1525 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1526 #else
1527 #ifdef RTL8192E
1528 //analog to digital off, for protection
1529 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1530 #endif
1531 #endif
1532 if (Offset >= 31)
1533 {
1534 priv->RfReg0Value[eRFPath] |= 0x140;
1535 //Switch to Reg_Mode2 for Reg 31-45
1536 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
1537 //modify offset
1538 NewOffset = Offset -30;
1539 }
1540 else if (Offset >= 16)
1541 {
1542 priv->RfReg0Value[eRFPath] |= 0x100;
1543 priv->RfReg0Value[eRFPath] &= (~0x40);
1544 //Switch to Reg_Mode 1 for Reg16-30
1545 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
1546
1547 NewOffset = Offset - 15;
1548 }
1549 else
1550 NewOffset = Offset;
1551 }
1552 else
1553 {
1554 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
1555 NewOffset = Offset;
1556 }
1557 //put desired read addr to LSSI control Register
1558 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
1559 //Issue a posedge trigger
1560 //
1561 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
1562 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
1563
1564
1565 // TODO: we should not delay such a long time. Ask help from SD3
1566 msleep(1);
1567
1568 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
1569
1570
1571 // Switch back to Reg_Mode0;
1572 if(priv->rf_chip == RF_8256)
1573 {
1574 priv->RfReg0Value[eRFPath] &= 0xebf;
1575
1576 rtl8192_setBBreg(
1577 dev,
1578 pPhyReg->rf3wireOffset,
1579 bMaskDWord,
1580 (priv->RfReg0Value[eRFPath] << 16));
1581
1582 #ifdef RTL8190P
1583 if(priv->rf_type == RF_2T4R)
1584 {
1585 //analog to digital on
1586 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
1587 }
1588 else if(priv->rf_type == RF_1T2R)
1589 {
1590 //analog to digital on
1591 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10]
1592 }
1593 #else
1594 #ifdef RTL8192E
1595 //analog to digital on
1596 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
1597 #endif
1598 #endif
1599 }
1600
1601
1602 return ret;
1603
1604 }
1605
1606 /******************************************************************************
1607 *function: This function write data to RF register
1608 * input: net_device dev
1609 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
1610 * u32 Offset //target address to be written
1611 * u32 Data //The new register data to be written
1612 * output: none
1613 * return: none
1614 * notice: For RF8256 only.
1615 ===========================================================
1616 *Reg Mode RegCTL[1] RegCTL[0] Note
1617 * (Reg00[12]) (Reg00[10])
1618 *===========================================================
1619 *Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
1620 *------------------------------------------------------------------
1621 *Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
1622 *------------------------------------------------------------------
1623 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
1624 *------------------------------------------------------------------
1625 * ****************************************************************************/
1626 static void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data)
1627 {
1628 struct r8192_priv *priv = ieee80211_priv(dev);
1629 u32 DataAndAddr = 0, NewOffset = 0;
1630 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
1631
1632 Offset &= 0x3f;
1633 if (priv->rf_chip == RF_8256)
1634 {
1635
1636 #ifdef RTL8190P
1637 //analog to digital off, for protection
1638 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1639 #else
1640 #ifdef RTL8192E
1641 //analog to digital off, for protection
1642 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1643 #endif
1644 #endif
1645
1646 if (Offset >= 31)
1647 {
1648 priv->RfReg0Value[eRFPath] |= 0x140;
1649 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
1650 NewOffset = Offset - 30;
1651 }
1652 else if (Offset >= 16)
1653 {
1654 priv->RfReg0Value[eRFPath] |= 0x100;
1655 priv->RfReg0Value[eRFPath] &= (~0x40);
1656 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
1657 NewOffset = Offset - 15;
1658 }
1659 else
1660 NewOffset = Offset;
1661 }
1662 else
1663 {
1664 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
1665 NewOffset = Offset;
1666 }
1667
1668 // Put write addr in [5:0] and write data in [31:16]
1669 DataAndAddr = (Data<<16) | (NewOffset&0x3f);
1670
1671 // Write Operation
1672 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
1673
1674
1675 if(Offset==0x0)
1676 priv->RfReg0Value[eRFPath] = Data;
1677
1678 // Switch back to Reg_Mode0;
1679 if(priv->rf_chip == RF_8256)
1680 {
1681 if(Offset != 0)
1682 {
1683 priv->RfReg0Value[eRFPath] &= 0xebf;
1684 rtl8192_setBBreg(
1685 dev,
1686 pPhyReg->rf3wireOffset,
1687 bMaskDWord,
1688 (priv->RfReg0Value[eRFPath] << 16));
1689 }
1690 #ifdef RTL8190P
1691 if(priv->rf_type == RF_2T4R)
1692 {
1693 //analog to digital on
1694 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
1695 }
1696 else if(priv->rf_type == RF_1T2R)
1697 {
1698 //analog to digital on
1699 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10]
1700 }
1701 #else
1702 #ifdef RTL8192E
1703 //analog to digital on
1704 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
1705 #endif
1706 #endif
1707 }
1708
1709 return;
1710 }
1711
1712 /******************************************************************************
1713 *function: This function set specific bits to RF register
1714 * input: net_device dev
1715 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
1716 * u32 RegAddr //target addr to be modified
1717 * u32 BitMask //taget bit pos in the addr to be modified
1718 * u32 Data //value to be write
1719 * output: none
1720 * return: none
1721 * notice:
1722 * ****************************************************************************/
1723 void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
1724 {
1725 struct r8192_priv *priv = ieee80211_priv(dev);
1726 u32 Original_Value, BitShift, New_Value;
1727 // u8 time = 0;
1728
1729 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1730 return;
1731 #ifdef RTL8192E
1732 if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter)
1733 return;
1734 #endif
1735 //spin_lock_irqsave(&priv->rf_lock, flags);
1736 //down(&priv->rf_sem);
1737
1738 RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
1739 if (priv->Rf_Mode == RF_OP_By_FW)
1740 {
1741 if (BitMask != bMask12Bits) // RF data is 12 bits only
1742 {
1743 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
1744 BitShift = rtl8192_CalculateBitShift(BitMask);
1745 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
1746
1747 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
1748 }else
1749 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
1750 udelay(200);
1751
1752 }
1753 else
1754 {
1755 if (BitMask != bMask12Bits) // RF data is 12 bits only
1756 {
1757 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
1758 BitShift = rtl8192_CalculateBitShift(BitMask);
1759 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
1760
1761 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
1762 }else
1763 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
1764 }
1765 //spin_unlock_irqrestore(&priv->rf_lock, flags);
1766 //up(&priv->rf_sem);
1767 return;
1768 }
1769
1770 /******************************************************************************
1771 *function: This function reads specific bits from RF register
1772 * input: net_device dev
1773 * u32 RegAddr //target addr to be readback
1774 * u32 BitMask //taget bit pos in the addr to be readback
1775 * output: none
1776 * return: u32 Data //the readback register value
1777 * notice:
1778 * ****************************************************************************/
1779 u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
1780 {
1781 u32 Original_Value, Readback_Value, BitShift;
1782 struct r8192_priv *priv = ieee80211_priv(dev);
1783 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1784 return 0;
1785 #ifdef RTL8192E
1786 if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter)
1787 return 0;
1788 #endif
1789 down(&priv->rf_sem);
1790 if (priv->Rf_Mode == RF_OP_By_FW)
1791 {
1792 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
1793 udelay(200);
1794 }
1795 else
1796 {
1797 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
1798
1799 }
1800 BitShift = rtl8192_CalculateBitShift(BitMask);
1801 Readback_Value = (Original_Value & BitMask) >> BitShift;
1802 up(&priv->rf_sem);
1803 // udelay(200);
1804 return (Readback_Value);
1805 }
1806
1807 /******************************************************************************
1808 *function: We support firmware to execute RF-R/W.
1809 * input: dev
1810 * output: none
1811 * return: none
1812 * notice:
1813 * ***************************************************************************/
1814 static u32 phy_FwRFSerialRead(
1815 struct net_device* dev,
1816 RF90_RADIO_PATH_E eRFPath,
1817 u32 Offset )
1818 {
1819 u32 retValue = 0;
1820 u32 Data = 0;
1821 u8 time = 0;
1822 //DbgPrint("FW RF CTRL\n\r");
1823 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
1824 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
1825 much time. This is only for site survey. */
1826 // 1. Read operation need not insert data. bit 0-11
1827 //Data &= bMask12Bits;
1828 // 2. Write RF register address. Bit 12-19
1829 Data |= ((Offset&0xFF)<<12);
1830 // 3. Write RF path. bit 20-21
1831 Data |= ((eRFPath&0x3)<<20);
1832 // 4. Set RF read indicator. bit 22=0
1833 //Data |= 0x00000;
1834 // 5. Trigger Fw to operate the command. bit 31
1835 Data |= 0x80000000;
1836 // 6. We can not execute read operation if bit 31 is 1.
1837 while (read_nic_dword(dev, QPNR)&0x80000000)
1838 {
1839 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
1840 if (time++ < 100)
1841 {
1842 //DbgPrint("FW not finish RF-R Time=%d\n\r", time);
1843 udelay(10);
1844 }
1845 else
1846 break;
1847 }
1848 // 7. Execute read operation.
1849 write_nic_dword(dev, QPNR, Data);
1850 // 8. Check if firmawre send back RF content.
1851 while (read_nic_dword(dev, QPNR)&0x80000000)
1852 {
1853 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
1854 if (time++ < 100)
1855 {
1856 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
1857 udelay(10);
1858 }
1859 else
1860 return (0);
1861 }
1862 retValue = read_nic_dword(dev, RF_DATA);
1863
1864 return (retValue);
1865
1866 } /* phy_FwRFSerialRead */
1867
1868 /******************************************************************************
1869 *function: We support firmware to execute RF-R/W.
1870 * input: dev
1871 * output: none
1872 * return: none
1873 * notice:
1874 * ***************************************************************************/
1875 static void
1876 phy_FwRFSerialWrite(
1877 struct net_device* dev,
1878 RF90_RADIO_PATH_E eRFPath,
1879 u32 Offset,
1880 u32 Data )
1881 {
1882 u8 time = 0;
1883
1884 //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
1885 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
1886 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
1887 much time. This is only for site survey. */
1888
1889 // 1. Set driver write bit and 12 bit data. bit 0-11
1890 //Data &= bMask12Bits; // Done by uper layer.
1891 // 2. Write RF register address. bit 12-19
1892 Data |= ((Offset&0xFF)<<12);
1893 // 3. Write RF path. bit 20-21
1894 Data |= ((eRFPath&0x3)<<20);
1895 // 4. Set RF write indicator. bit 22=1
1896 Data |= 0x400000;
1897 // 5. Trigger Fw to operate the command. bit 31=1
1898 Data |= 0x80000000;
1899
1900 // 6. Write operation. We can not write if bit 31 is 1.
1901 while (read_nic_dword(dev, QPNR)&0x80000000)
1902 {
1903 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
1904 if (time++ < 100)
1905 {
1906 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
1907 udelay(10);
1908 }
1909 else
1910 break;
1911 }
1912 // 7. No matter check bit. We always force the write. Because FW will
1913 // not accept the command.
1914 write_nic_dword(dev, QPNR, Data);
1915 /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
1916 to finish RF write operation. */
1917 /* 2008/01/17 MH We support delay in firmware side now. */
1918 //delay_us(20);
1919
1920 } /* phy_FwRFSerialWrite */
1921
1922
1923 /******************************************************************************
1924 *function: This function read BB parameters from Header file we gen,
1925 * and do register read/write
1926 * input: dev
1927 * output: none
1928 * return: none
1929 * notice: BB parameters may change all the time, so please make
1930 * sure it has been synced with the newest.
1931 * ***************************************************************************/
1932 void rtl8192_phy_configmac(struct net_device* dev)
1933 {
1934 u32 dwArrayLen = 0, i = 0;
1935 u32* pdwArray = NULL;
1936 struct r8192_priv *priv = ieee80211_priv(dev);
1937 #ifdef TO_DO_LIST
1938 if(Adapter->bInHctTest)
1939 {
1940 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_ArrayDTM\n");
1941 dwArrayLen = MACPHY_ArrayLengthDTM;
1942 pdwArray = Rtl819XMACPHY_ArrayDTM;
1943 }
1944 else if(priv->bTXPowerDataReadFromEEPORM)
1945 #endif
1946 if(priv->bTXPowerDataReadFromEEPORM)
1947 {
1948 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
1949 dwArrayLen = MACPHY_Array_PGLength;
1950 pdwArray = Rtl819XMACPHY_Array_PG;
1951
1952 }
1953 else
1954 {
1955 RT_TRACE(COMP_PHY,"Read rtl819XMACPHY_Array\n");
1956 dwArrayLen = MACPHY_ArrayLength;
1957 pdwArray = Rtl819XMACPHY_Array;
1958 }
1959 for(i = 0; i<dwArrayLen; i=i+3){
1960 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
1961 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
1962 if(pdwArray[i] == 0x318)
1963 {
1964 pdwArray[i+2] = 0x00000800;
1965 //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
1966 // ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1967 }
1968 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
1969 }
1970 return;
1971
1972 }
1973
1974 /******************************************************************************
1975 *function: This function do dirty work
1976 * input: dev
1977 * output: none
1978 * return: none
1979 * notice: BB parameters may change all the time, so please make
1980 * sure it has been synced with the newest.
1981 * ***************************************************************************/
1982
1983 void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType)
1984 {
1985 int i;
1986 //u8 ArrayLength;
1987 u32* Rtl819XPHY_REGArray_Table = NULL;
1988 u32* Rtl819XAGCTAB_Array_Table = NULL;
1989 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
1990 struct r8192_priv *priv = ieee80211_priv(dev);
1991 #ifdef TO_DO_LIST
1992 u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
1993 if(Adapter->bInHctTest)
1994 {
1995 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
1996 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
1997
1998 if(priv->RF_Type == RF_2T4R)
1999 {
2000 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
2001 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
2002 }
2003 else if (priv->RF_Type == RF_1T2R)
2004 {
2005 PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
2006 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
2007 }
2008 }
2009 else
2010 #endif
2011 {
2012 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
2013 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
2014 if(priv->rf_type == RF_2T4R)
2015 {
2016 PHY_REGArrayLen = PHY_REGArrayLength;
2017 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
2018 }
2019 else if (priv->rf_type == RF_1T2R)
2020 {
2021 PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
2022 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
2023 }
2024 }
2025
2026 if (ConfigType == BaseBand_Config_PHY_REG)
2027 {
2028 for (i=0; i<PHY_REGArrayLen; i+=2)
2029 {
2030 rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
2031 RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
2032 }
2033 }
2034 else if (ConfigType == BaseBand_Config_AGC_TAB)
2035 {
2036 for (i=0; i<AGCTAB_ArrayLen; i+=2)
2037 {
2038 rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
2039 RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]);
2040 }
2041 }
2042 return;
2043
2044
2045 }
2046 /******************************************************************************
2047 *function: This function initialize Register definition offset for Radio Path
2048 * A/B/C/D
2049 * input: net_device dev
2050 * output: none
2051 * return: none
2052 * notice: Initialization value here is constant and it should never be changed
2053 * ***************************************************************************/
2054 static void rtl8192_InitBBRFRegDef(struct net_device* dev)
2055 {
2056 struct r8192_priv *priv = ieee80211_priv(dev);
2057 // RF Interface Sowrtware Control
2058 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
2059 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
2060 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
2061 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
2062
2063 // RF Interface Readback Value
2064 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
2065 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
2066 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
2067 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
2068
2069 // RF Interface Output (and Enable)
2070 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
2071 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
2072 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
2073 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
2074
2075 // RF Interface (Output and) Enable
2076 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
2077 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
2078 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
2079 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
2080
2081 //Addr of LSSI. Wirte RF register by driver
2082 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
2083 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
2084 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
2085 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
2086
2087 // RF parameter
2088 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select
2089 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
2090 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
2091 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
2092
2093 // Tx AGC Gain Stage (same for all path. Should we remove this?)
2094 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2095 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2096 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2097 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2098
2099 // Tranceiver A~D HSSI Parameter-1
2100 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1
2101 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1
2102 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1
2103 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1
2104
2105 // Tranceiver A~D HSSI Parameter-2
2106 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2
2107 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2
2108 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2
2109 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1
2110
2111 // RF switch Control
2112 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
2113 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
2114 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
2115 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
2116
2117 // AGC control 1
2118 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
2119 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
2120 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
2121 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
2122
2123 // AGC control 2
2124 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
2125 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
2126 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
2127 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
2128
2129 // RX AFE control 1
2130 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
2131 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
2132 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
2133 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
2134
2135 // RX AFE control 1
2136 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
2137 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
2138 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
2139 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
2140
2141 // Tx AFE control 1
2142 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
2143 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
2144 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
2145 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
2146
2147 // Tx AFE control 2
2148 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
2149 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
2150 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
2151 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
2152
2153 // Tranceiver LSSI Readback
2154 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
2155 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
2156 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
2157 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
2158
2159 }
2160 /******************************************************************************
2161 *function: This function is to write register and then readback to make sure whether BB and RF is OK
2162 * input: net_device dev
2163 * HW90_BLOCK_E CheckBlock
2164 * RF90_RADIO_PATH_E eRFPath //only used when checkblock is HW90_BLOCK_RF
2165 * output: none
2166 * return: return whether BB and RF is ok(0:OK; 1:Fail)
2167 * notice: This function may be removed in the ASIC
2168 * ***************************************************************************/
2169 RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath)
2170 {
2171 //struct r8192_priv *priv = ieee80211_priv(dev);
2172 // BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
2173 RT_STATUS ret = RT_STATUS_SUCCESS;
2174 u32 i, CheckTimes = 4, dwRegRead = 0;
2175 u32 WriteAddr[4];
2176 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
2177 // Initialize register address offset to be checked
2178 WriteAddr[HW90_BLOCK_MAC] = 0x100;
2179 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
2180 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
2181 WriteAddr[HW90_BLOCK_RF] = 0x3;
2182 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock);
2183 for(i=0 ; i < CheckTimes ; i++)
2184 {
2185
2186 //
2187 // Write Data to register and readback
2188 //
2189 switch(CheckBlock)
2190 {
2191 case HW90_BLOCK_MAC:
2192 RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!");
2193 break;
2194
2195 case HW90_BLOCK_PHY0:
2196 case HW90_BLOCK_PHY1:
2197 write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
2198 dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
2199 break;
2200
2201 case HW90_BLOCK_RF:
2202 WriteData[i] &= 0xfff;
2203 rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]);
2204 // TODO: we should not delay for such a long time. Ask SD3
2205 mdelay(10);
2206 dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
2207 mdelay(10);
2208 break;
2209
2210 default:
2211 ret = RT_STATUS_FAILURE;
2212 break;
2213 }
2214
2215
2216 //
2217 // Check whether readback data is correct
2218 //
2219 if(dwRegRead != WriteData[i])
2220 {
2221 RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]);
2222 ret = RT_STATUS_FAILURE;
2223 break;
2224 }
2225 }
2226
2227 return ret;
2228 }
2229
2230
2231 /******************************************************************************
2232 *function: This function initialize BB&RF
2233 * input: net_device dev
2234 * output: none
2235 * return: none
2236 * notice: Initialization value may change all the time, so please make
2237 * sure it has been synced with the newest.
2238 * ***************************************************************************/
2239 static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev)
2240 {
2241 struct r8192_priv *priv = ieee80211_priv(dev);
2242 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
2243 u8 bRegValue = 0, eCheckItem = 0;
2244 u32 dwRegValue = 0;
2245 /**************************************
2246 //<1>Initialize BaseBand
2247 **************************************/
2248
2249 /*--set BB Global Reset--*/
2250 bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET);
2251 write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
2252
2253 /*---set BB reset Active---*/
2254 dwRegValue = read_nic_dword(dev, CPU_GEN);
2255 write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
2256
2257 /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
2258 // TODO: this function should be removed on ASIC , Emily 2007.2.2
2259 for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++)
2260 {
2261 rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path
2262 if(rtStatus != RT_STATUS_SUCCESS)
2263 {
2264 RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
2265 return rtStatus;
2266 }
2267 }
2268 /*---- Set CCK and OFDM Block "OFF"----*/
2269 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
2270 /*----BB Register Initilazation----*/
2271 //==m==>Set PHY REG From Header<==m==
2272 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
2273
2274 /*----Set BB reset de-Active----*/
2275 dwRegValue = read_nic_dword(dev, CPU_GEN);
2276 write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
2277
2278 /*----BB AGC table Initialization----*/
2279 //==m==>Set PHY REG From Header<==m==
2280 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
2281
2282 if (priv->card_8192_version > VERSION_8190_BD)
2283 {
2284 if(priv->rf_type == RF_2T4R)
2285 {
2286 // Antenna gain offset from B/C/D to A
2287 dwRegValue = ( priv->AntennaTxPwDiff[2]<<8 |
2288 priv->AntennaTxPwDiff[1]<<4 |
2289 priv->AntennaTxPwDiff[0]);
2290 }
2291 else
2292 dwRegValue = 0x0; //Antenna gain offset doesn't make sense in RF 1T2R.
2293 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
2294 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
2295
2296
2297 //XSTALLCap
2298 #ifdef RTL8190P
2299 dwRegValue = priv->CrystalCap & 0x3; // bit0~1 of crystal cap
2300 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap01, dwRegValue);
2301 dwRegValue = ((priv->CrystalCap & 0xc)>>2); // bit2~3 of crystal cap
2302 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, bXtalCap23, dwRegValue);
2303 #else
2304 #ifdef RTL8192E
2305 dwRegValue = priv->CrystalCap;
2306 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue);
2307 #endif
2308 #endif
2309
2310 }
2311
2312 // Check if the CCK HighPower is turned ON.
2313 // This is used to calculate PWDB.
2314 // priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
2315 return rtStatus;
2316 }
2317 /******************************************************************************
2318 *function: This function initialize BB&RF
2319 * input: net_device dev
2320 * output: none
2321 * return: none
2322 * notice: Initialization value may change all the time, so please make
2323 * sure it has been synced with the newest.
2324 * ***************************************************************************/
2325 RT_STATUS rtl8192_BBConfig(struct net_device* dev)
2326 {
2327 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
2328 rtl8192_InitBBRFRegDef(dev);
2329 //config BB&RF. As hardCode based initialization has not been well
2330 rtStatus = rtl8192_BB_Config_ParaFile(dev);
2331 return rtStatus;
2332 }
2333
2334 /******************************************************************************
2335 *function: This function obtains the initialization value of Tx power Level offset
2336 * input: net_device dev
2337 * output: none
2338 * return: none
2339 * ***************************************************************************/
2340 void rtl8192_phy_getTxPower(struct net_device* dev)
2341 {
2342 struct r8192_priv *priv = ieee80211_priv(dev);
2343 #ifdef RTL8190P
2344 priv->MCSTxPowerLevelOriginalOffset[0] =
2345 read_nic_dword(dev, MCS_TXAGC);
2346 priv->MCSTxPowerLevelOriginalOffset[1] =
2347 read_nic_dword(dev, (MCS_TXAGC+4));
2348 priv->CCKTxPowerLevelOriginalOffset =
2349 read_nic_dword(dev, CCK_TXAGC);
2350 #else
2351 #ifdef RTL8192E
2352 priv->MCSTxPowerLevelOriginalOffset[0] =
2353 read_nic_dword(dev, rTxAGC_Rate18_06);
2354 priv->MCSTxPowerLevelOriginalOffset[1] =
2355 read_nic_dword(dev, rTxAGC_Rate54_24);
2356 priv->MCSTxPowerLevelOriginalOffset[2] =
2357 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00);
2358 priv->MCSTxPowerLevelOriginalOffset[3] =
2359 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04);
2360 priv->MCSTxPowerLevelOriginalOffset[4] =
2361 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08);
2362 priv->MCSTxPowerLevelOriginalOffset[5] =
2363 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12);
2364 #endif
2365 #endif
2366
2367 // read rx initial gain
2368 priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1);
2369 priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
2370 priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1);
2371 priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
2372 RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
2373 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
2374 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
2375
2376 // read framesync
2377 priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3);
2378 priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2);
2379 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
2380 rOFDM0_RxDetector3, priv->framesync);
2381 // read SIFS (save the value read fome MACPHY_REG.txt)
2382 priv->SifsTime = read_nic_word(dev, SIFS);
2383 return;
2384 }
2385
2386 /******************************************************************************
2387 *function: This function obtains the initialization value of Tx power Level offset
2388 * input: net_device dev
2389 * output: none
2390 * return: none
2391 * ***************************************************************************/
2392 void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
2393 {
2394 struct r8192_priv *priv = ieee80211_priv(dev);
2395 u8 powerlevel = 0,powerlevelOFDM24G = 0;
2396 char ant_pwr_diff;
2397 u32 u4RegValue;
2398
2399 if(priv->epromtype == EPROM_93c46)
2400 {
2401 powerlevel = priv->TxPowerLevelCCK[channel-1];
2402 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
2403 }
2404 else if(priv->epromtype == EPROM_93c56)
2405 {
2406 if(priv->rf_type == RF_1T2R)
2407 {
2408 powerlevel = priv->TxPowerLevelCCK_C[channel-1];
2409 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
2410 }
2411 else if(priv->rf_type == RF_2T4R)
2412 {
2413 // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-C Tx
2414 // Power must be calculated by the antenna diff.
2415 // So we have to rewrite Antenna gain offset register here.
2416 powerlevel = priv->TxPowerLevelCCK_A[channel-1];
2417 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
2418
2419 ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
2420 -priv->TxPowerLevelOFDM24G_A[channel-1];
2421 ant_pwr_diff &= 0xf;
2422 //DbgPrint(" ant_pwr_diff = 0x%x", (u8)(ant_pwr_diff));
2423 priv->RF_C_TxPwDiff = ant_pwr_diff;
2424
2425 priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care
2426 priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);// RF-C
2427 priv->AntennaTxPwDiff[0] = 0;// RF-B, don't care
2428
2429 // Antenna gain offset from B/C/D to A
2430 u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 |
2431 priv->AntennaTxPwDiff[1]<<4 |
2432 priv->AntennaTxPwDiff[0]);
2433
2434 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
2435 (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
2436 }
2437 }
2438 #ifdef TODO
2439 //
2440 // CCX 2 S31, AP control of client transmit power:
2441 // 1. We shall not exceed Cell Power Limit as possible as we can.
2442 // 2. Tolerance is +/- 5dB.
2443 // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
2444 //
2445 // TODO:
2446 // 1. 802.11h power contraint
2447 //
2448 // 071011, by rcnjko.
2449 //
2450 if( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
2451 pMgntInfo->bWithCcxCellPwr &&
2452 channel == pMgntInfo->dot11CurrentChannelNumber)
2453 {
2454 u8 CckCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pMgntInfo->CcxCellPwr);
2455 u8 LegacyOfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pMgntInfo->CcxCellPwr);
2456 u8 OfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pMgntInfo->CcxCellPwr);
2457
2458 RT_TRACE(COMP_TXAGC, DBG_LOUD,
2459 ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2460 pMgntInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
2461 RT_TRACE(COMP_TXAGC, DBG_LOUD,
2462 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2463 channel, powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2464
2465 // CCK
2466 if(powerlevel > CckCellPwrIdx)
2467 powerlevel = CckCellPwrIdx;
2468 // Legacy OFDM, HT OFDM
2469 if(powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff > OfdmCellPwrIdx)
2470 {
2471 if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)
2472 {
2473 powerlevelOFDM24G = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff;
2474 }
2475 else
2476 {
2477 LegacyOfdmCellPwrIdx = 0;
2478 }
2479 }
2480
2481 RT_TRACE(COMP_TXAGC, DBG_LOUD,
2482 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
2483 powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2484 }
2485
2486 pHalData->CurrentCckTxPwrIdx = powerlevel;
2487 pHalData->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
2488 #endif
2489 switch(priv->rf_chip)
2490 {
2491 case RF_8225:
2492 // PHY_SetRF8225CckTxPower(Adapter, powerlevel);
2493 // PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
2494 break;
2495 case RF_8256:
2496 PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement
2497 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
2498 break;
2499 case RF_8258:
2500 break;
2501 default:
2502 RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n", __FUNCTION__);
2503 break;
2504 }
2505 return;
2506 }
2507
2508 /******************************************************************************
2509 *function: This function check Rf chip to do RF config
2510 * input: net_device dev
2511 * output: none
2512 * return: only 8256 is supported
2513 * ***************************************************************************/
2514 RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev)
2515 {
2516 struct r8192_priv *priv = ieee80211_priv(dev);
2517 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
2518 switch(priv->rf_chip)
2519 {
2520 case RF_8225:
2521 // rtStatus = PHY_RF8225_Config(Adapter);
2522 break;
2523 case RF_8256:
2524 rtStatus = PHY_RF8256_Config(dev);
2525 break;
2526
2527 case RF_8258:
2528 break;
2529 case RF_PSEUDO_11N:
2530 //rtStatus = PHY_RF8225_Config(Adapter);
2531 break;
2532
2533 default:
2534 RT_TRACE(COMP_ERR, "error chip id\n");
2535 break;
2536 }
2537 return rtStatus;
2538 }
2539
2540 /******************************************************************************
2541 *function: This function update Initial gain
2542 * input: net_device dev
2543 * output: none
2544 * return: As Windows has not implemented this, wait for complement
2545 * ***************************************************************************/
2546 void rtl8192_phy_updateInitGain(struct net_device* dev)
2547 {
2548 return;
2549 }
2550
2551 /******************************************************************************
2552 *function: This function read RF parameters from general head file, and do RF 3-wire
2553 * input: net_device dev
2554 * output: none
2555 * return: return code show if RF configuration is successful(0:pass, 1:fail)
2556 * Note: Delay may be required for RF configuration
2557 * ***************************************************************************/
2558 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
2559 {
2560
2561 int i;
2562 //u32* pRFArray;
2563 u8 ret = 0;
2564
2565 switch(eRFPath){
2566 case RF90_PATH_A:
2567 for(i = 0;i<RadioA_ArrayLength; i=i+2){
2568
2569 if(Rtl819XRadioA_Array[i] == 0xfe){
2570 msleep(100);
2571 continue;
2572 }
2573 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array[i], bMask12Bits, Rtl819XRadioA_Array[i+1]);
2574 //msleep(1);
2575
2576 }
2577 break;
2578 case RF90_PATH_B:
2579 for(i = 0;i<RadioB_ArrayLength; i=i+2){
2580
2581 if(Rtl819XRadioB_Array[i] == 0xfe){
2582 msleep(100);
2583 continue;
2584 }
2585 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array[i], bMask12Bits, Rtl819XRadioB_Array[i+1]);
2586 //msleep(1);
2587
2588 }
2589 break;
2590 case RF90_PATH_C:
2591 for(i = 0;i<RadioC_ArrayLength; i=i+2){
2592
2593 if(Rtl819XRadioC_Array[i] == 0xfe){
2594 msleep(100);
2595 continue;
2596 }
2597 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioC_Array[i], bMask12Bits, Rtl819XRadioC_Array[i+1]);
2598 //msleep(1);
2599
2600 }
2601 break;
2602 case RF90_PATH_D:
2603 for(i = 0;i<RadioD_ArrayLength; i=i+2){
2604
2605 if(Rtl819XRadioD_Array[i] == 0xfe){
2606 msleep(100);
2607 continue;
2608 }
2609 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioD_Array[i], bMask12Bits, Rtl819XRadioD_Array[i+1]);
2610 //msleep(1);
2611
2612 }
2613 break;
2614 default:
2615 break;
2616 }
2617
2618 return ret;;
2619
2620 }
2621 /******************************************************************************
2622 *function: This function set Tx Power of the channel
2623 * input: struct net_device *dev
2624 * u8 channel
2625 * output: none
2626 * return: none
2627 * Note:
2628 * ***************************************************************************/
2629 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
2630 {
2631 struct r8192_priv *priv = ieee80211_priv(dev);
2632 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
2633 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
2634
2635 switch(priv->rf_chip)
2636 {
2637 case RF_8225:
2638 #ifdef TO_DO_LIST
2639 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
2640 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
2641 #endif
2642 break;
2643
2644 case RF_8256:
2645 PHY_SetRF8256CCKTxPower(dev, powerlevel);
2646 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
2647 break;
2648
2649 case RF_8258:
2650 break;
2651 default:
2652 RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n");
2653 break;
2654 }
2655 return;
2656 }
2657 /****************************************************************************************
2658 *function: This function set command table variable(struct SwChnlCmd).
2659 * input: SwChnlCmd* CmdTable //table to be set.
2660 * u32 CmdTableIdx //variable index in table to be set
2661 * u32 CmdTableSz //table size.
2662 * SwChnlCmdID CmdID //command ID to set.
2663 * u32 Para1
2664 * u32 Para2
2665 * u32 msDelay
2666 * output:
2667 * return: true if finished, false otherwise
2668 * Note:
2669 * ************************************************************************************/
2670 static u8 rtl8192_phy_SetSwChnlCmdArray(
2671 SwChnlCmd* CmdTable,
2672 u32 CmdTableIdx,
2673 u32 CmdTableSz,
2674 SwChnlCmdID CmdID,
2675 u32 Para1,
2676 u32 Para2,
2677 u32 msDelay
2678 )
2679 {
2680 SwChnlCmd* pCmd;
2681
2682 if(CmdTable == NULL)
2683 {
2684 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n");
2685 return false;
2686 }
2687 if(CmdTableIdx >= CmdTableSz)
2688 {
2689 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
2690 CmdTableIdx, CmdTableSz);
2691 return false;
2692 }
2693
2694 pCmd = CmdTable + CmdTableIdx;
2695 pCmd->CmdID = CmdID;
2696 pCmd->Para1 = Para1;
2697 pCmd->Para2 = Para2;
2698 pCmd->msDelay = msDelay;
2699
2700 return true;
2701 }
2702 /******************************************************************************
2703 *function: This function set channel step by step
2704 * input: struct net_device *dev
2705 * u8 channel
2706 * u8* stage //3 stages
2707 * u8* step //
2708 * u32* delay //whether need to delay
2709 * output: store new stage, step and delay for next step(combine with function above)
2710 * return: true if finished, false otherwise
2711 * Note: Wait for simpler function to replace it //wb
2712 * ***************************************************************************/
2713 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay)
2714 {
2715 struct r8192_priv *priv = ieee80211_priv(dev);
2716 // PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
2717 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
2718 u32 PreCommonCmdCnt;
2719 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
2720 u32 PostCommonCmdCnt;
2721 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
2722 u32 RfDependCmdCnt;
2723 SwChnlCmd *CurrentCmd = NULL;
2724 //RF90_RADIO_PATH_E eRFPath;
2725 u8 eRFPath;
2726 // u32 RfRetVal;
2727 // u8 RetryCnt;
2728
2729 RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel);
2730 // RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
2731
2732 #ifdef ENABLE_DOT11D
2733 if (!IsLegalChannel(priv->ieee80211, channel))
2734 {
2735 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
2736 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
2737 }
2738 #endif
2739
2740 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
2741 //for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++)
2742 {
2743 //if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
2744 // return false;
2745 // <1> Fill up pre common command.
2746 PreCommonCmdCnt = 0;
2747 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2748 CmdID_SetTxPowerLevel, 0, 0, 0);
2749 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2750 CmdID_End, 0, 0, 0);
2751
2752 // <2> Fill up post common command.
2753 PostCommonCmdCnt = 0;
2754
2755 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
2756 CmdID_End, 0, 0, 0);
2757
2758 // <3> Fill up RF dependent command.
2759 RfDependCmdCnt = 0;
2760 switch( priv->rf_chip )
2761 {
2762 case RF_8225:
2763 if (!(channel >= 1 && channel <= 14))
2764 {
2765 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel);
2766 return false;
2767 }
2768 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2769 CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10);
2770 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2771 CmdID_End, 0, 0, 0);
2772 break;
2773
2774 case RF_8256:
2775 // TEST!! This is not the table for 8256!!
2776 if (!(channel >= 1 && channel <= 14))
2777 {
2778 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel);
2779 return false;
2780 }
2781 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2782 CmdID_RF_WriteReg, rZebra1_Channel, channel, 10);
2783 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2784 CmdID_End, 0, 0, 0);
2785 break;
2786
2787 case RF_8258:
2788 break;
2789
2790 default:
2791 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
2792 return false;
2793 break;
2794 }
2795
2796
2797 do{
2798 switch(*stage)
2799 {
2800 case 0:
2801 CurrentCmd=&PreCommonCmd[*step];
2802 break;
2803 case 1:
2804 CurrentCmd=&RfDependCmd[*step];
2805 break;
2806 case 2:
2807 CurrentCmd=&PostCommonCmd[*step];
2808 break;
2809 }
2810
2811 if(CurrentCmd->CmdID==CmdID_End)
2812 {
2813 if((*stage)==2)
2814 {
2815 return true;
2816 }
2817 else
2818 {
2819 (*stage)++;
2820 (*step)=0;
2821 continue;
2822 }
2823 }
2824
2825 switch(CurrentCmd->CmdID)
2826 {
2827 case CmdID_SetTxPowerLevel:
2828 if(priv->card_8192_version > (u8)VERSION_8190_BD) //xiong: consider it later!
2829 rtl8192_SetTxPowerLevel(dev,channel);
2830 break;
2831 case CmdID_WritePortUlong:
2832 write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
2833 break;
2834 case CmdID_WritePortUshort:
2835 write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
2836 break;
2837 case CmdID_WritePortUchar:
2838 write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
2839 break;
2840 case CmdID_RF_WriteReg:
2841 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
2842 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7);
2843 break;
2844 default:
2845 break;
2846 }
2847
2848 break;
2849 }while(true);
2850 }/*for(Number of RF paths)*/
2851
2852 (*delay)=CurrentCmd->msDelay;
2853 (*step)++;
2854 return false;
2855 }
2856
2857 /******************************************************************************
2858 *function: This function does acturally set channel work
2859 * input: struct net_device *dev
2860 * u8 channel
2861 * output: none
2862 * return: noin
2863 * Note: We should not call this function directly
2864 * ***************************************************************************/
2865 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
2866 {
2867 struct r8192_priv *priv = ieee80211_priv(dev);
2868 u32 delay = 0;
2869
2870 while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
2871 {
2872 if(delay>0)
2873 msleep(delay);//or mdelay? need further consideration
2874 if(!priv->up)
2875 break;
2876 }
2877 }
2878 /******************************************************************************
2879 *function: Callback routine of the work item for switch channel.
2880 * input:
2881 *
2882 * output: none
2883 * return: noin
2884 * ***************************************************************************/
2885 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
2886 {
2887
2888 struct r8192_priv *priv = ieee80211_priv(dev);
2889
2890 RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
2891
2892 RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __FUNCTION__, priv->chan, priv);
2893
2894 rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
2895
2896 RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
2897 }
2898
2899 /******************************************************************************
2900 *function: This function scheduled actural workitem to set channel
2901 * input: net_device dev
2902 * u8 channel //channel to set
2903 * output: none
2904 * return: return code show if workitem is scheduled(1:pass, 0:fail)
2905 * Note: Delay may be required for RF configuration
2906 * ***************************************************************************/
2907 u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
2908 {
2909 struct r8192_priv *priv = ieee80211_priv(dev);
2910 RT_TRACE(COMP_PHY, "=====>%s()\n", __FUNCTION__);
2911 if(!priv->up)
2912 return false;
2913 if(priv->SwChnlInProgress)
2914 return false;
2915
2916 // if(pHalData->SetBWModeInProgress)
2917 // return;
2918
2919 //--------------------------------------------
2920 switch(priv->ieee80211->mode)
2921 {
2922 case WIRELESS_MODE_A:
2923 case WIRELESS_MODE_N_5G:
2924 if (channel<=14){
2925 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
2926 return false;
2927 }
2928 break;
2929 case WIRELESS_MODE_B:
2930 if (channel>14){
2931 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
2932 return false;
2933 }
2934 break;
2935 case WIRELESS_MODE_G:
2936 case WIRELESS_MODE_N_24G:
2937 if (channel>14){
2938 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
2939 return false;
2940 }
2941 break;
2942 }
2943 //--------------------------------------------
2944
2945 priv->SwChnlInProgress = true;
2946 if(channel == 0)
2947 channel = 1;
2948
2949 priv->chan=channel;
2950
2951 priv->SwChnlStage=0;
2952 priv->SwChnlStep=0;
2953 // schedule_work(&(priv->SwChnlWorkItem));
2954 // rtl8192_SwChnl_WorkItem(dev);
2955 if(priv->up) {
2956 // queue_work(priv->priv_wq,&(priv->SwChnlWorkItem));
2957 rtl8192_SwChnl_WorkItem(dev);
2958 }
2959 priv->SwChnlInProgress = false;
2960 return true;
2961 }
2962
2963 static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev )
2964 {
2965 struct r8192_priv *priv = ieee80211_priv(dev);
2966
2967 switch(priv->CurrentChannelBW)
2968 {
2969 /* 20 MHz channel*/
2970 case HT_CHANNEL_WIDTH_20:
2971 //added by vivi, cck,tx power track, 20080703
2972 priv->CCKPresentAttentuation =
2973 priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference;
2974
2975 if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
2976 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
2977 if(priv->CCKPresentAttentuation < 0)
2978 priv->CCKPresentAttentuation = 0;
2979
2980 RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
2981
2982 if(priv->ieee80211->current_network.channel== 14 && !priv->bcck_in_ch14)
2983 {
2984 priv->bcck_in_ch14 = TRUE;
2985 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2986 }
2987 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
2988 {
2989 priv->bcck_in_ch14 = FALSE;
2990 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2991 }
2992 else
2993 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2994 break;
2995
2996 /* 40 MHz channel*/
2997 case HT_CHANNEL_WIDTH_20_40:
2998 //added by vivi, cck,tx power track, 20080703
2999 priv->CCKPresentAttentuation =
3000 priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference;
3001
3002 RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
3003 if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
3004 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
3005 if(priv->CCKPresentAttentuation < 0)
3006 priv->CCKPresentAttentuation = 0;
3007
3008 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
3009 {
3010 priv->bcck_in_ch14 = TRUE;
3011 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
3012 }
3013 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
3014 {
3015 priv->bcck_in_ch14 = FALSE;
3016 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
3017 }
3018 else
3019 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
3020 break;
3021 }
3022 }
3023
3024 #ifndef RTL8190P
3025 static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
3026 {
3027 struct r8192_priv *priv = ieee80211_priv(dev);
3028
3029 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
3030 priv->bcck_in_ch14 = TRUE;
3031 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
3032 priv->bcck_in_ch14 = FALSE;
3033
3034 //write to default index and tx power track will be done in dm.
3035 switch(priv->CurrentChannelBW)
3036 {
3037 /* 20 MHz channel*/
3038 case HT_CHANNEL_WIDTH_20:
3039 if(priv->Record_CCK_20Mindex == 0)
3040 priv->Record_CCK_20Mindex = 6; //set default value.
3041 priv->CCK_index = priv->Record_CCK_20Mindex;//6;
3042 RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n", priv->CCK_index);
3043 break;
3044
3045 /* 40 MHz channel*/
3046 case HT_CHANNEL_WIDTH_20_40:
3047 priv->CCK_index = priv->Record_CCK_40Mindex;//0;
3048 RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n", priv->CCK_index);
3049 break;
3050 }
3051 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
3052 }
3053 #endif
3054
3055 static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
3056 {
3057 #ifdef RTL8192E
3058 struct r8192_priv *priv = ieee80211_priv(dev);
3059 #endif
3060
3061 #ifdef RTL8190P
3062 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
3063 #else
3064 //if(pHalData->bDcut == TRUE)
3065 if(priv->IC_Cut >= IC_VersionCut_D)
3066 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
3067 else
3068 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev);
3069 #endif
3070 }
3071
3072
3073 //
3074 /******************************************************************************
3075 *function: Callback routine of the work item for set bandwidth mode.
3076 * input: struct net_device *dev
3077 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
3078 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
3079 * output: none
3080 * return: none
3081 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
3082 * test whether current work in the queue or not.//do I?
3083 * ***************************************************************************/
3084 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
3085 {
3086
3087 struct r8192_priv *priv = ieee80211_priv(dev);
3088 u8 regBwOpMode;
3089
3090 RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n", \
3091 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")
3092
3093
3094 if(priv->rf_chip== RF_PSEUDO_11N)
3095 {
3096 priv->SetBWModeInProgress= false;
3097 return;
3098 }
3099 if(!priv->up)
3100 {
3101 priv->SetBWModeInProgress= false;
3102 return;
3103 }
3104 //<1>Set MAC register
3105 regBwOpMode = read_nic_byte(dev, BW_OPMODE);
3106
3107 switch(priv->CurrentChannelBW)
3108 {
3109 case HT_CHANNEL_WIDTH_20:
3110 regBwOpMode |= BW_OPMODE_20MHZ;
3111 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3112 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3113 break;
3114
3115 case HT_CHANNEL_WIDTH_20_40:
3116 regBwOpMode &= ~BW_OPMODE_20MHZ;
3117 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3118 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3119 break;
3120
3121 default:
3122 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
3123 break;
3124 }
3125
3126 //<2>Set PHY related register
3127 switch(priv->CurrentChannelBW)
3128 {
3129 case HT_CHANNEL_WIDTH_20:
3130 // Add by Vivi 20071119
3131 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
3132 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
3133 // rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
3134
3135 // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
3136 // write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
3137 // write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
3138 // write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
3139 if(!priv->btxpower_tracking)
3140 {
3141 write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
3142 write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
3143 write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
3144 }
3145 else
3146 CCK_Tx_Power_Track_BW_Switch(dev);
3147
3148 #ifdef RTL8190P
3149 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1);
3150 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x44); // 0xc30 is for 8190 only, Emily
3151 #else
3152 #ifdef RTL8192E
3153 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
3154 #endif
3155 #endif
3156
3157 break;
3158 case HT_CHANNEL_WIDTH_20_40:
3159 // Add by Vivi 20071119
3160 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
3161 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
3162 //rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3163 //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
3164 //rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3165
3166 // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
3167 //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
3168 //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
3169 //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
3170 if(!priv->btxpower_tracking)
3171 {
3172 write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
3173 write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
3174 write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
3175 }
3176 else
3177 CCK_Tx_Power_Track_BW_Switch(dev);
3178
3179 // Set Control channel to upper or lower. These settings are required only for 40MHz
3180 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3181 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3182
3183
3184 #ifdef RTL8190P
3185 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0);
3186 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x42); // 0xc30 is for 8190 only, Emily
3187
3188 // Set whether CCK should be sent in upper or lower channel. Suggest by YN. 20071207
3189 // It is set in Tx descriptor for 8192x series
3190 if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
3191 {
3192 rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x01);
3193 }else if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
3194 {
3195 rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x02);
3196 }
3197
3198 #else
3199 #ifdef RTL8192E
3200 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
3201 #endif
3202 #endif
3203 break;
3204 default:
3205 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
3206 break;
3207
3208 }
3209 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
3210
3211 //<3>Set RF related register
3212 switch( priv->rf_chip )
3213 {
3214 case RF_8225:
3215 #ifdef TO_DO_LIST
3216 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
3217 #endif
3218 break;
3219
3220 case RF_8256:
3221 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
3222 break;
3223
3224 case RF_8258:
3225 // PHY_SetRF8258Bandwidth();
3226 break;
3227
3228 case RF_PSEUDO_11N:
3229 // Do Nothing
3230 break;
3231
3232 default:
3233 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
3234 break;
3235 }
3236 atomic_dec(&(priv->ieee80211->atm_swbw));
3237 priv->SetBWModeInProgress= false;
3238
3239 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
3240 }
3241
3242 /******************************************************************************
3243 *function: This function schedules bandwith switch work.
3244 * input: struct net_device *dev
3245 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
3246 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
3247 * output: none
3248 * return: none
3249 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
3250 * test whether current work in the queue or not.//do I?
3251 * ***************************************************************************/
3252 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
3253 {
3254 struct r8192_priv *priv = ieee80211_priv(dev);
3255
3256
3257 if(priv->SetBWModeInProgress)
3258 return;
3259
3260 atomic_inc(&(priv->ieee80211->atm_swbw));
3261 priv->SetBWModeInProgress= true;
3262
3263 priv->CurrentChannelBW = Bandwidth;
3264
3265 if(Offset==HT_EXTCHNL_OFFSET_LOWER)
3266 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
3267 else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
3268 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
3269 else
3270 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
3271
3272 //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem));
3273 // schedule_work(&(priv->SetBWModeWorkItem));
3274 rtl8192_SetBWModeWorkItem(dev);
3275
3276 }
3277
3278
3279 void InitialGain819xPci(struct net_device *dev, u8 Operation)
3280 {
3281 #define SCAN_RX_INITIAL_GAIN 0x17
3282 #define POWER_DETECTION_TH 0x08
3283 struct r8192_priv *priv = ieee80211_priv(dev);
3284 u32 BitMask;
3285 u8 initial_gain;
3286
3287 if(priv->up)
3288 {
3289 switch(Operation)
3290 {
3291 case IG_Backup:
3292 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
3293 initial_gain = SCAN_RX_INITIAL_GAIN;//pHalData->DefaultInitialGain[0];//
3294 BitMask = bMaskByte0;
3295 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3296 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3297 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
3298 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
3299 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
3300 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
3301 BitMask = bMaskByte2;
3302 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
3303
3304 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
3305 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
3306 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
3307 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
3308 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
3309
3310 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
3311 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
3312 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
3313 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
3314 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
3315 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
3316 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
3317 break;
3318 case IG_Restore:
3319 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
3320 BitMask = 0x7f; //Bit0~ Bit6
3321 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3322 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3323
3324 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
3325 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
3326 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
3327 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
3328 BitMask = bMaskByte2;
3329 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
3330
3331 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
3332 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
3333 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
3334 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
3335 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
3336
3337 rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
3338
3339
3340 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3341 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
3342 break;
3343 default:
3344 RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
3345 break;
3346 }
3347 }
3348 }
Tomato firmware and modifications.