release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/rt2860/rtmp_chip.h

   1 /*
   2  *************************************************************************
   3  * Ralink Tech Inc.
   4  * 5F., No.36, Taiyuan St., Jhubei City,
   5  * Hsinchu County 302,
   6  * Taiwan, R.O.C.
   7  *
   8  * (c) Copyright 2002-2007, Ralink Technology, Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify  *
  11  * it under the terms of the GNU General Public License as published by  *
  12  * the Free Software Foundation; either version 2 of the License, or     *
  13  * (at your option) any later version.                                   *
  14  *                                                                       *
  15  * This program is distributed in the hope that it will be useful,       *
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  * GNU General Public License for more details.                          *
  19  *                                                                       *
  20  * You should have received a copy of the GNU General Public License     *
  21  * along with this program; if not, write to the                         *
  22  * Free Software Foundation, Inc.,                                       *
  23  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  24  *                                                                       *
  25  *************************************************************************
  26
  27         Module Name:
  28         rtmp_chip.h
  29
  30         Abstract:
  31         Ralink Wireless Chip related definition & structures
  32
  33         Revision History:
  34         Who                     When              What
  35         --------        ----------        ----------------------------------------------
  36 */
  37
  38 #ifndef __RTMP_CHIP_H__
  39 #define __RTMP_CHIP_H__
  40
  41 #include "rtmp_type.h"
  42
  43 #ifdef RT2860
  44 #include "chip/rt2860.h"
  45 #endif /* RT2860 // */
  46 #ifdef RT2870
  47 #include "chip/rt2870.h"
  48 #endif /* RT2870 // */
  49 #ifdef RT3070
  50 #include "chip/rt3070.h"
  51 #endif /* RT3070 // */
  52 #ifdef RT3090
  53 #include "chip/rt3090.h"
  54 #endif /* RT3090 // */
  55
  56 /* We will have a cost down version which mac version is 0x3090xxxx */
  57 /* */
  58 /* RT3090A facts */
  59 /* */
  60 /* a) 2.4 GHz */
  61 /* b) Replacement for RT3090 */
  62 /* c) Internal LNA */
  63 /* d) Interference over channel #14 */
  64 /* e) New BBP features (e.g., SIG re-modulation) */
  65 /* */
  66 #define IS_RT3090A(_pAd)                                ((((_pAd)->MACVersion & 0xffff0000) == 0x30900000))
  67
  68 /* We will have a cost down version which mac version is 0x3090xxxx */
  69 #define IS_RT3090(_pAd)                         ((((_pAd)->MACVersion & 0xffff0000) == 0x30710000) || (IS_RT3090A(_pAd)))
  70
  71 #define IS_RT3070(_pAd)         (((_pAd)->MACVersion & 0xffff0000) == 0x30700000)
  72 #define IS_RT3071(_pAd)         (((_pAd)->MACVersion & 0xffff0000) == 0x30710000)
  73 #define IS_RT2070(_pAd)         (((_pAd)->RfIcType == RFIC_2020) || ((_pAd)->EFuseTag == 0x27))
  74
  75 #define IS_RT30xx(_pAd)         (((_pAd)->MACVersion & 0xfff00000) == 0x30700000||IS_RT3090A(_pAd))
  76 /*#define IS_RT305X(_pAd)               ((_pAd)->MACVersion == 0x28720200) */
  77
  78 /* RT3572, 3592, 3562, 3062 share the same MAC version */
  79 #define IS_RT3572(_pAd)         (((_pAd)->MACVersion & 0xffff0000) == 0x35720000)
  80 #define IS_VERSION_BEFORE_F(_pAd)                       (((_pAd)->MACVersion&0xffff) <= 0x0211)
  81 /* F version is 0x0212, E version is 0x0211. 309x can save more power after F version. */
  82 #define IS_VERSION_AFTER_F(_pAd)                        ((((_pAd)->MACVersion&0xffff) >= 0x0212) || (((_pAd)->b3090ESpecialChip == TRUE)))
  83 /* */
  84 /* RT3390 facts */
  85 /* */
  86 /* a) Base on RT3090 (RF IC: RT3020) */
  87 /* b) 2.4 GHz */
  88 /* c) 1x1 */
  89 /* d) Single chip */
  90 /* e) Internal components: PA and LNA */
  91 /* */
  92 /*RT3390,RT3370 */
  93 #define IS_RT3390(_pAd)                         (((_pAd)->MACVersion & 0xFFFF0000) == 0x33900000)
  94
  95 /* ------------------------------------------------------ */
  96 /* PCI registers - base address 0x0000 */
  97 /* ------------------------------------------------------ */
  98 #define CHIP_PCI_CFG            0x0000
  99 #define CHIP_PCI_EECTRL         0x0004
 100 #define CHIP_PCI_MCUCTRL        0x0008
 101
 102 #define OPT_14                  0x114
 103
 104 #define RETRY_LIMIT             10
 105
 106 /* ------------------------------------------------------ */
 107 /* BBP & RF     definition */
 108 /* ------------------------------------------------------ */
 109 #define BUSY                            1
 110 #define IDLE                            0
 111
 112 /*------------------------------------------------------------------------- */
 113 /* EEPROM definition */
 114 /*------------------------------------------------------------------------- */
 115 #define EEDO                        0x08
 116 #define EEDI                        0x04
 117 #define EECS                        0x02
 118 #define EESK                        0x01
 119 #define EERL                        0x80
 120
 121 #define EEPROM_WRITE_OPCODE         0x05
 122 #define EEPROM_READ_OPCODE          0x06
 123 #define EEPROM_EWDS_OPCODE          0x10
 124 #define EEPROM_EWEN_OPCODE          0x13
 125
 126 #define NUM_EEPROM_BBP_PARMS            19      /* Include NIC Config 0, 1, CR, TX ALC step, BBPs */
 127 #define NUM_EEPROM_TX_G_PARMS           7
 128 #define EEPROM_NIC1_OFFSET          0x34        /* The address is from NIC config 0, not BBP register ID */
 129 #define EEPROM_NIC2_OFFSET          0x36        /* The address is from NIC config 0, not BBP register ID */
 130 #define EEPROM_BBP_BASE_OFFSET          0xf0    /* The address is from NIC config 0, not BBP register ID */
 131 #define EEPROM_G_TX_PWR_OFFSET          0x52
 132 #define EEPROM_G_TX2_PWR_OFFSET         0x60
 133 #define EEPROM_LED1_OFFSET                      0x3c
 134 #define EEPROM_LED2_OFFSET                      0x3e
 135 #define EEPROM_LED3_OFFSET                      0x40
 136 #define EEPROM_LNA_OFFSET                       0x44
 137 #define EEPROM_RSSI_BG_OFFSET           0x46
 138 #define EEPROM_TXMIXER_GAIN_2_4G        0x48
 139 #define EEPROM_RSSI_A_OFFSET            0x4a
 140 #define EEPROM_TXMIXER_GAIN_5G          0x4c
 141 #define EEPROM_DEFINE_MAX_TXPWR         0x4e
 142 #define EEPROM_TXPOWER_BYRATE_20MHZ_2_4G        0xde    /* 20MHZ 2.4G tx power. */
 143 #define EEPROM_TXPOWER_BYRATE_40MHZ_2_4G        0xee    /* 40MHZ 2.4G tx power. */
 144 #define EEPROM_TXPOWER_BYRATE_20MHZ_5G          0xfa    /* 20MHZ 5G tx power. */
 145 #define EEPROM_TXPOWER_BYRATE_40MHZ_5G          0x10a   /* 40MHZ 5G tx power. */
 146 #define EEPROM_A_TX_PWR_OFFSET      0x78
 147 #define EEPROM_A_TX2_PWR_OFFSET      0xa6
 148 /*#define EEPROM_Japan_TX_PWR_OFFSET      0x90 // 802.11j */
 149 /*#define EEPROM_Japan_TX2_PWR_OFFSET      0xbe */
 150 /*#define EEPROM_TSSI_REF_OFFSET        0x54 */
 151 /*#define EEPROM_TSSI_DELTA_OFFSET      0x24 */
 152 /*#define EEPROM_CCK_TX_PWR_OFFSET  0x62 */
 153 /*#define EEPROM_CALIBRATE_OFFSET       0x7c */
 154 #define EEPROM_VERSION_OFFSET       0x02
 155 #define EEPROM_FREQ_OFFSET                      0x3a
 156 #define EEPROM_TXPOWER_BYRATE   0xde    /* 20MHZ power. */
 157 #define EEPROM_TXPOWER_DELTA            0x50    /* 20MHZ AND 40 MHZ use different power. This is delta in 40MHZ. */
 158 #define VALID_EEPROM_VERSION        1
 159
 160 /*
 161   *   EEPROM operation related marcos
 162   */
 163 #define RT28xx_EEPROM_READ16(_pAd, _offset, _value)                     \
 164         (_pAd)->chipOps.eeread((struct rt_rtmp_adapter *)(_pAd), (u16)(_offset), (u16 *)&(_value))
 165
 166 /* ------------------------------------------------------------------- */
 167 /*  E2PROM data layout */
 168 /* ------------------------------------------------------------------- */
 169
 170 /* */
 171 /* MCU_LEDCS: MCU LED Control Setting. */
 172 /* */
 173 typedef union _MCU_LEDCS_STRUC {
 174         struct {
 175                 u8 LedMode:7;
 176                 u8 Polarity:1;
 177         } field;
 178         u8 word;
 179 } MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;
 180
 181 /* */
 182 /* EEPROM antenna select format */
 183 /* */
 184 typedef union _EEPROM_ANTENNA_STRUC {
 185         struct {
 186                 u16 RxPath:4;   /* 1: 1R, 2: 2R, 3: 3R */
 187                 u16 TxPath:4;   /* 1: 1T, 2: 2T */
 188                 u16 RfIcType:4; /* see E2PROM document */
 189                 u16 Rsv:4;
 190         } field;
 191         u16 word;
 192 } EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;
 193
 194 typedef union _EEPROM_NIC_CINFIG2_STRUC {
 195         struct {
 196                 u16 HardwareRadioControl:1;     /* 1:enable, 0:disable */
 197                 u16 DynamicTxAgcControl:1;      /* */
 198                 u16 ExternalLNAForG:1;  /* */
 199                 u16 ExternalLNAForA:1;  /* external LNA enable for 2.4G */
 200                 u16 CardbusAcceleration:1;      /* ! NOTE: 0 - enable, 1 - disable */
 201                 u16 BW40MSidebandForG:1;
 202                 u16 BW40MSidebandForA:1;
 203                 u16 EnableWPSPBC:1;     /* WPS PBC Control bit */
 204                 u16 BW40MAvailForG:1;   /* 0:enable, 1:disable */
 205                 u16 BW40MAvailForA:1;   /* 0:enable, 1:disable */
 206                 u16 Rsv1:1;     /* must be 0 */
 207                 u16 AntDiversity:1;     /* Antenna diversity */
 208                 u16 Rsv2:3;     /* must be 0 */
 209                 u16 DACTestBit:1;       /* control if driver should patch the DAC issue */
 210         } field;
 211         u16 word;
 212 } EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;
 213
 214 /* */
 215 /* TX_PWR Value valid range 0xFA(-6) ~ 0x24(36) */
 216 /* */
 217 typedef union _EEPROM_TX_PWR_STRUC {
 218         struct {
 219                 char Byte0;     /* Low Byte */
 220                 char Byte1;     /* High Byte */
 221         } field;
 222         u16 word;
 223 } EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;
 224
 225 typedef union _EEPROM_VERSION_STRUC {
 226         struct {
 227                 u8 FaeReleaseNumber;    /* Low Byte */
 228                 u8 Version;     /* High Byte */
 229         } field;
 230         u16 word;
 231 } EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;
 232
 233 typedef union _EEPROM_LED_STRUC {
 234         struct {
 235                 u16 PolarityRDY_G:1;    /* Polarity RDY_G setting. */
 236                 u16 PolarityRDY_A:1;    /* Polarity RDY_A setting. */
 237                 u16 PolarityACT:1;      /* Polarity ACT setting. */
 238                 u16 PolarityGPIO_0:1;   /* Polarity GPIO#0 setting. */
 239                 u16 PolarityGPIO_1:1;   /* Polarity GPIO#1 setting. */
 240                 u16 PolarityGPIO_2:1;   /* Polarity GPIO#2 setting. */
 241                 u16 PolarityGPIO_3:1;   /* Polarity GPIO#3 setting. */
 242                 u16 PolarityGPIO_4:1;   /* Polarity GPIO#4 setting. */
 243                 u16 LedMode:5;  /* Led mode. */
 244                 u16 Rsvd:3;     /* Reserved */
 245         } field;
 246         u16 word;
 247 } EEPROM_LED_STRUC, *PEEPROM_LED_STRUC;
 248
 249 typedef union _EEPROM_TXPOWER_DELTA_STRUC {
 250         struct {
 251                 u8 DeltaValue:6;        /* Tx Power dalta value (MAX=4) */
 252                 u8 Type:1;      /* 1: plus the delta value, 0: minus the delta value */
 253                 u8 TxPowerEnable:1;     /* Enable */
 254         } field;
 255         u8 value;
 256 } EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC;
 257
 258 #endif /* __RTMP_CHIP_H__ // */