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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / staging / otus / 80211core / wlan.h
blob26c18b837cfced36c8bc95ac1f5e0bf02427cfa6
1 /*
2 * Copyright (c) 2007-2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16 /* */
17 /* Module Name : wlan_defs.h */
18 /* */
19 /* Abstract */
20 /* This module contains WLAN definitions. */
21 /* */
22 /* NOTES */
23 /* None */
24 /* */
25 /************************************************************************/
26
27 #ifndef _WLAN_H
28 #define _WLAN_H
29
30
31 #define ZM_EXTERNAL_ALLOC_BUF 0
32 #define ZM_INTERNAL_ALLOC_BUF 1
33
34 #define ZM_SIZE_OF_CTRL_SET 8
35 #define ZM_SIZE_OF_IV 4
36 #define ZM_SIZE_OF_EXT_IV 4
37 #define ZM_SIZE_OF_MIC 8
38 #define ZM_SIZE_OF_CCX_MIC 8
39 #define ZM_SIZE_OF_WLAN_DATA_HEADER 24
40 #define ZM_SIZE_OF_QOS_CTRL 2
41
42 /* Header definition */
43 #define ZM_SIZE_OF_WLAN_WDS_HEADER 32
44 #define ZM_SIZE_OF_SNAP_HEADER 8
45
46 #define ZM_WLAN_HEADER_A1_OFFSET 4
47 #define ZM_WLAN_HEADER_A2_OFFSET 10
48 #define ZM_WLAN_HEADER_A3_OFFSET 16
49 #define ZM_WLAN_HEADER_A4_OFFSET 24
50 #define ZM_WLAN_HEADER_IV_OFFSET 24
51 #define ZM_SIZE_OF_WLAN_DATA_HEADER 24
52
53 /* Port definition */
54 #define ZM_PORT_DISABLED 0
55 #define ZM_PORT_ENABLED 1
56
57 /* Frame Type */
58 #define ZM_WLAN_MANAGEMENT_FRAME 0x0
59 #define ZM_WLAN_CONTROL_FRAME 0x4
60 #define ZM_WLAN_DATA_FRAME 0x8
61
62 /* Frame Subtype */
63 #define ZM_WLAN_FRAME_TYPE_ASOCREQ 0x00
64 #define ZM_WLAN_FRAME_TYPE_ASOCRSP 0x10
65 #define ZM_WLAN_FRAME_TYPE_REASOCREQ 0x20
66 #define ZM_WLAN_FRAME_TYPE_REASOCRSP 0x30
67 #define ZM_WLAN_FRAME_TYPE_PROBEREQ 0x40
68 #define ZM_WLAN_FRAME_TYPE_PROBERSP 0x50
69 /* 0x60, 0x70 => Reserved */
70 #define ZM_WLAN_FRAME_TYPE_BEACON 0x80
71 #define ZM_WLAN_FRAME_TYPE_ATIM 0x90
72 #define ZM_WLAN_FRAME_TYPE_DISASOC 0xA0
73 #define ZM_WLAN_FRAME_TYPE_AUTH 0xB0
74 #define ZM_WLAN_FRAME_TYPE_DEAUTH 0xC0
75 #define ZM_WLAN_FRAME_TYPE_ACTION 0xD0
76
77 /* Frame type and subtype */
78 #define ZM_WLAN_FRAME_TYPE_NULL 0x48
79 #define ZM_WLAN_FRAME_TYPE_BAR 0x84
80 #define ZM_WLAN_FRAME_TYPE_BA 0x94
81 #define ZM_WLAN_FRAME_TYPE_PSPOLL 0xA4
82 #define ZM_WLAN_FRAME_TYPE_RTS 0xB4
83 #define ZM_WLAN_FRAME_TYPE_CTS 0xC4
84 #define ZM_WLAN_FRAME_TYPE_QOS_NULL 0xC8
85
86 /* action frame */
87 #define ZM_WLAN_SPECTRUM_MANAGEMENT_ACTION_FRAME 0
88 #define ZM_WLAN_QOS_ACTION_FRAME 1
89 #define ZM_WLAN_DLS_ACTION_FRAME 2
90 #define ZM_WLAN_BLOCK_ACK_ACTION_FRAME 3
91 /* block ack action frame*/
92 #define ZM_WLAN_ADDBA_REQUEST_FRAME 0
93 #define ZM_WLAN_ADDBA_RESPONSE_FRAME 1
94 #define ZM_WLAN_DELBA_FRAME 2
95
96 /* Element ID */
97 #define ZM_WLAN_EID_SSID 0
98 #define ZM_WLAN_EID_SUPPORT_RATE 1
99 #define ZM_WLAN_EID_FH 2
100 #define ZM_WLAN_EID_DS 3
101 #define ZM_WLAN_EID_CFS 4
102 #define ZM_WLAN_EID_TIM 5
103 #define ZM_WLAN_EID_IBSS 6
104 #define ZM_WLAN_EID_COUNTRY 7
105 /* reserved 8-15 */
106 #define ZM_WLAN_EID_CHALLENGE 16
107 /* reserved 17-31 */
108 #define ZM_WLAN_EID_POWER_CONSTRAINT 32
109 #define ZM_WLAN_EID_POWER_CAPABILITY 33
110 #define ZM_WLAN_EID_TPC_REQUEST 34
111 #define ZM_WLAN_EID_TPC_REPORT 35
112 #define ZM_WLAN_EID_SUPPORTED_CHANNELS 36
113 #define ZM_WLAN_EID_CHANNEL_SWITCH_ANNOUNCE 37
114 #define ZM_WLAN_EID_MEASUREMENT_REQUEST 38
115 #define ZM_WLAN_EID_MEASUREMENT_REPORT 39
116 #define ZM_WLAN_EID_QUIET 40
117 #define ZM_WLAN_EID_IBSS_DFS 41
118 #define ZM_WLAN_EID_ERP 42
119 #define ZM_WLAN_PREN2_EID_HTCAPABILITY 45
120 #define ZM_WLAN_EID_RSN_IE 48
121 #define ZM_WLAN_EID_EXTENDED_RATE 50
122 #define ZM_WLAN_EID_HT_CAPABILITY 51
123 #define ZM_WLAN_EID_EXTENDED_HT_CAPABILITY 52
124 #define ZM_WLAN_EID_NEW_EXT_CHANNEL_OFFSET 53
125 #define ZM_WLAN_PREN2_EID_HTINFORMATION 61
126 #define ZM_WLAN_PREN2_EID_SECONDCHOFFSET 62
127 #ifdef ZM_ENABLE_CENC
128 #define ZM_WLAN_EID_CENC_IE 68
129 #endif //ZM_ENABLE_CENC
130 #define ZM_WLAN_EID_VENDOR_PRIVATE 221 /* Vendor private space; must demux OUI */
131 #define ZM_WLAN_EID_WPA_IE 221
132 #define ZM_WLAN_EID_WPS_IE 221
133 #define ZM_WLAN_EID_WIFI_IE 221
134
135 /* ERP information element */
136 #define ZM_WLAN_NON_ERP_PRESENT_BIT 0x1
137 #define ZM_WLAN_USE_PROTECTION_BIT 0x2
138 #define ZM_WLAN_BARKER_PREAMBLE_MODE_BIT 0x4
139
140 /* Channel frequency, in MHz */
141 #define ZM_CH_G_1 2412
142 #define ZM_CH_G_2 2417
143 #define ZM_CH_G_3 2422
144 #define ZM_CH_G_4 2427
145 #define ZM_CH_G_5 2432
146 #define ZM_CH_G_6 2437
147 #define ZM_CH_G_7 2442
148 #define ZM_CH_G_8 2447
149 #define ZM_CH_G_9 2452
150 #define ZM_CH_G_10 2457
151 #define ZM_CH_G_11 2462
152 #define ZM_CH_G_12 2467
153 #define ZM_CH_G_13 2472
154 #define ZM_CH_G_14 2484
155 #define ZM_CH_A_184 4920
156 #define ZM_CH_A_188 4940
157 #define ZM_CH_A_192 4960
158 #define ZM_CH_A_196 4980
159 #define ZM_CH_A_8 5040
160 #define ZM_CH_A_12 5060
161 #define ZM_CH_A_16 5080
162 #define ZM_CH_A_36 5180
163 #define ZM_CH_A_40 5200
164 #define ZM_CH_A_44 5220
165 #define ZM_CH_A_48 5240
166 #define ZM_CH_A_52 5260
167 #define ZM_CH_A_56 5280
168 #define ZM_CH_A_60 5300
169 #define ZM_CH_A_64 5320
170 #define ZM_CH_A_100 5500
171 #define ZM_CH_A_104 5520
172 #define ZM_CH_A_108 5540
173 #define ZM_CH_A_112 5560
174 #define ZM_CH_A_116 5580
175 #define ZM_CH_A_120 5600
176 #define ZM_CH_A_124 5620
177 #define ZM_CH_A_128 5640
178 #define ZM_CH_A_132 5660
179 #define ZM_CH_A_136 5680
180 #define ZM_CH_A_140 5700
181 #define ZM_CH_A_149 5745
182 #define ZM_CH_A_153 5765
183 #define ZM_CH_A_157 5785
184 #define ZM_CH_A_161 5805
185 #define ZM_CH_A_165 5825
186
187
188 /* AP : STA table => STA Type */
189 #define ZM_11B_STA 0x0
190 #define ZM_11G_STA 0x2
191 #define ZM_11N_STA 0x4
192
193 /* AP : timeout */
194 #define ZM_MS_PER_TICK 10
195 #define ZM_TICK_PER_SECOND (1000/ZM_MS_PER_TICK)
196 #define ZM_TICK_PER_MINUTE (60*1000/ZM_MS_PER_TICK)
197 #define ZM_PREAUTH_TIMEOUT_MS 1000 /* 1 sec */
198 #define ZM_AUTH_TIMEOUT_MS 1000 /* 1 sec */
199
200 /* Error code */
201 #define ZM_SUCCESS 0
202 #define ZM_ERR_TX_PORT_DISABLED 1
203 #define ZM_ERR_BUFFER_DMA_ADDR 2
204 #define ZM_ERR_FREE_TXD_EXHAUSTED 3
205 #define ZM_ERR_TX_BUFFER_UNAVAILABLE 4
206 #define ZM_ERR_BCMC_PS_BUFFER_UNAVAILABLE 5
207 #define ZM_ERR_UNI_PS_BUFFER_UNAVAILABLE 6
208 #define ZM_ERR_EXCEED_PRIORITY_THRESHOLD 7
209 #define ZM_ERR_VMMQ_FULL 8
210 #define ZM_ERR_FLUSH_PS_QUEUE 9
211 #define ZM_ERR_CMD_INT_MISSED 15 /* Polling cmd int timeout*/
212 /* Rx */
213 #define ZM_ERR_RX_FRAME_TYPE 20
214 #define ZM_ERR_MIN_RX_ENCRYPT_FRAME_LENGTH 21
215 #define ZM_ERR_MIN_RX_FRAME_LENGTH 22
216 #define ZM_ERR_MAX_RX_FRAME_LENGTH 23
217 #define ZM_ERR_RX_DUPLICATE 24
218 #define ZM_ERR_RX_SRC_ADDR_IS_OWN_MAC 25
219 #define ZM_ERR_MIN_RX_PROTOCOL_VERSION 26
220 #define ZM_ERR_WPA_GK_NOT_INSTALLED 27
221 #define ZM_ERR_STA_NOT_ASSOCIATED 28
222 #define ZM_ERR_DATA_BEFORE_CONNECTED 29
223 #define ZM_ERR_DATA_NOT_ENCRYPTED 30
224 #define ZM_ERR_DATA_BSSID_NOT_MATCHED 31
225 #define ZM_ERR_RX_BAR_FRAME 32
226 #define ZM_ERR_OUT_OF_ORDER_NULL_DATA 33
227
228 /* ZFI */
229 #define ZM_ERR_INVALID_TX_RATE 40
230 #define ZM_ERR_WDS_PORT_ID 41
231
232 /* QUEUE */
233 #define ZM_ERR_QUEUE_FULL 50
234 #define ZM_ERR_STA_UAPSD_QUEUE_FULL 51
235 #define ZM_ERR_AP_UAPSD_QUEUE_FULL 52
236
237 /* Maximum Rx frame length */
238 #if ZM_LARGEPAYLOAD_TEST == 1
239 #define ZM_WLAN_MAX_RX_SIZE 16384
240 #else
241 #define ZM_WLAN_MAX_RX_SIZE 8192
242 #endif
243
244 /* PCI DMA test error code */
245 #define ZM_ERR_INTERRUPT_MISSED 100
246 #define ZM_ERR_OWN_BIT_NOT_CLEARED 101
247 #define ZM_ERR_RX_SEQ_NUMBER 102
248 #define ZM_ERR_RX_LENGTH 103
249 #define ZM_ERR_RX_DATA 104
250 #define ZM_ERR_RX_DESCRIPTOR_NUM 105
251 /* Common register test error code */
252 #define ZM_ERR_REGISTER_ACCESS 110 /* Register R/W test fail*/
253 #define ZM_ERR_CLEAR_INTERRUPT_FLAG 111
254 #define ZM_ERR_COMMAND_RESPONSE 112
255 #define ZM_ERR_INTERRUPT_GENERATE 113
256 #define ZM_ERR_INTERRUPT_ACK 114
257 #define ZM_ERR_SCRATCH_ACCESS 115
258 #define ZM_ERR_INTERRUPT_MASK_ACCESS 116
259 #define ZM_ERR_SHARE_MEMORY_PCI_ACCESS 117
260 #define ZM_ERR_SHARE_MEMORY_FW_ACCESS 118
261 #define ZM_ERR_SHARE_MEMORY_DISABLE 119
262 #define ZM_ERR_SHARE_MEMORY_TEST_RESPONSE 120
263
264 /* Firmware Download error code */
265 #define ZM_ERR_FIRMWARE_DOWNLOAD_TIMEOUT 150
266 #define ZM_ERR_FIRMWARE_DOWNLOAD_INT_FLAG 151
267 #define ZM_ERR_FIRMWARE_READY_TIMEOUT 152
268 #define ZM_ERR_FIRMWARE_WRONG_TYPE 153
269
270 /* Debug */
271 #define ZM_LV_0 0//Debug level 0, Disable debug message
272 #define ZM_LV_1 1//Debug level 1, Show minimum information
273 #define ZM_LV_2 2//Debug level 2, Show medium message
274 #define ZM_LV_3 3//Debug level 3, Show all
275
276 #define ZM_SCANMSG_LEV ZM_LV_1
277 #define ZM_TXMSG_LEV ZM_LV_0//ZM_LV_0
278 #define ZM_RXMSG_LEV ZM_LV_0
279 #define ZM_MMMSG_LEV ZM_LV_0
280 #define ZM_DESMSG_LEV ZM_LV_0//ZM_LV_0
281 #define ZM_BUFMSG_LEV ZM_LV_0//ZM_LV_1
282 #define ZM_INITMSG_LEV ZM_LV_0
283
284 #define zm_msg0_scan(lv, msg) if (ZM_SCANMSG_LEV >= lv) \
285 {zm_debug_msg0(msg);}
286 #define zm_msg1_scan(lv, msg, val) if (ZM_SCANMSG_LEV >= lv) \
287 {zm_debug_msg1(msg, val);}
288 #define zm_msg2_scan(lv, msg, val) if (ZM_SCANMSG_LEV >= lv) \
289 {zm_debug_msg2(msg, val);}
290
291 #define zm_msg0_tx(lv, msg) if (ZM_TXMSG_LEV >= lv) \
292 {zm_debug_msg0(msg);}
293 #define zm_msg1_tx(lv, msg, val) if (ZM_TXMSG_LEV >= lv) \
294 {zm_debug_msg1(msg, val);}
295 #define zm_msg2_tx(lv, msg, val) if (ZM_TXMSG_LEV >= lv) \
296 {zm_debug_msg2(msg, val);}
297
298 #define zm_msg0_rx(lv, msg) if (ZM_RXMSG_LEV >= lv) \
299 {zm_debug_msg0(msg);}
300 #define zm_msg1_rx(lv, msg, val) if (ZM_RXMSG_LEV >= lv) \
301 {zm_debug_msg1(msg, val);}
302 #define zm_msg2_rx(lv, msg, val) if (ZM_RXMSG_LEV >= lv) \
303 {zm_debug_msg2(msg, val);}
304
305 #define zm_msg0_mm(lv, msg) if (ZM_MMMSG_LEV >= lv) \
306 {zm_debug_msg0(msg);}
307 #define zm_msg1_mm(lv, msg, val) if (ZM_MMMSG_LEV >= lv) \
308 {zm_debug_msg1(msg, val);}
309 #define zm_msg2_mm(lv, msg, val) if (ZM_MMMSG_LEV >= lv) \
310 {zm_debug_msg2(msg, val);}
311
312 #define zm_msg0_des(lv, msg) if (ZM_DESMSG_LEV >= lv) \
313 {zm_debug_msg0(msg);}
314 #define zm_msg1_des(lv, msg, val) if (ZM_DESMSG_LEV >= lv) \
315 {zm_debug_msg1(msg, val);}
316 #define zm_msg2_des(lv, msg, val) if (ZM_DESMSG_LEV >= lv) \
317 {zm_debug_msg2(msg, val);}
318
319 #define zm_msg0_buf(lv, msg) if (ZM_BUFMSG_LEV >= lv) \
320 {zm_debug_msg0(msg);}
321 #define zm_msg1_buf(lv, msg, val) if (ZM_BUFMSG_LEV >= lv) \
322 {zm_debug_msg1(msg, val);}
323 #define zm_msg2_buf(lv, msg, val) if (ZM_BUFMSG_LEV >= lv) \
324 {zm_debug_msg2(msg, val);}
325
326 #define zm_msg0_init(lv, msg) if (ZM_INITMSG_LEV >= lv) \
327 {zm_debug_msg0(msg);}
328 #define zm_msg1_init(lv, msg, val) if (ZM_INITMSG_LEV >= lv) \
329 {zm_debug_msg1(msg, val);}
330 #define zm_msg2_init(lv, msg, val) if (ZM_INITMSG_LEV >= lv) \
331 {zm_debug_msg2(msg, val);}
332
333 #define ZM_MAX_AP_SUPPORT 2 /* Must <= 8 */
334 #define ZM_MAX_WDS_SUPPORT 6 /* Must <= 6 */
335 #define ZM_MAX_STA_SUPPORT 16 /* Must <= 64 */
336
337 /* STA table state */
338 #define ZM_STATE_AUTH 1
339 #define ZM_STATE_PREAUTH 2
340 #define ZM_STATE_ASOC 3
341
342 /* Rate set */
343 #define ZM_RATE_SET_CCK 0
344 #define ZM_RATE_SET_OFDM 1
345
346 /* HT PT */
347 #define ZM_PREAMBLE_TYPE_MIXED_MODE 0
348 #define ZM_PREAMBLE_TYPE_GREEN_FIELD 1
349
350 /* HT bandwidth */
351 #define ZM_BANDWIDTH_20MHZ 0
352 #define ZM_BANDWIDTH_40MHZ 1
353
354 /* MIC status */
355 #define ZM_MIC_SUCCESS 0
356 #define ZM_MIC_FAILURE 1
357
358 /* ICV status */
359 #define ZM_ICV_SUCCESS 0
360 #define ZM_ICV_FAILURE 1
361
362 /* definition check */
363 #if (ZM_MAX_AP_SUPPORT > 8)
364 definition error, ZM_MAX_AP_SUPPORT > 8
365 #endif
366 #if (ZM_MAX_AP_SUPPORT > 64)
367 definition error, ZM_MAX_STA_SUPPORT > 64
368 #endif
369
370 /* Transmission Rate information */
371
372 /* WLAN frame format */
373 #define ZM_PLCP_HEADER_SIZE 5
374 #define ZM_ETHERNET_ADDRESS_LENGTH 6
375 #define ZM_TIMESTAMP_OFFSET 0
376 #define ZM_BEACON_INTERVAL_OFFSET 8
377 #define ZM_CAPABILITY_OFFSET 10
378
379 /* Reason Code */
380 /* An unsolicited notification management frame of */
381 /* type Disassocation or Deauthentication was generated. */
382 #ifdef ZM_REASON_CODE
383 #define ZM_WLAN_REASON_CODE_UNSPECIFIED 1
384 #define ZM_WLAN_FRAME_DISASOC_DEAUTH_REASON_CODE 24
385 #endif
386
387 struct zsWlanManagementFrameHeader
388 {
389 //u8_t plcpHdr[ZM_PLCP_HEADER_SIZE];
390 u8_t frameCtrl[2];
391 u8_t duration[2];
392 u8_t da[ZM_ETHERNET_ADDRESS_LENGTH];
393 u8_t sa[ZM_ETHERNET_ADDRESS_LENGTH];
394 u8_t bssid[ZM_ETHERNET_ADDRESS_LENGTH];
395 u8_t seqCtrl[2];
396 u8_t body[1];
397 };
398
399 struct zsWlanProbeRspFrameHeader
400 {
401 //u8_t plcpHdr[ZM_PLCP_HEADER_SIZE];
402 u8_t frameCtrl[2];
403 u8_t duration[2];
404 u8_t da[ZM_ETHERNET_ADDRESS_LENGTH];
405 u8_t sa[ZM_ETHERNET_ADDRESS_LENGTH];
406 u8_t bssid[ZM_ETHERNET_ADDRESS_LENGTH];
407 u8_t seqCtrl[2];
408 u8_t timeStamp[8];
409 u8_t beaconInterval[2];
410 u8_t capability[2];
411 u8_t ssid[ZM_MAX_SSID_LENGTH + 2]; // EID(1) + Length(1) + SSID(32)
412 } ;
413
414 #define zsWlanBeaconFrameHeader zsWlanProbeRspFrameHeader
415
416 struct zsWlanAuthFrameHeader
417 {
418 //u8_t plcpHdr[ZM_PLCP_HEADER_SIZE];
419 u8_t frameCtrl[2];
420 u8_t duration[2];
421 u8_t address1[ZM_ETHERNET_ADDRESS_LENGTH];
422 u8_t address2[ZM_ETHERNET_ADDRESS_LENGTH];
423 u8_t address3[ZM_ETHERNET_ADDRESS_LENGTH];
424 u8_t seqCtrl[2];
425 u16_t algo;
426 u16_t seq;
427 u16_t status;
428 u8_t challengeText[255]; // the first 2 bytes are information ID, length
429 };
430
431 struct zsWlanAssoFrameHeader
432 {
433 //u8_t plcpHdr[PLCP_HEADER_SIZE];
434 u8_t frameCtrl[2];
435 u8_t duration[2];
436 u8_t address1[ZM_ETHERNET_ADDRESS_LENGTH];
437 u8_t address2[ZM_ETHERNET_ADDRESS_LENGTH];
438 u8_t address3[ZM_ETHERNET_ADDRESS_LENGTH];
439 u8_t seqCtrl[2];
440 u8_t capability[2];
441 u16_t status;
442 u16_t aid;
443 //u8_t supportedRates[10];
444 };
445
446 struct zsFrag
447 {
448 zbuf_t* buf[16];
449 u16_t bufType[16];
450 u16_t seq[16];
451 u8_t flag[16];
452
453 };
454
455 //================================
456 // Hardware related definitions
457 //================================
458 #define ZM_MAC_REG_BASE 0x1c3000
459
460 #define ZM_MAC_REG_ATIM_WINDOW (ZM_MAC_REG_BASE + 0x51C)
461 #define ZM_MAC_REG_BCN_PERIOD (ZM_MAC_REG_BASE + 0x520)
462 #define ZM_MAC_REG_PRETBTT (ZM_MAC_REG_BASE + 0x524)
463
464 #define ZM_MAC_REG_MAC_ADDR_L (ZM_MAC_REG_BASE + 0x610)
465 #define ZM_MAC_REG_MAC_ADDR_H (ZM_MAC_REG_BASE + 0x614)
466
467 #define ZM_MAC_REG_GROUP_HASH_TBL_L (ZM_MAC_REG_BASE + 0x624)
468 #define ZM_MAC_REG_GROUP_HASH_TBL_H (ZM_MAC_REG_BASE + 0x628)
469
470 #define ZM_MAC_REG_BASIC_RATE (ZM_MAC_REG_BASE + 0x630)
471 #define ZM_MAC_REG_MANDATORY_RATE (ZM_MAC_REG_BASE + 0x634)
472 #define ZM_MAC_REG_RTS_CTS_RATE (ZM_MAC_REG_BASE + 0x638)
473 #define ZM_MAC_REG_BACKOFF_PROTECT (ZM_MAC_REG_BASE + 0x63c)
474 #define ZM_MAC_REG_RX_THRESHOLD (ZM_MAC_REG_BASE + 0x640)
475 #define ZM_MAC_REG_RX_PE_DELAY (ZM_MAC_REG_BASE + 0x64C)
476
477 #define ZM_MAC_REG_DYNAMIC_SIFS_ACK (ZM_MAC_REG_BASE + 0x658)
478 #define ZM_MAC_REG_SNIFFER (ZM_MAC_REG_BASE + 0x674)
479 #define ZM_MAC_REG_TX_UNDERRUN (ZM_MAC_REG_BASE + 0x688)
480 #define ZM_MAC_REG_RX_TOTAL (ZM_MAC_REG_BASE + 0x6A0)
481 #define ZM_MAC_REG_RX_CRC32 (ZM_MAC_REG_BASE + 0x6A4)
482 #define ZM_MAC_REG_RX_CRC16 (ZM_MAC_REG_BASE + 0x6A8)
483 #define ZM_MAC_REG_RX_ERR_UNI (ZM_MAC_REG_BASE + 0x6AC)
484 #define ZM_MAC_REG_RX_OVERRUN (ZM_MAC_REG_BASE + 0x6B0)
485 #define ZM_MAC_REG_RX_ERR_MUL (ZM_MAC_REG_BASE + 0x6BC)
486 #define ZM_MAC_REG_TX_RETRY (ZM_MAC_REG_BASE + 0x6CC)
487 #define ZM_MAC_REG_TX_TOTAL (ZM_MAC_REG_BASE + 0x6F4)
488
489
490 #define ZM_MAC_REG_ACK_EXTENSION (ZM_MAC_REG_BASE + 0x690)
491 #define ZM_MAC_REG_EIFS_AND_SIFS (ZM_MAC_REG_BASE + 0x698)
492
493 #define ZM_MAC_REG_SLOT_TIME (ZM_MAC_REG_BASE + 0x6F0)
494
495 #define ZM_MAC_REG_ROLL_CALL_TBL_L (ZM_MAC_REG_BASE + 0x704)
496 #define ZM_MAC_REG_ROLL_CALL_TBL_H (ZM_MAC_REG_BASE + 0x708)
497
498 #define ZM_MAC_REG_AC0_CW (ZM_MAC_REG_BASE + 0xB00)
499 #define ZM_MAC_REG_AC1_CW (ZM_MAC_REG_BASE + 0xB04)
500 #define ZM_MAC_REG_AC2_CW (ZM_MAC_REG_BASE + 0xB08)
501 #define ZM_MAC_REG_AC3_CW (ZM_MAC_REG_BASE + 0xB0C)
502 #define ZM_MAC_REG_AC4_CW (ZM_MAC_REG_BASE + 0xB10)
503 #define ZM_MAC_REG_AC1_AC0_AIFS (ZM_MAC_REG_BASE + 0xB14)
504 #define ZM_MAC_REG_AC3_AC2_AIFS (ZM_MAC_REG_BASE + 0xB18)
505
506 #define ZM_MAC_REG_RETRY_MAX (ZM_MAC_REG_BASE + 0xB28)
507
508 #define ZM_MAC_REG_TXOP_NOT_ENOUGH_INDICATION (ZM_MAC_REG_BASE + 0xB30)
509
510 #define ZM_MAC_REG_AC1_AC0_TXOP (ZM_MAC_REG_BASE + 0xB44)
511 #define ZM_MAC_REG_AC3_AC2_TXOP (ZM_MAC_REG_BASE + 0xB48)
512
513 #define ZM_MAC_REG_ACK_TABLE (ZM_MAC_REG_BASE + 0xC00)
514
515 #define ZM_MAC_REG_BCN_ADDR (ZM_MAC_REG_BASE + 0xD84)
516 #define ZM_MAC_REG_BCN_LENGTH (ZM_MAC_REG_BASE + 0xD88)
517
518 #define ZM_MAC_REG_BCN_PLCP (ZM_MAC_REG_BASE + 0xD90)
519 #define ZM_MAC_REG_BCN_CTRL (ZM_MAC_REG_BASE + 0xD94)
520
521 #define ZM_MAC_REG_BCN_HT1 (ZM_MAC_REG_BASE + 0xDA0)
522 #define ZM_MAC_REG_BCN_HT2 (ZM_MAC_REG_BASE + 0xDA4)
523
524
525 #define ZM_RX_STATUS_IS_MIC_FAIL(rxStatus) rxStatus->Tail.Data.ErrorIndication & ZM_BIT_6
526
527 //================================
528 //================================
529
530 #ifdef ZM_ENABLE_NATIVE_WIFI
531 #define ZM_80211_FRAME_HEADER_LEN 24
532 #define ZM_80211_FRAME_TYPE_OFFSET 30 // ZM_80211_FRAME_HEADER_LEN + SNAP
533 #define ZM_80211_FRAME_IP_OFFSET 32 // ZM_80211_FRAME_HEADER_LEN + SNAP + TYPE
534 #else
535 #define ZM_80211_FRAME_HEADER_LEN 14
536 #define ZM_80211_FRAME_TYPE_OFFSET 12 // ZM_80211_FRAME_HEADER_LEN + SNAP
537 #define ZM_80211_FRAME_IP_OFFSET 14 // ZM_80211_FRAME_HEADER_LEN + SNAP + TYPE
538 #endif
539
540 #define ZM_BSS_INFO_VALID_BIT 0x01
541 #define ZM_BSS_INFO_UPDATED_BIT 0x02
542
543
544
545
546
547 #define ZM_ERROR_INDICATION_RX_TIMEOUT 0x01
548 #define ZM_ERROR_INDICATION_OVERRUN 0x02
549 #define ZM_ERROR_INDICATION_DECRYPT_ERROR 0x04
550 #define ZM_ERROR_INDICATION_CRC32_ERROR 0x08
551 #define ZM_ERROR_INDICATION_ADDR_NOT_MATCH 0x10
552 #define ZM_ERROR_INDICATION_CRC16_ERROR 0x20
553 #define ZM_ERROR_INDICATION_MIC_ERROR 0x40
554
555 #define ZM_RXMAC_STATUS_MOD_TYPE_CCK 0x00
556 #define ZM_RXMAC_STATUS_MOD_TYPE_OFDM 0x01
557 #define ZM_RXMAC_STATUS_MOD_TYPE_HT_OFDM 0x02
558 #define ZM_RXMAC_STATUS_MOD_TYPE_DL_OFDM 0x03
559 #define ZM_RXMAC_STATUS_TOTAL_ERROR 0x80
560
561
562
563
564
565 #define ZM_MAX_LED_NUMBER 2
566
567 #define ZM_LED_DISABLE_MODE 0x0
568 #define ZM_LED_LINK_MODE 0x1
569 #define ZM_LED_LINK_TR_MODE 0x2
570 #define ZM_LED_TR_ON_MODE 0x3
571 #define ZM_LED_TR_OFF_MODE 0x4
572
573 #define ZM_LED_CTRL_FLAG_ALPHA 0x1
574
575 struct zsLedStruct
576 {
577 u32_t counter;
578 u32_t counter100ms;
579 u16_t ledLinkState;
580 u16_t ledMode[ZM_MAX_LED_NUMBER];
581 u32_t txTraffic;
582 u32_t rxTraffic;
583 u8_t LEDCtrlType;
584 u8_t LEDCtrlFlag; // Control Flag for vendors
585 u8_t LEDCtrlFlagFromReg; // Control Flag for vendors in registry
586 };
587
588
589 //HAL+ capability bits definition
590 #define ZM_HP_CAP_11N 0x1
591 #define ZM_HP_CAP_11N_ONE_TX_STREAM 0x2
592 #define ZM_HP_CAP_2G 0x4
593 #define ZM_HP_CAP_5G 0x8
594
595 #endif /* #ifndef _WLAN_H */
Tomato firmware and modifications.