release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/lirc/lirc_it87.h

   1 /* lirc_it87.h */
   2 /* SECTION: Definitions */
   3
   4 /********************************* ITE IT87xx ************************/
   5
   6 /* based on the following documentation from ITE:
   7    a) IT8712F Preliminary CIR Programming Guide V0.1
   8    b) IT8705F Simple LPC I/O Preliminary Specification V0.3
   9    c) IT8712F EC-LPC I/O Preliminary Specification V0.5
  10 */
  11
  12 /* IT8712/05 Ports: */
  13 #define IT87_ADRPORT      0x2e
  14 #define IT87_DATAPORT     0x2f
  15 #define IT87_INIT         {0x87, 0x01, 0x55, 0x55}
  16
  17 /* alternate Ports: */
  18 /*
  19 #define IT87_ADRPORT      0x4e
  20 #define IT87_DATAPORT     0x4f
  21 #define IT87_INIT         {0x87, 0x01, 0x55, 0xaa}
  22  */
  23
  24 /* IT8712/05 Registers */
  25 #define IT87_CFGCTRL      0x2
  26 #define IT87_LDN          0x7
  27 #define IT87_CHIP_ID1     0x20
  28 #define IT87_CHIP_ID2     0x21
  29 #define IT87_CFG_VERSION  0x22
  30 #define IT87_SWSUSPEND    0x23
  31
  32 #define IT8712_CIR_LDN    0xa
  33 #define IT8705_CIR_LDN    0x7
  34
  35 /* CIR Configuration Registers: */
  36 #define IT87_CIR_ACT      0x30
  37 #define IT87_CIR_BASE_MSB 0x60
  38 #define IT87_CIR_BASE_LSB 0x61
  39 #define IT87_CIR_IRQ      0x70
  40 #define IT87_CIR_CONFIG   0xf0
  41
  42 /* List of IT87_CIR registers: offset to BaseAddr */
  43 #define IT87_CIR_DR   0
  44 #define IT87_CIR_IER  1
  45 #define IT87_CIR_RCR  2
  46 #define IT87_CIR_TCR1 3
  47 #define IT87_CIR_TCR2 4
  48 #define IT87_CIR_TSR  5
  49 #define IT87_CIR_RSR  6
  50 #define IT87_CIR_BDLR 5
  51 #define IT87_CIR_BDHR 6
  52 #define IT87_CIR_IIR  7
  53
  54 /* Bit Definition */
  55 /* IER: */
  56 #define IT87_CIR_IER_TM_EN   0x80
  57 #define IT87_CIR_IER_RESEVED 0x40
  58 #define IT87_CIR_IER_RESET   0x20
  59 #define IT87_CIR_IER_BR      0x10
  60 #define IT87_CIR_IER_IEC     0x8
  61 #define IT87_CIR_IER_RFOIE   0x4
  62 #define IT87_CIR_IER_RDAIE   0x2
  63 #define IT87_CIR_IER_TLDLIE  0x1
  64
  65 /* RCR: */
  66 #define IT87_CIR_RCR_RDWOS  0x80
  67 #define IT87_CIR_RCR_HCFS   0x40
  68 #define IT87_CIR_RCR_RXEN   0x20
  69 #define IT87_CIR_RCR_RXEND  0x10
  70 #define IT87_CIR_RCR_RXACT  0x8
  71 #define IT87_CIR_RCR_RXDCR  0x7
  72
  73 /* TCR1: */
  74 #define IT87_CIR_TCR1_FIFOCLR 0x80
  75 #define IT87_CIR_TCR1_ILE     0x40
  76 #define IT87_CIR_TCR1_FIFOTL  0x30
  77 #define IT87_CIR_TCR1_TXRLE   0x8
  78 #define IT87_CIR_TCR1_TXENDF  0x4
  79 #define IT87_CIR_TCR1_TXMPM   0x3
  80
  81 /* TCR2: */
  82 #define IT87_CIR_TCR2_CFQ   0xf8
  83 #define IT87_CIR_TCR2_TXMPW 0x7
  84
  85 /* TSR: */
  86 #define IT87_CIR_TSR_RESERVED 0xc0
  87 #define IT87_CIR_TSR_TXFBC    0x3f
  88
  89 /* RSR: */
  90 #define IT87_CIR_RSR_RXFTO    0x80
  91 #define IT87_CIR_RSR_RESERVED 0x40
  92 #define IT87_CIR_RSR_RXFBC    0x3f
  93
  94 /* IIR: */
  95 #define IT87_CIR_IIR_RESERVED 0xf8
  96 #define IT87_CIR_IIR_IID      0x6
  97 #define IT87_CIR_IIR_IIP      0x1
  98
  99 /* TM: */
 100 #define IT87_CIR_TM_IL_SEL    0x80
 101 #define IT87_CIR_TM_RESERVED  0x40
 102 #define IT87_CIR_TM_TM_REG    0x3f
 103
 104 #define IT87_CIR_FIFO_SIZE 32
 105
 106 /* Baudratedivisor for IT87: power of 2: only 1,2,4 or 8) */
 107 #define IT87_CIR_BAUDRATE_DIVISOR 0x1
 108 #define IT87_CIR_DEFAULT_IOBASE 0x310
 109 #define IT87_CIR_DEFAULT_IRQ    0x7
 110 #define IT87_CIR_SPACE 0x00
 111 #define IT87_CIR_PULSE 0xff
 112 #define IT87_CIR_FREQ_MIN 27
 113 #define IT87_CIR_FREQ_MAX 58
 114 #define TIME_CONST (IT87_CIR_BAUDRATE_DIVISOR * 8000000ul / 115200ul)
 115
 116 /********************************* ITE IT87xx ************************/