release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/cxt1e1/libsbew.h

   1 /*
   2  * $Id: libsbew.h,v 2.1 2005/10/27 18:54:19 rickd PMCC4_3_1B $
   3  */
   4
   5 #ifndef _INC_LIBSBEW_H_
   6 #define _INC_LIBSBEW_H_
   7
   8 /*-----------------------------------------------------------------------------
   9  * libsbew.h - common library elements, charge across mulitple boards
  10  *
  11  *   This file contains common Ioctl structures and contents definitions.
  12  *
  13  * Copyright (C) 2004-2005  SBE, Inc.
  14  *
  15  *   This program is free software; you can redistribute it and/or modify
  16  *   it under the terms of the GNU General Public License as published by
  17  *   the Free Software Foundation; either version 2 of the License, or
  18  *   (at your option) any later version.
  19  *
  20  *   This program is distributed in the hope that it will be useful,
  21  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  *   GNU General Public License for more details.
  24  *
  25  * For further information, contact via email: support@sbei.com
  26  * SBE, Inc.  San Ramon, California  U.S.A.
  27  *-----------------------------------------------------------------------------
  28  * RCS info:
  29  * RCS revision: $Revision: 2.1 $
  30  * Last changed on $Date: 2005/10/27 18:54:19 $
  31  * Changed by $Author: rickd $
  32  *-----------------------------------------------------------------------------
  33  * $Log: libsbew.h,v $
  34  * Revision 2.1  2005/10/27 18:54:19  rickd
  35  * Add E1PLAIN support.
  36  *
  37  * Revision 2.0  2005/09/28 00:10:08  rickd
  38  * Customized for PMCC4 comet-per-port design.
  39  *
  40  * Revision 1.15  2005/03/29 00:51:31  rickd
  41  * File imported from C1T3 port, Revision 1.15
  42  *-----------------------------------------------------------------------------
  43  */
  44
  45 #ifndef __KERNEL__
  46 #include <sys/types.h>
  47 #endif
  48
  49 #ifdef __cplusplus
  50 extern      "C"
  51 {
  52 #endif
  53
  54 /********************************/
  55 /**  set driver logging level  **/
  56 /********************************/
  57
  58 /* routine/ioctl: wancfg_set_loglevel() - SBE_IOC_SET_LOGLEVEL */
  59
  60 #define LOG_NONE          0
  61 #define LOG_ERROR         1
  62 #define LOG_SBEBUG3       3     /* hidden, for development/debug usage */
  63 #define LOG_LSCHANGE      5     /* line state change logging */
  64 #define LOG_LSIMMEDIATE   6     /* line state change logging w/o hysterisis */
  65 #define LOG_WARN          8
  66 #define LOG_MONITOR      10
  67 #define LOG_SBEBUG12     12     /* hidden, for development/debug usage */
  68 #define LOG_MONITOR2     14     /* hidden, for development/debug usage */
  69 #define LOG_DEBUG        16
  70
  71     /* TEMPORARY DEFINES *//* RLD DEBUG */
  72 #define c4_LOG_NONE      LOG_NONE
  73 #define c4_LOG_ERROR     LOG_ERROR
  74 #define c4_LOG_WARN      LOG_WARN
  75 #define c4_LOG_sTrace    LOG_MONITOR    /* do some trace logging into
  76                                          * functions */
  77 #define c4_LOG_DEBUG     LOG_DEBUG
  78 #define c4_LOG_MAX       LOG_DEBUG
  79
  80
  81
  82 /******************************/
  83 /**  get driver information  **/
  84 /******************************/
  85
  86 /* routine/ioctl: wancfg_get_drvinfo() - SBE_IOC_GET_DRVINFO */
  87
  88 #define REL_STRLEN   80
  89     struct sbe_drv_info
  90     {
  91         int         rel_strlen;
  92         char        release[REL_STRLEN];
  93     };
  94
  95
  96 /*****************************/
  97 /**  get board information  **/
  98 /*****************************/
  99
 100 /* routine/ioctl: wancfg_get_brdinfo() - SBE_IOC_GET_BRDINFO */
 101
 102 #define CHNM_STRLEN   16
 103     struct sbe_brd_info
 104     {
 105         u_int32_t brd_id;       /* SBE's unique PCI VENDOR/DEVID */
 106         u_int32_t   brd_sn;
 107         int         brd_chan_cnt;       /* number of channels being used */
 108         int         brd_port_cnt;       /* number of ports being used */
 109         unsigned char brdno;    /* our board number */
 110         unsigned char brd_pci_speed;    /* PCI speed, 33/66Mhz */
 111                     u_int8_t brd_mac_addr[6];
 112         char        first_iname[CHNM_STRLEN];   /* first assigned channel's
 113                                                  * interface name */
 114         char        last_iname[CHNM_STRLEN];    /* last assigned channel's
 115                                                  * interface name */
 116         u_int8_t    brd_hdw_id; /* on/board unique hdw ID */
 117         u_int8_t    reserved8[3];       /* alignment preservation */
 118         u_int32_t   reserved32[3];      /* size preservation */
 119     };
 120
 121 /* These IDs are sometimes available thru pci_ids.h, but not currently. */
 122
 123 #define PCI_VENDOR_ID_SBE              0x1176
 124 #define PCI_DEVICE_ID_WANPMC_C4T1E1    0x0701   /* BID 0x0X, BTYP 0x0X */
 125 #define PCI_DEVICE_ID_WANPTMC_C4T1E1   0x0702   /* BID 0x41 */
 126 #define PCI_DEVICE_ID_WANADAPT_HC4T1E1 0x0703   /* BID 0x44 */
 127 #define PCI_DEVICE_ID_WANPTMC_256T3_T1 0x0704   /* BID 0x42 (T1 Version) */
 128 #define PCI_DEVICE_ID_WANPCI_C4T1E1    0x0705   /* BID 0x1X, BTYP 0x0X */
 129 #define PCI_DEVICE_ID_WANPMC_C1T3      0x0706   /* BID 0x45 */
 130 #define PCI_DEVICE_ID_WANPCI_C2T1E1    0x0707   /* BID 0x1X, BTYP 0x2X */
 131 #define PCI_DEVICE_ID_WANPCI_C1T1E1    0x0708   /* BID 0x1X, BTYP 0x1X */
 132 #define PCI_DEVICE_ID_WANPMC_C2T1E1    0x0709   /* BID 0x0X, BTYP 0x2X */
 133 #define PCI_DEVICE_ID_WANPMC_C1T1E1    0x070A   /* BID 0x0X, BTYP 0x1X */
 134 #define PCI_DEVICE_ID_WANPTMC_256T3_E1 0x070B   /* BID 0x46 (E1 Version) */
 135 #define PCI_DEVICE_ID_WANPTMC_C24TE1   0x070C   /* BID 0x47 */
 136 #define PCI_DEVICE_ID_WANPMC_C4T1E1_L  0x070D   /* BID 0x2X, BTYPE 0x0X w/FP
 137                                                  * LEDs */
 138 #define PCI_DEVICE_ID_WANPMC_C2T1E1_L  0x070E   /* BID 0x2X, BTYPE 0x2X w/FP
 139                                                  * LEDs */
 140 #define PCI_DEVICE_ID_WANPMC_C1T1E1_L  0x070F   /* BID 0x2X, BTYPE 0x1X w/FP
 141                                                  * LEDs */
 142 #define PCI_DEVICE_ID_WANPMC_2SSI      0x0801
 143 #define PCI_DEVICE_ID_WANPCI_4SSI      0x0802
 144 #define PCI_DEVICE_ID_WANPMC_2T3E3     0x0900   /* BID 0x43 */
 145 #define SBE_BOARD_ID(v,id)           ((v<<16) | id)
 146
 147 #define BINFO_PCI_SPEED_unk     0
 148 #define BINFO_PCI_SPEED_33      1
 149 #define BINFO_PCI_SPEED_66      2
 150
 151 /***************************/
 152 /**  obtain interface ID  **/
 153 /***************************/
 154
 155 /* routine/ioctl: wancfg_get_iid() - SBE_IOC_IID_GET */
 156
 157     struct sbe_iid_info
 158     {
 159         u_int32_t   channum;    /* channel requested */
 160         char        iname[CHNM_STRLEN]; /* channel's interface name */
 161     };
 162
 163 /**************************************/
 164 /**  get board address information  **/
 165 /**************************************/
 166
 167 /* routine/ioctl: wancfg_get_brdaddr() - SBE_IOC_BRDADDR_GET */
 168
 169     struct sbe_brd_addr
 170     {
 171         unsigned char func;     /* select PCI address space function */
 172         unsigned char brdno;    /* returns brdno requested */
 173         unsigned char irq;
 174         unsigned char size;     /* returns size of address */
 175 #define BRDADDR_SIZE_64  1
 176 #define BRDADDR_SIZE_32  2
 177         int         reserved1;  /* mod64 align, reserved for future use */
 178
 179         union
 180         {
 181             unsigned long virt64;       /* virtual/mapped address */
 182             u_int32_t   virt32[2];
 183         }           v;
 184         union
 185         {
 186             unsigned long phys64;       /* physical bus address */
 187             u_int32_t   phys32[2];
 188         }           p;
 189         int         reserved2[4];       /* reserved for future use */
 190     };
 191
 192 /**********************************/
 193 /**  read/write board registers  **/
 194 /**********************************/
 195
 196 /* routine/ioctl: wancfg_read_vec() - SBE_IOC_READ_VEC */
 197 /* routine/ioctl: wancfg_write_vec() - SBE_IOC_WRITE_VEC */
 198
 199     struct sbecom_wrt_vec
 200     {
 201         u_int32_t   reg;
 202         u_int32_t   data;
 203     };
 204
 205 #define C1T3_CHIP_MSCC_32        0x01000000
 206 #define C1T3_CHIP_TECT3_8        0x02000000
 207 #define C1T3_CHIP_CPLD_8         0x03000000
 208 #define C1T3_CHIP_EEPROM_8       0x04000000
 209
 210 #define W256T3_CHIP_MUSYCC_32    0x02000000
 211 #define W256T3_CHIP_TEMUX_8      0x10000000
 212 #define W256T3_CHIP_T8110_8      0x20000000
 213 #define W256T3_CHIP_T8110_32     0x22000000
 214 #define W256T3_CHIP_CPLD_8       0x30000000
 215 #define W256T3_CHIP_EEPROM_8     0x40000000
 216
 217
 218 /**********************************/
 219 /**  read write port parameters  **/
 220 /**********************************/
 221
 222 /* routine/ioctl: wancfg_getset_port_param() - SBE_IOC_PORT_GET */
 223 /* routine/ioctl: wancfg_set_port_param() - SBE_IOC_PORT_SET */
 224
 225 /* NOTE: this structure supports hardware which supports individual per/port control */
 226
 227 struct sbecom_port_param
 228 {
 229     u_int8_t    portnum;
 230     u_int8_t    port_mode;           /* variations of T1 or E1 mode */
 231     u_int8_t    portStatus;
 232     u_int8_t    portP;          /* more port parameters (clock source - 0x80;
 233                                  * and LBO - 0xf; */
 234                                 /* bits 0x70 are reserved for future use ) */
 235 #ifdef SBE_PMCC4_ENABLE
 236         u_int32_t   hypersize;  /* RLD DEBUG - add this in until I learn how to make this entry obsolete */
 237 #endif
 238     int         reserved[3-1];    /* reserved for future use */
 239     int    _res[4];
 240 };
 241
 242 #define CFG_CLK_PORT_MASK      0x80     /* Loop timing */
 243 #define CFG_CLK_PORT_INTERNAL  0x80     /* Loop timing */
 244 #define CFG_CLK_PORT_EXTERNAL  0x00     /* Loop timing */
 245
 246 #define CFG_LBO_MASK      0x0F
 247 #define CFG_LBO_unk       0     /* <not defined> */
 248 #define CFG_LBO_LH0       1     /* T1 Long Haul (default) */
 249 #define CFG_LBO_LH7_5     2     /* T1 Long Haul */
 250 #define CFG_LBO_LH15      3     /* T1 Long Haul */
 251 #define CFG_LBO_LH22_5    4     /* T1 Long Haul */
 252 #define CFG_LBO_SH110     5     /* T1 Short Haul */
 253 #define CFG_LBO_SH220     6     /* T1 Short Haul */
 254 #define CFG_LBO_SH330     7     /* T1 Short Haul */
 255 #define CFG_LBO_SH440     8     /* T1 Short Haul */
 256 #define CFG_LBO_SH550     9     /* T1 Short Haul */
 257 #define CFG_LBO_SH660     10    /* T1 Short Haul */
 258 #define CFG_LBO_E75       11    /* E1 75 Ohm */
 259 #define CFG_LBO_E120      12    /* E1 120 Ohm (default) */
 260
 261
 262 /*************************************/
 263 /**  read write channel parameters  **/
 264 /*************************************/
 265
 266 /* routine/ioctl: wancfg_getset_chan_param() - SBE_IOC_CHAN_GET */
 267 /* routine/ioctl: wancfg_set_chan_param() - SBE_IOC_CHAN_SET */
 268
 269 /* NOTE: this structure supports hardware which supports individual per/channel control */
 270
 271     struct sbecom_chan_param
 272     {
 273         u_int32_t   channum;    /* 0: */
 274 #ifdef SBE_PMCC4_ENABLE
 275         u_int32_t   card;  /* RLD DEBUG - add this in until I learn how to make this entry obsolete */
 276         u_int32_t   port;  /* RLD DEBUG - add this in until I learn how to make this entry obsolete */
 277         u_int8_t bitmask[32];
 278 #endif
 279         u_int32_t   intr_mask;  /* 4: interrupt mask, specify ored
 280                                  * (SS7_)INTR_* to disable */
 281         u_int8_t    status;     /* 8: channel transceiver status (TX_ENABLED,
 282                                  * RX_ENABLED) */
 283         u_int8_t    chan_mode;  /* 9: protocol mode */
 284         u_int8_t    idlecode;   /* A: idle code, in (FLAG_7E, FLAG_FF,
 285                                  * FLAG_00) */
 286         u_int8_t    pad_fill_count;     /* B: pad fill count (1-127), 0 - pad
 287                                          * fill disabled */
 288         u_int8_t    data_inv;   /* C: channel data inversion selection */
 289         u_int8_t    mode_56k;   /* D: 56kbps mode */
 290         u_int8_t    reserved[2 + 8];    /* E: */
 291     };
 292
 293 /* SS7 interrupt signals <intr_mask> */
 294 #define SS7_INTR_SFILT      0x00000020
 295 #define SS7_INTR_SDEC       0x00000040
 296 #define SS7_INTR_SINC       0x00000080
 297 #define SS7_INTR_SUERR      0x00000100
 298 /* Other interrupts that can be masked */
 299 #define INTR_BUFF           0x00000002
 300 #define INTR_EOM            0x00000004
 301 #define INTR_MSG            0x00000008
 302 #define INTR_IDLE           0x00000010
 303
 304 /* transceiver status flags <status> */
 305 #define TX_ENABLED          0x01
 306 #define RX_ENABLED          0x02
 307
 308 /* Protocol modes <mode> */
 309 #define CFG_CH_PROTO_TRANS         0
 310 #define CFG_CH_PROTO_SS7           1
 311 #define CFG_CH_PROTO_HDLC_FCS16    2
 312 #define CFG_CH_PROTO_HDLC_FCS32    3
 313 #define CFG_CH_PROTO_ISLP_MODE     4
 314
 315 /* Possible idle code assignments <idlecode> */
 316 #define CFG_CH_FLAG_7E      0
 317 #define CFG_CH_FLAG_FF      1
 318 #define CFG_CH_FLAG_00      2
 319
 320 /* data inversion selection <data_inv> */
 321 #define CFG_CH_DINV_NONE    0x00
 322 #define CFG_CH_DINV_RX      0x01
 323 #define CFG_CH_DINV_TX      0x02
 324
 325
 326 /* Posssible resettable chipsets/functions */
 327 #define RESET_DEV_TEMUX     1
 328 #define RESET_DEV_TECT3     RESET_DEV_TEMUX
 329 #define RESET_DEV_PLL       2
 330
 331
 332 /*********************************************/
 333 /**  read reset channel thruput statistics  **/
 334 /*********************************************/
 335
 336 /* routine/ioctl: wancfg_get_chan_stats() - SBE_IOC_CHAN_GET_STAT */
 337 /* routine/ioctl: wancfg_del_chan_stats() - SBE_IOC_CHAN_DEL_STAT */
 338 /* routine/ioctl: wancfg_get_card_chan_stats() - SBE_IOC_CARD_CHAN_STAT */
 339
 340     struct sbecom_chan_stats
 341     {
 342         unsigned long rx_packets;       /* total packets received       */
 343         unsigned long tx_packets;       /* total packets transmitted    */
 344         unsigned long rx_bytes; /* total bytes received         */
 345         unsigned long tx_bytes; /* total bytes transmitted      */
 346         unsigned long rx_errors;/* bad packets received         */
 347         unsigned long tx_errors;/* packet transmit problems     */
 348         unsigned long rx_dropped;       /* no space in linux buffers    */
 349         unsigned long tx_dropped;       /* no space available in linux  */
 350
 351         /* detailed rx_errors: */
 352         unsigned long rx_length_errors;
 353         unsigned long rx_over_errors;   /* receiver ring buff overflow  */
 354         unsigned long rx_crc_errors;    /* recved pkt with crc error    */
 355         unsigned long rx_frame_errors;  /* recv'd frame alignment error */
 356         unsigned long rx_fifo_errors;   /* recv'r fifo overrun          */
 357         unsigned long rx_missed_errors; /* receiver missed packet       */
 358
 359         /* detailed tx_errors */
 360         unsigned long tx_aborted_errors;
 361         unsigned long tx_fifo_errors;
 362         unsigned long tx_pending;
 363     };
 364
 365
 366 /****************************************/
 367 /**  read write card level parameters  **/
 368 /****************************************/
 369
 370  /* NOTE: this structure supports hardware which supports per/card control */
 371
 372     struct sbecom_card_param
 373     {
 374         u_int8_t    framing_type;       /* 0: CBP or M13 */
 375         u_int8_t    loopback;   /* 1: one of LOOPBACK_* */
 376         u_int8_t    line_build_out;     /* 2: boolean */
 377         u_int8_t    receive_eq; /* 3: boolean */
 378         u_int8_t    transmit_ones;      /* 4: boolean */
 379         u_int8_t    clock;      /* 5: 0 - internal, i>0 - external (recovered
 380                                  * from framer i) */
 381         u_int8_t    h110enable; /* 6: */
 382         u_int8_t    disable_leds;       /* 7: */
 383         u_int8_t    reserved1;  /* 8: available - old 256t3 hypersized, but
 384                                  * never used */
 385         u_int8_t    rear_io;    /* 9: rear I/O off/on */
 386         u_int8_t    disable_tx; /* A: disable TX off/on */
 387         u_int8_t    mute_los;   /* B: mute LOS off/on */
 388         u_int8_t    los_threshold;      /* C: LOS threshold norm/low
 389                                          * (default: norm) */
 390         u_int8_t    ds1_mode;   /* D: DS1 mode T1/E1 (default: T1) */
 391         u_int8_t    ds3_unchan; /* E: DS3 unchannelized mode off/on */
 392         u_int8_t    reserved[1 + 16];   /* reserved for expansion - must be
 393                                          * ZERO filled */
 394     };
 395
 396 /* framing types <framing_type> */
 397 #define FRAMING_M13                0
 398 #define FRAMING_CBP                1
 399
 400 /* card level loopback options <loopback> */
 401 #define CFG_CARD_LOOPBACK_NONE     0x00
 402 #define CFG_CARD_LOOPBACK_DIAG     0x01
 403 #define CFG_CARD_LOOPBACK_LINE     0x02
 404 #define CFG_CARD_LOOPBACK_PAYLOAD  0x03
 405
 406 /* line level loopback options <loopback> */
 407 #define CFG_LIU_LOOPBACK_NONE      0x00
 408 #define CFG_LIU_LOOPBACK_ANALOG    0x10
 409 #define CFG_LIU_LOOPBACK_DIGITAL   0x11
 410 #define CFG_LIU_LOOPBACK_REMOTE    0x12
 411
 412 /* card level clock options <clock> */
 413 #define CFG_CLK_INTERNAL           0x00
 414 #define CFG_CLK_EXTERNAL           0x01
 415
 416 /* legacy 256T3 loopback values */
 417 #define LOOPBACK_NONE              0
 418 #define LOOPBACK_LIU_ANALOG        1
 419 #define LOOPBACK_LIU_DIGITAL       2
 420 #define LOOPBACK_FRAMER_DS3        3
 421 #define LOOPBACK_FRAMER_T1         4
 422 #define LOOPBACK_LIU_REMOTE        5
 423
 424 /* DS1 mode <ds1_mode> */
 425 #define CFG_DS1_MODE_MASK          0x0f
 426 #define CFG_DS1_MODE_T1            0x00
 427 #define CFG_DS1_MODE_E1            0x01
 428 #define CFG_DS1_MODE_CHANGE        0x80
 429
 430 /* DS3 unchannelized values <ds1_unchan> */
 431 #define CFG_DS3_UNCHAN_MASK        0x01
 432 #define CFG_DS3_UNCHAN_OFF         0x00
 433 #define CFG_DS3_UNCHAN_ON          0x01
 434
 435
 436 /************************************/
 437 /**  read write framer parameters  **/
 438 /************************************/
 439
 440 /* routine/ioctl: wancfg_get_framer() - SBE_IOC_FRAMER_GET */
 441 /* routine/ioctl: wancfg_set_framer() - SBE_IOC_FRAMER_SET */
 442
 443     struct sbecom_framer_param
 444     {
 445         u_int8_t    framer_num;
 446         u_int8_t    frame_type; /* SF, ESF, E1PLAIN, E1CAS, E1CRC, E1CRC+CAS */
 447         u_int8_t    loopback_type;      /* DIGITAL, LINE, PAYLOAD */
 448         u_int8_t    auto_alarms;/* auto alarms */
 449         u_int8_t    reserved[12];       /* reserved for expansion - must be
 450                                          * ZERO filled */
 451     };
 452
 453 /* frame types <frame_type> */
 454 #define CFG_FRAME_NONE             0
 455 #define CFG_FRAME_SF               1    /* T1 B8ZS */
 456 #define CFG_FRAME_ESF              2    /* T1 B8ZS */
 457 #define CFG_FRAME_E1PLAIN          3    /* HDB3 w/o CAS,CRC */
 458 #define CFG_FRAME_E1CAS            4    /* HDB3 */
 459 #define CFG_FRAME_E1CRC            5    /* HDB3 */
 460 #define CFG_FRAME_E1CRC_CAS        6    /* HDB3 */
 461 #define CFG_FRAME_SF_AMI           7    /* T1 AMI */
 462 #define CFG_FRAME_ESF_AMI          8    /* T1 AMI */
 463 #define CFG_FRAME_E1PLAIN_AMI      9    /* E1 AMI w/o CAS,CRC */
 464 #define CFG_FRAME_E1CAS_AMI       10    /* E1 AMI */
 465 #define CFG_FRAME_E1CRC_AMI       11    /* E1 AMI */
 466 #define CFG_FRAME_E1CRC_CAS_AMI   12    /* E1 AMI */
 467
 468 #define IS_FRAME_ANY_T1(field) \
 469                     (((field) == CFG_FRAME_NONE) || \
 470                      ((field) == CFG_FRAME_SF)   || \
 471                      ((field) == CFG_FRAME_ESF)  || \
 472                      ((field) == CFG_FRAME_SF_AMI) || \
 473                      ((field) == CFG_FRAME_ESF_AMI))
 474
 475 #define IS_FRAME_ANY_T1ESF(field) \
 476                     (((field) == CFG_FRAME_ESF) || \
 477                      ((field) == CFG_FRAME_ESF_AMI))
 478
 479 #define IS_FRAME_ANY_E1(field) \
 480                     (((field) == CFG_FRAME_E1PLAIN) || \
 481                      ((field) == CFG_FRAME_E1CAS)   || \
 482                      ((field) == CFG_FRAME_E1CRC)   || \
 483                      ((field) == CFG_FRAME_E1CRC_CAS) || \
 484                      ((field) == CFG_FRAME_E1PLAIN_AMI) || \
 485                      ((field) == CFG_FRAME_E1CAS_AMI) || \
 486                      ((field) == CFG_FRAME_E1CRC_AMI) || \
 487                      ((field) == CFG_FRAME_E1CRC_CAS_AMI))
 488
 489 #define IS_FRAME_ANY_AMI(field) \
 490                     (((field) == CFG_FRAME_SF_AMI) || \
 491                      ((field) == CFG_FRAME_ESF_AMI) || \
 492                      ((field) == CFG_FRAME_E1PLAIN_AMI) || \
 493                      ((field) == CFG_FRAME_E1CAS_AMI) || \
 494                      ((field) == CFG_FRAME_E1CRC_AMI) || \
 495                      ((field) == CFG_FRAME_E1CRC_CAS_AMI))
 496
 497 /* frame level loopback options <loopback_type> */
 498 #define CFG_FRMR_LOOPBACK_NONE     0
 499 #define CFG_FRMR_LOOPBACK_DIAG     1
 500 #define CFG_FRMR_LOOPBACK_LINE     2
 501 #define CFG_FRMR_LOOPBACK_PAYLOAD  3
 502
 503
 504 /****************************************/
 505 /**  read reset card error statistics  **/
 506 /****************************************/
 507
 508 /* routine/ioctl: wancfg_get_card_stats() - SBE_IOC_CARD_GET_STAT */
 509 /* routine/ioctl: wancfg_del_card_stats() - SBE_IOC_CARD_DEL_STAT */
 510
 511     struct temux_card_stats
 512     {
 513         struct temux_stats
 514         {
 515             /* TEMUX DS3 PMON counters */
 516             u_int32_t   lcv;
 517             u_int32_t   err_framing;
 518             u_int32_t   febe;
 519             u_int32_t   err_cpbit;
 520             u_int32_t   err_parity;
 521             /* TEMUX DS3 FRMR status */
 522             u_int8_t    los;
 523             u_int8_t    oof;
 524             u_int8_t    red;
 525             u_int8_t    yellow;
 526             u_int8_t    idle;
 527             u_int8_t    ais;
 528             u_int8_t    cbit;
 529             /* TEMUX DS3 FEAC receiver */
 530             u_int8_t    feac;
 531             u_int8_t    feac_last;
 532         }           t;
 533         u_int32_t   tx_pending; /* total */
 534     };
 535
 536 /**************************************************************/
 537
 538     struct wancfg
 539     {
 540         int         cs, ds;
 541         char       *p;
 542     };
 543     typedef struct wancfg wcfg_t;
 544
 545     extern wcfg_t *wancfg_init (char *, char *);
 546     extern int  wancfg_card_blink (wcfg_t *, int);
 547     extern int  wancfg_ctl (wcfg_t *, int, void *, int, void *, int);
 548     extern int  wancfg_del_card_stats (wcfg_t *);
 549     extern int  wancfg_del_chan_stats (wcfg_t *, int);
 550     extern int  wancfg_enable_ports (wcfg_t *, int);
 551     extern int  wancfg_free (wcfg_t *);
 552     extern int  wancfg_get_brdaddr (wcfg_t *, struct sbe_brd_addr *);
 553     extern int  wancfg_get_brdinfo (wcfg_t *, struct sbe_brd_info *);
 554     extern int  wancfg_get_card (wcfg_t *, struct sbecom_card_param *);
 555     extern int  wancfg_get_card_chan_stats (wcfg_t *, struct sbecom_chan_stats *);
 556     extern int  wancfg_get_card_sn (wcfg_t *);
 557     extern int  wancfg_get_card_stats (wcfg_t *, struct temux_card_stats *);
 558     extern int  wancfg_get_chan (wcfg_t *, int, struct sbecom_chan_param *);
 559     extern int  wancfg_get_chan_stats (wcfg_t *, int, struct sbecom_chan_stats *);
 560     extern int  wancfg_get_drvinfo (wcfg_t *, int, struct sbe_drv_info *);
 561     extern int  wancfg_get_framer (wcfg_t *, int, struct sbecom_framer_param *);
 562     extern int  wancfg_get_iid (wcfg_t *, int, struct sbe_iid_info *);
 563     extern int  wancfg_get_sn (wcfg_t *, unsigned int *);
 564     extern int  wancfg_read (wcfg_t *, int, struct sbecom_wrt_vec *);
 565     extern int  wancfg_reset_device (wcfg_t *, int);
 566     extern int  wancfg_set_card (wcfg_t *, struct sbecom_card_param *);
 567     extern int  wancfg_set_chan (wcfg_t *, int, struct sbecom_chan_param *);
 568     extern int  wancfg_set_framer (wcfg_t *, int, struct sbecom_framer_param *);
 569     extern int  wancfg_set_loglevel (wcfg_t *, uint);
 570     extern int  wancfg_write (wcfg_t *, int, struct sbecom_wrt_vec *);
 571
 572 #ifdef NOT_YET_COMMON
 573     extern int  wancfg_get_tsioc (wcfg_t *, struct wanc1t3_ts_hdr *, struct wanc1t3_ts_param *);
 574     extern int  wancfg_set_tsioc (wcfg_t *, struct wanc1t3_ts_param *);
 575 #endif
 576
 577 #ifdef __cplusplus
 578 }
 579 #endif
 580
 581 #endif                          /*** _INC_LIBSBEW_H_ ***/