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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / staging / comedi / drivers / s626.c
blobdb0d14bd349bb7f8f9f1b2da6ec56aeee9ea989c
1 /*
2 comedi/drivers/s626.c
3 Sensoray s626 Comedi driver
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
7
8 Based on Sensoray Model 626 Linux driver Version 0.2
9 Copyright (C) 2002-2004 Sensoray Co., Inc.
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24
25 */
26
27 /*
28 Driver: s626
29 Description: Sensoray 626 driver
30 Devices: [Sensoray] 626 (s626)
31 Authors: Gianluca Palli <gpalli@deis.unibo.it>,
32 Updated: Fri, 15 Feb 2008 10:28:42 +0000
33 Status: experimental
34
35 Configuration options:
36 [0] - PCI bus of device (optional)
37 [1] - PCI slot of device (optional)
38 If bus/slot is not specified, the first supported
39 PCI device found will be used.
40
41 INSN_CONFIG instructions:
42 analog input:
43 none
44
45 analog output:
46 none
47
48 digital channel:
49 s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
50 supported configuration options:
51 INSN_CONFIG_DIO_QUERY
52 COMEDI_INPUT
53 COMEDI_OUTPUT
54
55 encoder:
56 Every channel must be configured before reading.
57
58 Example code
59
60 insn.insn=INSN_CONFIG; //configuration instruction
61 insn.n=1; //number of operation (must be 1)
62 insn.data=&initialvalue; //initial value loaded into encoder
63 //during configuration
64 insn.subdev=5; //encoder subdevice
65 insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
66 //to configure
67
68 comedi_do_insn(cf,&insn); //executing configuration
69 */
70
71 #include <linux/interrupt.h>
72 #include <linux/kernel.h>
73 #include <linux/types.h>
74
75 #include "../comedidev.h"
76
77 #include "comedi_pci.h"
78
79 #include "comedi_fc.h"
80 #include "s626.h"
81
82 MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>");
83 MODULE_DESCRIPTION("Sensoray 626 Comedi driver module");
84 MODULE_LICENSE("GPL");
85
86 struct s626_board {
87 const char *name;
88 int ai_chans;
89 int ai_bits;
90 int ao_chans;
91 int ao_bits;
92 int dio_chans;
93 int dio_banks;
94 int enc_chans;
95 };
96
97 static const struct s626_board s626_boards[] = {
98 {
99 .name = "s626",
100 .ai_chans = S626_ADC_CHANNELS,
101 .ai_bits = 14,
102 .ao_chans = S626_DAC_CHANNELS,
103 .ao_bits = 13,
104 .dio_chans = S626_DIO_CHANNELS,
105 .dio_banks = S626_DIO_BANKS,
106 .enc_chans = S626_ENCODER_CHANNELS,
107 }
108 };
109
110 #define thisboard ((const struct s626_board *)dev->board_ptr)
111 #define PCI_VENDOR_ID_S626 0x1131
112 #define PCI_DEVICE_ID_S626 0x7146
113
114 /*
115 * For devices with vendor:device id == 0x1131:0x7146 you must specify
116 * also subvendor:subdevice ids, because otherwise it will conflict with
117 * Philips SAA7146 media/dvb based cards.
118 */
119 static DEFINE_PCI_DEVICE_TABLE(s626_pci_table) = {
120 {PCI_VENDOR_ID_S626, PCI_DEVICE_ID_S626, 0x6000, 0x0272, 0, 0, 0},
121 {0}
122 };
123
124 MODULE_DEVICE_TABLE(pci, s626_pci_table);
125
126 static int s626_attach(struct comedi_device *dev, struct comedi_devconfig *it);
127 static int s626_detach(struct comedi_device *dev);
128
129 static struct comedi_driver driver_s626 = {
130 .driver_name = "s626",
131 .module = THIS_MODULE,
132 .attach = s626_attach,
133 .detach = s626_detach,
134 };
135
136 struct s626_private {
137 struct pci_dev *pdev;
138 void *base_addr;
139 int got_regions;
140 short allocatedBuf;
141 uint8_t ai_cmd_running; /* ai_cmd is running */
142 uint8_t ai_continous; /* continous aquisition */
143 int ai_sample_count; /* number of samples to acquire */
144 unsigned int ai_sample_timer;
145 /* time between samples in units of the timer */
146 int ai_convert_count; /* conversion counter */
147 unsigned int ai_convert_timer;
148 /* time between conversion in units of the timer */
149 uint16_t CounterIntEnabs;
150 /* Counter interrupt enable mask for MISC2 register. */
151 uint8_t AdcItems; /* Number of items in ADC poll list. */
152 struct bufferDMA RPSBuf; /* DMA buffer used to hold ADC (RPS1) program. */
153 struct bufferDMA ANABuf;
154 /* DMA buffer used to receive ADC data and hold DAC data. */
155 uint32_t *pDacWBuf;
156 /* Pointer to logical adrs of DMA buffer used to hold DAC data. */
157 uint16_t Dacpol; /* Image of DAC polarity register. */
158 uint8_t TrimSetpoint[12]; /* Images of TrimDAC setpoints */
159 uint16_t ChargeEnabled; /* Image of MISC2 Battery */
160 /* Charge Enabled (0 or WRMISC2_CHARGE_ENABLE). */
161 uint16_t WDInterval; /* Image of MISC2 watchdog interval control bits. */
162 uint32_t I2CAdrs;
163 /* I2C device address for onboard EEPROM (board rev dependent). */
164 /* short I2Cards; */
165 unsigned int ao_readback[S626_DAC_CHANNELS];
166 };
167
168 struct dio_private {
169 uint16_t RDDIn;
170 uint16_t WRDOut;
171 uint16_t RDEdgSel;
172 uint16_t WREdgSel;
173 uint16_t RDCapSel;
174 uint16_t WRCapSel;
175 uint16_t RDCapFlg;
176 uint16_t RDIntSel;
177 uint16_t WRIntSel;
178 };
179
180 static struct dio_private dio_private_A = {
181 .RDDIn = LP_RDDINA,
182 .WRDOut = LP_WRDOUTA,
183 .RDEdgSel = LP_RDEDGSELA,
184 .WREdgSel = LP_WREDGSELA,
185 .RDCapSel = LP_RDCAPSELA,
186 .WRCapSel = LP_WRCAPSELA,
187 .RDCapFlg = LP_RDCAPFLGA,
188 .RDIntSel = LP_RDINTSELA,
189 .WRIntSel = LP_WRINTSELA,
190 };
191
192 static struct dio_private dio_private_B = {
193 .RDDIn = LP_RDDINB,
194 .WRDOut = LP_WRDOUTB,
195 .RDEdgSel = LP_RDEDGSELB,
196 .WREdgSel = LP_WREDGSELB,
197 .RDCapSel = LP_RDCAPSELB,
198 .WRCapSel = LP_WRCAPSELB,
199 .RDCapFlg = LP_RDCAPFLGB,
200 .RDIntSel = LP_RDINTSELB,
201 .WRIntSel = LP_WRINTSELB,
202 };
203
204 static struct dio_private dio_private_C = {
205 .RDDIn = LP_RDDINC,
206 .WRDOut = LP_WRDOUTC,
207 .RDEdgSel = LP_RDEDGSELC,
208 .WREdgSel = LP_WREDGSELC,
209 .RDCapSel = LP_RDCAPSELC,
210 .WRCapSel = LP_WRCAPSELC,
211 .RDCapFlg = LP_RDCAPFLGC,
212 .RDIntSel = LP_RDINTSELC,
213 .WRIntSel = LP_WRINTSELC,
214 };
215
216 /* to group dio devices (48 bits mask and data are not allowed ???)
217 static struct dio_private *dio_private_word[]={
218 &dio_private_A,
219 &dio_private_B,
220 &dio_private_C,
221 };
222 */
223
224 #define devpriv ((struct s626_private *)dev->private)
225 #define diopriv ((struct dio_private *)s->private)
226
227 static int __devinit driver_s626_pci_probe(struct pci_dev *dev,
228 const struct pci_device_id *ent)
229 {
230 return comedi_pci_auto_config(dev, driver_s626.driver_name);
231 }
232
233 static void __devexit driver_s626_pci_remove(struct pci_dev *dev)
234 {
235 comedi_pci_auto_unconfig(dev);
236 }
237
238 static struct pci_driver driver_s626_pci_driver = {
239 .id_table = s626_pci_table,
240 .probe = &driver_s626_pci_probe,
241 .remove = __devexit_p(&driver_s626_pci_remove)
242 };
243
244 static int __init driver_s626_init_module(void)
245 {
246 int retval;
247
248 retval = comedi_driver_register(&driver_s626);
249 if (retval < 0)
250 return retval;
251
252 driver_s626_pci_driver.name = (char *)driver_s626.driver_name;
253 return pci_register_driver(&driver_s626_pci_driver);
254 }
255
256 static void __exit driver_s626_cleanup_module(void)
257 {
258 pci_unregister_driver(&driver_s626_pci_driver);
259 comedi_driver_unregister(&driver_s626);
260 }
261
262 module_init(driver_s626_init_module);
263 module_exit(driver_s626_cleanup_module);
264
265 /* ioctl routines */
266 static int s626_ai_insn_config(struct comedi_device *dev,
267 struct comedi_subdevice *s,
268 struct comedi_insn *insn, unsigned int *data);
269 /* static int s626_ai_rinsn(struct comedi_device *dev,struct comedi_subdevice *s,struct comedi_insn *insn,unsigned int *data); */
270 static int s626_ai_insn_read(struct comedi_device *dev,
271 struct comedi_subdevice *s,
272 struct comedi_insn *insn, unsigned int *data);
273 static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
274 static int s626_ai_cmdtest(struct comedi_device *dev,
275 struct comedi_subdevice *s, struct comedi_cmd *cmd);
276 static int s626_ai_cancel(struct comedi_device *dev,
277 struct comedi_subdevice *s);
278 static int s626_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
279 struct comedi_insn *insn, unsigned int *data);
280 static int s626_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
281 struct comedi_insn *insn, unsigned int *data);
282 static int s626_dio_insn_bits(struct comedi_device *dev,
283 struct comedi_subdevice *s,
284 struct comedi_insn *insn, unsigned int *data);
285 static int s626_dio_insn_config(struct comedi_device *dev,
286 struct comedi_subdevice *s,
287 struct comedi_insn *insn, unsigned int *data);
288 static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan);
289 static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int gruop,
290 unsigned int mask);
291 static int s626_dio_clear_irq(struct comedi_device *dev);
292 static int s626_enc_insn_config(struct comedi_device *dev,
293 struct comedi_subdevice *s,
294 struct comedi_insn *insn, unsigned int *data);
295 static int s626_enc_insn_read(struct comedi_device *dev,
296 struct comedi_subdevice *s,
297 struct comedi_insn *insn, unsigned int *data);
298 static int s626_enc_insn_write(struct comedi_device *dev,
299 struct comedi_subdevice *s,
300 struct comedi_insn *insn, unsigned int *data);
301 static int s626_ns_to_timer(int *nanosec, int round_mode);
302 static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd);
303 static int s626_ai_inttrig(struct comedi_device *dev,
304 struct comedi_subdevice *s, unsigned int trignum);
305 static irqreturn_t s626_irq_handler(int irq, void *d);
306 static unsigned int s626_ai_reg_to_uint(int data);
307 /* static unsigned int s626_uint_to_reg(struct comedi_subdevice *s, int data); */
308
309 /* end ioctl routines */
310
311 /* internal routines */
312 static void s626_dio_init(struct comedi_device *dev);
313 static void ResetADC(struct comedi_device *dev, uint8_t * ppl);
314 static void LoadTrimDACs(struct comedi_device *dev);
315 static void WriteTrimDAC(struct comedi_device *dev, uint8_t LogicalChan,
316 uint8_t DacData);
317 static uint8_t I2Cread(struct comedi_device *dev, uint8_t addr);
318 static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val);
319 static void SetDAC(struct comedi_device *dev, uint16_t chan, short dacdata);
320 static void SendDAC(struct comedi_device *dev, uint32_t val);
321 static void WriteMISC2(struct comedi_device *dev, uint16_t NewImage);
322 static void DEBItransfer(struct comedi_device *dev);
323 static uint16_t DEBIread(struct comedi_device *dev, uint16_t addr);
324 static void DEBIwrite(struct comedi_device *dev, uint16_t addr, uint16_t wdata);
325 static void DEBIreplace(struct comedi_device *dev, uint16_t addr, uint16_t mask,
326 uint16_t wdata);
327 static void CloseDMAB(struct comedi_device *dev, struct bufferDMA *pdma,
328 size_t bsize);
329
330 /* COUNTER OBJECT ------------------------------------------------ */
331 struct enc_private {
332 /* Pointers to functions that differ for A and B counters: */
333 uint16_t(*GetEnable) (struct comedi_device *dev, struct enc_private *); /* Return clock enable. */
334 uint16_t(*GetIntSrc) (struct comedi_device *dev, struct enc_private *); /* Return interrupt source. */
335 uint16_t(*GetLoadTrig) (struct comedi_device *dev, struct enc_private *); /* Return preload trigger source. */
336 uint16_t(*GetMode) (struct comedi_device *dev, struct enc_private *); /* Return standardized operating mode. */
337 void (*PulseIndex) (struct comedi_device *dev, struct enc_private *); /* Generate soft index strobe. */
338 void (*SetEnable) (struct comedi_device *dev, struct enc_private *, uint16_t enab); /* Program clock enable. */
339 void (*SetIntSrc) (struct comedi_device *dev, struct enc_private *, uint16_t IntSource); /* Program interrupt source. */
340 void (*SetLoadTrig) (struct comedi_device *dev, struct enc_private *, uint16_t Trig); /* Program preload trigger source. */
341 void (*SetMode) (struct comedi_device *dev, struct enc_private *, uint16_t Setup, uint16_t DisableIntSrc); /* Program standardized operating mode. */
342 void (*ResetCapFlags) (struct comedi_device *dev, struct enc_private *); /* Reset event capture flags. */
343
344 uint16_t MyCRA; /* Address of CRA register. */
345 uint16_t MyCRB; /* Address of CRB register. */
346 uint16_t MyLatchLsw; /* Address of Latch least-significant-word */
347 /* register. */
348 uint16_t MyEventBits[4]; /* Bit translations for IntSrc -->RDMISC2. */
349 };
350
351 #define encpriv ((struct enc_private *)(dev->subdevices+5)->private)
352
353 /* counters routines */
354 static void s626_timer_load(struct comedi_device *dev, struct enc_private *k,
355 int tick);
356 static uint32_t ReadLatch(struct comedi_device *dev, struct enc_private *k);
357 static void ResetCapFlags_A(struct comedi_device *dev, struct enc_private *k);
358 static void ResetCapFlags_B(struct comedi_device *dev, struct enc_private *k);
359 static uint16_t GetMode_A(struct comedi_device *dev, struct enc_private *k);
360 static uint16_t GetMode_B(struct comedi_device *dev, struct enc_private *k);
361 static void SetMode_A(struct comedi_device *dev, struct enc_private *k,
362 uint16_t Setup, uint16_t DisableIntSrc);
363 static void SetMode_B(struct comedi_device *dev, struct enc_private *k,
364 uint16_t Setup, uint16_t DisableIntSrc);
365 static void SetEnable_A(struct comedi_device *dev, struct enc_private *k,
366 uint16_t enab);
367 static void SetEnable_B(struct comedi_device *dev, struct enc_private *k,
368 uint16_t enab);
369 static uint16_t GetEnable_A(struct comedi_device *dev, struct enc_private *k);
370 static uint16_t GetEnable_B(struct comedi_device *dev, struct enc_private *k);
371 static void SetLatchSource(struct comedi_device *dev, struct enc_private *k,
372 uint16_t value);
373 /* static uint16_t GetLatchSource(struct comedi_device *dev, struct enc_private *k ); */
374 static void SetLoadTrig_A(struct comedi_device *dev, struct enc_private *k,
375 uint16_t Trig);
376 static void SetLoadTrig_B(struct comedi_device *dev, struct enc_private *k,
377 uint16_t Trig);
378 static uint16_t GetLoadTrig_A(struct comedi_device *dev, struct enc_private *k);
379 static uint16_t GetLoadTrig_B(struct comedi_device *dev, struct enc_private *k);
380 static void SetIntSrc_B(struct comedi_device *dev, struct enc_private *k,
381 uint16_t IntSource);
382 static void SetIntSrc_A(struct comedi_device *dev, struct enc_private *k,
383 uint16_t IntSource);
384 static uint16_t GetIntSrc_A(struct comedi_device *dev, struct enc_private *k);
385 static uint16_t GetIntSrc_B(struct comedi_device *dev, struct enc_private *k);
386 /* static void SetClkMult(struct comedi_device *dev, struct enc_private *k, uint16_t value ) ; */
387 /* static uint16_t GetClkMult(struct comedi_device *dev, struct enc_private *k ) ; */
388 /* static void SetIndexPol(struct comedi_device *dev, struct enc_private *k, uint16_t value ); */
389 /* static uint16_t GetClkPol(struct comedi_device *dev, struct enc_private *k ) ; */
390 /* static void SetIndexSrc( struct comedi_device *dev,struct enc_private *k, uint16_t value ); */
391 /* static uint16_t GetClkSrc( struct comedi_device *dev,struct enc_private *k ); */
392 /* static void SetIndexSrc( struct comedi_device *dev,struct enc_private *k, uint16_t value ); */
393 /* static uint16_t GetIndexSrc( struct comedi_device *dev,struct enc_private *k ); */
394 static void PulseIndex_A(struct comedi_device *dev, struct enc_private *k);
395 static void PulseIndex_B(struct comedi_device *dev, struct enc_private *k);
396 static void Preload(struct comedi_device *dev, struct enc_private *k,
397 uint32_t value);
398 static void CountersInit(struct comedi_device *dev);
399 /* end internal routines */
400
401 /* Counter objects constructor. */
402
403 /* Counter overflow/index event flag masks for RDMISC2. */
404 #define INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4)))
405 #define OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
406 #define EVBITS(C) { 0, OVERMASK(C), INDXMASK(C), OVERMASK(C) | INDXMASK(C) }
407
408 /* Translation table to map IntSrc into equivalent RDMISC2 event flag bits. */
409 /* static const uint16_t EventBits[][4] = { EVBITS(0), EVBITS(1), EVBITS(2), EVBITS(3), EVBITS(4), EVBITS(5) }; */
410
411 /* struct enc_private; */
412 static struct enc_private enc_private_data[] = {
413 {
414 .GetEnable = GetEnable_A,
415 .GetIntSrc = GetIntSrc_A,
416 .GetLoadTrig = GetLoadTrig_A,
417 .GetMode = GetMode_A,
418 .PulseIndex = PulseIndex_A,
419 .SetEnable = SetEnable_A,
420 .SetIntSrc = SetIntSrc_A,
421 .SetLoadTrig = SetLoadTrig_A,
422 .SetMode = SetMode_A,
423 .ResetCapFlags = ResetCapFlags_A,
424 .MyCRA = LP_CR0A,
425 .MyCRB = LP_CR0B,
426 .MyLatchLsw = LP_CNTR0ALSW,
427 .MyEventBits = EVBITS(0),
428 },
429 {
430 .GetEnable = GetEnable_A,
431 .GetIntSrc = GetIntSrc_A,
432 .GetLoadTrig = GetLoadTrig_A,
433 .GetMode = GetMode_A,
434 .PulseIndex = PulseIndex_A,
435 .SetEnable = SetEnable_A,
436 .SetIntSrc = SetIntSrc_A,
437 .SetLoadTrig = SetLoadTrig_A,
438 .SetMode = SetMode_A,
439 .ResetCapFlags = ResetCapFlags_A,
440 .MyCRA = LP_CR1A,
441 .MyCRB = LP_CR1B,
442 .MyLatchLsw = LP_CNTR1ALSW,
443 .MyEventBits = EVBITS(1),
444 },
445 {
446 .GetEnable = GetEnable_A,
447 .GetIntSrc = GetIntSrc_A,
448 .GetLoadTrig = GetLoadTrig_A,
449 .GetMode = GetMode_A,
450 .PulseIndex = PulseIndex_A,
451 .SetEnable = SetEnable_A,
452 .SetIntSrc = SetIntSrc_A,
453 .SetLoadTrig = SetLoadTrig_A,
454 .SetMode = SetMode_A,
455 .ResetCapFlags = ResetCapFlags_A,
456 .MyCRA = LP_CR2A,
457 .MyCRB = LP_CR2B,
458 .MyLatchLsw = LP_CNTR2ALSW,
459 .MyEventBits = EVBITS(2),
460 },
461 {
462 .GetEnable = GetEnable_B,
463 .GetIntSrc = GetIntSrc_B,
464 .GetLoadTrig = GetLoadTrig_B,
465 .GetMode = GetMode_B,
466 .PulseIndex = PulseIndex_B,
467 .SetEnable = SetEnable_B,
468 .SetIntSrc = SetIntSrc_B,
469 .SetLoadTrig = SetLoadTrig_B,
470 .SetMode = SetMode_B,
471 .ResetCapFlags = ResetCapFlags_B,
472 .MyCRA = LP_CR0A,
473 .MyCRB = LP_CR0B,
474 .MyLatchLsw = LP_CNTR0BLSW,
475 .MyEventBits = EVBITS(3),
476 },
477 {
478 .GetEnable = GetEnable_B,
479 .GetIntSrc = GetIntSrc_B,
480 .GetLoadTrig = GetLoadTrig_B,
481 .GetMode = GetMode_B,
482 .PulseIndex = PulseIndex_B,
483 .SetEnable = SetEnable_B,
484 .SetIntSrc = SetIntSrc_B,
485 .SetLoadTrig = SetLoadTrig_B,
486 .SetMode = SetMode_B,
487 .ResetCapFlags = ResetCapFlags_B,
488 .MyCRA = LP_CR1A,
489 .MyCRB = LP_CR1B,
490 .MyLatchLsw = LP_CNTR1BLSW,
491 .MyEventBits = EVBITS(4),
492 },
493 {
494 .GetEnable = GetEnable_B,
495 .GetIntSrc = GetIntSrc_B,
496 .GetLoadTrig = GetLoadTrig_B,
497 .GetMode = GetMode_B,
498 .PulseIndex = PulseIndex_B,
499 .SetEnable = SetEnable_B,
500 .SetIntSrc = SetIntSrc_B,
501 .SetLoadTrig = SetLoadTrig_B,
502 .SetMode = SetMode_B,
503 .ResetCapFlags = ResetCapFlags_B,
504 .MyCRA = LP_CR2A,
505 .MyCRB = LP_CR2B,
506 .MyLatchLsw = LP_CNTR2BLSW,
507 .MyEventBits = EVBITS(5),
508 },
509 };
510
511 /* enab/disable a function or test status bit(s) that are accessed */
512 /* through Main Control Registers 1 or 2. */
513 #define MC_ENABLE(REGADRS, CTRLWORD) writel(((uint32_t)(CTRLWORD) << 16) | (uint32_t)(CTRLWORD), devpriv->base_addr+(REGADRS))
514
515 #define MC_DISABLE(REGADRS, CTRLWORD) writel((uint32_t)(CTRLWORD) << 16 , devpriv->base_addr+(REGADRS))
516
517 #define MC_TEST(REGADRS, CTRLWORD) ((readl(devpriv->base_addr+(REGADRS)) & CTRLWORD) != 0)
518
519 /* #define WR7146(REGARDS,CTRLWORD)
520 writel(CTRLWORD,(uint32_t)(devpriv->base_addr+(REGARDS))) */
521 #define WR7146(REGARDS, CTRLWORD) writel(CTRLWORD, devpriv->base_addr+(REGARDS))
522
523 /* #define RR7146(REGARDS)
524 readl((uint32_t)(devpriv->base_addr+(REGARDS))) */
525 #define RR7146(REGARDS) readl(devpriv->base_addr+(REGARDS))
526
527 #define BUGFIX_STREG(REGADRS) (REGADRS - 4)
528
529 /* Write a time slot control record to TSL2. */
530 #define VECTPORT(VECTNUM) (P_TSL2 + ((VECTNUM) << 2))
531 #define SETVECT(VECTNUM, VECTVAL) WR7146(VECTPORT(VECTNUM), (VECTVAL))
532
533 /* Code macros used for constructing I2C command bytes. */
534 #define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24))
535 #define I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16))
536 #define I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8))
537
538 static const struct comedi_lrange s626_range_table = { 2, {
539 RANGE(-5, 5),
540 RANGE(-10, 10),
541 }
542 };
543
544 static int s626_attach(struct comedi_device *dev, struct comedi_devconfig *it)
545 {
546 /* uint8_t PollList; */
547 /* uint16_t AdcData; */
548 /* uint16_t StartVal; */
549 /* uint16_t index; */
550 /* unsigned int data[16]; */
551 int result;
552 int i;
553 int ret;
554 resource_size_t resourceStart;
555 dma_addr_t appdma;
556 struct comedi_subdevice *s;
557 const struct pci_device_id *ids;
558 struct pci_dev *pdev = NULL;
559
560 if (alloc_private(dev, sizeof(struct s626_private)) < 0)
561 return -ENOMEM;
562
563 for (i = 0; i < (ARRAY_SIZE(s626_pci_table) - 1) && !pdev; i++) {
564 ids = &s626_pci_table[i];
565 do {
566 pdev = pci_get_subsys(ids->vendor, ids->device,
567 ids->subvendor, ids->subdevice,
568 pdev);
569
570 if ((it->options[0] || it->options[1]) && pdev) {
571 /* matches requested bus/slot */
572 if (pdev->bus->number == it->options[0] &&
573 PCI_SLOT(pdev->devfn) == it->options[1])
574 break;
575 } else
576 break;
577 } while (1);
578 }
579 devpriv->pdev = pdev;
580
581 if (pdev == NULL) {
582 printk(KERN_ERR "s626_attach: Board not present!!!\n");
583 return -ENODEV;
584 }
585
586 result = comedi_pci_enable(pdev, "s626");
587 if (result < 0) {
588 printk(KERN_ERR "s626_attach: comedi_pci_enable fails\n");
589 return -ENODEV;
590 }
591 devpriv->got_regions = 1;
592
593 resourceStart = pci_resource_start(devpriv->pdev, 0);
594
595 devpriv->base_addr = ioremap(resourceStart, SIZEOF_ADDRESS_SPACE);
596 if (devpriv->base_addr == NULL) {
597 printk(KERN_ERR "s626_attach: IOREMAP failed\n");
598 return -ENODEV;
599 }
600
601 if (devpriv->base_addr) {
602 /* disable master interrupt */
603 writel(0, devpriv->base_addr + P_IER);
604
605 /* soft reset */
606 writel(MC1_SOFT_RESET, devpriv->base_addr + P_MC1);
607
608 DEBUG("s626_attach: DMA ALLOCATION\n");
609
610 /* adc buffer allocation */
611 devpriv->allocatedBuf = 0;
612
613 devpriv->ANABuf.LogicalBase =
614 pci_alloc_consistent(devpriv->pdev, DMABUF_SIZE, &appdma);
615
616 if (devpriv->ANABuf.LogicalBase == NULL) {
617 printk(KERN_ERR "s626_attach: DMA Memory mapping error\n");
618 return -ENOMEM;
619 }
620
621 devpriv->ANABuf.PhysicalBase = appdma;
622
623 DEBUG
624 ("s626_attach: AllocDMAB ADC Logical=%p, bsize=%d, Physical=0x%x\n",
625 devpriv->ANABuf.LogicalBase, DMABUF_SIZE,
626 (uint32_t) devpriv->ANABuf.PhysicalBase);
627
628 devpriv->allocatedBuf++;
629
630 devpriv->RPSBuf.LogicalBase =
631 pci_alloc_consistent(devpriv->pdev, DMABUF_SIZE, &appdma);
632
633 if (devpriv->RPSBuf.LogicalBase == NULL) {
634 printk(KERN_ERR "s626_attach: DMA Memory mapping error\n");
635 return -ENOMEM;
636 }
637
638 devpriv->RPSBuf.PhysicalBase = appdma;
639
640 DEBUG
641 ("s626_attach: AllocDMAB RPS Logical=%p, bsize=%d, Physical=0x%x\n",
642 devpriv->RPSBuf.LogicalBase, DMABUF_SIZE,
643 (uint32_t) devpriv->RPSBuf.PhysicalBase);
644
645 devpriv->allocatedBuf++;
646
647 }
648
649 dev->board_ptr = s626_boards;
650 dev->board_name = thisboard->name;
651
652 if (alloc_subdevices(dev, 6) < 0)
653 return -ENOMEM;
654
655 dev->iobase = (unsigned long)devpriv->base_addr;
656 dev->irq = devpriv->pdev->irq;
657
658 /* set up interrupt handler */
659 if (dev->irq == 0) {
660 printk(KERN_ERR " unknown irq (bad)\n");
661 } else {
662 ret = request_irq(dev->irq, s626_irq_handler, IRQF_SHARED,
663 "s626", dev);
664
665 if (ret < 0) {
666 printk(KERN_ERR " irq not available\n");
667 dev->irq = 0;
668 }
669 }
670
671 DEBUG("s626_attach: -- it opts %d,%d --\n",
672 it->options[0], it->options[1]);
673
674 s = dev->subdevices + 0;
675 /* analog input subdevice */
676 dev->read_subdev = s;
677 /* we support single-ended (ground) and differential */
678 s->type = COMEDI_SUBD_AI;
679 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_CMD_READ;
680 s->n_chan = thisboard->ai_chans;
681 s->maxdata = (0xffff >> 2);
682 s->range_table = &s626_range_table;
683 s->len_chanlist = thisboard->ai_chans; /* This is the maximum chanlist
684 length that the board can
685 handle */
686 s->insn_config = s626_ai_insn_config;
687 s->insn_read = s626_ai_insn_read;
688 s->do_cmd = s626_ai_cmd;
689 s->do_cmdtest = s626_ai_cmdtest;
690 s->cancel = s626_ai_cancel;
691
692 s = dev->subdevices + 1;
693 /* analog output subdevice */
694 s->type = COMEDI_SUBD_AO;
695 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
696 s->n_chan = thisboard->ao_chans;
697 s->maxdata = (0x3fff);
698 s->range_table = &range_bipolar10;
699 s->insn_write = s626_ao_winsn;
700 s->insn_read = s626_ao_rinsn;
701
702 s = dev->subdevices + 2;
703 /* digital I/O subdevice */
704 s->type = COMEDI_SUBD_DIO;
705 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
706 s->n_chan = S626_DIO_CHANNELS;
707 s->maxdata = 1;
708 s->io_bits = 0xffff;
709 s->private = &dio_private_A;
710 s->range_table = &range_digital;
711 s->insn_config = s626_dio_insn_config;
712 s->insn_bits = s626_dio_insn_bits;
713
714 s = dev->subdevices + 3;
715 /* digital I/O subdevice */
716 s->type = COMEDI_SUBD_DIO;
717 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
718 s->n_chan = 16;
719 s->maxdata = 1;
720 s->io_bits = 0xffff;
721 s->private = &dio_private_B;
722 s->range_table = &range_digital;
723 s->insn_config = s626_dio_insn_config;
724 s->insn_bits = s626_dio_insn_bits;
725
726 s = dev->subdevices + 4;
727 /* digital I/O subdevice */
728 s->type = COMEDI_SUBD_DIO;
729 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
730 s->n_chan = 16;
731 s->maxdata = 1;
732 s->io_bits = 0xffff;
733 s->private = &dio_private_C;
734 s->range_table = &range_digital;
735 s->insn_config = s626_dio_insn_config;
736 s->insn_bits = s626_dio_insn_bits;
737
738 s = dev->subdevices + 5;
739 /* encoder (counter) subdevice */
740 s->type = COMEDI_SUBD_COUNTER;
741 s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
742 s->n_chan = thisboard->enc_chans;
743 s->private = enc_private_data;
744 s->insn_config = s626_enc_insn_config;
745 s->insn_read = s626_enc_insn_read;
746 s->insn_write = s626_enc_insn_write;
747 s->maxdata = 0xffffff;
748 s->range_table = &range_unknown;
749
750 /* stop ai_command */
751 devpriv->ai_cmd_running = 0;
752
753 if (devpriv->base_addr && (devpriv->allocatedBuf == 2)) {
754 dma_addr_t pPhysBuf;
755 uint16_t chan;
756
757 /* enab DEBI and audio pins, enable I2C interface. */
758 MC_ENABLE(P_MC1, MC1_DEBI | MC1_AUDIO | MC1_I2C);
759 /* Configure DEBI operating mode. */
760 WR7146(P_DEBICFG, DEBI_CFG_SLAVE16 /* Local bus is 16 */
761 /* bits wide. */
762 | (DEBI_TOUT << DEBI_CFG_TOUT_BIT)
763
764 /* Declare DEBI */
765 /* transfer timeout */
766 /* interval. */
767 |DEBI_SWAP /* Set up byte lane */
768 /* steering. */
769 | DEBI_CFG_INTEL); /* Intel-compatible */
770 /* local bus (DEBI */
771 /* never times out). */
772 DEBUG("s626_attach: %d debi init -- %d\n",
773 DEBI_CFG_SLAVE16 | (DEBI_TOUT << DEBI_CFG_TOUT_BIT) |
774 DEBI_SWAP | DEBI_CFG_INTEL,
775 DEBI_CFG_INTEL | DEBI_CFG_TOQ | DEBI_CFG_INCQ |
776 DEBI_CFG_16Q);
777
778 /* DEBI INIT S626 WR7146( P_DEBICFG, DEBI_CFG_INTEL | DEBI_CFG_TOQ */
779 /* | DEBI_CFG_INCQ| DEBI_CFG_16Q); //end */
780
781 /* Paging is disabled. */
782 WR7146(P_DEBIPAGE, DEBI_PAGE_DISABLE); /* Disable MMU paging. */
783
784 /* Init GPIO so that ADC Start* is negated. */
785 WR7146(P_GPIO, GPIO_BASE | GPIO1_HI);
786
787 /* IsBoardRevA is a boolean that indicates whether the board is RevA.
788 *
789 * VERSION 2.01 CHANGE: REV A & B BOARDS NOW SUPPORTED BY DYNAMIC
790 * EEPROM ADDRESS SELECTION. Initialize the I2C interface, which
791 * is used to access the onboard serial EEPROM. The EEPROM's I2C
792 * DeviceAddress is hardwired to a value that is dependent on the
793 * 626 board revision. On all board revisions, the EEPROM stores
794 * TrimDAC calibration constants for analog I/O. On RevB and
795 * higher boards, the DeviceAddress is hardwired to 0 to enable
796 * the EEPROM to also store the PCI SubVendorID and SubDeviceID;
797 * this is the address at which the SAA7146 expects a
798 * configuration EEPROM to reside. On RevA boards, the EEPROM
799 * device address, which is hardwired to 4, prevents the SAA7146
800 * from retrieving PCI sub-IDs, so the SAA7146 uses its built-in
801 * default values, instead.
802 */
803
804 /* devpriv->I2Cards= IsBoardRevA ? 0xA8 : 0xA0; // Set I2C EEPROM */
805 /* DeviceType (0xA0) */
806 /* and DeviceAddress<<1. */
807
808 devpriv->I2CAdrs = 0xA0; /* I2C device address for onboard */
809 /* eeprom(revb) */
810
811 /* Issue an I2C ABORT command to halt any I2C operation in */
812 /* progress and reset BUSY flag. */
813 WR7146(P_I2CSTAT, I2C_CLKSEL | I2C_ABORT);
814 /* Write I2C control: abort any I2C activity. */
815 MC_ENABLE(P_MC2, MC2_UPLD_IIC);
816 /* Invoke command upload */
817 while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0)
818 ;
819 /* and wait for upload to complete. */
820
821 /* Per SAA7146 data sheet, write to STATUS reg twice to
822 * reset all I2C error flags. */
823 for (i = 0; i < 2; i++) {
824 WR7146(P_I2CSTAT, I2C_CLKSEL);
825 /* Write I2C control: reset error flags. */
826 MC_ENABLE(P_MC2, MC2_UPLD_IIC); /* Invoke command upload */
827 while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
828 ;
829 /* and wait for upload to complete. */
830 }
831
832 /* Init audio interface functional attributes: set DAC/ADC
833 * serial clock rates, invert DAC serial clock so that
834 * DAC data setup times are satisfied, enable DAC serial
835 * clock out.
836 */
837
838 WR7146(P_ACON2, ACON2_INIT);
839
840 /* Set up TSL1 slot list, which is used to control the
841 * accumulation of ADC data: RSD1 = shift data in on SD1.
842 * SIB_A1 = store data uint8_t at next available location in
843 * FB BUFFER1 register. */
844 WR7146(P_TSL1, RSD1 | SIB_A1);
845 /* Fetch ADC high data uint8_t. */
846 WR7146(P_TSL1 + 4, RSD1 | SIB_A1 | EOS);
847 /* Fetch ADC low data uint8_t; end of TSL1. */
848
849 /* enab TSL1 slot list so that it executes all the time. */
850 WR7146(P_ACON1, ACON1_ADCSTART);
851
852 /* Initialize RPS registers used for ADC. */
853
854 /* Physical start of RPS program. */
855 WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
856
857 WR7146(P_RPSPAGE1, 0);
858 /* RPS program performs no explicit mem writes. */
859 WR7146(P_RPS1_TOUT, 0); /* Disable RPS timeouts. */
860
861
862 /* PollList = EOPL; // Create a simple polling */
863 /* // list for analog input */
864 /* // channel 0. */
865 /* ResetADC( dev, &PollList ); */
866
867 /* s626_ai_rinsn(dev,dev->subdevices,NULL,data); //( &AdcData ); // */
868 /* //Get initial ADC */
869 /* //value. */
870
871 /* StartVal = data[0]; */
872
873 /* // VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED EXECUTION. */
874 /* // Invoke ADCs until the new ADC value differs from the initial */
875 /* // value or a timeout occurs. The timeout protects against the */
876 /* // possibility that the driver is restarting and the ADC data is a */
877 /* // fixed value resulting from the applied ADC analog input being */
878 /* // unusually quiet or at the rail. */
879
880 /* for ( index = 0; index < 500; index++ ) */
881 /* { */
882 /* s626_ai_rinsn(dev,dev->subdevices,NULL,data); */
883 /* AdcData = data[0]; //ReadADC( &AdcData ); */
884 /* if ( AdcData != StartVal ) */
885 /* break; */
886 /* } */
887
888 /* end initADC */
889
890 /* init the DAC interface */
891
892 /* Init Audio2's output DMAC attributes: burst length = 1
893 * DWORD, threshold = 1 DWORD.
894 */
895 WR7146(P_PCI_BT_A, 0);
896
897 /* Init Audio2's output DMA physical addresses. The protection
898 * address is set to 1 DWORD past the base address so that a
899 * single DWORD will be transferred each time a DMA transfer is
900 * enabled. */
901
902 pPhysBuf =
903 devpriv->ANABuf.PhysicalBase +
904 (DAC_WDMABUF_OS * sizeof(uint32_t));
905
906 WR7146(P_BASEA2_OUT, (uint32_t) pPhysBuf); /* Buffer base adrs. */
907 WR7146(P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t))); /* Protection address. */
908
909 /* Cache Audio2's output DMA buffer logical address. This is
910 * where DAC data is buffered for A2 output DMA transfers. */
911 devpriv->pDacWBuf =
912 (uint32_t *) devpriv->ANABuf.LogicalBase + DAC_WDMABUF_OS;
913
914 /* Audio2's output channels does not use paging. The protection
915 * violation handling bit is set so that the DMAC will
916 * automatically halt and its PCI address pointer will be reset
917 * when the protection address is reached. */
918
919 WR7146(P_PAGEA2_OUT, 8);
920
921 /* Initialize time slot list 2 (TSL2), which is used to control
922 * the clock generation for and serialization of data to be sent
923 * to the DAC devices. Slot 0 is a NOP that is used to trap TSL
924 * execution; this permits other slots to be safely modified
925 * without first turning off the TSL sequencer (which is
926 * apparently impossible to do). Also, SD3 (which is driven by a
927 * pull-up resistor) is shifted in and stored to the MSB of
928 * FB_BUFFER2 to be used as evidence that the slot sequence has
929 * not yet finished executing.
930 */
931
932 SETVECT(0, XSD2 | RSD3 | SIB_A2 | EOS);
933 /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2. */
934
935 /* Initialize slot 1, which is constant. Slot 1 causes a
936 * DWORD to be transferred from audio channel 2's output FIFO
937 * to the FIFO's output buffer so that it can be serialized
938 * and sent to the DAC during subsequent slots. All remaining
939 * slots are dynamically populated as required by the target
940 * DAC device.
941 */
942 SETVECT(1, LF_A2);
943 /* Slot 1: Fetch DWORD from Audio2's output FIFO. */
944
945 /* Start DAC's audio interface (TSL2) running. */
946 WR7146(P_ACON1, ACON1_DACSTART);
947
948 /* end init DAC interface */
949
950 /* Init Trim DACs to calibrated values. Do it twice because the
951 * SAA7146 audio channel does not always reset properly and
952 * sometimes causes the first few TrimDAC writes to malfunction.
953 */
954
955 LoadTrimDACs(dev);
956 LoadTrimDACs(dev); /* Insurance. */
957
958 /* Manually init all gate array hardware in case this is a soft
959 * reset (we have no way of determining whether this is a warm
960 * or cold start). This is necessary because the gate array will
961 * reset only in response to a PCI hard reset; there is no soft
962 * reset function. */
963
964 /* Init all DAC outputs to 0V and init all DAC setpoint and
965 * polarity images.
966 */
967 for (chan = 0; chan < S626_DAC_CHANNELS; chan++)
968 SetDAC(dev, chan, 0);
969
970 /* Init image of WRMISC2 Battery Charger Enabled control bit.
971 * This image is used when the state of the charger control bit,
972 * which has no direct hardware readback mechanism, is queried.
973 */
974 devpriv->ChargeEnabled = 0;
975
976 /* Init image of watchdog timer interval in WRMISC2. This image
977 * maintains the value of the control bits of MISC2 are
978 * continuously reset to zero as long as the WD timer is disabled.
979 */
980 devpriv->WDInterval = 0;
981
982 /* Init Counter Interrupt enab mask for RDMISC2. This mask is
983 * applied against MISC2 when testing to determine which timer
984 * events are requesting interrupt service.
985 */
986 devpriv->CounterIntEnabs = 0;
987
988 /* Init counters. */
989 CountersInit(dev);
990
991 /* Without modifying the state of the Battery Backup enab, disable
992 * the watchdog timer, set DIO channels 0-5 to operate in the
993 * standard DIO (vs. counter overflow) mode, disable the battery
994 * charger, and reset the watchdog interval selector to zero.
995 */
996 WriteMISC2(dev, (uint16_t) (DEBIread(dev,
997 LP_RDMISC2) &
998 MISC2_BATT_ENABLE));
999
1000 /* Initialize the digital I/O subsystem. */
1001 s626_dio_init(dev);
1002
1003 /* enable interrupt test */
1004 /* writel(IRQ_GPIO3 | IRQ_RPS1,devpriv->base_addr+P_IER); */
1005 }
1006
1007 DEBUG("s626_attach: comedi%d s626 attached %04x\n", dev->minor,
1008 (uint32_t) devpriv->base_addr);
1009
1010 return 1;
1011 }
1012
1013 static unsigned int s626_ai_reg_to_uint(int data)
1014 {
1015 unsigned int tempdata;
1016
1017 tempdata = (data >> 18);
1018 if (tempdata & 0x2000)
1019 tempdata &= 0x1fff;
1020 else
1021 tempdata += (1 << 13);
1022
1023 return tempdata;
1024 }
1025
1026 /* static unsigned int s626_uint_to_reg(struct comedi_subdevice *s, int data){ */
1027 /* return 0; */
1028 /* } */
1029
1030 static irqreturn_t s626_irq_handler(int irq, void *d)
1031 {
1032 struct comedi_device *dev = d;
1033 struct comedi_subdevice *s;
1034 struct comedi_cmd *cmd;
1035 struct enc_private *k;
1036 unsigned long flags;
1037 int32_t *readaddr;
1038 uint32_t irqtype, irqstatus;
1039 int i = 0;
1040 short tempdata;
1041 uint8_t group;
1042 uint16_t irqbit;
1043
1044 DEBUG("s626_irq_handler: interrupt request recieved!!!\n");
1045
1046 if (dev->attached == 0)
1047 return IRQ_NONE;
1048 /* lock to avoid race with comedi_poll */
1049 spin_lock_irqsave(&dev->spinlock, flags);
1050
1051 /* save interrupt enable register state */
1052 irqstatus = readl(devpriv->base_addr + P_IER);
1053
1054 /* read interrupt type */
1055 irqtype = readl(devpriv->base_addr + P_ISR);
1056
1057 /* disable master interrupt */
1058 writel(0, devpriv->base_addr + P_IER);
1059
1060 /* clear interrupt */
1061 writel(irqtype, devpriv->base_addr + P_ISR);
1062
1063 /* do somethings */
1064 DEBUG("s626_irq_handler: interrupt type %d\n", irqtype);
1065
1066 switch (irqtype) {
1067 case IRQ_RPS1: /* end_of_scan occurs */
1068
1069 DEBUG("s626_irq_handler: RPS1 irq detected\n");
1070
1071 /* manage ai subdevice */
1072 s = dev->subdevices;
1073 cmd = &(s->async->cmd);
1074
1075 /* Init ptr to DMA buffer that holds new ADC data. We skip the
1076 * first uint16_t in the buffer because it contains junk data from
1077 * the final ADC of the previous poll list scan.
1078 */
1079 readaddr = (int32_t *) devpriv->ANABuf.LogicalBase + 1;
1080
1081 /* get the data and hand it over to comedi */
1082 for (i = 0; i < (s->async->cmd.chanlist_len); i++) {
1083 /* Convert ADC data to 16-bit integer values and copy to application */
1084 /* buffer. */
1085 tempdata = s626_ai_reg_to_uint((int)*readaddr);
1086 readaddr++;
1087
1088 /* put data into read buffer */
1089 /* comedi_buf_put(s->async, tempdata); */
1090 if (cfc_write_to_buffer(s, tempdata) == 0)
1091 printk
1092 ("s626_irq_handler: cfc_write_to_buffer error!\n");
1093
1094 DEBUG("s626_irq_handler: ai channel %d acquired: %d\n",
1095 i, tempdata);
1096 }
1097
1098 /* end of scan occurs */
1099 s->async->events |= COMEDI_CB_EOS;
1100
1101 if (!(devpriv->ai_continous))
1102 devpriv->ai_sample_count--;
1103 if (devpriv->ai_sample_count <= 0) {
1104 devpriv->ai_cmd_running = 0;
1105
1106 /* Stop RPS program. */
1107 MC_DISABLE(P_MC1, MC1_ERPS1);
1108
1109 /* send end of acquisition */
1110 s->async->events |= COMEDI_CB_EOA;
1111
1112 /* disable master interrupt */
1113 irqstatus = 0;
1114 }
1115
1116 if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT) {
1117 DEBUG
1118 ("s626_irq_handler: enable interrupt on dio channel %d\n",
1119 cmd->scan_begin_arg);
1120
1121 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1122
1123 DEBUG("s626_irq_handler: External trigger is set!!!\n");
1124 }
1125 /* tell comedi that data is there */
1126 DEBUG("s626_irq_handler: events %d\n", s->async->events);
1127 comedi_event(dev, s);
1128 break;
1129 case IRQ_GPIO3: /* check dio and conter interrupt */
1130
1131 DEBUG("s626_irq_handler: GPIO3 irq detected\n");
1132
1133 /* manage ai subdevice */
1134 s = dev->subdevices;
1135 cmd = &(s->async->cmd);
1136
1137 /* s626_dio_clear_irq(dev); */
1138
1139 for (group = 0; group < S626_DIO_BANKS; group++) {
1140 irqbit = 0;
1141 /* read interrupt type */
1142 irqbit = DEBIread(dev,
1143 ((struct dio_private *)(dev->
1144 subdevices +
1145 2 +
1146 group)->
1147 private)->RDCapFlg);
1148
1149 /* check if interrupt is generated from dio channels */
1150 if (irqbit) {
1151 s626_dio_reset_irq(dev, group, irqbit);
1152 DEBUG
1153 ("s626_irq_handler: check interrupt on dio group %d %d\n",
1154 group, i);
1155 if (devpriv->ai_cmd_running) {
1156 /* check if interrupt is an ai acquisition start trigger */
1157 if ((irqbit >> (cmd->start_arg -
1158 (16 * group)))
1159 == 1 && cmd->start_src == TRIG_EXT) {
1160 DEBUG
1161 ("s626_irq_handler: Edge capture interrupt recieved from channel %d\n",
1162 cmd->start_arg);
1163
1164 /* Start executing the RPS program. */
1165 MC_ENABLE(P_MC1, MC1_ERPS1);
1166
1167 DEBUG
1168 ("s626_irq_handler: aquisition start triggered!!!\n");
1169
1170 if (cmd->scan_begin_src ==
1171 TRIG_EXT) {
1172 DEBUG
1173 ("s626_ai_cmd: enable interrupt on dio channel %d\n",
1174 cmd->
1175 scan_begin_arg);
1176
1177 s626_dio_set_irq(dev,
1178 cmd->scan_begin_arg);
1179
1180 DEBUG
1181 ("s626_irq_handler: External scan trigger is set!!!\n");
1182 }
1183 }
1184 if ((irqbit >> (cmd->scan_begin_arg -
1185 (16 * group)))
1186 == 1
1187 && cmd->scan_begin_src ==
1188 TRIG_EXT) {
1189 DEBUG
1190 ("s626_irq_handler: Edge capture interrupt recieved from channel %d\n",
1191 cmd->scan_begin_arg);
1192
1193 /* Trigger ADC scan loop start by setting RPS Signal 0. */
1194 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1195
1196 DEBUG
1197 ("s626_irq_handler: scan triggered!!! %d\n",
1198 devpriv->ai_sample_count);
1199 if (cmd->convert_src ==
1200 TRIG_EXT) {
1201
1202 DEBUG
1203 ("s626_ai_cmd: enable interrupt on dio channel %d group %d\n",
1204 cmd->convert_arg -
1205 (16 * group),
1206 group);
1207
1208 devpriv->ai_convert_count
1209 = cmd->chanlist_len;
1210
1211 s626_dio_set_irq(dev,
1212 cmd->convert_arg);
1213
1214 DEBUG
1215 ("s626_irq_handler: External convert trigger is set!!!\n");
1216 }
1217
1218 if (cmd->convert_src ==
1219 TRIG_TIMER) {
1220 k = &encpriv[5];
1221 devpriv->ai_convert_count
1222 = cmd->chanlist_len;
1223 k->SetEnable(dev, k,
1224 CLKENAB_ALWAYS);
1225 }
1226 }
1227 if ((irqbit >> (cmd->convert_arg -
1228 (16 * group)))
1229 == 1
1230 && cmd->convert_src == TRIG_EXT) {
1231 DEBUG
1232 ("s626_irq_handler: Edge capture interrupt recieved from channel %d\n",
1233 cmd->convert_arg);
1234
1235 /* Trigger ADC scan loop start by setting RPS Signal 0. */
1236 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1237
1238 DEBUG
1239 ("s626_irq_handler: adc convert triggered!!!\n");
1240
1241 devpriv->ai_convert_count--;
1242
1243 if (devpriv->ai_convert_count >
1244 0) {
1245
1246 DEBUG
1247 ("s626_ai_cmd: enable interrupt on dio channel %d group %d\n",
1248 cmd->convert_arg -
1249 (16 * group),
1250 group);
1251
1252 s626_dio_set_irq(dev,
1253 cmd->convert_arg);
1254
1255 DEBUG
1256 ("s626_irq_handler: External trigger is set!!!\n");
1257 }
1258 }
1259 }
1260 break;
1261 }
1262 }
1263
1264 /* read interrupt type */
1265 irqbit = DEBIread(dev, LP_RDMISC2);
1266
1267 /* check interrupt on counters */
1268 DEBUG("s626_irq_handler: check counters interrupt %d\n",
1269 irqbit);
1270
1271 if (irqbit & IRQ_COINT1A) {
1272 DEBUG
1273 ("s626_irq_handler: interrupt on counter 1A overflow\n");
1274 k = &encpriv[0];
1275
1276 /* clear interrupt capture flag */
1277 k->ResetCapFlags(dev, k);
1278 }
1279 if (irqbit & IRQ_COINT2A) {
1280 DEBUG
1281 ("s626_irq_handler: interrupt on counter 2A overflow\n");
1282 k = &encpriv[1];
1283
1284 /* clear interrupt capture flag */
1285 k->ResetCapFlags(dev, k);
1286 }
1287 if (irqbit & IRQ_COINT3A) {
1288 DEBUG
1289 ("s626_irq_handler: interrupt on counter 3A overflow\n");
1290 k = &encpriv[2];
1291
1292 /* clear interrupt capture flag */
1293 k->ResetCapFlags(dev, k);
1294 }
1295 if (irqbit & IRQ_COINT1B) {
1296 DEBUG
1297 ("s626_irq_handler: interrupt on counter 1B overflow\n");
1298 k = &encpriv[3];
1299
1300 /* clear interrupt capture flag */
1301 k->ResetCapFlags(dev, k);
1302 }
1303 if (irqbit & IRQ_COINT2B) {
1304 DEBUG
1305 ("s626_irq_handler: interrupt on counter 2B overflow\n");
1306 k = &encpriv[4];
1307
1308 /* clear interrupt capture flag */
1309 k->ResetCapFlags(dev, k);
1310
1311 if (devpriv->ai_convert_count > 0) {
1312 devpriv->ai_convert_count--;
1313 if (devpriv->ai_convert_count == 0)
1314 k->SetEnable(dev, k, CLKENAB_INDEX);
1315
1316 if (cmd->convert_src == TRIG_TIMER) {
1317 DEBUG
1318 ("s626_irq_handler: conver timer trigger!!! %d\n",
1319 devpriv->ai_convert_count);
1320
1321 /* Trigger ADC scan loop start by setting RPS Signal 0. */
1322 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1323 }
1324 }
1325 }
1326 if (irqbit & IRQ_COINT3B) {
1327 DEBUG
1328 ("s626_irq_handler: interrupt on counter 3B overflow\n");
1329 k = &encpriv[5];
1330
1331 /* clear interrupt capture flag */
1332 k->ResetCapFlags(dev, k);
1333
1334 if (cmd->scan_begin_src == TRIG_TIMER) {
1335 DEBUG
1336 ("s626_irq_handler: scan timer trigger!!!\n");
1337
1338 /* Trigger ADC scan loop start by setting RPS Signal 0. */
1339 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1340 }
1341
1342 if (cmd->convert_src == TRIG_TIMER) {
1343 DEBUG
1344 ("s626_irq_handler: convert timer trigger is set\n");
1345 k = &encpriv[4];
1346 devpriv->ai_convert_count = cmd->chanlist_len;
1347 k->SetEnable(dev, k, CLKENAB_ALWAYS);
1348 }
1349 }
1350 }
1351
1352 /* enable interrupt */
1353 writel(irqstatus, devpriv->base_addr + P_IER);
1354
1355 DEBUG("s626_irq_handler: exit interrupt service routine.\n");
1356
1357 spin_unlock_irqrestore(&dev->spinlock, flags);
1358 return IRQ_HANDLED;
1359 }
1360
1361 static int s626_detach(struct comedi_device *dev)
1362 {
1363 if (devpriv) {
1364 /* stop ai_command */
1365 devpriv->ai_cmd_running = 0;
1366
1367 if (devpriv->base_addr) {
1368 /* interrupt mask */
1369 WR7146(P_IER, 0); /* Disable master interrupt. */
1370 WR7146(P_ISR, IRQ_GPIO3 | IRQ_RPS1); /* Clear board's IRQ status flag. */
1371
1372 /* Disable the watchdog timer and battery charger. */
1373 WriteMISC2(dev, 0);
1374
1375 /* Close all interfaces on 7146 device. */
1376 WR7146(P_MC1, MC1_SHUTDOWN);
1377 WR7146(P_ACON1, ACON1_BASE);
1378
1379 CloseDMAB(dev, &devpriv->RPSBuf, DMABUF_SIZE);
1380 CloseDMAB(dev, &devpriv->ANABuf, DMABUF_SIZE);
1381 }
1382
1383 if (dev->irq)
1384 free_irq(dev->irq, dev);
1385
1386 if (devpriv->base_addr)
1387 iounmap(devpriv->base_addr);
1388
1389 if (devpriv->pdev) {
1390 if (devpriv->got_regions)
1391 comedi_pci_disable(devpriv->pdev);
1392 pci_dev_put(devpriv->pdev);
1393 }
1394 }
1395
1396 DEBUG("s626_detach: S626 detached!\n");
1397
1398 return 0;
1399 }
1400
1401 /*
1402 * this functions build the RPS program for hardware driven acquistion
1403 */
1404 void ResetADC(struct comedi_device *dev, uint8_t * ppl)
1405 {
1406 register uint32_t *pRPS;
1407 uint32_t JmpAdrs;
1408 uint16_t i;
1409 uint16_t n;
1410 uint32_t LocalPPL;
1411 struct comedi_cmd *cmd = &(dev->subdevices->async->cmd);
1412
1413 /* Stop RPS program in case it is currently running. */
1414 MC_DISABLE(P_MC1, MC1_ERPS1);
1415
1416 /* Set starting logical address to write RPS commands. */
1417 pRPS = (uint32_t *) devpriv->RPSBuf.LogicalBase;
1418
1419 /* Initialize RPS instruction pointer. */
1420 WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
1421
1422 /* Construct RPS program in RPSBuf DMA buffer */
1423
1424 if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) {
1425 DEBUG("ResetADC: scan_begin pause inserted\n");
1426 /* Wait for Start trigger. */
1427 *pRPS++ = RPS_PAUSE | RPS_SIGADC;
1428 *pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
1429 }
1430
1431 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
1432 /* Write DEBI Write command and address to shadow RAM. */
1433
1434 *pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
1435 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
1436 /* Write DEBI immediate data to shadow RAM: */
1437
1438 *pRPS++ = GSEL_BIPOLAR5V;
1439 /* arbitrary immediate data value. */
1440
1441 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
1442 /* Reset "shadow RAM uploaded" flag. */
1443 *pRPS++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */
1444 *pRPS++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to finish. */
1445
1446 /* Digitize all slots in the poll list. This is implemented as a
1447 * for loop to limit the slot count to 16 in case the application
1448 * forgot to set the EOPL flag in the final slot.
1449 */
1450 for (devpriv->AdcItems = 0; devpriv->AdcItems < 16; devpriv->AdcItems++) {
1451 /* Convert application's poll list item to private board class
1452 * format. Each app poll list item is an uint8_t with form
1453 * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
1454 * +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
1455 */
1456 LocalPPL =
1457 (*ppl << 8) | (*ppl & 0x10 ? GSEL_BIPOLAR5V :
1458 GSEL_BIPOLAR10V);
1459
1460 /* Switch ADC analog gain. */
1461 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2); /* Write DEBI command */
1462 /* and address to */
1463 /* shadow RAM. */
1464 *pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
1465 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2); /* Write DEBI */
1466 /* immediate data to */
1467 /* shadow RAM. */
1468 *pRPS++ = LocalPPL;
1469 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI; /* Reset "shadow RAM uploaded" */
1470 /* flag. */
1471 *pRPS++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */
1472 *pRPS++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to */
1473 /* finish. */
1474
1475 /* Select ADC analog input channel. */
1476 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
1477 /* Write DEBI command and address to shadow RAM. */
1478 *pRPS++ = DEBI_CMD_WRWORD | LP_ISEL;
1479 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
1480 /* Write DEBI immediate data to shadow RAM. */
1481 *pRPS++ = LocalPPL;
1482 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
1483 /* Reset "shadow RAM uploaded" flag. */
1484
1485 *pRPS++ = RPS_UPLOAD | RPS_DEBI;
1486 /* Invoke shadow RAM upload. */
1487
1488 *pRPS++ = RPS_PAUSE | RPS_DEBI;
1489 /* Wait for shadow upload to finish. */
1490
1491 /* Delay at least 10 microseconds for analog input settling.
1492 * Instead of padding with NOPs, we use RPS_JUMP instructions
1493 * here; this allows us to produce a longer delay than is
1494 * possible with NOPs because each RPS_JUMP flushes the RPS'
1495 * instruction prefetch pipeline.
1496 */
1497 JmpAdrs =
1498 (uint32_t) devpriv->RPSBuf.PhysicalBase +
1499 (uint32_t) ((unsigned long)pRPS -
1500 (unsigned long)devpriv->RPSBuf.LogicalBase);
1501 for (i = 0; i < (10 * RPSCLK_PER_US / 2); i++) {
1502 JmpAdrs += 8; /* Repeat to implement time delay: */
1503 *pRPS++ = RPS_JUMP; /* Jump to next RPS instruction. */
1504 *pRPS++ = JmpAdrs;
1505 }
1506
1507 if (cmd != NULL && cmd->convert_src != TRIG_NOW) {
1508 DEBUG("ResetADC: convert pause inserted\n");
1509 /* Wait for Start trigger. */
1510 *pRPS++ = RPS_PAUSE | RPS_SIGADC;
1511 *pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
1512 }
1513 /* Start ADC by pulsing GPIO1. */
1514 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */
1515 *pRPS++ = GPIO_BASE | GPIO1_LO;
1516 *pRPS++ = RPS_NOP;
1517 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1518 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */
1519 *pRPS++ = GPIO_BASE | GPIO1_HI;
1520
1521 /* Wait for ADC to complete (GPIO2 is asserted high when ADC not
1522 * busy) and for data from previous conversion to shift into FB
1523 * BUFFER 1 register.
1524 */
1525 *pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
1526
1527 /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
1528 *pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2);
1529 *pRPS++ =
1530 (uint32_t) devpriv->ANABuf.PhysicalBase +
1531 (devpriv->AdcItems << 2);
1532
1533 /* If this slot's EndOfPollList flag is set, all channels have */
1534 /* now been processed. */
1535 if (*ppl++ & EOPL) {
1536 devpriv->AdcItems++; /* Adjust poll list item count. */
1537 break; /* Exit poll list processing loop. */
1538 }
1539 }
1540 DEBUG("ResetADC: ADC items %d\n", devpriv->AdcItems);
1541
1542 /* VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US. Allow the
1543 * ADC to stabilize for 2 microseconds before starting the final
1544 * (dummy) conversion. This delay is necessary to allow sufficient
1545 * time between last conversion finished and the start of the dummy
1546 * conversion. Without this delay, the last conversion's data value
1547 * is sometimes set to the previous conversion's data value.
1548 */
1549 for (n = 0; n < (2 * RPSCLK_PER_US); n++)
1550 *pRPS++ = RPS_NOP;
1551
1552 /* Start a dummy conversion to cause the data from the last
1553 * conversion of interest to be shifted in.
1554 */
1555 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */
1556 *pRPS++ = GPIO_BASE | GPIO1_LO;
1557 *pRPS++ = RPS_NOP;
1558 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1559 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */
1560 *pRPS++ = GPIO_BASE | GPIO1_HI;
1561
1562 /* Wait for the data from the last conversion of interest to arrive
1563 * in FB BUFFER 1 register.
1564 */
1565 *pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
1566
1567 /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */
1568 *pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2); /* */
1569 *pRPS++ =
1570 (uint32_t) devpriv->ANABuf.PhysicalBase + (devpriv->AdcItems << 2);
1571
1572 /* Indicate ADC scan loop is finished. */
1573 /* *pRPS++= RPS_CLRSIGNAL | RPS_SIGADC ; // Signal ReadADC() that scan is done. */
1574
1575 /* invoke interrupt */
1576 if (devpriv->ai_cmd_running == 1) {
1577 DEBUG("ResetADC: insert irq in ADC RPS task\n");
1578 *pRPS++ = RPS_IRQ;
1579 }
1580 /* Restart RPS program at its beginning. */
1581 *pRPS++ = RPS_JUMP; /* Branch to start of RPS program. */
1582 *pRPS++ = (uint32_t) devpriv->RPSBuf.PhysicalBase;
1583
1584 /* End of RPS program build */
1585 }
1586
1587 /* TO COMPLETE, IF NECESSARY */
1588 static int s626_ai_insn_config(struct comedi_device *dev,
1589 struct comedi_subdevice *s,
1590 struct comedi_insn *insn, unsigned int *data)
1591 {
1592
1593 return -EINVAL;
1594 }
1595
1596 /* static int s626_ai_rinsn(struct comedi_device *dev,struct comedi_subdevice *s,struct comedi_insn *insn,unsigned int *data) */
1597 /* { */
1598 /* register uint8_t i; */
1599 /* register int32_t *readaddr; */
1600
1601 /* DEBUG("as626_ai_rinsn: ai_rinsn enter\n"); */
1602
1603 /* Trigger ADC scan loop start by setting RPS Signal 0. */
1604 /* MC_ENABLE( P_MC2, MC2_ADC_RPS ); */
1605
1606 /* Wait until ADC scan loop is finished (RPS Signal 0 reset). */
1607 /* while ( MC_TEST( P_MC2, MC2_ADC_RPS ) ); */
1608
1609 /* Init ptr to DMA buffer that holds new ADC data. We skip the
1610 * first uint16_t in the buffer because it contains junk data from
1611 * the final ADC of the previous poll list scan.
1612 */
1613 /* readaddr = (uint32_t *)devpriv->ANABuf.LogicalBase + 1; */
1614
1615 /* Convert ADC data to 16-bit integer values and copy to application buffer. */
1616 /* for ( i = 0; i < devpriv->AdcItems; i++ ) { */
1617 /* *data = s626_ai_reg_to_uint( *readaddr++ ); */
1618 /* DEBUG("s626_ai_rinsn: data %d\n",*data); */
1619 /* data++; */
1620 /* } */
1621
1622 /* DEBUG("s626_ai_rinsn: ai_rinsn escape\n"); */
1623 /* return i; */
1624 /* } */
1625
1626 static int s626_ai_insn_read(struct comedi_device *dev,
1627 struct comedi_subdevice *s,
1628 struct comedi_insn *insn, unsigned int *data)
1629 {
1630 uint16_t chan = CR_CHAN(insn->chanspec);
1631 uint16_t range = CR_RANGE(insn->chanspec);
1632 uint16_t AdcSpec = 0;
1633 uint32_t GpioImage;
1634 int n;
1635
1636 /* interrupt call test */
1637 /* writel(IRQ_GPIO3,devpriv->base_addr+P_PSR); */
1638 /* Writing a logical 1 into any of the RPS_PSR bits causes the
1639 * corresponding interrupt to be generated if enabled
1640 */
1641
1642 DEBUG("s626_ai_insn_read: entering\n");
1643
1644 /* Convert application's ADC specification into form
1645 * appropriate for register programming.
1646 */
1647 if (range == 0)
1648 AdcSpec = (chan << 8) | (GSEL_BIPOLAR5V);
1649 else
1650 AdcSpec = (chan << 8) | (GSEL_BIPOLAR10V);
1651
1652 /* Switch ADC analog gain. */
1653 DEBIwrite(dev, LP_GSEL, AdcSpec); /* Set gain. */
1654
1655 /* Select ADC analog input channel. */
1656 DEBIwrite(dev, LP_ISEL, AdcSpec); /* Select channel. */
1657
1658 for (n = 0; n < insn->n; n++) {
1659
1660 /* Delay 10 microseconds for analog input settling. */
1661 udelay(10);
1662
1663 /* Start ADC by pulsing GPIO1 low. */
1664 GpioImage = RR7146(P_GPIO);
1665 /* Assert ADC Start command */
1666 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1667 /* and stretch it out. */
1668 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1669 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1670 /* Negate ADC Start command. */
1671 WR7146(P_GPIO, GpioImage | GPIO1_HI);
1672
1673 /* Wait for ADC to complete (GPIO2 is asserted high when */
1674 /* ADC not busy) and for data from previous conversion to */
1675 /* shift into FB BUFFER 1 register. */
1676
1677 /* Wait for ADC done. */
1678 while (!(RR7146(P_PSR) & PSR_GPIO2))
1679 ;
1680
1681 /* Fetch ADC data. */
1682 if (n != 0)
1683 data[n - 1] = s626_ai_reg_to_uint(RR7146(P_FB_BUFFER1));
1684
1685 /* Allow the ADC to stabilize for 4 microseconds before
1686 * starting the next (final) conversion. This delay is
1687 * necessary to allow sufficient time between last
1688 * conversion finished and the start of the next
1689 * conversion. Without this delay, the last conversion's
1690 * data value is sometimes set to the previous
1691 * conversion's data value.
1692 */
1693 udelay(4);
1694 }
1695
1696 /* Start a dummy conversion to cause the data from the
1697 * previous conversion to be shifted in. */
1698 GpioImage = RR7146(P_GPIO);
1699
1700 /* Assert ADC Start command */
1701 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1702 /* and stretch it out. */
1703 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1704 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1705 /* Negate ADC Start command. */
1706 WR7146(P_GPIO, GpioImage | GPIO1_HI);
1707
1708 /* Wait for the data to arrive in FB BUFFER 1 register. */
1709
1710 /* Wait for ADC done. */
1711 while (!(RR7146(P_PSR) & PSR_GPIO2))
1712 ;
1713
1714 /* Fetch ADC data from audio interface's input shift register. */
1715
1716 /* Fetch ADC data. */
1717 if (n != 0)
1718 data[n - 1] = s626_ai_reg_to_uint(RR7146(P_FB_BUFFER1));
1719
1720 DEBUG("s626_ai_insn_read: samples %d, data %d\n", n, data[n - 1]);
1721
1722 return n;
1723 }
1724
1725 static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd)
1726 {
1727
1728 int n;
1729
1730 for (n = 0; n < cmd->chanlist_len; n++) {
1731 if (CR_RANGE((cmd->chanlist)[n]) == 0)
1732 ppl[n] = (CR_CHAN((cmd->chanlist)[n])) | (RANGE_5V);
1733 else
1734 ppl[n] = (CR_CHAN((cmd->chanlist)[n])) | (RANGE_10V);
1735 }
1736 if (n != 0)
1737 ppl[n - 1] |= EOPL;
1738
1739 return n;
1740 }
1741
1742 static int s626_ai_inttrig(struct comedi_device *dev,
1743 struct comedi_subdevice *s, unsigned int trignum)
1744 {
1745 if (trignum != 0)
1746 return -EINVAL;
1747
1748 DEBUG("s626_ai_inttrig: trigger adc start...");
1749
1750 /* Start executing the RPS program. */
1751 MC_ENABLE(P_MC1, MC1_ERPS1);
1752
1753 s->async->inttrig = NULL;
1754
1755 DEBUG(" done\n");
1756
1757 return 1;
1758 }
1759
1760 /* TO COMPLETE */
1761 static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1762 {
1763
1764 uint8_t ppl[16];
1765 struct comedi_cmd *cmd = &s->async->cmd;
1766 struct enc_private *k;
1767 int tick;
1768
1769 DEBUG("s626_ai_cmd: entering command function\n");
1770
1771 if (devpriv->ai_cmd_running) {
1772 printk(KERN_ERR "s626_ai_cmd: Another ai_cmd is running %d\n",
1773 dev->minor);
1774 return -EBUSY;
1775 }
1776 /* disable interrupt */
1777 writel(0, devpriv->base_addr + P_IER);
1778
1779 /* clear interrupt request */
1780 writel(IRQ_RPS1 | IRQ_GPIO3, devpriv->base_addr + P_ISR);
1781
1782 /* clear any pending interrupt */
1783 s626_dio_clear_irq(dev);
1784 /* s626_enc_clear_irq(dev); */
1785
1786 /* reset ai_cmd_running flag */
1787 devpriv->ai_cmd_running = 0;
1788
1789 /* test if cmd is valid */
1790 if (cmd == NULL) {
1791 DEBUG("s626_ai_cmd: NULL command\n");
1792 return -EINVAL;
1793 } else {
1794 DEBUG("s626_ai_cmd: command recieved!!!\n");
1795 }
1796
1797 if (dev->irq == 0) {
1798 comedi_error(dev,
1799 "s626_ai_cmd: cannot run command without an irq");
1800 return -EIO;
1801 }
1802
1803 s626_ai_load_polllist(ppl, cmd);
1804 devpriv->ai_cmd_running = 1;
1805 devpriv->ai_convert_count = 0;
1806
1807 switch (cmd->scan_begin_src) {
1808 case TRIG_FOLLOW:
1809 break;
1810 case TRIG_TIMER:
1811 /* set a conter to generate adc trigger at scan_begin_arg interval */
1812 k = &encpriv[5];
1813 tick = s626_ns_to_timer((int *)&cmd->scan_begin_arg,
1814 cmd->flags & TRIG_ROUND_MASK);
1815
1816 /* load timer value and enable interrupt */
1817 s626_timer_load(dev, k, tick);
1818 k->SetEnable(dev, k, CLKENAB_ALWAYS);
1819
1820 DEBUG("s626_ai_cmd: scan trigger timer is set with value %d\n",
1821 tick);
1822
1823 break;
1824 case TRIG_EXT:
1825 /* set the digital line and interrupt for scan trigger */
1826 if (cmd->start_src != TRIG_EXT)
1827 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1828
1829 DEBUG("s626_ai_cmd: External scan trigger is set!!!\n");
1830
1831 break;
1832 }
1833
1834 switch (cmd->convert_src) {
1835 case TRIG_NOW:
1836 break;
1837 case TRIG_TIMER:
1838 /* set a conter to generate adc trigger at convert_arg interval */
1839 k = &encpriv[4];
1840 tick = s626_ns_to_timer((int *)&cmd->convert_arg,
1841 cmd->flags & TRIG_ROUND_MASK);
1842
1843 /* load timer value and enable interrupt */
1844 s626_timer_load(dev, k, tick);
1845 k->SetEnable(dev, k, CLKENAB_INDEX);
1846
1847 DEBUG
1848 ("s626_ai_cmd: convert trigger timer is set with value %d\n",
1849 tick);
1850 break;
1851 case TRIG_EXT:
1852 /* set the digital line and interrupt for convert trigger */
1853 if (cmd->scan_begin_src != TRIG_EXT
1854 && cmd->start_src == TRIG_EXT)
1855 s626_dio_set_irq(dev, cmd->convert_arg);
1856
1857 DEBUG("s626_ai_cmd: External convert trigger is set!!!\n");
1858
1859 break;
1860 }
1861
1862 switch (cmd->stop_src) {
1863 case TRIG_COUNT:
1864 /* data arrives as one packet */
1865 devpriv->ai_sample_count = cmd->stop_arg;
1866 devpriv->ai_continous = 0;
1867 break;
1868 case TRIG_NONE:
1869 /* continous aquisition */
1870 devpriv->ai_continous = 1;
1871 devpriv->ai_sample_count = 0;
1872 break;
1873 }
1874
1875 ResetADC(dev, ppl);
1876
1877 switch (cmd->start_src) {
1878 case TRIG_NOW:
1879 /* Trigger ADC scan loop start by setting RPS Signal 0. */
1880 /* MC_ENABLE( P_MC2, MC2_ADC_RPS ); */
1881
1882 /* Start executing the RPS program. */
1883 MC_ENABLE(P_MC1, MC1_ERPS1);
1884
1885 DEBUG("s626_ai_cmd: ADC triggered\n");
1886 s->async->inttrig = NULL;
1887 break;
1888 case TRIG_EXT:
1889 /* configure DIO channel for acquisition trigger */
1890 s626_dio_set_irq(dev, cmd->start_arg);
1891
1892 DEBUG("s626_ai_cmd: External start trigger is set!!!\n");
1893
1894 s->async->inttrig = NULL;
1895 break;
1896 case TRIG_INT:
1897 s->async->inttrig = s626_ai_inttrig;
1898 break;
1899 }
1900
1901 /* enable interrupt */
1902 writel(IRQ_GPIO3 | IRQ_RPS1, devpriv->base_addr + P_IER);
1903
1904 DEBUG("s626_ai_cmd: command function terminated\n");
1905
1906 return 0;
1907 }
1908
1909 static int s626_ai_cmdtest(struct comedi_device *dev,
1910 struct comedi_subdevice *s, struct comedi_cmd *cmd)
1911 {
1912 int err = 0;
1913 int tmp;
1914
1915 /* cmdtest tests a particular command to see if it is valid. Using
1916 * the cmdtest ioctl, a user can create a valid cmd and then have it
1917 * executes by the cmd ioctl.
1918 *
1919 * cmdtest returns 1,2,3,4 or 0, depending on which tests the
1920 * command passes. */
1921
1922 /* step 1: make sure trigger sources are trivially valid */
1923
1924 tmp = cmd->start_src;
1925 cmd->start_src &= TRIG_NOW | TRIG_INT | TRIG_EXT;
1926 if (!cmd->start_src || tmp != cmd->start_src)
1927 err++;
1928
1929 tmp = cmd->scan_begin_src;
1930 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW;
1931 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
1932 err++;
1933
1934 tmp = cmd->convert_src;
1935 cmd->convert_src &= TRIG_TIMER | TRIG_EXT | TRIG_NOW;
1936 if (!cmd->convert_src || tmp != cmd->convert_src)
1937 err++;
1938
1939 tmp = cmd->scan_end_src;
1940 cmd->scan_end_src &= TRIG_COUNT;
1941 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
1942 err++;
1943
1944 tmp = cmd->stop_src;
1945 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
1946 if (!cmd->stop_src || tmp != cmd->stop_src)
1947 err++;
1948
1949 if (err)
1950 return 1;
1951
1952 /* step 2: make sure trigger sources are unique and mutually
1953 compatible */
1954
1955 /* note that mutual compatibility is not an issue here */
1956 if (cmd->scan_begin_src != TRIG_TIMER &&
1957 cmd->scan_begin_src != TRIG_EXT
1958 && cmd->scan_begin_src != TRIG_FOLLOW)
1959 err++;
1960 if (cmd->convert_src != TRIG_TIMER &&
1961 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW)
1962 err++;
1963 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
1964 err++;
1965
1966 if (err)
1967 return 2;
1968
1969 /* step 3: make sure arguments are trivially compatible */
1970
1971 if (cmd->start_src != TRIG_EXT && cmd->start_arg != 0) {
1972 cmd->start_arg = 0;
1973 err++;
1974 }
1975
1976 if (cmd->start_src == TRIG_EXT && cmd->start_arg > 39) {
1977 cmd->start_arg = 39;
1978 err++;
1979 }
1980
1981 if (cmd->scan_begin_src == TRIG_EXT && cmd->scan_begin_arg > 39) {
1982 cmd->scan_begin_arg = 39;
1983 err++;
1984 }
1985
1986 if (cmd->convert_src == TRIG_EXT && cmd->convert_arg > 39) {
1987 cmd->convert_arg = 39;
1988 err++;
1989 }
1990 #define MAX_SPEED 200000 /* in nanoseconds */
1991 #define MIN_SPEED 2000000000 /* in nanoseconds */
1992
1993 if (cmd->scan_begin_src == TRIG_TIMER) {
1994 if (cmd->scan_begin_arg < MAX_SPEED) {
1995 cmd->scan_begin_arg = MAX_SPEED;
1996 err++;
1997 }
1998 if (cmd->scan_begin_arg > MIN_SPEED) {
1999 cmd->scan_begin_arg = MIN_SPEED;
2000 err++;
2001 }
2002 } else {
2003 /* external trigger */
2004 /* should be level/edge, hi/lo specification here */
2005 /* should specify multiple external triggers */
2006 /* if(cmd->scan_begin_arg>9){ */
2007 /* cmd->scan_begin_arg=9; */
2008 /* err++; */
2009 /* } */
2010 }
2011 if (cmd->convert_src == TRIG_TIMER) {
2012 if (cmd->convert_arg < MAX_SPEED) {
2013 cmd->convert_arg = MAX_SPEED;
2014 err++;
2015 }
2016 if (cmd->convert_arg > MIN_SPEED) {
2017 cmd->convert_arg = MIN_SPEED;
2018 err++;
2019 }
2020 } else {
2021 /* external trigger */
2022 /* see above */
2023 /* if(cmd->convert_arg>9){ */
2024 /* cmd->convert_arg=9; */
2025 /* err++; */
2026 /* } */
2027 }
2028
2029 if (cmd->scan_end_arg != cmd->chanlist_len) {
2030 cmd->scan_end_arg = cmd->chanlist_len;
2031 err++;
2032 }
2033 if (cmd->stop_src == TRIG_COUNT) {
2034 if (cmd->stop_arg > 0x00ffffff) {
2035 cmd->stop_arg = 0x00ffffff;
2036 err++;
2037 }
2038 } else {
2039 /* TRIG_NONE */
2040 if (cmd->stop_arg != 0) {
2041 cmd->stop_arg = 0;
2042 err++;
2043 }
2044 }
2045
2046 if (err)
2047 return 3;
2048
2049 /* step 4: fix up any arguments */
2050
2051 if (cmd->scan_begin_src == TRIG_TIMER) {
2052 tmp = cmd->scan_begin_arg;
2053 s626_ns_to_timer((int *)&cmd->scan_begin_arg,
2054 cmd->flags & TRIG_ROUND_MASK);
2055 if (tmp != cmd->scan_begin_arg)
2056 err++;
2057 }
2058 if (cmd->convert_src == TRIG_TIMER) {
2059 tmp = cmd->convert_arg;
2060 s626_ns_to_timer((int *)&cmd->convert_arg,
2061 cmd->flags & TRIG_ROUND_MASK);
2062 if (tmp != cmd->convert_arg)
2063 err++;
2064 if (cmd->scan_begin_src == TRIG_TIMER &&
2065 cmd->scan_begin_arg <
2066 cmd->convert_arg * cmd->scan_end_arg) {
2067 cmd->scan_begin_arg =
2068 cmd->convert_arg * cmd->scan_end_arg;
2069 err++;
2070 }
2071 }
2072
2073 if (err)
2074 return 4;
2075
2076 return 0;
2077 }
2078
2079 static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
2080 {
2081 /* Stop RPS program in case it is currently running. */
2082 MC_DISABLE(P_MC1, MC1_ERPS1);
2083
2084 /* disable master interrupt */
2085 writel(0, devpriv->base_addr + P_IER);
2086
2087 devpriv->ai_cmd_running = 0;
2088
2089 return 0;
2090 }
2091
2092 /* This function doesn't require a particular form, this is just what
2093 * happens to be used in some of the drivers. It should convert ns
2094 * nanoseconds to a counter value suitable for programming the device.
2095 * Also, it should adjust ns so that it cooresponds to the actual time
2096 * that the device will use. */
2097 static int s626_ns_to_timer(int *nanosec, int round_mode)
2098 {
2099 int divider, base;
2100
2101 base = 500; /* 2MHz internal clock */
2102
2103 switch (round_mode) {
2104 case TRIG_ROUND_NEAREST:
2105 default:
2106 divider = (*nanosec + base / 2) / base;
2107 break;
2108 case TRIG_ROUND_DOWN:
2109 divider = (*nanosec) / base;
2110 break;
2111 case TRIG_ROUND_UP:
2112 divider = (*nanosec + base - 1) / base;
2113 break;
2114 }
2115
2116 *nanosec = base * divider;
2117 return divider - 1;
2118 }
2119
2120 static int s626_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
2121 struct comedi_insn *insn, unsigned int *data)
2122 {
2123
2124 int i;
2125 uint16_t chan = CR_CHAN(insn->chanspec);
2126 int16_t dacdata;
2127
2128 for (i = 0; i < insn->n; i++) {
2129 dacdata = (int16_t) data[i];
2130 devpriv->ao_readback[CR_CHAN(insn->chanspec)] = data[i];
2131 dacdata -= (0x1fff);
2132
2133 SetDAC(dev, chan, dacdata);
2134 }
2135
2136 return i;
2137 }
2138
2139 static int s626_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
2140 struct comedi_insn *insn, unsigned int *data)
2141 {
2142 int i;
2143
2144 for (i = 0; i < insn->n; i++)
2145 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
2146
2147 return i;
2148 }
2149
2150 /* *************** DIGITAL I/O FUNCTIONS ***************
2151 * All DIO functions address a group of DIO channels by means of
2152 * "group" argument. group may be 0, 1 or 2, which correspond to DIO
2153 * ports A, B and C, respectively.
2154 */
2155
2156 static void s626_dio_init(struct comedi_device *dev)
2157 {
2158 uint16_t group;
2159 struct comedi_subdevice *s;
2160
2161 /* Prepare to treat writes to WRCapSel as capture disables. */
2162 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
2163
2164 /* For each group of sixteen channels ... */
2165 for (group = 0; group < S626_DIO_BANKS; group++) {
2166 s = dev->subdevices + 2 + group;
2167 DEBIwrite(dev, diopriv->WRIntSel, 0); /* Disable all interrupts. */
2168 DEBIwrite(dev, diopriv->WRCapSel, 0xFFFF); /* Disable all event */
2169 /* captures. */
2170 DEBIwrite(dev, diopriv->WREdgSel, 0); /* Init all DIOs to */
2171 /* default edge */
2172 /* polarity. */
2173 DEBIwrite(dev, diopriv->WRDOut, 0); /* Program all outputs */
2174 /* to inactive state. */
2175 }
2176 DEBUG("s626_dio_init: DIO initialized\n");
2177 }
2178
2179 /* DIO devices are slightly special. Although it is possible to
2180 * implement the insn_read/insn_write interface, it is much more
2181 * useful to applications if you implement the insn_bits interface.
2182 * This allows packed reading/writing of the DIO channels. The comedi
2183 * core can convert between insn_bits and insn_read/write */
2184
2185 static int s626_dio_insn_bits(struct comedi_device *dev,
2186 struct comedi_subdevice *s,
2187 struct comedi_insn *insn, unsigned int *data)
2188 {
2189
2190 /* Length of data must be 2 (mask and new data, see below) */
2191 if (insn->n == 0)
2192 return 0;
2193
2194 if (insn->n != 2) {
2195 printk
2196 ("comedi%d: s626: s626_dio_insn_bits(): Invalid instruction length\n",
2197 dev->minor);
2198 return -EINVAL;
2199 }
2200
2201 /*
2202 * The insn data consists of a mask in data[0] and the new data in
2203 * data[1]. The mask defines which bits we are concerning about.
2204 * The new data must be anded with the mask. Each channel
2205 * corresponds to a bit.
2206 */
2207 if (data[0]) {
2208 /* Check if requested ports are configured for output */
2209 if ((s->io_bits & data[0]) != data[0])
2210 return -EIO;
2211
2212 s->state &= ~data[0];
2213 s->state |= data[0] & data[1];
2214
2215 /* Write out the new digital output lines */
2216
2217 DEBIwrite(dev, diopriv->WRDOut, s->state);
2218 }
2219 data[1] = DEBIread(dev, diopriv->RDDIn);
2220
2221 return 2;
2222 }
2223
2224 static int s626_dio_insn_config(struct comedi_device *dev,
2225 struct comedi_subdevice *s,
2226 struct comedi_insn *insn, unsigned int *data)
2227 {
2228
2229 switch (data[0]) {
2230 case INSN_CONFIG_DIO_QUERY:
2231 data[1] =
2232 (s->
2233 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
2234 COMEDI_INPUT;
2235 return insn->n;
2236 break;
2237 case COMEDI_INPUT:
2238 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
2239 break;
2240 case COMEDI_OUTPUT:
2241 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
2242 break;
2243 default:
2244 return -EINVAL;
2245 break;
2246 }
2247 DEBIwrite(dev, diopriv->WRDOut, s->io_bits);
2248
2249 return 1;
2250 }
2251
2252 static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan)
2253 {
2254 unsigned int group;
2255 unsigned int bitmask;
2256 unsigned int status;
2257
2258 /* select dio bank */
2259 group = chan / 16;
2260 bitmask = 1 << (chan - (16 * group));
2261 DEBUG("s626_dio_set_irq: enable interrupt on dio channel %d group %d\n",
2262 chan - (16 * group), group);
2263
2264 /* set channel to capture positive edge */
2265 status = DEBIread(dev,
2266 ((struct dio_private *)(dev->subdevices + 2 +
2267 group)->private)->RDEdgSel);
2268 DEBIwrite(dev,
2269 ((struct dio_private *)(dev->subdevices + 2 +
2270 group)->private)->WREdgSel,
2271 bitmask | status);
2272
2273 /* enable interrupt on selected channel */
2274 status = DEBIread(dev,
2275 ((struct dio_private *)(dev->subdevices + 2 +
2276 group)->private)->RDIntSel);
2277 DEBIwrite(dev,
2278 ((struct dio_private *)(dev->subdevices + 2 +
2279 group)->private)->WRIntSel,
2280 bitmask | status);
2281
2282 /* enable edge capture write command */
2283 DEBIwrite(dev, LP_MISC1, MISC1_EDCAP);
2284
2285 /* enable edge capture on selected channel */
2286 status = DEBIread(dev,
2287 ((struct dio_private *)(dev->subdevices + 2 +
2288 group)->private)->RDCapSel);
2289 DEBIwrite(dev,
2290 ((struct dio_private *)(dev->subdevices + 2 +
2291 group)->private)->WRCapSel,
2292 bitmask | status);
2293
2294 return 0;
2295 }
2296
2297 static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group,
2298 unsigned int mask)
2299 {
2300 DEBUG
2301 ("s626_dio_reset_irq: disable interrupt on dio channel %d group %d\n",
2302 mask, group);
2303
2304 /* disable edge capture write command */
2305 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
2306
2307 /* enable edge capture on selected channel */
2308 DEBIwrite(dev,
2309 ((struct dio_private *)(dev->subdevices + 2 +
2310 group)->private)->WRCapSel, mask);
2311
2312 return 0;
2313 }
2314
2315 static int s626_dio_clear_irq(struct comedi_device *dev)
2316 {
2317 unsigned int group;
2318
2319 /* disable edge capture write command */
2320 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
2321
2322 for (group = 0; group < S626_DIO_BANKS; group++) {
2323 /* clear pending events and interrupt */
2324 DEBIwrite(dev,
2325 ((struct dio_private *)(dev->subdevices + 2 +
2326 group)->private)->WRCapSel,
2327 0xffff);
2328 }
2329
2330 return 0;
2331 }
2332
2333 /* Now this function initializes the value of the counter (data[0])
2334 and set the subdevice. To complete with trigger and interrupt
2335 configuration */
2336 static int s626_enc_insn_config(struct comedi_device *dev,
2337 struct comedi_subdevice *s,
2338 struct comedi_insn *insn, unsigned int *data)
2339 {
2340 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
2341 /* index. */
2342 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
2343 (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is Counter. */
2344 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
2345 /* ( CNTDIR_UP << BF_CLKPOL ) | // Count direction is Down. */
2346 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
2347 (CLKENAB_INDEX << BF_CLKENAB);
2348 /* uint16_t DisableIntSrc=TRUE; */
2349 /* uint32_t Preloadvalue; //Counter initial value */
2350 uint16_t valueSrclatch = LATCHSRC_AB_READ;
2351 uint16_t enab = CLKENAB_ALWAYS;
2352 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
2353
2354 DEBUG("s626_enc_insn_config: encoder config\n");
2355
2356 /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */
2357
2358 k->SetMode(dev, k, Setup, TRUE);
2359 Preload(dev, k, *(insn->data));
2360 k->PulseIndex(dev, k);
2361 SetLatchSource(dev, k, valueSrclatch);
2362 k->SetEnable(dev, k, (uint16_t) (enab != 0));
2363
2364 return insn->n;
2365 }
2366
2367 static int s626_enc_insn_read(struct comedi_device *dev,
2368 struct comedi_subdevice *s,
2369 struct comedi_insn *insn, unsigned int *data)
2370 {
2371
2372 int n;
2373 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
2374
2375 DEBUG("s626_enc_insn_read: encoder read channel %d\n",
2376 CR_CHAN(insn->chanspec));
2377
2378 for (n = 0; n < insn->n; n++)
2379 data[n] = ReadLatch(dev, k);
2380
2381 DEBUG("s626_enc_insn_read: encoder sample %d\n", data[n]);
2382
2383 return n;
2384 }
2385
2386 static int s626_enc_insn_write(struct comedi_device *dev,
2387 struct comedi_subdevice *s,
2388 struct comedi_insn *insn, unsigned int *data)
2389 {
2390
2391 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
2392
2393 DEBUG("s626_enc_insn_write: encoder write channel %d\n",
2394 CR_CHAN(insn->chanspec));
2395
2396 /* Set the preload register */
2397 Preload(dev, k, data[0]);
2398
2399 /* Software index pulse forces the preload register to load */
2400 /* into the counter */
2401 k->SetLoadTrig(dev, k, 0);
2402 k->PulseIndex(dev, k);
2403 k->SetLoadTrig(dev, k, 2);
2404
2405 DEBUG("s626_enc_insn_write: End encoder write\n");
2406
2407 return 1;
2408 }
2409
2410 static void s626_timer_load(struct comedi_device *dev, struct enc_private *k,
2411 int tick)
2412 {
2413 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
2414 /* index. */
2415 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
2416 (CLKSRC_TIMER << BF_CLKSRC) | /* Operating mode is Timer. */
2417 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
2418 (CNTDIR_DOWN << BF_CLKPOL) | /* Count direction is Down. */
2419 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
2420 (CLKENAB_INDEX << BF_CLKENAB);
2421 uint16_t valueSrclatch = LATCHSRC_A_INDXA;
2422 /* uint16_t enab=CLKENAB_ALWAYS; */
2423
2424 k->SetMode(dev, k, Setup, FALSE);
2425
2426 /* Set the preload register */
2427 Preload(dev, k, tick);
2428
2429 /* Software index pulse forces the preload register to load */
2430 /* into the counter */
2431 k->SetLoadTrig(dev, k, 0);
2432 k->PulseIndex(dev, k);
2433
2434 /* set reload on counter overflow */
2435 k->SetLoadTrig(dev, k, 1);
2436
2437 /* set interrupt on overflow */
2438 k->SetIntSrc(dev, k, INTSRC_OVER);
2439
2440 SetLatchSource(dev, k, valueSrclatch);
2441 /* k->SetEnable(dev,k,(uint16_t)(enab != 0)); */
2442 }
2443
2444 /* *********** DAC FUNCTIONS *********** */
2445
2446 /* Slot 0 base settings. */
2447 #define VECT0 (XSD2 | RSD3 | SIB_A2)
2448 /* Slot 0 always shifts in 0xFF and store it to FB_BUFFER2. */
2449
2450 /* TrimDac LogicalChan-to-PhysicalChan mapping table. */
2451 static uint8_t trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };
2452
2453 /* TrimDac LogicalChan-to-EepromAdrs mapping table. */
2454 static uint8_t trimadrs[] = { 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63 };
2455
2456 static void LoadTrimDACs(struct comedi_device *dev)
2457 {
2458 register uint8_t i;
2459
2460 /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */
2461 for (i = 0; i < ARRAY_SIZE(trimchan); i++)
2462 WriteTrimDAC(dev, i, I2Cread(dev, trimadrs[i]));
2463 }
2464
2465 static void WriteTrimDAC(struct comedi_device *dev, uint8_t LogicalChan,
2466 uint8_t DacData)
2467 {
2468 uint32_t chan;
2469
2470 /* Save the new setpoint in case the application needs to read it back later. */
2471 devpriv->TrimSetpoint[LogicalChan] = (uint8_t) DacData;
2472
2473 /* Map logical channel number to physical channel number. */
2474 chan = (uint32_t) trimchan[LogicalChan];
2475
2476 /* Set up TSL2 records for TrimDac write operation. All slots shift
2477 * 0xFF in from pulled-up SD3 so that the end of the slot sequence
2478 * can be detected.
2479 */
2480
2481 SETVECT(2, XSD2 | XFIFO_1 | WS3);
2482 /* Slot 2: Send high uint8_t to target TrimDac. */
2483 SETVECT(3, XSD2 | XFIFO_0 | WS3);
2484 /* Slot 3: Send low uint8_t to target TrimDac. */
2485 SETVECT(4, XSD2 | XFIFO_3 | WS1);
2486 /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running. */
2487 SETVECT(5, XSD2 | XFIFO_2 | WS1 | EOS);
2488 /* Slot 5: Send NOP low uint8_t to DAC0. */
2489
2490 /* Construct and transmit target DAC's serial packet:
2491 * ( 0000 AAAA ), ( DDDD DDDD ),( 0x00 ),( 0x00 ) where A<3:0> is the
2492 * DAC channel's address, and D<7:0> is the DAC setpoint. Append a
2493 * WORD value (that writes a channel 0 NOP command to a non-existent
2494 * main DAC channel) that serves to keep the clock running after the
2495 * packet has been sent to the target DAC.
2496 */
2497
2498 /* Address the DAC channel within the trimdac device. */
2499 SendDAC(dev, ((uint32_t) chan << 8)
2500 | (uint32_t) DacData); /* Include DAC setpoint data. */
2501 }
2502
2503 /* ************** EEPROM ACCESS FUNCTIONS ************** */
2504 /* Read uint8_t from EEPROM. */
2505
2506 static uint8_t I2Cread(struct comedi_device *dev, uint8_t addr)
2507 {
2508 uint8_t rtnval;
2509
2510 /* Send EEPROM target address. */
2511 if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CW)
2512 /* Byte2 = I2C command: write to I2C EEPROM device. */
2513 | I2C_B1(I2C_ATTRSTOP, addr)
2514 /* Byte1 = EEPROM internal target address. */
2515 | I2C_B0(I2C_ATTRNOP, 0))) { /* Byte0 = Not sent. */
2516 /* Abort function and declare error if handshake failed. */
2517 DEBUG("I2Cread: error handshake I2Cread a\n");
2518 return 0;
2519 }
2520 /* Execute EEPROM read. */
2521 if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CR)
2522
2523 /* Byte2 = I2C */
2524 /* command: read */
2525 /* from I2C EEPROM */
2526 /* device. */
2527 |I2C_B1(I2C_ATTRSTOP, 0)
2528
2529 /* Byte1 receives */
2530 /* uint8_t from */
2531 /* EEPROM. */
2532 |I2C_B0(I2C_ATTRNOP, 0))) { /* Byte0 = Not sent. */
2533
2534 /* Abort function and declare error if handshake failed. */
2535 DEBUG("I2Cread: error handshake I2Cread b\n");
2536 return 0;
2537 }
2538 /* Return copy of EEPROM value. */
2539 rtnval = (uint8_t) (RR7146(P_I2CCTRL) >> 16);
2540 return rtnval;
2541 }
2542
2543 static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val)
2544 {
2545 /* Write I2C command to I2C Transfer Control shadow register. */
2546 WR7146(P_I2CCTRL, val);
2547
2548 /* Upload I2C shadow registers into working registers and wait for */
2549 /* upload confirmation. */
2550
2551 MC_ENABLE(P_MC2, MC2_UPLD_IIC);
2552 while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
2553 ;
2554
2555 /* Wait until I2C bus transfer is finished or an error occurs. */
2556 while ((RR7146(P_I2CCTRL) & (I2C_BUSY | I2C_ERR)) == I2C_BUSY)
2557 ;
2558
2559 /* Return non-zero if I2C error occured. */
2560 return RR7146(P_I2CCTRL) & I2C_ERR;
2561
2562 }
2563
2564 /* Private helper function: Write setpoint to an application DAC channel. */
2565
2566 static void SetDAC(struct comedi_device *dev, uint16_t chan, short dacdata)
2567 {
2568 register uint16_t signmask;
2569 register uint32_t WSImage;
2570
2571 /* Adjust DAC data polarity and set up Polarity Control Register */
2572 /* image. */
2573 signmask = 1 << chan;
2574 if (dacdata < 0) {
2575 dacdata = -dacdata;
2576 devpriv->Dacpol |= signmask;
2577 } else
2578 devpriv->Dacpol &= ~signmask;
2579
2580 /* Limit DAC setpoint value to valid range. */
2581 if ((uint16_t) dacdata > 0x1FFF)
2582 dacdata = 0x1FFF;
2583
2584 /* Set up TSL2 records (aka "vectors") for DAC update. Vectors V2
2585 * and V3 transmit the setpoint to the target DAC. V4 and V5 send
2586 * data to a non-existent TrimDac channel just to keep the clock
2587 * running after sending data to the target DAC. This is necessary
2588 * to eliminate the clock glitch that would otherwise occur at the
2589 * end of the target DAC's serial data stream. When the sequence
2590 * restarts at V0 (after executing V5), the gate array automatically
2591 * disables gating for the DAC clock and all DAC chip selects.
2592 */
2593
2594 WSImage = (chan & 2) ? WS1 : WS2;
2595 /* Choose DAC chip select to be asserted. */
2596 SETVECT(2, XSD2 | XFIFO_1 | WSImage);
2597 /* Slot 2: Transmit high data byte to target DAC. */
2598 SETVECT(3, XSD2 | XFIFO_0 | WSImage);
2599 /* Slot 3: Transmit low data byte to target DAC. */
2600 SETVECT(4, XSD2 | XFIFO_3 | WS3);
2601 /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
2602 SETVECT(5, XSD2 | XFIFO_2 | WS3 | EOS);
2603 /* Slot 5: running after writing target DAC's low data byte. */
2604
2605 /* Construct and transmit target DAC's serial packet:
2606 * ( A10D DDDD ),( DDDD DDDD ),( 0x0F ),( 0x00 ) where A is chan<0>,
2607 * and D<12:0> is the DAC setpoint. Append a WORD value (that writes
2608 * to a non-existent TrimDac channel) that serves to keep the clock
2609 * running after the packet has been sent to the target DAC.
2610 */
2611 SendDAC(dev, 0x0F000000
2612 /* Continue clock after target DAC data (write to non-existent trimdac). */
2613 | 0x00004000
2614 /* Address the two main dual-DAC devices (TSL's chip select enables
2615 * target device). */
2616 | ((uint32_t) (chan & 1) << 15)
2617 /* Address the DAC channel within the device. */
2618 | (uint32_t) dacdata); /* Include DAC setpoint data. */
2619
2620 }
2621
2622 /* Private helper function: Transmit serial data to DAC via Audio
2623 * channel 2. Assumes: (1) TSL2 slot records initialized, and (2)
2624 * Dacpol contains valid target image.
2625 */
2626
2627 static void SendDAC(struct comedi_device *dev, uint32_t val)
2628 {
2629
2630 /* START THE SERIAL CLOCK RUNNING ------------- */
2631
2632 /* Assert DAC polarity control and enable gating of DAC serial clock
2633 * and audio bit stream signals. At this point in time we must be
2634 * assured of being in time slot 0. If we are not in slot 0, the
2635 * serial clock and audio stream signals will be disabled; this is
2636 * because the following DEBIwrite statement (which enables signals
2637 * to be passed through the gate array) would execute before the
2638 * trailing edge of WS1/WS3 (which turns off the signals), thus
2639 * causing the signals to be inactive during the DAC write.
2640 */
2641 DEBIwrite(dev, LP_DACPOL, devpriv->Dacpol);
2642
2643 /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */
2644
2645 /* Copy DAC setpoint value to DAC's output DMA buffer. */
2646
2647 /* WR7146( (uint32_t)devpriv->pDacWBuf, val ); */
2648 *devpriv->pDacWBuf = val;
2649
2650 /* enab the output DMA transfer. This will cause the DMAC to copy
2651 * the DAC's data value to A2's output FIFO. The DMA transfer will
2652 * then immediately terminate because the protection address is
2653 * reached upon transfer of the first DWORD value.
2654 */
2655 MC_ENABLE(P_MC1, MC1_A2OUT);
2656
2657 /* While the DMA transfer is executing ... */
2658
2659 /* Reset Audio2 output FIFO's underflow flag (along with any other
2660 * FIFO underflow/overflow flags). When set, this flag will
2661 * indicate that we have emerged from slot 0.
2662 */
2663 WR7146(P_ISR, ISR_AFOU);
2664
2665 /* Wait for the DMA transfer to finish so that there will be data
2666 * available in the FIFO when time slot 1 tries to transfer a DWORD
2667 * from the FIFO to the output buffer register. We test for DMA
2668 * Done by polling the DMAC enable flag; this flag is automatically
2669 * cleared when the transfer has finished.
2670 */
2671 while ((RR7146(P_MC1) & MC1_A2OUT) != 0)
2672 ;
2673
2674 /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
2675
2676 /* FIFO data is now available, so we enable execution of time slots
2677 * 1 and higher by clearing the EOS flag in slot 0. Note that SD3
2678 * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
2679 * detection.
2680 */
2681 SETVECT(0, XSD2 | RSD3 | SIB_A2);
2682
2683 /* Wait for slot 1 to execute to ensure that the Packet will be
2684 * transmitted. This is detected by polling the Audio2 output FIFO
2685 * underflow flag, which will be set when slot 1 execution has
2686 * finished transferring the DAC's data DWORD from the output FIFO
2687 * to the output buffer register.
2688 */
2689 while ((RR7146(P_SSR) & SSR_AF2_OUT) == 0)
2690 ;
2691
2692 /* Set up to trap execution at slot 0 when the TSL sequencer cycles
2693 * back to slot 0 after executing the EOS in slot 5. Also,
2694 * simultaneously shift out and in the 0x00 that is ALWAYS the value
2695 * stored in the last byte to be shifted out of the FIFO's DWORD
2696 * buffer register.
2697 */
2698 SETVECT(0, XSD2 | XFIFO_2 | RSD2 | SIB_A2 | EOS);
2699
2700 /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */
2701
2702 /* Wait for the TSL to finish executing all time slots before
2703 * exiting this function. We must do this so that the next DAC
2704 * write doesn't start, thereby enabling clock/chip select signals:
2705 *
2706 * 1. Before the TSL sequence cycles back to slot 0, which disables
2707 * the clock/cs signal gating and traps slot // list execution.
2708 * we have not yet finished slot 5 then the clock/cs signals are
2709 * still gated and we have not finished transmitting the stream.
2710 *
2711 * 2. While slots 2-5 are executing due to a late slot 0 trap. In
2712 * this case, the slot sequence is currently repeating, but with
2713 * clock/cs signals disabled. We must wait for slot 0 to trap
2714 * execution before setting up the next DAC setpoint DMA transfer
2715 * and enabling the clock/cs signals. To detect the end of slot 5,
2716 * we test for the FB_BUFFER2 MSB contents to be equal to 0xFF. If
2717 * the TSL has not yet finished executing slot 5 ...
2718 */
2719 if ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0) {
2720 /* The trap was set on time and we are still executing somewhere
2721 * in slots 2-5, so we now wait for slot 0 to execute and trap
2722 * TSL execution. This is detected when FB_BUFFER2 MSB changes
2723 * from 0xFF to 0x00, which slot 0 causes to happen by shifting
2724 * out/in on SD2 the 0x00 that is always referenced by slot 5.
2725 */
2726 while ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0)
2727 ;
2728 }
2729 /* Either (1) we were too late setting the slot 0 trap; the TSL
2730 * sequencer restarted slot 0 before we could set the EOS trap flag,
2731 * or (2) we were not late and execution is now trapped at slot 0.
2732 * In either case, we must now change slot 0 so that it will store
2733 * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes.
2734 * In order to do this, we reprogram slot 0 so that it will shift in
2735 * SD3, which is driven only by a pull-up resistor.
2736 */
2737 SETVECT(0, RSD3 | SIB_A2 | EOS);
2738
2739 /* Wait for slot 0 to execute, at which time the TSL is setup for
2740 * the next DAC write. This is detected when FB_BUFFER2 MSB changes
2741 * from 0x00 to 0xFF.
2742 */
2743 while ((RR7146(P_FB_BUFFER2) & 0xFF000000) == 0)
2744 ;
2745 }
2746
2747 static void WriteMISC2(struct comedi_device *dev, uint16_t NewImage)
2748 {
2749 DEBIwrite(dev, LP_MISC1, MISC1_WENABLE); /* enab writes to */
2750 /* MISC2 register. */
2751 DEBIwrite(dev, LP_WRMISC2, NewImage); /* Write new image to MISC2. */
2752 DEBIwrite(dev, LP_MISC1, MISC1_WDISABLE); /* Disable writes to MISC2. */
2753 }
2754
2755 /* Initialize the DEBI interface for all transfers. */
2756
2757 static uint16_t DEBIread(struct comedi_device *dev, uint16_t addr)
2758 {
2759 uint16_t retval;
2760
2761 /* Set up DEBI control register value in shadow RAM. */
2762 WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr);
2763
2764 /* Execute the DEBI transfer. */
2765 DEBItransfer(dev);
2766
2767 /* Fetch target register value. */
2768 retval = (uint16_t) RR7146(P_DEBIAD);
2769
2770 /* Return register value. */
2771 return retval;
2772 }
2773
2774 /* Execute a DEBI transfer. This must be called from within a */
2775 /* critical section. */
2776 static void DEBItransfer(struct comedi_device *dev)
2777 {
2778 /* Initiate upload of shadow RAM to DEBI control register. */
2779 MC_ENABLE(P_MC2, MC2_UPLD_DEBI);
2780
2781 /* Wait for completion of upload from shadow RAM to DEBI control */
2782 /* register. */
2783 while (!MC_TEST(P_MC2, MC2_UPLD_DEBI))
2784 ;
2785
2786 /* Wait until DEBI transfer is done. */
2787 while (RR7146(P_PSR) & PSR_DEBI_S)
2788 ;
2789 }
2790
2791 /* Write a value to a gate array register. */
2792 static void DEBIwrite(struct comedi_device *dev, uint16_t addr, uint16_t wdata)
2793 {
2794
2795 /* Set up DEBI control register value in shadow RAM. */
2796 WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr);
2797 WR7146(P_DEBIAD, wdata);
2798
2799 /* Execute the DEBI transfer. */
2800 DEBItransfer(dev);
2801 }
2802
2803 /* Replace the specified bits in a gate array register. Imports: mask
2804 * specifies bits that are to be preserved, wdata is new value to be
2805 * or'd with the masked original.
2806 */
2807 static void DEBIreplace(struct comedi_device *dev, uint16_t addr, uint16_t mask,
2808 uint16_t wdata)
2809 {
2810
2811 /* Copy target gate array register into P_DEBIAD register. */
2812 WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr);
2813 /* Set up DEBI control reg value in shadow RAM. */
2814 DEBItransfer(dev); /* Execute the DEBI Read transfer. */
2815
2816 /* Write back the modified image. */
2817 WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr);
2818 /* Set up DEBI control reg value in shadow RAM. */
2819
2820 WR7146(P_DEBIAD, wdata | ((uint16_t) RR7146(P_DEBIAD) & mask));
2821 /* Modify the register image. */
2822 DEBItransfer(dev); /* Execute the DEBI Write transfer. */
2823 }
2824
2825 static void CloseDMAB(struct comedi_device *dev, struct bufferDMA *pdma,
2826 size_t bsize)
2827 {
2828 void *vbptr;
2829 dma_addr_t vpptr;
2830
2831 DEBUG("CloseDMAB: Entering S626DRV_CloseDMAB():\n");
2832 if (pdma == NULL)
2833 return;
2834 /* find the matching allocation from the board struct */
2835
2836 vbptr = pdma->LogicalBase;
2837 vpptr = pdma->PhysicalBase;
2838 if (vbptr) {
2839 pci_free_consistent(devpriv->pdev, bsize, vbptr, vpptr);
2840 pdma->LogicalBase = 0;
2841 pdma->PhysicalBase = 0;
2842
2843 DEBUG("CloseDMAB(): Logical=%p, bsize=%d, Physical=0x%x\n",
2844 vbptr, bsize, (uint32_t) vpptr);
2845 }
2846 }
2847
2848 /* ****** COUNTER FUNCTIONS ******* */
2849 /* All counter functions address a specific counter by means of the
2850 * "Counter" argument, which is a logical counter number. The Counter
2851 * argument may have any of the following legal values: 0=0A, 1=1A,
2852 * 2=2A, 3=0B, 4=1B, 5=2B.
2853 */
2854
2855 /* Forward declarations for functions that are common to both A and B counters: */
2856
2857 /* ****** PRIVATE COUNTER FUNCTIONS ****** */
2858
2859 /* Read a counter's output latch. */
2860
2861 static uint32_t ReadLatch(struct comedi_device *dev, struct enc_private *k)
2862 {
2863 register uint32_t value;
2864
2865 /* Latch counts and fetch LSW of latched counts value. */
2866 value = (uint32_t) DEBIread(dev, k->MyLatchLsw);
2867
2868 /* Fetch MSW of latched counts and combine with LSW. */
2869 value |= ((uint32_t) DEBIread(dev, k->MyLatchLsw + 2) << 16);
2870
2871
2872 /* Return latched counts. */
2873 return value;
2874 }
2875
2876 /* Reset a counter's index and overflow event capture flags. */
2877
2878 static void ResetCapFlags_A(struct comedi_device *dev, struct enc_private *k)
2879 {
2880 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
2881 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A);
2882 }
2883
2884 static void ResetCapFlags_B(struct comedi_device *dev, struct enc_private *k)
2885 {
2886 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
2887 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B);
2888 }
2889
2890 /* Return counter setup in a format (COUNTER_SETUP) that is consistent */
2891 /* for both A and B counters. */
2892
2893 static uint16_t GetMode_A(struct comedi_device *dev, struct enc_private *k)
2894 {
2895 register uint16_t cra;
2896 register uint16_t crb;
2897 register uint16_t setup;
2898
2899 /* Fetch CRA and CRB register images. */
2900 cra = DEBIread(dev, k->MyCRA);
2901 crb = DEBIread(dev, k->MyCRB);
2902
2903 /* Populate the standardized counter setup bit fields. Note: */
2904 /* IndexSrc is restricted to ENC_X or IndxPol. */
2905 setup = ((cra & STDMSK_LOADSRC) /* LoadSrc = LoadSrcA. */
2906 |((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & STDMSK_LATCHSRC) /* LatchSrc = LatchSrcA. */
2907 |((cra << (STDBIT_INTSRC - CRABIT_INTSRC_A)) & STDMSK_INTSRC) /* IntSrc = IntSrcA. */
2908 |((cra << (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1))) & STDMSK_INDXSRC) /* IndxSrc = IndxSrcA<1>. */
2909 |((cra >> (CRABIT_INDXPOL_A - STDBIT_INDXPOL)) & STDMSK_INDXPOL) /* IndxPol = IndxPolA. */
2910 |((crb >> (CRBBIT_CLKENAB_A - STDBIT_CLKENAB)) & STDMSK_CLKENAB)); /* ClkEnab = ClkEnabA. */
2911
2912 /* Adjust mode-dependent parameters. */
2913 if (cra & (2 << CRABIT_CLKSRC_A)) /* If Timer mode (ClkSrcA<1> == 1): */
2914 setup |= ((CLKSRC_TIMER << STDBIT_CLKSRC) /* Indicate Timer mode. */
2915 |((cra << (STDBIT_CLKPOL - CRABIT_CLKSRC_A)) & STDMSK_CLKPOL) /* Set ClkPol to indicate count direction (ClkSrcA<0>). */
2916 |(MULT_X1 << STDBIT_CLKMULT)); /* ClkMult must be 1x in Timer mode. */
2917
2918 else /* If Counter mode (ClkSrcA<1> == 0): */
2919 setup |= ((CLKSRC_COUNTER << STDBIT_CLKSRC) /* Indicate Counter mode. */
2920 |((cra >> (CRABIT_CLKPOL_A - STDBIT_CLKPOL)) & STDMSK_CLKPOL) /* Pass through ClkPol. */
2921 |(((cra & CRAMSK_CLKMULT_A) == (MULT_X0 << CRABIT_CLKMULT_A)) ? /* Force ClkMult to 1x if not legal, else pass through. */
2922 (MULT_X1 << STDBIT_CLKMULT) :
2923 ((cra >> (CRABIT_CLKMULT_A -
2924 STDBIT_CLKMULT)) & STDMSK_CLKMULT)));
2925
2926 /* Return adjusted counter setup. */
2927 return setup;
2928 }
2929
2930 static uint16_t GetMode_B(struct comedi_device *dev, struct enc_private *k)
2931 {
2932 register uint16_t cra;
2933 register uint16_t crb;
2934 register uint16_t setup;
2935
2936 /* Fetch CRA and CRB register images. */
2937 cra = DEBIread(dev, k->MyCRA);
2938 crb = DEBIread(dev, k->MyCRB);
2939
2940 /* Populate the standardized counter setup bit fields. Note: */
2941 /* IndexSrc is restricted to ENC_X or IndxPol. */
2942 setup = (((crb << (STDBIT_INTSRC - CRBBIT_INTSRC_B)) & STDMSK_INTSRC) /* IntSrc = IntSrcB. */
2943 |((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & STDMSK_LATCHSRC) /* LatchSrc = LatchSrcB. */
2944 |((crb << (STDBIT_LOADSRC - CRBBIT_LOADSRC_B)) & STDMSK_LOADSRC) /* LoadSrc = LoadSrcB. */
2945 |((crb << (STDBIT_INDXPOL - CRBBIT_INDXPOL_B)) & STDMSK_INDXPOL) /* IndxPol = IndxPolB. */
2946 |((crb >> (CRBBIT_CLKENAB_B - STDBIT_CLKENAB)) & STDMSK_CLKENAB) /* ClkEnab = ClkEnabB. */
2947 |((cra >> ((CRABIT_INDXSRC_B + 1) - STDBIT_INDXSRC)) & STDMSK_INDXSRC)); /* IndxSrc = IndxSrcB<1>. */
2948
2949 /* Adjust mode-dependent parameters. */
2950 if ((crb & CRBMSK_CLKMULT_B) == (MULT_X0 << CRBBIT_CLKMULT_B)) /* If Extender mode (ClkMultB == MULT_X0): */
2951 setup |= ((CLKSRC_EXTENDER << STDBIT_CLKSRC) /* Indicate Extender mode. */
2952 |(MULT_X1 << STDBIT_CLKMULT) /* Indicate multiplier is 1x. */
2953 |((cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & STDMSK_CLKPOL)); /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */
2954
2955 else if (cra & (2 << CRABIT_CLKSRC_B)) /* If Timer mode (ClkSrcB<1> == 1): */
2956 setup |= ((CLKSRC_TIMER << STDBIT_CLKSRC) /* Indicate Timer mode. */
2957 |(MULT_X1 << STDBIT_CLKMULT) /* Indicate multiplier is 1x. */
2958 |((cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & STDMSK_CLKPOL)); /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */
2959
2960 else /* If Counter mode (ClkSrcB<1> == 0): */
2961 setup |= ((CLKSRC_COUNTER << STDBIT_CLKSRC) /* Indicate Timer mode. */
2962 |((crb >> (CRBBIT_CLKMULT_B - STDBIT_CLKMULT)) & STDMSK_CLKMULT) /* Clock multiplier is passed through. */
2963 |((crb << (STDBIT_CLKPOL - CRBBIT_CLKPOL_B)) & STDMSK_CLKPOL)); /* Clock polarity is passed through. */
2964
2965 /* Return adjusted counter setup. */
2966 return setup;
2967 }
2968
2969 /*
2970 * Set the operating mode for the specified counter. The setup
2971 * parameter is treated as a COUNTER_SETUP data type. The following
2972 * parameters are programmable (all other parms are ignored): ClkMult,
2973 * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
2974 */
2975
2976 static void SetMode_A(struct comedi_device *dev, struct enc_private *k,
2977 uint16_t Setup, uint16_t DisableIntSrc)
2978 {
2979 register uint16_t cra;
2980 register uint16_t crb;
2981 register uint16_t setup = Setup; /* Cache the Standard Setup. */
2982
2983 /* Initialize CRA and CRB images. */
2984 cra = ((setup & CRAMSK_LOADSRC_A) /* Preload trigger is passed through. */
2985 |((setup & STDMSK_INDXSRC) >> (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1)))); /* IndexSrc is restricted to ENC_X or IndxPol. */
2986
2987 crb = (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A /* Reset any pending CounterA event captures. */
2988 | ((setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_A - STDBIT_CLKENAB))); /* Clock enable is passed through. */
2989
2990 /* Force IntSrc to Disabled if DisableIntSrc is asserted. */
2991 if (!DisableIntSrc)
2992 cra |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC -
2993 CRABIT_INTSRC_A));
2994
2995 /* Populate all mode-dependent attributes of CRA & CRB images. */
2996 switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
2997 case CLKSRC_EXTENDER: /* Extender Mode: Force to Timer mode */
2998 /* (Extender valid only for B counters). */
2999
3000 case CLKSRC_TIMER: /* Timer Mode: */
3001 cra |= ((2 << CRABIT_CLKSRC_A) /* ClkSrcA<1> selects system clock */
3002 |((setup & STDMSK_CLKPOL) >> (STDBIT_CLKPOL - CRABIT_CLKSRC_A)) /* with count direction (ClkSrcA<0>) obtained from ClkPol. */
3003 |(1 << CRABIT_CLKPOL_A) /* ClkPolA behaves as always-on clock enable. */
3004 |(MULT_X1 << CRABIT_CLKMULT_A)); /* ClkMult must be 1x. */
3005 break;
3006
3007 default: /* Counter Mode: */
3008 cra |= (CLKSRC_COUNTER /* Select ENC_C and ENC_D as clock/direction inputs. */
3009 | ((setup & STDMSK_CLKPOL) << (CRABIT_CLKPOL_A - STDBIT_CLKPOL)) /* Clock polarity is passed through. */
3010 |(((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) ? /* Force multiplier to x1 if not legal, otherwise pass through. */
3011 (MULT_X1 << CRABIT_CLKMULT_A) :
3012 ((setup & STDMSK_CLKMULT) << (CRABIT_CLKMULT_A -
3013 STDBIT_CLKMULT))));
3014 }
3015
3016 /* Force positive index polarity if IndxSrc is software-driven only, */
3017 /* otherwise pass it through. */
3018 if (~setup & STDMSK_INDXSRC)
3019 cra |= ((setup & STDMSK_INDXPOL) << (CRABIT_INDXPOL_A -
3020 STDBIT_INDXPOL));
3021
3022 /* If IntSrc has been forced to Disabled, update the MISC2 interrupt */
3023 /* enable mask to indicate the counter interrupt is disabled. */
3024 if (DisableIntSrc)
3025 devpriv->CounterIntEnabs &= ~k->MyEventBits[3];
3026
3027 /* While retaining CounterB and LatchSrc configurations, program the */
3028 /* new counter operating mode. */
3029 DEBIreplace(dev, k->MyCRA, CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B, cra);
3030 DEBIreplace(dev, k->MyCRB,
3031 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A)), crb);
3032 }
3033
3034 static void SetMode_B(struct comedi_device *dev, struct enc_private *k,
3035 uint16_t Setup, uint16_t DisableIntSrc)
3036 {
3037 register uint16_t cra;
3038 register uint16_t crb;
3039 register uint16_t setup = Setup; /* Cache the Standard Setup. */
3040
3041 /* Initialize CRA and CRB images. */
3042 cra = ((setup & STDMSK_INDXSRC) << ((CRABIT_INDXSRC_B + 1) - STDBIT_INDXSRC)); /* IndexSrc field is restricted to ENC_X or IndxPol. */
3043
3044 crb = (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B /* Reset event captures and disable interrupts. */
3045 | ((setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_B - STDBIT_CLKENAB)) /* Clock enable is passed through. */
3046 |((setup & STDMSK_LOADSRC) >> (STDBIT_LOADSRC - CRBBIT_LOADSRC_B))); /* Preload trigger source is passed through. */
3047
3048 /* Force IntSrc to Disabled if DisableIntSrc is asserted. */
3049 if (!DisableIntSrc)
3050 crb |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC -
3051 CRBBIT_INTSRC_B));
3052
3053 /* Populate all mode-dependent attributes of CRA & CRB images. */
3054 switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
3055 case CLKSRC_TIMER: /* Timer Mode: */
3056 cra |= ((2 << CRABIT_CLKSRC_B) /* ClkSrcB<1> selects system clock */
3057 |((setup & STDMSK_CLKPOL) << (CRABIT_CLKSRC_B - STDBIT_CLKPOL))); /* with direction (ClkSrcB<0>) obtained from ClkPol. */
3058 crb |= ((1 << CRBBIT_CLKPOL_B) /* ClkPolB behaves as always-on clock enable. */
3059 |(MULT_X1 << CRBBIT_CLKMULT_B)); /* ClkMultB must be 1x. */
3060 break;
3061
3062 case CLKSRC_EXTENDER: /* Extender Mode: */
3063 cra |= ((2 << CRABIT_CLKSRC_B) /* ClkSrcB source is OverflowA (same as "timer") */
3064 |((setup & STDMSK_CLKPOL) << (CRABIT_CLKSRC_B - STDBIT_CLKPOL))); /* with direction obtained from ClkPol. */
3065 crb |= ((1 << CRBBIT_CLKPOL_B) /* ClkPolB controls IndexB -- always set to active. */
3066 |(MULT_X0 << CRBBIT_CLKMULT_B)); /* ClkMultB selects OverflowA as the clock source. */
3067 break;
3068
3069 default: /* Counter Mode: */
3070 cra |= (CLKSRC_COUNTER << CRABIT_CLKSRC_B); /* Select ENC_C and ENC_D as clock/direction inputs. */
3071 crb |= (((setup & STDMSK_CLKPOL) >> (STDBIT_CLKPOL - CRBBIT_CLKPOL_B)) /* ClkPol is passed through. */
3072 |(((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) ? /* Force ClkMult to x1 if not legal, otherwise pass through. */
3073 (MULT_X1 << CRBBIT_CLKMULT_B) :
3074 ((setup & STDMSK_CLKMULT) << (CRBBIT_CLKMULT_B -
3075 STDBIT_CLKMULT))));
3076 }
3077
3078 /* Force positive index polarity if IndxSrc is software-driven only, */
3079 /* otherwise pass it through. */
3080 if (~setup & STDMSK_INDXSRC)
3081 crb |= ((setup & STDMSK_INDXPOL) >> (STDBIT_INDXPOL -
3082 CRBBIT_INDXPOL_B));
3083
3084 /* If IntSrc has been forced to Disabled, update the MISC2 interrupt */
3085 /* enable mask to indicate the counter interrupt is disabled. */
3086 if (DisableIntSrc)
3087 devpriv->CounterIntEnabs &= ~k->MyEventBits[3];
3088
3089 /* While retaining CounterA and LatchSrc configurations, program the */
3090 /* new counter operating mode. */
3091 DEBIreplace(dev, k->MyCRA,
3092 (uint16_t) (~(CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B)), cra);
3093 DEBIreplace(dev, k->MyCRB, CRBMSK_CLKENAB_A | CRBMSK_LATCHSRC, crb);
3094 }
3095
3096 /* Return/set a counter's enable. enab: 0=always enabled, 1=enabled by index. */
3097
3098 static void SetEnable_A(struct comedi_device *dev, struct enc_private *k,
3099 uint16_t enab)
3100 {
3101 DEBUG("SetEnable_A: SetEnable_A enter 3541\n");
3102 DEBIreplace(dev, k->MyCRB,
3103 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A)),
3104 (uint16_t) (enab << CRBBIT_CLKENAB_A));
3105 }
3106
3107 static void SetEnable_B(struct comedi_device *dev, struct enc_private *k,
3108 uint16_t enab)
3109 {
3110 DEBIreplace(dev, k->MyCRB,
3111 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_B)),
3112 (uint16_t) (enab << CRBBIT_CLKENAB_B));
3113 }
3114
3115 static uint16_t GetEnable_A(struct comedi_device *dev, struct enc_private *k)
3116 {
3117 return (DEBIread(dev, k->MyCRB) >> CRBBIT_CLKENAB_A) & 1;
3118 }
3119
3120 static uint16_t GetEnable_B(struct comedi_device *dev, struct enc_private *k)
3121 {
3122 return (DEBIread(dev, k->MyCRB) >> CRBBIT_CLKENAB_B) & 1;
3123 }
3124
3125 /* Return/set a counter pair's latch trigger source. 0: On read
3126 * access, 1: A index latches A, 2: B index latches B, 3: A overflow
3127 * latches B.
3128 */
3129
3130 static void SetLatchSource(struct comedi_device *dev, struct enc_private *k,
3131 uint16_t value)
3132 {
3133 DEBUG("SetLatchSource: SetLatchSource enter 3550\n");
3134 DEBIreplace(dev, k->MyCRB,
3135 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_LATCHSRC)),
3136 (uint16_t) (value << CRBBIT_LATCHSRC));
3137
3138 DEBUG("SetLatchSource: SetLatchSource exit\n");
3139 }
3140
3141 /*
3142 * static uint16_t GetLatchSource(struct comedi_device *dev, struct enc_private *k )
3143 * {
3144 * return ( DEBIread( dev, k->MyCRB) >> CRBBIT_LATCHSRC ) & 3;
3145 * }
3146 */
3147
3148 /*
3149 * Return/set the event that will trigger transfer of the preload
3150 * register into the counter. 0=ThisCntr_Index, 1=ThisCntr_Overflow,
3151 * 2=OverflowA (B counters only), 3=disabled.
3152 */
3153
3154 static void SetLoadTrig_A(struct comedi_device *dev, struct enc_private *k,
3155 uint16_t Trig)
3156 {
3157 DEBIreplace(dev, k->MyCRA, (uint16_t) (~CRAMSK_LOADSRC_A),
3158 (uint16_t) (Trig << CRABIT_LOADSRC_A));
3159 }
3160
3161 static void SetLoadTrig_B(struct comedi_device *dev, struct enc_private *k,
3162 uint16_t Trig)
3163 {
3164 DEBIreplace(dev, k->MyCRB,
3165 (uint16_t) (~(CRBMSK_LOADSRC_B | CRBMSK_INTCTRL)),
3166 (uint16_t) (Trig << CRBBIT_LOADSRC_B));
3167 }
3168
3169 static uint16_t GetLoadTrig_A(struct comedi_device *dev, struct enc_private *k)
3170 {
3171 return (DEBIread(dev, k->MyCRA) >> CRABIT_LOADSRC_A) & 3;
3172 }
3173
3174 static uint16_t GetLoadTrig_B(struct comedi_device *dev, struct enc_private *k)
3175 {
3176 return (DEBIread(dev, k->MyCRB) >> CRBBIT_LOADSRC_B) & 3;
3177 }
3178
3179 /* Return/set counter interrupt source and clear any captured
3180 * index/overflow events. IntSource: 0=Disabled, 1=OverflowOnly,
3181 * 2=IndexOnly, 3=IndexAndOverflow.
3182 */
3183
3184 static void SetIntSrc_A(struct comedi_device *dev, struct enc_private *k,
3185 uint16_t IntSource)
3186 {
3187 /* Reset any pending counter overflow or index captures. */
3188 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
3189 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A);
3190
3191 /* Program counter interrupt source. */
3192 DEBIreplace(dev, k->MyCRA, ~CRAMSK_INTSRC_A,
3193 (uint16_t) (IntSource << CRABIT_INTSRC_A));
3194
3195 /* Update MISC2 interrupt enable mask. */
3196 devpriv->CounterIntEnabs =
3197 (devpriv->CounterIntEnabs & ~k->
3198 MyEventBits[3]) | k->MyEventBits[IntSource];
3199 }
3200
3201 static void SetIntSrc_B(struct comedi_device *dev, struct enc_private *k,
3202 uint16_t IntSource)
3203 {
3204 uint16_t crb;
3205
3206 /* Cache writeable CRB register image. */
3207 crb = DEBIread(dev, k->MyCRB) & ~CRBMSK_INTCTRL;
3208
3209 /* Reset any pending counter overflow or index captures. */
3210 DEBIwrite(dev, k->MyCRB,
3211 (uint16_t) (crb | CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B));
3212
3213 /* Program counter interrupt source. */
3214 DEBIwrite(dev, k->MyCRB,
3215 (uint16_t) ((crb & ~CRBMSK_INTSRC_B) | (IntSource <<
3216 CRBBIT_INTSRC_B)));
3217
3218 /* Update MISC2 interrupt enable mask. */
3219 devpriv->CounterIntEnabs =
3220 (devpriv->CounterIntEnabs & ~k->
3221 MyEventBits[3]) | k->MyEventBits[IntSource];
3222 }
3223
3224 static uint16_t GetIntSrc_A(struct comedi_device *dev, struct enc_private *k)
3225 {
3226 return (DEBIread(dev, k->MyCRA) >> CRABIT_INTSRC_A) & 3;
3227 }
3228
3229 static uint16_t GetIntSrc_B(struct comedi_device *dev, struct enc_private *k)
3230 {
3231 return (DEBIread(dev, k->MyCRB) >> CRBBIT_INTSRC_B) & 3;
3232 }
3233
3234 /* Return/set the clock multiplier. */
3235
3236 /* static void SetClkMult(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */
3237 /* { */
3238 /* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKMULT ) | ( value << STDBIT_CLKMULT ) ), FALSE ); */
3239 /* } */
3240
3241 /* static uint16_t GetClkMult(struct comedi_device *dev, struct enc_private *k ) */
3242 /* { */
3243 /* return ( k->GetMode(dev, k ) >> STDBIT_CLKMULT ) & 3; */
3244 /* } */
3245
3246 /* Return/set the clock polarity. */
3247
3248 /* static void SetClkPol( struct comedi_device *dev,struct enc_private *k, uint16_t value ) */
3249 /* { */
3250 /* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKPOL ) | ( value << STDBIT_CLKPOL ) ), FALSE ); */
3251 /* } */
3252
3253 /* static uint16_t GetClkPol(struct comedi_device *dev, struct enc_private *k ) */
3254 /* { */
3255 /* return ( k->GetMode(dev, k ) >> STDBIT_CLKPOL ) & 1; */
3256 /* } */
3257
3258 /* Return/set the clock source. */
3259
3260 /* static void SetClkSrc( struct comedi_device *dev,struct enc_private *k, uint16_t value ) */
3261 /* { */
3262 /* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKSRC ) | ( value << STDBIT_CLKSRC ) ), FALSE ); */
3263 /* } */
3264
3265 /* static uint16_t GetClkSrc( struct comedi_device *dev,struct enc_private *k ) */
3266 /* { */
3267 /* return ( k->GetMode(dev, k ) >> STDBIT_CLKSRC ) & 3; */
3268 /* } */
3269
3270 /* Return/set the index polarity. */
3271
3272 /* static void SetIndexPol(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */
3273 /* { */
3274 /* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_INDXPOL ) | ( (value != 0) << STDBIT_INDXPOL ) ), FALSE ); */
3275 /* } */
3276
3277 /* static uint16_t GetIndexPol(struct comedi_device *dev, struct enc_private *k ) */
3278 /* { */
3279 /* return ( k->GetMode(dev, k ) >> STDBIT_INDXPOL ) & 1; */
3280 /* } */
3281
3282 /* Return/set the index source. */
3283
3284 /* static void SetIndexSrc(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */
3285 /* { */
3286 /* DEBUG("SetIndexSrc: set index src enter 3700\n"); */
3287 /* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_INDXSRC ) | ( (value != 0) << STDBIT_INDXSRC ) ), FALSE ); */
3288 /* } */
3289
3290 /* static uint16_t GetIndexSrc(struct comedi_device *dev, struct enc_private *k ) */
3291 /* { */
3292 /* return ( k->GetMode(dev, k ) >> STDBIT_INDXSRC ) & 1; */
3293 /* } */
3294
3295 /* Generate an index pulse. */
3296
3297 static void PulseIndex_A(struct comedi_device *dev, struct enc_private *k)
3298 {
3299 register uint16_t cra;
3300
3301 DEBUG("PulseIndex_A: pulse index enter\n");
3302
3303 cra = DEBIread(dev, k->MyCRA); /* Pulse index. */
3304 DEBIwrite(dev, k->MyCRA, (uint16_t) (cra ^ CRAMSK_INDXPOL_A));
3305 DEBUG("PulseIndex_A: pulse index step1\n");
3306 DEBIwrite(dev, k->MyCRA, cra);
3307 }
3308
3309 static void PulseIndex_B(struct comedi_device *dev, struct enc_private *k)
3310 {
3311 register uint16_t crb;
3312
3313 crb = DEBIread(dev, k->MyCRB) & ~CRBMSK_INTCTRL; /* Pulse index. */
3314 DEBIwrite(dev, k->MyCRB, (uint16_t) (crb ^ CRBMSK_INDXPOL_B));
3315 DEBIwrite(dev, k->MyCRB, crb);
3316 }
3317
3318 /* Write value into counter preload register. */
3319
3320 static void Preload(struct comedi_device *dev, struct enc_private *k,
3321 uint32_t value)
3322 {
3323 DEBUG("Preload: preload enter\n");
3324 DEBIwrite(dev, (uint16_t) (k->MyLatchLsw), (uint16_t) value); /* Write value to preload register. */
3325 DEBUG("Preload: preload step 1\n");
3326 DEBIwrite(dev, (uint16_t) (k->MyLatchLsw + 2),
3327 (uint16_t) (value >> 16));
3328 }
3329
3330 static void CountersInit(struct comedi_device *dev)
3331 {
3332 int chan;
3333 struct enc_private *k;
3334 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
3335 /* index. */
3336 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
3337 (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is counter. */
3338 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
3339 (CNTDIR_UP << BF_CLKPOL) | /* Count direction is up. */
3340 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
3341 (CLKENAB_INDEX << BF_CLKENAB); /* Enabled by index */
3342
3343 /* Disable all counter interrupts and clear any captured counter events. */
3344 for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) {
3345 k = &encpriv[chan];
3346 k->SetMode(dev, k, Setup, TRUE);
3347 k->SetIntSrc(dev, k, 0);
3348 k->ResetCapFlags(dev, k);
3349 k->SetEnable(dev, k, CLKENAB_ALWAYS);
3350 }
3351 DEBUG("CountersInit: counters initialized\n");
3352
3353 }
Tomato firmware and modifications.