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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / staging / comedi / drivers / ni_labpc.c
blob61d62de1ea93fee96e5d67080f5a88198b4090fc
1 /*
2 comedi/drivers/ni_labpc.c
3 Driver for National Instruments Lab-PC series boards and compatibles
4 Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19
20 ************************************************************************
21 */
22 /*
23 Driver: ni_labpc
24 Description: National Instruments Lab-PC (& compatibles)
25 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
26 Devices: [National Instruments] Lab-PC-1200 (labpc-1200),
27 Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc)
28 Status: works
29
30 Tested with lab-pc-1200. For the older Lab-PC+, not all input ranges
31 and analog references will work, the available ranges/arefs will
32 depend on how you have configured the jumpers on your board
33 (see your owner's manual).
34
35 Kernel-level ISA plug-and-play support for the lab-pc-1200
36 boards has not
37 yet been added to the driver, mainly due to the fact that
38 I don't know the device id numbers. If you have one
39 of these boards,
40 please file a bug report at https://bugs.comedi.org/
41 so I can get the necessary information from you.
42
43 The 1200 series boards have onboard calibration dacs for correcting
44 analog input/output offsets and gains. The proper settings for these
45 caldacs are stored on the board's eeprom. To read the caldac values
46 from the eeprom and store them into a file that can be then be used by
47 comedilib, use the comedi_calibrate program.
48
49 Configuration options - ISA boards:
50 [0] - I/O port base address
51 [1] - IRQ (optional, required for timed or externally triggered conversions)
52 [2] - DMA channel (optional)
53
54 Configuration options - PCI boards:
55 [0] - bus (optional)
56 [1] - slot (optional)
57
58 The Lab-pc+ has quirky chanlist requirements
59 when scanning multiple channels. Multiple channel scan
60 sequence must start at highest channel, then decrement down to
61 channel 0. The rest of the cards can scan down like lab-pc+ or scan
62 up from channel zero. Chanlists consisting of all one channel
63 are also legal, and allow you to pace conversions in bursts.
64
65 */
66
67 /*
68
69 NI manuals:
70 341309a (labpc-1200 register manual)
71 340914a (pci-1200)
72 320502b (lab-pc+)
73
74 */
75
76 #undef LABPC_DEBUG
77 /* #define LABPC_DEBUG enable debugging messages */
78
79 #include <linux/interrupt.h>
80 #include <linux/slab.h>
81 #include "../comedidev.h"
82
83 #include <linux/delay.h>
84 #include <asm/dma.h>
85
86 #include "8253.h"
87 #include "8255.h"
88 #include "mite.h"
89 #include "comedi_fc.h"
90 #include "ni_labpc.h"
91
92 #define DRV_NAME "ni_labpc"
93
94 /* size of io region used by board */
95 #define LABPC_SIZE 32
96 /* 2 MHz master clock */
97 #define LABPC_TIMER_BASE 500
98
99 /* Registers for the lab-pc+ */
100
101 /* write-only registers */
102 #define COMMAND1_REG 0x0
103 #define ADC_GAIN_MASK (0x7 << 4)
104 #define ADC_CHAN_BITS(x) ((x) & 0x7)
105 /* enables multi channel scans */
106 #define ADC_SCAN_EN_BIT 0x80
107 #define COMMAND2_REG 0x1
108 /* enable pretriggering (used in conjunction with SWTRIG) */
109 #define PRETRIG_BIT 0x1
110 /* enable paced conversions on external trigger */
111 #define HWTRIG_BIT 0x2
112 /* enable paced conversions */
113 #define SWTRIG_BIT 0x4
114 /* use two cascaded counters for pacing */
115 #define CASCADE_BIT 0x8
116 #define DAC_PACED_BIT(channel) (0x40 << ((channel) & 0x1))
117 #define COMMAND3_REG 0x2
118 /* enable dma transfers */
119 #define DMA_EN_BIT 0x1
120 /* enable interrupts for 8255 */
121 #define DIO_INTR_EN_BIT 0x2
122 /* enable dma terminal count interrupt */
123 #define DMATC_INTR_EN_BIT 0x4
124 /* enable timer interrupt */
125 #define TIMER_INTR_EN_BIT 0x8
126 /* enable error interrupt */
127 #define ERR_INTR_EN_BIT 0x10
128 /* enable fifo not empty interrupt */
129 #define ADC_FNE_INTR_EN_BIT 0x20
130 #define ADC_CONVERT_REG 0x3
131 #define DAC_LSB_REG(channel) (0x4 + 2 * ((channel) & 0x1))
132 #define DAC_MSB_REG(channel) (0x5 + 2 * ((channel) & 0x1))
133 #define ADC_CLEAR_REG 0x8
134 #define DMATC_CLEAR_REG 0xa
135 #define TIMER_CLEAR_REG 0xc
136 /* 1200 boards only */
137 #define COMMAND6_REG 0xe
138 /* select ground or common-mode reference */
139 #define ADC_COMMON_BIT 0x1
140 /* adc unipolar */
141 #define ADC_UNIP_BIT 0x2
142 /* dac unipolar */
143 #define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1))
144 /* enable fifo half full interrupt */
145 #define ADC_FHF_INTR_EN_BIT 0x20
146 /* enable interrupt on end of hardware count */
147 #define A1_INTR_EN_BIT 0x40
148 /* scan up from channel zero instead of down to zero */
149 #define ADC_SCAN_UP_BIT 0x80
150 #define COMMAND4_REG 0xf
151 /* enables 'interval' scanning */
152 #define INTERVAL_SCAN_EN_BIT 0x1
153 /* enables external signal on counter b1 output to trigger scan */
154 #define EXT_SCAN_EN_BIT 0x2
155 /* chooses direction (output or input) for EXTCONV* line */
156 #define EXT_CONVERT_OUT_BIT 0x4
157 /* chooses differential inputs for adc (in conjunction with board jumper) */
158 #define ADC_DIFF_BIT 0x8
159 #define EXT_CONVERT_DISABLE_BIT 0x10
160 /* 1200 boards only, calibration stuff */
161 #define COMMAND5_REG 0x1c
162 /* enable eeprom for write */
163 #define EEPROM_WRITE_UNPROTECT_BIT 0x4
164 /* enable dithering */
165 #define DITHER_EN_BIT 0x8
166 /* load calibration dac */
167 #define CALDAC_LOAD_BIT 0x10
168 /* serial clock - rising edge writes, falling edge reads */
169 #define SCLOCK_BIT 0x20
170 /* serial data bit for writing to eeprom or calibration dacs */
171 #define SDATA_BIT 0x40
172 /* enable eeprom for read/write */
173 #define EEPROM_EN_BIT 0x80
174 #define INTERVAL_COUNT_REG 0x1e
175 #define INTERVAL_LOAD_REG 0x1f
176 #define INTERVAL_LOAD_BITS 0x1
177
178 /* read-only registers */
179 #define STATUS1_REG 0x0
180 /* data is available in fifo */
181 #define DATA_AVAIL_BIT 0x1
182 /* overrun has occurred */
183 #define OVERRUN_BIT 0x2
184 /* fifo overflow */
185 #define OVERFLOW_BIT 0x4
186 /* timer interrupt has occured */
187 #define TIMER_BIT 0x8
188 /* dma terminal count has occured */
189 #define DMATC_BIT 0x10
190 /* external trigger has occured */
191 #define EXT_TRIG_BIT 0x40
192 /* 1200 boards only */
193 #define STATUS2_REG 0x1d
194 /* programmable eeprom serial output */
195 #define EEPROM_OUT_BIT 0x1
196 /* counter A1 terminal count */
197 #define A1_TC_BIT 0x2
198 /* fifo not half full */
199 #define FNHF_BIT 0x4
200 #define ADC_FIFO_REG 0xa
201
202 #define DIO_BASE_REG 0x10
203 #define COUNTER_A_BASE_REG 0x14
204 #define COUNTER_A_CONTROL_REG (COUNTER_A_BASE_REG + 0x3)
205 /* check modes put conversion pacer output in harmless state (a0 mode 2) */
206 #define INIT_A0_BITS 0x14
207 /* put hardware conversion counter output in harmless state (a1 mode 0) */
208 #define INIT_A1_BITS 0x70
209 #define COUNTER_B_BASE_REG 0x18
210
211 static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it);
212 static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
213 static irqreturn_t labpc_interrupt(int irq, void *d);
214 static int labpc_drain_fifo(struct comedi_device *dev);
215 static void labpc_drain_dma(struct comedi_device *dev);
216 static void handle_isa_dma(struct comedi_device *dev);
217 static void labpc_drain_dregs(struct comedi_device *dev);
218 static int labpc_ai_cmdtest(struct comedi_device *dev,
219 struct comedi_subdevice *s, struct comedi_cmd *cmd);
220 static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
221 static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
222 struct comedi_insn *insn, unsigned int *data);
223 static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
224 struct comedi_insn *insn, unsigned int *data);
225 static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
226 struct comedi_insn *insn, unsigned int *data);
227 static int labpc_calib_read_insn(struct comedi_device *dev,
228 struct comedi_subdevice *s,
229 struct comedi_insn *insn, unsigned int *data);
230 static int labpc_calib_write_insn(struct comedi_device *dev,
231 struct comedi_subdevice *s,
232 struct comedi_insn *insn, unsigned int *data);
233 static int labpc_eeprom_read_insn(struct comedi_device *dev,
234 struct comedi_subdevice *s,
235 struct comedi_insn *insn, unsigned int *data);
236 static int labpc_eeprom_write_insn(struct comedi_device *dev,
237 struct comedi_subdevice *s,
238 struct comedi_insn *insn,
239 unsigned int *data);
240 static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd);
241 static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd);
242 #ifdef CONFIG_COMEDI_PCI
243 static int labpc_find_device(struct comedi_device *dev, int bus, int slot);
244 #endif
245 static int labpc_dio_mem_callback(int dir, int port, int data,
246 unsigned long arg);
247 static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
248 unsigned int num_bits);
249 static unsigned int labpc_serial_in(struct comedi_device *dev);
250 static unsigned int labpc_eeprom_read(struct comedi_device *dev,
251 unsigned int address);
252 static unsigned int labpc_eeprom_read_status(struct comedi_device *dev);
253 static unsigned int labpc_eeprom_write(struct comedi_device *dev,
254 unsigned int address,
255 unsigned int value);
256 static void write_caldac(struct comedi_device *dev, unsigned int channel,
257 unsigned int value);
258
259 enum scan_mode {
260 MODE_SINGLE_CHAN,
261 MODE_SINGLE_CHAN_INTERVAL,
262 MODE_MULT_CHAN_UP,
263 MODE_MULT_CHAN_DOWN,
264 };
265
266 /* analog input ranges */
267 #define NUM_LABPC_PLUS_AI_RANGES 16
268 /* indicates unipolar ranges */
269 static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = {
270 0,
271 0,
272 0,
273 0,
274 0,
275 0,
276 0,
277 0,
278 1,
279 1,
280 1,
281 1,
282 1,
283 1,
284 1,
285 1,
286 };
287
288 /* map range index to gain bits */
289 static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = {
290 0x00,
291 0x10,
292 0x20,
293 0x30,
294 0x40,
295 0x50,
296 0x60,
297 0x70,
298 0x00,
299 0x10,
300 0x20,
301 0x30,
302 0x40,
303 0x50,
304 0x60,
305 0x70,
306 };
307
308 static const struct comedi_lrange range_labpc_plus_ai = {
309 NUM_LABPC_PLUS_AI_RANGES,
310 {
311 BIP_RANGE(5),
312 BIP_RANGE(4),
313 BIP_RANGE(2.5),
314 BIP_RANGE(1),
315 BIP_RANGE(0.5),
316 BIP_RANGE(0.25),
317 BIP_RANGE(0.1),
318 BIP_RANGE(0.05),
319 UNI_RANGE(10),
320 UNI_RANGE(8),
321 UNI_RANGE(5),
322 UNI_RANGE(2),
323 UNI_RANGE(1),
324 UNI_RANGE(0.5),
325 UNI_RANGE(0.2),
326 UNI_RANGE(0.1),
327 }
328 };
329
330 #define NUM_LABPC_1200_AI_RANGES 14
331 /* indicates unipolar ranges */
332 const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = {
333 0,
334 0,
335 0,
336 0,
337 0,
338 0,
339 0,
340 1,
341 1,
342 1,
343 1,
344 1,
345 1,
346 1,
347 };
348
349 /* map range index to gain bits */
350 const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = {
351 0x00,
352 0x20,
353 0x30,
354 0x40,
355 0x50,
356 0x60,
357 0x70,
358 0x00,
359 0x20,
360 0x30,
361 0x40,
362 0x50,
363 0x60,
364 0x70,
365 };
366
367 const struct comedi_lrange range_labpc_1200_ai = {
368 NUM_LABPC_1200_AI_RANGES,
369 {
370 BIP_RANGE(5),
371 BIP_RANGE(2.5),
372 BIP_RANGE(1),
373 BIP_RANGE(0.5),
374 BIP_RANGE(0.25),
375 BIP_RANGE(0.1),
376 BIP_RANGE(0.05),
377 UNI_RANGE(10),
378 UNI_RANGE(5),
379 UNI_RANGE(2),
380 UNI_RANGE(1),
381 UNI_RANGE(0.5),
382 UNI_RANGE(0.2),
383 UNI_RANGE(0.1),
384 }
385 };
386
387 /* analog output ranges */
388 #define AO_RANGE_IS_UNIPOLAR 0x1
389 static const struct comedi_lrange range_labpc_ao = {
390 2,
391 {
392 BIP_RANGE(5),
393 UNI_RANGE(10),
394 }
395 };
396
397 /* functions that do inb/outb and readb/writeb so we can use
398 * function pointers to decide which to use */
399 static inline unsigned int labpc_inb(unsigned long address)
400 {
401 return inb(address);
402 }
403
404 static inline void labpc_outb(unsigned int byte, unsigned long address)
405 {
406 outb(byte, address);
407 }
408
409 static inline unsigned int labpc_readb(unsigned long address)
410 {
411 return readb((void *)address);
412 }
413
414 static inline void labpc_writeb(unsigned int byte, unsigned long address)
415 {
416 writeb(byte, (void *)address);
417 }
418
419 static const struct labpc_board_struct labpc_boards[] = {
420 {
421 .name = "lab-pc-1200",
422 .ai_speed = 10000,
423 .bustype = isa_bustype,
424 .register_layout = labpc_1200_layout,
425 .has_ao = 1,
426 .ai_range_table = &range_labpc_1200_ai,
427 .ai_range_code = labpc_1200_ai_gain_bits,
428 .ai_range_is_unipolar = labpc_1200_is_unipolar,
429 .ai_scan_up = 1,
430 .memory_mapped_io = 0,
431 },
432 {
433 .name = "lab-pc-1200ai",
434 .ai_speed = 10000,
435 .bustype = isa_bustype,
436 .register_layout = labpc_1200_layout,
437 .has_ao = 0,
438 .ai_range_table = &range_labpc_1200_ai,
439 .ai_range_code = labpc_1200_ai_gain_bits,
440 .ai_range_is_unipolar = labpc_1200_is_unipolar,
441 .ai_scan_up = 1,
442 .memory_mapped_io = 0,
443 },
444 {
445 .name = "lab-pc+",
446 .ai_speed = 12000,
447 .bustype = isa_bustype,
448 .register_layout = labpc_plus_layout,
449 .has_ao = 1,
450 .ai_range_table = &range_labpc_plus_ai,
451 .ai_range_code = labpc_plus_ai_gain_bits,
452 .ai_range_is_unipolar = labpc_plus_is_unipolar,
453 .ai_scan_up = 0,
454 .memory_mapped_io = 0,
455 },
456 #ifdef CONFIG_COMEDI_PCI
457 {
458 .name = "pci-1200",
459 .device_id = 0x161,
460 .ai_speed = 10000,
461 .bustype = pci_bustype,
462 .register_layout = labpc_1200_layout,
463 .has_ao = 1,
464 .ai_range_table = &range_labpc_1200_ai,
465 .ai_range_code = labpc_1200_ai_gain_bits,
466 .ai_range_is_unipolar = labpc_1200_is_unipolar,
467 .ai_scan_up = 1,
468 .memory_mapped_io = 1,
469 },
470 /* dummy entry so pci board works when comedi_config is passed driver name */
471 {
472 .name = DRV_NAME,
473 .bustype = pci_bustype,
474 },
475 #endif
476 };
477
478 /*
479 * Useful for shorthand access to the particular board structure
480 */
481 #define thisboard ((struct labpc_board_struct *)dev->board_ptr)
482
483 /* size in bytes of dma buffer */
484 static const int dma_buffer_size = 0xff00;
485 /* 2 bytes per sample */
486 static const int sample_size = 2;
487
488 #define devpriv ((struct labpc_private *)dev->private)
489
490 static struct comedi_driver driver_labpc = {
491 .driver_name = DRV_NAME,
492 .module = THIS_MODULE,
493 .attach = labpc_attach,
494 .detach = labpc_common_detach,
495 .num_names = ARRAY_SIZE(labpc_boards),
496 .board_name = &labpc_boards[0].name,
497 .offset = sizeof(struct labpc_board_struct),
498 };
499
500 #ifdef CONFIG_COMEDI_PCI
501 static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = {
502 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x161)},
503 {0}
504 };
505
506 MODULE_DEVICE_TABLE(pci, labpc_pci_table);
507 #endif /* CONFIG_COMEDI_PCI */
508
509 static inline int labpc_counter_load(struct comedi_device *dev,
510 unsigned long base_address,
511 unsigned int counter_number,
512 unsigned int count, unsigned int mode)
513 {
514 if (thisboard->memory_mapped_io)
515 return i8254_mm_load((void *)base_address, 0, counter_number,
516 count, mode);
517 else
518 return i8254_load(base_address, 0, counter_number, count, mode);
519 }
520
521 int labpc_common_attach(struct comedi_device *dev, unsigned long iobase,
522 unsigned int irq, unsigned int dma_chan)
523 {
524 struct comedi_subdevice *s;
525 int i;
526 unsigned long dma_flags, isr_flags;
527 short lsb, msb;
528
529 printk(KERN_ERR "comedi%d: ni_labpc: %s, io 0x%lx", dev->minor,
530 thisboard->name,
531 iobase);
532 if (irq)
533 printk(", irq %u", irq);
534 if (dma_chan)
535 printk(", dma %u", dma_chan);
536 printk("\n");
537
538 if (iobase == 0) {
539 printk(KERN_ERR "io base address is zero!\n");
540 return -EINVAL;
541 }
542 /* request io regions for isa boards */
543 if (thisboard->bustype == isa_bustype) {
544 /* check if io addresses are available */
545 if (!request_region(iobase, LABPC_SIZE,
546 driver_labpc.driver_name)) {
547 printk(KERN_ERR "I/O port conflict\n");
548 return -EIO;
549 }
550 }
551 dev->iobase = iobase;
552
553 if (thisboard->memory_mapped_io) {
554 devpriv->read_byte = labpc_readb;
555 devpriv->write_byte = labpc_writeb;
556 } else {
557 devpriv->read_byte = labpc_inb;
558 devpriv->write_byte = labpc_outb;
559 }
560 /* initialize board's command registers */
561 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
562 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
563 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
564 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
565 if (thisboard->register_layout == labpc_1200_layout) {
566 devpriv->write_byte(devpriv->command5_bits,
567 dev->iobase + COMMAND5_REG);
568 devpriv->write_byte(devpriv->command6_bits,
569 dev->iobase + COMMAND6_REG);
570 }
571
572 /* grab our IRQ */
573 if (irq) {
574 isr_flags = 0;
575 if (thisboard->bustype == pci_bustype
576 || thisboard->bustype == pcmcia_bustype)
577 isr_flags |= IRQF_SHARED;
578 if (request_irq(irq, labpc_interrupt, isr_flags,
579 driver_labpc.driver_name, dev)) {
580 printk(KERN_ERR "unable to allocate irq %u\n", irq);
581 return -EINVAL;
582 }
583 }
584 dev->irq = irq;
585
586 /* grab dma channel */
587 if (dma_chan > 3) {
588 printk(KERN_ERR " invalid dma channel %u\n", dma_chan);
589 return -EINVAL;
590 } else if (dma_chan) {
591 /* allocate dma buffer */
592 devpriv->dma_buffer =
593 kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA);
594 if (devpriv->dma_buffer == NULL) {
595 printk(KERN_ERR " failed to allocate dma buffer\n");
596 return -ENOMEM;
597 }
598 if (request_dma(dma_chan, driver_labpc.driver_name)) {
599 printk(KERN_ERR " failed to allocate dma channel %u\n",
600 dma_chan);
601 return -EINVAL;
602 }
603 devpriv->dma_chan = dma_chan;
604 dma_flags = claim_dma_lock();
605 disable_dma(devpriv->dma_chan);
606 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ);
607 release_dma_lock(dma_flags);
608 }
609
610 dev->board_name = thisboard->name;
611
612 if (alloc_subdevices(dev, 5) < 0)
613 return -ENOMEM;
614
615 /* analog input subdevice */
616 s = dev->subdevices + 0;
617 dev->read_subdev = s;
618 s->type = COMEDI_SUBD_AI;
619 s->subdev_flags =
620 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ;
621 s->n_chan = 8;
622 s->len_chanlist = 8;
623 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */
624 s->range_table = thisboard->ai_range_table;
625 s->do_cmd = labpc_ai_cmd;
626 s->do_cmdtest = labpc_ai_cmdtest;
627 s->insn_read = labpc_ai_rinsn;
628 s->cancel = labpc_cancel;
629
630 /* analog output */
631 s = dev->subdevices + 1;
632 if (thisboard->has_ao) {
633 /*
634 * Could provide command support, except it only has a
635 * one sample hardware buffer for analog output and no
636 * underrun flag.
637 */
638 s->type = COMEDI_SUBD_AO;
639 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND;
640 s->n_chan = NUM_AO_CHAN;
641 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */
642 s->range_table = &range_labpc_ao;
643 s->insn_read = labpc_ao_rinsn;
644 s->insn_write = labpc_ao_winsn;
645 /* initialize analog outputs to a known value */
646 for (i = 0; i < s->n_chan; i++) {
647 devpriv->ao_value[i] = s->maxdata / 2;
648 lsb = devpriv->ao_value[i] & 0xff;
649 msb = (devpriv->ao_value[i] >> 8) & 0xff;
650 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i));
651 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i));
652 }
653 } else {
654 s->type = COMEDI_SUBD_UNUSED;
655 }
656
657 /* 8255 dio */
658 s = dev->subdevices + 2;
659 /* if board uses io memory we have to give a custom callback
660 * function to the 8255 driver */
661 if (thisboard->memory_mapped_io)
662 subdev_8255_init(dev, s, labpc_dio_mem_callback,
663 (unsigned long)(dev->iobase + DIO_BASE_REG));
664 else
665 subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG);
666
667 /* calibration subdevices for boards that have one */
668 s = dev->subdevices + 3;
669 if (thisboard->register_layout == labpc_1200_layout) {
670 s->type = COMEDI_SUBD_CALIB;
671 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
672 s->n_chan = 16;
673 s->maxdata = 0xff;
674 s->insn_read = labpc_calib_read_insn;
675 s->insn_write = labpc_calib_write_insn;
676
677 for (i = 0; i < s->n_chan; i++)
678 write_caldac(dev, i, s->maxdata / 2);
679 } else
680 s->type = COMEDI_SUBD_UNUSED;
681
682 /* EEPROM */
683 s = dev->subdevices + 4;
684 if (thisboard->register_layout == labpc_1200_layout) {
685 s->type = COMEDI_SUBD_MEMORY;
686 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
687 s->n_chan = EEPROM_SIZE;
688 s->maxdata = 0xff;
689 s->insn_read = labpc_eeprom_read_insn;
690 s->insn_write = labpc_eeprom_write_insn;
691
692 for (i = 0; i < EEPROM_SIZE; i++)
693 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i);
694 #ifdef LABPC_DEBUG
695 printk(KERN_ERR " eeprom:");
696 for (i = 0; i < EEPROM_SIZE; i++)
697 printk(" %i:0x%x ", i, devpriv->eeprom_data[i]);
698 printk("\n");
699 #endif
700 } else
701 s->type = COMEDI_SUBD_UNUSED;
702
703 return 0;
704 }
705
706 static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it)
707 {
708 unsigned long iobase = 0;
709 unsigned int irq = 0;
710 unsigned int dma_chan = 0;
711 #ifdef CONFIG_COMEDI_PCI
712 int retval;
713 #endif
714
715 /* allocate and initialize dev->private */
716 if (alloc_private(dev, sizeof(struct labpc_private)) < 0)
717 return -ENOMEM;
718
719 /* get base address, irq etc. based on bustype */
720 switch (thisboard->bustype) {
721 case isa_bustype:
722 iobase = it->options[0];
723 irq = it->options[1];
724 dma_chan = it->options[2];
725 break;
726 case pci_bustype:
727 #ifdef CONFIG_COMEDI_PCI
728 retval = labpc_find_device(dev, it->options[0], it->options[1]);
729 if (retval < 0)
730 return retval;
731 retval = mite_setup(devpriv->mite);
732 if (retval < 0)
733 return retval;
734 iobase = (unsigned long)devpriv->mite->daq_io_addr;
735 irq = mite_irq(devpriv->mite);
736 #else
737 printk(KERN_ERR " this driver has not been built with PCI "
738 "support.\n");
739 return -EINVAL;
740 #endif
741 break;
742 case pcmcia_bustype:
743 printk
744 (" this driver does not support pcmcia cards, use ni_labpc_cs.o\n");
745 return -EINVAL;
746 break;
747 default:
748 printk(KERN_ERR "bug! couldn't determine board type\n");
749 return -EINVAL;
750 break;
751 }
752
753 return labpc_common_attach(dev, iobase, irq, dma_chan);
754 }
755
756 /* adapted from ni_pcimio for finding mite based boards (pc-1200) */
757 #ifdef CONFIG_COMEDI_PCI
758 static int labpc_find_device(struct comedi_device *dev, int bus, int slot)
759 {
760 struct mite_struct *mite;
761 int i;
762 for (mite = mite_devices; mite; mite = mite->next) {
763 if (mite->used)
764 continue;
765 /* if bus/slot are specified then make sure we have the right bus/slot */
766 if (bus || slot) {
767 if (bus != mite->pcidev->bus->number
768 || slot != PCI_SLOT(mite->pcidev->devfn))
769 continue;
770 }
771 for (i = 0; i < driver_labpc.num_names; i++) {
772 if (labpc_boards[i].bustype != pci_bustype)
773 continue;
774 if (mite_device_id(mite) == labpc_boards[i].device_id) {
775 devpriv->mite = mite;
776 /* fixup board pointer, in case we were using the dummy "ni_labpc" entry */
777 dev->board_ptr = &labpc_boards[i];
778 return 0;
779 }
780 }
781 }
782 printk(KERN_ERR "no device found\n");
783 mite_list_devices();
784 return -EIO;
785 }
786 #endif
787
788 int labpc_common_detach(struct comedi_device *dev)
789 {
790 printk(KERN_ERR "comedi%d: ni_labpc: detach\n", dev->minor);
791
792 if (dev->subdevices)
793 subdev_8255_cleanup(dev, dev->subdevices + 2);
794
795 /* only free stuff if it has been allocated by _attach */
796 if (devpriv->dma_buffer)
797 kfree(devpriv->dma_buffer);
798 if (devpriv->dma_chan)
799 free_dma(devpriv->dma_chan);
800 if (dev->irq)
801 free_irq(dev->irq, dev);
802 if (thisboard->bustype == isa_bustype && dev->iobase)
803 release_region(dev->iobase, LABPC_SIZE);
804 #ifdef CONFIG_COMEDI_PCI
805 if (devpriv->mite)
806 mite_unsetup(devpriv->mite);
807 #endif
808
809 return 0;
810 };
811
812 static void labpc_clear_adc_fifo(const struct comedi_device *dev)
813 {
814 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
815 devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
816 devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
817 }
818
819 static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
820 {
821 unsigned long flags;
822
823 spin_lock_irqsave(&dev->spinlock, flags);
824 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
825 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
826 spin_unlock_irqrestore(&dev->spinlock, flags);
827
828 devpriv->command3_bits = 0;
829 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
830
831 return 0;
832 }
833
834 static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd)
835 {
836 if (cmd->chanlist_len == 1)
837 return MODE_SINGLE_CHAN;
838
839 /* chanlist may be NULL during cmdtest. */
840 if (cmd->chanlist == NULL)
841 return MODE_MULT_CHAN_UP;
842
843 if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1]))
844 return MODE_SINGLE_CHAN_INTERVAL;
845
846 if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1]))
847 return MODE_MULT_CHAN_UP;
848
849 if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1]))
850 return MODE_MULT_CHAN_DOWN;
851
852 printk(KERN_ERR "ni_labpc: bug! this should never happen\n");
853
854 return 0;
855 }
856
857 static int labpc_ai_chanlist_invalid(const struct comedi_device *dev,
858 const struct comedi_cmd *cmd)
859 {
860 int mode, channel, range, aref, i;
861
862 if (cmd->chanlist == NULL)
863 return 0;
864
865 mode = labpc_ai_scan_mode(cmd);
866
867 if (mode == MODE_SINGLE_CHAN)
868 return 0;
869
870 if (mode == MODE_SINGLE_CHAN_INTERVAL) {
871 if (cmd->chanlist_len > 0xff) {
872 comedi_error(dev,
873 "ni_labpc: chanlist too long for single channel interval mode\n");
874 return 1;
875 }
876 }
877
878 channel = CR_CHAN(cmd->chanlist[0]);
879 range = CR_RANGE(cmd->chanlist[0]);
880 aref = CR_AREF(cmd->chanlist[0]);
881
882 for (i = 0; i < cmd->chanlist_len; i++) {
883
884 switch (mode) {
885 case MODE_SINGLE_CHAN_INTERVAL:
886 if (CR_CHAN(cmd->chanlist[i]) != channel) {
887 comedi_error(dev,
888 "channel scanning order specified in chanlist is not supported by hardware.\n");
889 return 1;
890 }
891 break;
892 case MODE_MULT_CHAN_UP:
893 if (CR_CHAN(cmd->chanlist[i]) != i) {
894 comedi_error(dev,
895 "channel scanning order specified in chanlist is not supported by hardware.\n");
896 return 1;
897 }
898 break;
899 case MODE_MULT_CHAN_DOWN:
900 if (CR_CHAN(cmd->chanlist[i]) !=
901 cmd->chanlist_len - i - 1) {
902 comedi_error(dev,
903 "channel scanning order specified in chanlist is not supported by hardware.\n");
904 return 1;
905 }
906 break;
907 default:
908 printk(KERN_ERR "ni_labpc: bug! in chanlist check\n");
909 return 1;
910 break;
911 }
912
913 if (CR_RANGE(cmd->chanlist[i]) != range) {
914 comedi_error(dev,
915 "entries in chanlist must all have the same range\n");
916 return 1;
917 }
918
919 if (CR_AREF(cmd->chanlist[i]) != aref) {
920 comedi_error(dev,
921 "entries in chanlist must all have the same reference\n");
922 return 1;
923 }
924 }
925
926 return 0;
927 }
928
929 static int labpc_use_continuous_mode(const struct comedi_cmd *cmd)
930 {
931 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN)
932 return 1;
933
934 if (cmd->scan_begin_src == TRIG_FOLLOW)
935 return 1;
936
937 return 0;
938 }
939
940 static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd)
941 {
942 if (cmd->convert_src != TRIG_TIMER)
943 return 0;
944
945 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
946 cmd->scan_begin_src == TRIG_TIMER)
947 return cmd->scan_begin_arg;
948
949 return cmd->convert_arg;
950 }
951
952 static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, unsigned int ns)
953 {
954 if (cmd->convert_src != TRIG_TIMER)
955 return;
956
957 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
958 cmd->scan_begin_src == TRIG_TIMER) {
959 cmd->scan_begin_arg = ns;
960 if (cmd->convert_arg > cmd->scan_begin_arg)
961 cmd->convert_arg = cmd->scan_begin_arg;
962 } else
963 cmd->convert_arg = ns;
964 }
965
966 static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd)
967 {
968 if (cmd->scan_begin_src != TRIG_TIMER)
969 return 0;
970
971 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
972 cmd->convert_src == TRIG_TIMER)
973 return 0;
974
975 return cmd->scan_begin_arg;
976 }
977
978 static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, unsigned int ns)
979 {
980 if (cmd->scan_begin_src != TRIG_TIMER)
981 return;
982
983 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
984 cmd->convert_src == TRIG_TIMER)
985 return;
986
987 cmd->scan_begin_arg = ns;
988 }
989
990 static int labpc_ai_cmdtest(struct comedi_device *dev,
991 struct comedi_subdevice *s, struct comedi_cmd *cmd)
992 {
993 int err = 0;
994 int tmp, tmp2;
995 int stop_mask;
996
997 /* step 1: make sure trigger sources are trivially valid */
998
999 tmp = cmd->start_src;
1000 cmd->start_src &= TRIG_NOW | TRIG_EXT;
1001 if (!cmd->start_src || tmp != cmd->start_src)
1002 err++;
1003
1004 tmp = cmd->scan_begin_src;
1005 cmd->scan_begin_src &= TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT;
1006 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
1007 err++;
1008
1009 tmp = cmd->convert_src;
1010 cmd->convert_src &= TRIG_TIMER | TRIG_EXT;
1011 if (!cmd->convert_src || tmp != cmd->convert_src)
1012 err++;
1013
1014 tmp = cmd->scan_end_src;
1015 cmd->scan_end_src &= TRIG_COUNT;
1016 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
1017 err++;
1018
1019 tmp = cmd->stop_src;
1020 stop_mask = TRIG_COUNT | TRIG_NONE;
1021 if (thisboard->register_layout == labpc_1200_layout)
1022 stop_mask |= TRIG_EXT;
1023 cmd->stop_src &= stop_mask;
1024 if (!cmd->stop_src || tmp != cmd->stop_src)
1025 err++;
1026
1027 if (err)
1028 return 1;
1029
1030 /* step 2: make sure trigger sources are unique and mutually compatible */
1031
1032 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT)
1033 err++;
1034 if (cmd->scan_begin_src != TRIG_TIMER &&
1035 cmd->scan_begin_src != TRIG_FOLLOW &&
1036 cmd->scan_begin_src != TRIG_EXT)
1037 err++;
1038 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT)
1039 err++;
1040 if (cmd->stop_src != TRIG_COUNT &&
1041 cmd->stop_src != TRIG_EXT && cmd->stop_src != TRIG_NONE)
1042 err++;
1043
1044 /* can't have external stop and start triggers at once */
1045 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT)
1046 err++;
1047
1048 if (err)
1049 return 2;
1050
1051 /* step 3: make sure arguments are trivially compatible */
1052
1053 if (cmd->start_arg == TRIG_NOW && cmd->start_arg != 0) {
1054 cmd->start_arg = 0;
1055 err++;
1056 }
1057
1058 if (!cmd->chanlist_len)
1059 err++;
1060
1061 if (cmd->scan_end_arg != cmd->chanlist_len) {
1062 cmd->scan_end_arg = cmd->chanlist_len;
1063 err++;
1064 }
1065
1066 if (cmd->convert_src == TRIG_TIMER) {
1067 if (cmd->convert_arg < thisboard->ai_speed) {
1068 cmd->convert_arg = thisboard->ai_speed;
1069 err++;
1070 }
1071 }
1072 /* make sure scan timing is not too fast */
1073 if (cmd->scan_begin_src == TRIG_TIMER) {
1074 if (cmd->convert_src == TRIG_TIMER &&
1075 cmd->scan_begin_arg <
1076 cmd->convert_arg * cmd->chanlist_len) {
1077 cmd->scan_begin_arg =
1078 cmd->convert_arg * cmd->chanlist_len;
1079 err++;
1080 }
1081 if (cmd->scan_begin_arg <
1082 thisboard->ai_speed * cmd->chanlist_len) {
1083 cmd->scan_begin_arg =
1084 thisboard->ai_speed * cmd->chanlist_len;
1085 err++;
1086 }
1087 }
1088 /* stop source */
1089 switch (cmd->stop_src) {
1090 case TRIG_COUNT:
1091 if (!cmd->stop_arg) {
1092 cmd->stop_arg = 1;
1093 err++;
1094 }
1095 break;
1096 case TRIG_NONE:
1097 if (cmd->stop_arg != 0) {
1098 cmd->stop_arg = 0;
1099 err++;
1100 }
1101 break;
1102 /*
1103 * TRIG_EXT doesn't care since it doesn't
1104 * trigger off a numbered channel
1105 */
1106 default:
1107 break;
1108 }
1109
1110 if (err)
1111 return 3;
1112
1113 /* step 4: fix up any arguments */
1114
1115 tmp = cmd->convert_arg;
1116 tmp2 = cmd->scan_begin_arg;
1117 labpc_adc_timing(dev, cmd);
1118 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg)
1119 err++;
1120
1121 if (err)
1122 return 4;
1123
1124 if (labpc_ai_chanlist_invalid(dev, cmd))
1125 return 5;
1126
1127 return 0;
1128 }
1129
1130 static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1131 {
1132 int channel, range, aref;
1133 unsigned long irq_flags;
1134 int ret;
1135 struct comedi_async *async = s->async;
1136 struct comedi_cmd *cmd = &async->cmd;
1137 enum transfer_type xfer;
1138 unsigned long flags;
1139
1140 if (!dev->irq) {
1141 comedi_error(dev, "no irq assigned, cannot perform command");
1142 return -1;
1143 }
1144
1145 range = CR_RANGE(cmd->chanlist[0]);
1146 aref = CR_AREF(cmd->chanlist[0]);
1147
1148 /* make sure board is disabled before setting up aquisition */
1149 spin_lock_irqsave(&dev->spinlock, flags);
1150 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1151 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1152 spin_unlock_irqrestore(&dev->spinlock, flags);
1153
1154 devpriv->command3_bits = 0;
1155 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1156
1157 /* initialize software conversion count */
1158 if (cmd->stop_src == TRIG_COUNT)
1159 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
1160
1161 /* setup hardware conversion counter */
1162 if (cmd->stop_src == TRIG_EXT) {
1163 /*
1164 * load counter a1 with count of 3
1165 * (pc+ manual says this is minimum allowed) using mode 0
1166 */
1167 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1168 1, 3, 0);
1169 if (ret < 0) {
1170 comedi_error(dev, "error loading counter a1");
1171 return -1;
1172 }
1173 } else /*
1174 * otherwise, just put a1 in mode 0
1175 * with no count to set its output low
1176 */
1177 devpriv->write_byte(INIT_A1_BITS,
1178 dev->iobase + COUNTER_A_CONTROL_REG);
1179
1180 /* figure out what method we will use to transfer data */
1181 if (devpriv->dma_chan && /* need a dma channel allocated */
1182 /*
1183 * dma unsafe at RT priority,
1184 * and too much setup time for TRIG_WAKE_EOS for
1185 */
1186 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 &&
1187 /* only available on the isa boards */
1188 thisboard->bustype == isa_bustype) {
1189 xfer = isa_dma_transfer;
1190 /* pc-plus has no fifo-half full interrupt */
1191 } else if (thisboard->register_layout == labpc_1200_layout &&
1192 /* wake-end-of-scan should interrupt on fifo not empty */
1193 (cmd->flags & TRIG_WAKE_EOS) == 0 &&
1194 /* make sure we are taking more than just a few points */
1195 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) {
1196 xfer = fifo_half_full_transfer;
1197 } else
1198 xfer = fifo_not_empty_transfer;
1199 devpriv->current_transfer = xfer;
1200
1201 /* setup command6 register for 1200 boards */
1202 if (thisboard->register_layout == labpc_1200_layout) {
1203 /* reference inputs to ground or common? */
1204 if (aref != AREF_GROUND)
1205 devpriv->command6_bits |= ADC_COMMON_BIT;
1206 else
1207 devpriv->command6_bits &= ~ADC_COMMON_BIT;
1208 /* bipolar or unipolar range? */
1209 if (thisboard->ai_range_is_unipolar[range])
1210 devpriv->command6_bits |= ADC_UNIP_BIT;
1211 else
1212 devpriv->command6_bits &= ~ADC_UNIP_BIT;
1213 /* interrupt on fifo half full? */
1214 if (xfer == fifo_half_full_transfer)
1215 devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT;
1216 else
1217 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1218 /* enable interrupt on counter a1 terminal count? */
1219 if (cmd->stop_src == TRIG_EXT)
1220 devpriv->command6_bits |= A1_INTR_EN_BIT;
1221 else
1222 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1223 /* are we scanning up or down through channels? */
1224 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP)
1225 devpriv->command6_bits |= ADC_SCAN_UP_BIT;
1226 else
1227 devpriv->command6_bits &= ~ADC_SCAN_UP_BIT;
1228 /* write to register */
1229 devpriv->write_byte(devpriv->command6_bits,
1230 dev->iobase + COMMAND6_REG);
1231 }
1232
1233 /* setup channel list, etc (command1 register) */
1234 devpriv->command1_bits = 0;
1235 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP)
1236 channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
1237 else
1238 channel = CR_CHAN(cmd->chanlist[0]);
1239 /* munge channel bits for differential / scan disabled mode */
1240 if (labpc_ai_scan_mode(cmd) != MODE_SINGLE_CHAN && aref == AREF_DIFF)
1241 channel *= 2;
1242 devpriv->command1_bits |= ADC_CHAN_BITS(channel);
1243 devpriv->command1_bits |= thisboard->ai_range_code[range];
1244 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1245 /* manual says to set scan enable bit on second pass */
1246 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP ||
1247 labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_DOWN) {
1248 devpriv->command1_bits |= ADC_SCAN_EN_BIT;
1249 /* need a brief delay before enabling scan, or scan
1250 * list will get screwed when you switch
1251 * between scan up to scan down mode - dunno why */
1252 udelay(1);
1253 devpriv->write_byte(devpriv->command1_bits,
1254 dev->iobase + COMMAND1_REG);
1255 }
1256 /* setup any external triggering/pacing (command4 register) */
1257 devpriv->command4_bits = 0;
1258 if (cmd->convert_src != TRIG_EXT)
1259 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1260 if (labpc_use_continuous_mode(cmd) == 0) {
1261 devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT;
1262 if (cmd->scan_begin_src == TRIG_EXT)
1263 devpriv->command4_bits |= EXT_SCAN_EN_BIT;
1264 }
1265 /* single-ended/differential */
1266 if (aref == AREF_DIFF)
1267 devpriv->command4_bits |= ADC_DIFF_BIT;
1268 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1269
1270 devpriv->write_byte(cmd->chanlist_len,
1271 dev->iobase + INTERVAL_COUNT_REG);
1272 /* load count */
1273 devpriv->write_byte(INTERVAL_LOAD_BITS,
1274 dev->iobase + INTERVAL_LOAD_REG);
1275
1276 if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) {
1277 /* set up pacing */
1278 labpc_adc_timing(dev, cmd);
1279 /* load counter b0 in mode 3 */
1280 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1281 0, devpriv->divisor_b0, 3);
1282 if (ret < 0) {
1283 comedi_error(dev, "error loading counter b0");
1284 return -1;
1285 }
1286 }
1287 /* set up conversion pacing */
1288 if (labpc_ai_convert_period(cmd)) {
1289 /* load counter a0 in mode 2 */
1290 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1291 0, devpriv->divisor_a0, 2);
1292 if (ret < 0) {
1293 comedi_error(dev, "error loading counter a0");
1294 return -1;
1295 }
1296 } else
1297 devpriv->write_byte(INIT_A0_BITS,
1298 dev->iobase + COUNTER_A_CONTROL_REG);
1299
1300 /* set up scan pacing */
1301 if (labpc_ai_scan_period(cmd)) {
1302 /* load counter b1 in mode 2 */
1303 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1304 1, devpriv->divisor_b1, 2);
1305 if (ret < 0) {
1306 comedi_error(dev, "error loading counter b1");
1307 return -1;
1308 }
1309 }
1310
1311 labpc_clear_adc_fifo(dev);
1312
1313 /* set up dma transfer */
1314 if (xfer == isa_dma_transfer) {
1315 irq_flags = claim_dma_lock();
1316 disable_dma(devpriv->dma_chan);
1317 /* clear flip-flop to make sure 2-byte registers for
1318 * count and address get set correctly */
1319 clear_dma_ff(devpriv->dma_chan);
1320 set_dma_addr(devpriv->dma_chan,
1321 virt_to_bus(devpriv->dma_buffer));
1322 /* set appropriate size of transfer */
1323 devpriv->dma_transfer_size = labpc_suggest_transfer_size(*cmd);
1324 if (cmd->stop_src == TRIG_COUNT &&
1325 devpriv->count * sample_size < devpriv->dma_transfer_size) {
1326 devpriv->dma_transfer_size =
1327 devpriv->count * sample_size;
1328 }
1329 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size);
1330 enable_dma(devpriv->dma_chan);
1331 release_dma_lock(irq_flags);
1332 /* enable board's dma */
1333 devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT;
1334 } else
1335 devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT;
1336
1337 /* enable error interrupts */
1338 devpriv->command3_bits |= ERR_INTR_EN_BIT;
1339 /* enable fifo not empty interrupt? */
1340 if (xfer == fifo_not_empty_transfer)
1341 devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT;
1342 else
1343 devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT;
1344 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1345
1346 /* startup aquisition */
1347
1348 /* command2 reg */
1349 /* use 2 cascaded counters for pacing */
1350 spin_lock_irqsave(&dev->spinlock, flags);
1351 devpriv->command2_bits |= CASCADE_BIT;
1352 switch (cmd->start_src) {
1353 case TRIG_EXT:
1354 devpriv->command2_bits |= HWTRIG_BIT;
1355 devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT;
1356 break;
1357 case TRIG_NOW:
1358 devpriv->command2_bits |= SWTRIG_BIT;
1359 devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT;
1360 break;
1361 default:
1362 comedi_error(dev, "bug with start_src");
1363 return -1;
1364 break;
1365 }
1366 switch (cmd->stop_src) {
1367 case TRIG_EXT:
1368 devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT;
1369 break;
1370 case TRIG_COUNT:
1371 case TRIG_NONE:
1372 break;
1373 default:
1374 comedi_error(dev, "bug with stop_src");
1375 return -1;
1376 }
1377 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1378 spin_unlock_irqrestore(&dev->spinlock, flags);
1379
1380 return 0;
1381 }
1382
1383 /* interrupt service routine */
1384 static irqreturn_t labpc_interrupt(int irq, void *d)
1385 {
1386 struct comedi_device *dev = d;
1387 struct comedi_subdevice *s = dev->read_subdev;
1388 struct comedi_async *async;
1389 struct comedi_cmd *cmd;
1390
1391 if (dev->attached == 0) {
1392 comedi_error(dev, "premature interrupt");
1393 return IRQ_HANDLED;
1394 }
1395
1396 async = s->async;
1397 cmd = &async->cmd;
1398 async->events = 0;
1399
1400 /* read board status */
1401 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1402 if (thisboard->register_layout == labpc_1200_layout)
1403 devpriv->status2_bits =
1404 devpriv->read_byte(dev->iobase + STATUS2_REG);
1405
1406 if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT |
1407 OVERRUN_BIT | DATA_AVAIL_BIT)) == 0
1408 && (devpriv->status2_bits & A1_TC_BIT) == 0
1409 && (devpriv->status2_bits & FNHF_BIT)) {
1410 return IRQ_NONE;
1411 }
1412
1413 if (devpriv->status1_bits & OVERRUN_BIT) {
1414 /* clear error interrupt */
1415 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1416 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1417 comedi_event(dev, s);
1418 comedi_error(dev, "overrun");
1419 return IRQ_HANDLED;
1420 }
1421
1422 if (devpriv->current_transfer == isa_dma_transfer) {
1423 /*
1424 * if a dma terminal count of external stop trigger
1425 * has occurred
1426 */
1427 if (devpriv->status1_bits & DMATC_BIT ||
1428 (thisboard->register_layout == labpc_1200_layout
1429 && devpriv->status2_bits & A1_TC_BIT)) {
1430 handle_isa_dma(dev);
1431 }
1432 } else
1433 labpc_drain_fifo(dev);
1434
1435 if (devpriv->status1_bits & TIMER_BIT) {
1436 comedi_error(dev, "handled timer interrupt?");
1437 /* clear it */
1438 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG);
1439 }
1440
1441 if (devpriv->status1_bits & OVERFLOW_BIT) {
1442 /* clear error interrupt */
1443 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1444 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1445 comedi_event(dev, s);
1446 comedi_error(dev, "overflow");
1447 return IRQ_HANDLED;
1448 }
1449 /* handle external stop trigger */
1450 if (cmd->stop_src == TRIG_EXT) {
1451 if (devpriv->status2_bits & A1_TC_BIT) {
1452 labpc_drain_dregs(dev);
1453 labpc_cancel(dev, s);
1454 async->events |= COMEDI_CB_EOA;
1455 }
1456 }
1457
1458 /* TRIG_COUNT end of acquisition */
1459 if (cmd->stop_src == TRIG_COUNT) {
1460 if (devpriv->count == 0) {
1461 labpc_cancel(dev, s);
1462 async->events |= COMEDI_CB_EOA;
1463 }
1464 }
1465
1466 comedi_event(dev, s);
1467 return IRQ_HANDLED;
1468 }
1469
1470 /* read all available samples from ai fifo */
1471 static int labpc_drain_fifo(struct comedi_device *dev)
1472 {
1473 unsigned int lsb, msb;
1474 short data;
1475 struct comedi_async *async = dev->read_subdev->async;
1476 const int timeout = 10000;
1477 unsigned int i;
1478
1479 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1480
1481 for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout;
1482 i++) {
1483 /* quit if we have all the data we want */
1484 if (async->cmd.stop_src == TRIG_COUNT) {
1485 if (devpriv->count == 0)
1486 break;
1487 devpriv->count--;
1488 }
1489 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1490 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1491 data = (msb << 8) | lsb;
1492 cfc_write_to_buffer(dev->read_subdev, data);
1493 devpriv->status1_bits =
1494 devpriv->read_byte(dev->iobase + STATUS1_REG);
1495 }
1496 if (i == timeout) {
1497 comedi_error(dev, "ai timeout, fifo never empties");
1498 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1499 return -1;
1500 }
1501
1502 return 0;
1503 }
1504
1505 static void labpc_drain_dma(struct comedi_device *dev)
1506 {
1507 struct comedi_subdevice *s = dev->read_subdev;
1508 struct comedi_async *async = s->async;
1509 int status;
1510 unsigned long flags;
1511 unsigned int max_points, num_points, residue, leftover;
1512 int i;
1513
1514 status = devpriv->status1_bits;
1515
1516 flags = claim_dma_lock();
1517 disable_dma(devpriv->dma_chan);
1518 /* clear flip-flop to make sure 2-byte registers for
1519 * count and address get set correctly */
1520 clear_dma_ff(devpriv->dma_chan);
1521
1522 /* figure out how many points to read */
1523 max_points = devpriv->dma_transfer_size / sample_size;
1524 /* residue is the number of points left to be done on the dma
1525 * transfer. It should always be zero at this point unless
1526 * the stop_src is set to external triggering.
1527 */
1528 residue = get_dma_residue(devpriv->dma_chan) / sample_size;
1529 num_points = max_points - residue;
1530 if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT)
1531 num_points = devpriv->count;
1532
1533 /* figure out how many points will be stored next time */
1534 leftover = 0;
1535 if (async->cmd.stop_src != TRIG_COUNT) {
1536 leftover = devpriv->dma_transfer_size / sample_size;
1537 } else if (devpriv->count > num_points) {
1538 leftover = devpriv->count - num_points;
1539 if (leftover > max_points)
1540 leftover = max_points;
1541 }
1542
1543 /* write data to comedi buffer */
1544 for (i = 0; i < num_points; i++)
1545 cfc_write_to_buffer(s, devpriv->dma_buffer[i]);
1546
1547 if (async->cmd.stop_src == TRIG_COUNT)
1548 devpriv->count -= num_points;
1549
1550 /* set address and count for next transfer */
1551 set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer));
1552 set_dma_count(devpriv->dma_chan, leftover * sample_size);
1553 release_dma_lock(flags);
1554
1555 async->events |= COMEDI_CB_BLOCK;
1556 }
1557
1558 static void handle_isa_dma(struct comedi_device *dev)
1559 {
1560 labpc_drain_dma(dev);
1561
1562 enable_dma(devpriv->dma_chan);
1563
1564 /* clear dma tc interrupt */
1565 devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG);
1566 }
1567
1568 /* makes sure all data acquired by board is transfered to comedi (used
1569 * when aquisition is terminated by stop_src == TRIG_EXT). */
1570 static void labpc_drain_dregs(struct comedi_device *dev)
1571 {
1572 if (devpriv->current_transfer == isa_dma_transfer)
1573 labpc_drain_dma(dev);
1574
1575 labpc_drain_fifo(dev);
1576 }
1577
1578 static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1579 struct comedi_insn *insn, unsigned int *data)
1580 {
1581 int i, n;
1582 int chan, range;
1583 int lsb, msb;
1584 int timeout = 1000;
1585 unsigned long flags;
1586
1587 /* disable timed conversions */
1588 spin_lock_irqsave(&dev->spinlock, flags);
1589 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1590 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1591 spin_unlock_irqrestore(&dev->spinlock, flags);
1592
1593 /* disable interrupt generation and dma */
1594 devpriv->command3_bits = 0;
1595 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1596
1597 /* set gain and channel */
1598 devpriv->command1_bits = 0;
1599 chan = CR_CHAN(insn->chanspec);
1600 range = CR_RANGE(insn->chanspec);
1601 devpriv->command1_bits |= thisboard->ai_range_code[range];
1602 /* munge channel bits for differential/scan disabled mode */
1603 if (CR_AREF(insn->chanspec) == AREF_DIFF)
1604 chan *= 2;
1605 devpriv->command1_bits |= ADC_CHAN_BITS(chan);
1606 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1607
1608 /* setup command6 register for 1200 boards */
1609 if (thisboard->register_layout == labpc_1200_layout) {
1610 /* reference inputs to ground or common? */
1611 if (CR_AREF(insn->chanspec) != AREF_GROUND)
1612 devpriv->command6_bits |= ADC_COMMON_BIT;
1613 else
1614 devpriv->command6_bits &= ~ADC_COMMON_BIT;
1615 /* bipolar or unipolar range? */
1616 if (thisboard->ai_range_is_unipolar[range])
1617 devpriv->command6_bits |= ADC_UNIP_BIT;
1618 else
1619 devpriv->command6_bits &= ~ADC_UNIP_BIT;
1620 /* don't interrupt on fifo half full */
1621 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1622 /* don't enable interrupt on counter a1 terminal count? */
1623 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1624 /* write to register */
1625 devpriv->write_byte(devpriv->command6_bits,
1626 dev->iobase + COMMAND6_REG);
1627 }
1628 /* setup command4 register */
1629 devpriv->command4_bits = 0;
1630 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1631 /* single-ended/differential */
1632 if (CR_AREF(insn->chanspec) == AREF_DIFF)
1633 devpriv->command4_bits |= ADC_DIFF_BIT;
1634 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1635
1636 /*
1637 * initialize pacer counter output to make sure it doesn't
1638 * cause any problems
1639 */
1640 devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG);
1641
1642 labpc_clear_adc_fifo(dev);
1643
1644 for (n = 0; n < insn->n; n++) {
1645 /* trigger conversion */
1646 devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG);
1647
1648 for (i = 0; i < timeout; i++) {
1649 if (devpriv->read_byte(dev->iobase +
1650 STATUS1_REG) & DATA_AVAIL_BIT)
1651 break;
1652 udelay(1);
1653 }
1654 if (i == timeout) {
1655 comedi_error(dev, "timeout");
1656 return -ETIME;
1657 }
1658 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1659 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1660 data[n] = (msb << 8) | lsb;
1661 }
1662
1663 return n;
1664 }
1665
1666 /* analog output insn */
1667 static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
1668 struct comedi_insn *insn, unsigned int *data)
1669 {
1670 int channel, range;
1671 unsigned long flags;
1672 int lsb, msb;
1673
1674 channel = CR_CHAN(insn->chanspec);
1675
1676 /* turn off pacing of analog output channel */
1677 /* note: hardware bug in daqcard-1200 means pacing cannot
1678 * be independently enabled/disabled for its the two channels */
1679 spin_lock_irqsave(&dev->spinlock, flags);
1680 devpriv->command2_bits &= ~DAC_PACED_BIT(channel);
1681 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1682 spin_unlock_irqrestore(&dev->spinlock, flags);
1683
1684 /* set range */
1685 if (thisboard->register_layout == labpc_1200_layout) {
1686 range = CR_RANGE(insn->chanspec);
1687 if (range & AO_RANGE_IS_UNIPOLAR)
1688 devpriv->command6_bits |= DAC_UNIP_BIT(channel);
1689 else
1690 devpriv->command6_bits &= ~DAC_UNIP_BIT(channel);
1691 /* write to register */
1692 devpriv->write_byte(devpriv->command6_bits,
1693 dev->iobase + COMMAND6_REG);
1694 }
1695 /* send data */
1696 lsb = data[0] & 0xff;
1697 msb = (data[0] >> 8) & 0xff;
1698 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel));
1699 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel));
1700
1701 /* remember value for readback */
1702 devpriv->ao_value[channel] = data[0];
1703
1704 return 1;
1705 }
1706
1707 /* analog output readback insn */
1708 static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1709 struct comedi_insn *insn, unsigned int *data)
1710 {
1711 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
1712
1713 return 1;
1714 }
1715
1716 static int labpc_calib_read_insn(struct comedi_device *dev,
1717 struct comedi_subdevice *s,
1718 struct comedi_insn *insn, unsigned int *data)
1719 {
1720 data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)];
1721
1722 return 1;
1723 }
1724
1725 static int labpc_calib_write_insn(struct comedi_device *dev,
1726 struct comedi_subdevice *s,
1727 struct comedi_insn *insn, unsigned int *data)
1728 {
1729 int channel = CR_CHAN(insn->chanspec);
1730
1731 write_caldac(dev, channel, data[0]);
1732 return 1;
1733 }
1734
1735 static int labpc_eeprom_read_insn(struct comedi_device *dev,
1736 struct comedi_subdevice *s,
1737 struct comedi_insn *insn, unsigned int *data)
1738 {
1739 data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)];
1740
1741 return 1;
1742 }
1743
1744 static int labpc_eeprom_write_insn(struct comedi_device *dev,
1745 struct comedi_subdevice *s,
1746 struct comedi_insn *insn, unsigned int *data)
1747 {
1748 int channel = CR_CHAN(insn->chanspec);
1749 int ret;
1750
1751 /* only allow writes to user area of eeprom */
1752 if (channel < 16 || channel > 127) {
1753 printk
1754 ("eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)");
1755 return -EINVAL;
1756 }
1757
1758 ret = labpc_eeprom_write(dev, channel, data[0]);
1759 if (ret < 0)
1760 return ret;
1761
1762 return 1;
1763 }
1764
1765 /* utility function that suggests a dma transfer size in bytes */
1766 static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd)
1767 {
1768 unsigned int size;
1769 unsigned int freq;
1770
1771 if (cmd.convert_src == TRIG_TIMER)
1772 freq = 1000000000 / cmd.convert_arg;
1773 /* return some default value */
1774 else
1775 freq = 0xffffffff;
1776
1777 /* make buffer fill in no more than 1/3 second */
1778 size = (freq / 3) * sample_size;
1779
1780 /* set a minimum and maximum size allowed */
1781 if (size > dma_buffer_size)
1782 size = dma_buffer_size - dma_buffer_size % sample_size;
1783 else if (size < sample_size)
1784 size = sample_size;
1785
1786 return size;
1787 }
1788
1789 /* figures out what counter values to use based on command */
1790 static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
1791 {
1792 /* max value for 16 bit counter in mode 2 */
1793 const int max_counter_value = 0x10000;
1794 /* min value for 16 bit counter in mode 2 */
1795 const int min_counter_value = 2;
1796 unsigned int base_period;
1797
1798 /*
1799 * if both convert and scan triggers are TRIG_TIMER, then they
1800 * both rely on counter b0
1801 */
1802 if (labpc_ai_convert_period(cmd) && labpc_ai_scan_period(cmd)) {
1803 /*
1804 * pick the lowest b0 divisor value we can (for maximum input
1805 * clock speed on convert and scan counters)
1806 */
1807 devpriv->divisor_b0 = (labpc_ai_scan_period(cmd) - 1) /
1808 (LABPC_TIMER_BASE * max_counter_value) + 1;
1809 if (devpriv->divisor_b0 < min_counter_value)
1810 devpriv->divisor_b0 = min_counter_value;
1811 if (devpriv->divisor_b0 > max_counter_value)
1812 devpriv->divisor_b0 = max_counter_value;
1813
1814 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0;
1815
1816 /* set a0 for conversion frequency and b1 for scan frequency */
1817 switch (cmd->flags & TRIG_ROUND_MASK) {
1818 default:
1819 case TRIG_ROUND_NEAREST:
1820 devpriv->divisor_a0 =
1821 (labpc_ai_convert_period(cmd) +
1822 (base_period / 2)) / base_period;
1823 devpriv->divisor_b1 =
1824 (labpc_ai_scan_period(cmd) +
1825 (base_period / 2)) / base_period;
1826 break;
1827 case TRIG_ROUND_UP:
1828 devpriv->divisor_a0 =
1829 (labpc_ai_convert_period(cmd) + (base_period -
1830 1)) / base_period;
1831 devpriv->divisor_b1 =
1832 (labpc_ai_scan_period(cmd) + (base_period -
1833 1)) / base_period;
1834 break;
1835 case TRIG_ROUND_DOWN:
1836 devpriv->divisor_a0 =
1837 labpc_ai_convert_period(cmd) / base_period;
1838 devpriv->divisor_b1 =
1839 labpc_ai_scan_period(cmd) / base_period;
1840 break;
1841 }
1842 /* make sure a0 and b1 values are acceptable */
1843 if (devpriv->divisor_a0 < min_counter_value)
1844 devpriv->divisor_a0 = min_counter_value;
1845 if (devpriv->divisor_a0 > max_counter_value)
1846 devpriv->divisor_a0 = max_counter_value;
1847 if (devpriv->divisor_b1 < min_counter_value)
1848 devpriv->divisor_b1 = min_counter_value;
1849 if (devpriv->divisor_b1 > max_counter_value)
1850 devpriv->divisor_b1 = max_counter_value;
1851 /* write corrected timings to command */
1852 labpc_set_ai_convert_period(cmd,
1853 base_period * devpriv->divisor_a0);
1854 labpc_set_ai_scan_period(cmd,
1855 base_period * devpriv->divisor_b1);
1856 /*
1857 * if only one TRIG_TIMER is used, we can employ the generic
1858 * cascaded timing functions
1859 */
1860 } else if (labpc_ai_scan_period(cmd)) {
1861 unsigned int scan_period;
1862
1863 scan_period = labpc_ai_scan_period(cmd);
1864 /*
1865 * calculate cascaded counter values
1866 * that give desired scan timing
1867 */
1868 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1869 &(devpriv->divisor_b1),
1870 &(devpriv->divisor_b0),
1871 &scan_period,
1872 cmd->flags & TRIG_ROUND_MASK);
1873 labpc_set_ai_scan_period(cmd, scan_period);
1874 } else if (labpc_ai_convert_period(cmd)) {
1875 unsigned int convert_period;
1876
1877 convert_period = labpc_ai_convert_period(cmd);
1878 /*
1879 * calculate cascaded counter values
1880 * that give desired conversion timing
1881 */
1882 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1883 &(devpriv->divisor_a0),
1884 &(devpriv->divisor_b0),
1885 &convert_period,
1886 cmd->flags & TRIG_ROUND_MASK);
1887 labpc_set_ai_convert_period(cmd, convert_period);
1888 }
1889 }
1890
1891 static int labpc_dio_mem_callback(int dir, int port, int data,
1892 unsigned long iobase)
1893 {
1894 if (dir) {
1895 writeb(data, (void *)(iobase + port));
1896 return 0;
1897 } else {
1898 return readb((void *)(iobase + port));
1899 }
1900 }
1901
1902 /* lowlevel write to eeprom/dac */
1903 static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
1904 unsigned int value_width)
1905 {
1906 int i;
1907
1908 for (i = 1; i <= value_width; i++) {
1909 /* clear serial clock */
1910 devpriv->command5_bits &= ~SCLOCK_BIT;
1911 /* send bits most significant bit first */
1912 if (value & (1 << (value_width - i)))
1913 devpriv->command5_bits |= SDATA_BIT;
1914 else
1915 devpriv->command5_bits &= ~SDATA_BIT;
1916 udelay(1);
1917 devpriv->write_byte(devpriv->command5_bits,
1918 dev->iobase + COMMAND5_REG);
1919 /* set clock to load bit */
1920 devpriv->command5_bits |= SCLOCK_BIT;
1921 udelay(1);
1922 devpriv->write_byte(devpriv->command5_bits,
1923 dev->iobase + COMMAND5_REG);
1924 }
1925 }
1926
1927 /* lowlevel read from eeprom */
1928 static unsigned int labpc_serial_in(struct comedi_device *dev)
1929 {
1930 unsigned int value = 0;
1931 int i;
1932 const int value_width = 8; /* number of bits wide values are */
1933
1934 for (i = 1; i <= value_width; i++) {
1935 /* set serial clock */
1936 devpriv->command5_bits |= SCLOCK_BIT;
1937 udelay(1);
1938 devpriv->write_byte(devpriv->command5_bits,
1939 dev->iobase + COMMAND5_REG);
1940 /* clear clock bit */
1941 devpriv->command5_bits &= ~SCLOCK_BIT;
1942 udelay(1);
1943 devpriv->write_byte(devpriv->command5_bits,
1944 dev->iobase + COMMAND5_REG);
1945 /* read bits most significant bit first */
1946 udelay(1);
1947 devpriv->status2_bits =
1948 devpriv->read_byte(dev->iobase + STATUS2_REG);
1949 if (devpriv->status2_bits & EEPROM_OUT_BIT)
1950 value |= 1 << (value_width - i);
1951 }
1952
1953 return value;
1954 }
1955
1956 static unsigned int labpc_eeprom_read(struct comedi_device *dev,
1957 unsigned int address)
1958 {
1959 unsigned int value;
1960 /* bits to tell eeprom to expect a read */
1961 const int read_instruction = 0x3;
1962 /* 8 bit write lengths to eeprom */
1963 const int write_length = 8;
1964
1965 /* enable read/write to eeprom */
1966 devpriv->command5_bits &= ~EEPROM_EN_BIT;
1967 udelay(1);
1968 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1969 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
1970 udelay(1);
1971 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1972
1973 /* send read instruction */
1974 labpc_serial_out(dev, read_instruction, write_length);
1975 /* send 8 bit address to read from */
1976 labpc_serial_out(dev, address, write_length);
1977 /* read result */
1978 value = labpc_serial_in(dev);
1979
1980 /* disable read/write to eeprom */
1981 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
1982 udelay(1);
1983 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1984
1985 return value;
1986 }
1987
1988 static unsigned int labpc_eeprom_write(struct comedi_device *dev,
1989 unsigned int address, unsigned int value)
1990 {
1991 const int write_enable_instruction = 0x6;
1992 const int write_instruction = 0x2;
1993 const int write_length = 8; /* 8 bit write lengths to eeprom */
1994 const int write_in_progress_bit = 0x1;
1995 const int timeout = 10000;
1996 int i;
1997
1998 /* make sure there isn't already a write in progress */
1999 for (i = 0; i < timeout; i++) {
2000 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) ==
2001 0)
2002 break;
2003 }
2004 if (i == timeout) {
2005 comedi_error(dev, "eeprom write timed out");
2006 return -ETIME;
2007 }
2008 /* update software copy of eeprom */
2009 devpriv->eeprom_data[address] = value;
2010
2011 /* enable read/write to eeprom */
2012 devpriv->command5_bits &= ~EEPROM_EN_BIT;
2013 udelay(1);
2014 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2015 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
2016 udelay(1);
2017 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2018
2019 /* send write_enable instruction */
2020 labpc_serial_out(dev, write_enable_instruction, write_length);
2021 devpriv->command5_bits &= ~EEPROM_EN_BIT;
2022 udelay(1);
2023 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2024
2025 /* send write instruction */
2026 devpriv->command5_bits |= EEPROM_EN_BIT;
2027 udelay(1);
2028 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2029 labpc_serial_out(dev, write_instruction, write_length);
2030 /* send 8 bit address to write to */
2031 labpc_serial_out(dev, address, write_length);
2032 /* write value */
2033 labpc_serial_out(dev, value, write_length);
2034 devpriv->command5_bits &= ~EEPROM_EN_BIT;
2035 udelay(1);
2036 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2037
2038 /* disable read/write to eeprom */
2039 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2040 udelay(1);
2041 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2042
2043 return 0;
2044 }
2045
2046 static unsigned int labpc_eeprom_read_status(struct comedi_device *dev)
2047 {
2048 unsigned int value;
2049 const int read_status_instruction = 0x5;
2050 const int write_length = 8; /* 8 bit write lengths to eeprom */
2051
2052 /* enable read/write to eeprom */
2053 devpriv->command5_bits &= ~EEPROM_EN_BIT;
2054 udelay(1);
2055 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2056 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
2057 udelay(1);
2058 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2059
2060 /* send read status instruction */
2061 labpc_serial_out(dev, read_status_instruction, write_length);
2062 /* read result */
2063 value = labpc_serial_in(dev);
2064
2065 /* disable read/write to eeprom */
2066 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2067 udelay(1);
2068 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2069
2070 return value;
2071 }
2072
2073 /* writes to 8 bit calibration dacs */
2074 static void write_caldac(struct comedi_device *dev, unsigned int channel,
2075 unsigned int value)
2076 {
2077 if (value == devpriv->caldac[channel])
2078 return;
2079 devpriv->caldac[channel] = value;
2080
2081 /* clear caldac load bit and make sure we don't write to eeprom */
2082 devpriv->command5_bits &=
2083 ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2084 udelay(1);
2085 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2086
2087 /* write 4 bit channel */
2088 labpc_serial_out(dev, channel, 4);
2089 /* write 8 bit caldac value */
2090 labpc_serial_out(dev, value, 8);
2091
2092 /* set and clear caldac bit to load caldac value */
2093 devpriv->command5_bits |= CALDAC_LOAD_BIT;
2094 udelay(1);
2095 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2096 devpriv->command5_bits &= ~CALDAC_LOAD_BIT;
2097 udelay(1);
2098 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2099 }
2100
2101 #ifdef CONFIG_COMEDI_PCI
2102 static int __devinit driver_labpc_pci_probe(struct pci_dev *dev,
2103 const struct pci_device_id *ent)
2104 {
2105 return comedi_pci_auto_config(dev, driver_labpc.driver_name);
2106 }
2107
2108 static void __devexit driver_labpc_pci_remove(struct pci_dev *dev)
2109 {
2110 comedi_pci_auto_unconfig(dev);
2111 }
2112
2113 static struct pci_driver driver_labpc_pci_driver = {
2114 .id_table = labpc_pci_table,
2115 .probe = &driver_labpc_pci_probe,
2116 .remove = __devexit_p(&driver_labpc_pci_remove)
2117 };
2118
2119 static int __init driver_labpc_init_module(void)
2120 {
2121 int retval;
2122
2123 retval = comedi_driver_register(&driver_labpc);
2124 if (retval < 0)
2125 return retval;
2126
2127 driver_labpc_pci_driver.name = (char *)driver_labpc.driver_name;
2128 return pci_register_driver(&driver_labpc_pci_driver);
2129 }
2130
2131 static void __exit driver_labpc_cleanup_module(void)
2132 {
2133 pci_unregister_driver(&driver_labpc_pci_driver);
2134 comedi_driver_unregister(&driver_labpc);
2135 }
2136
2137 module_init(driver_labpc_init_module);
2138 module_exit(driver_labpc_cleanup_module);
2139 #else
2140 static int __init driver_labpc_init_module(void)
2141 {
2142 return comedi_driver_register(&driver_labpc);
2143 }
2144
2145 static void __exit driver_labpc_cleanup_module(void)
2146 {
2147 comedi_driver_unregister(&driver_labpc);
2148 }
2149
2150 module_init(driver_labpc_init_module);
2151 module_exit(driver_labpc_cleanup_module);
2152 #endif
2153
2154 EXPORT_SYMBOL_GPL(labpc_common_attach);
2155 EXPORT_SYMBOL_GPL(labpc_common_detach);
2156 EXPORT_SYMBOL_GPL(range_labpc_1200_ai);
2157 EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits);
2158 EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar);
2159
2160 MODULE_AUTHOR("Comedi http://www.comedi.org");
2161 MODULE_DESCRIPTION("Comedi low-level driver");
2162 MODULE_LICENSE("GPL");
Tomato firmware and modifications.