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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / sh / intc.c
blob1f87c015ee9375b7592f05045f4bb527013a7711
1 /*
2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
3 *
4 * Copyright (C) 2007, 2008 Magnus Damm
5 * Copyright (C) 2009, 2010 Paul Mundt
6 *
7 * Based on intc2.c and ipr.c
8 *
9 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
10 * Copyright (C) 2000 Kazumoto Kojima
11 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
12 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
13 * Copyright (C) 2005, 2006 Paul Mundt
14 *
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
17 * for more details.
18 */
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21 #include <linux/init.h>
22 #include <linux/irq.h>
23 #include <linux/module.h>
24 #include <linux/io.h>
25 #include <linux/slab.h>
26 #include <linux/interrupt.h>
27 #include <linux/sh_intc.h>
28 #include <linux/sysdev.h>
29 #include <linux/list.h>
30 #include <linux/topology.h>
31 #include <linux/bitmap.h>
32 #include <linux/cpumask.h>
33 #include <asm/sizes.h>
34
35 #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
36 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
37 ((addr_e) << 16) | ((addr_d << 24)))
38
39 #define _INTC_SHIFT(h) (h & 0x1f)
40 #define _INTC_WIDTH(h) ((h >> 5) & 0xf)
41 #define _INTC_FN(h) ((h >> 9) & 0xf)
42 #define _INTC_MODE(h) ((h >> 13) & 0x7)
43 #define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
44 #define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
45
46 struct intc_handle_int {
47 unsigned int irq;
48 unsigned long handle;
49 };
50
51 struct intc_window {
52 phys_addr_t phys;
53 void __iomem *virt;
54 unsigned long size;
55 };
56
57 struct intc_desc_int {
58 struct list_head list;
59 struct sys_device sysdev;
60 pm_message_t state;
61 unsigned long *reg;
62 #ifdef CONFIG_SMP
63 unsigned long *smp;
64 #endif
65 unsigned int nr_reg;
66 struct intc_handle_int *prio;
67 unsigned int nr_prio;
68 struct intc_handle_int *sense;
69 unsigned int nr_sense;
70 struct intc_window *window;
71 unsigned int nr_windows;
72 struct irq_chip chip;
73 };
74
75 static LIST_HEAD(intc_list);
76
77 /*
78 * The intc_irq_map provides a global map of bound IRQ vectors for a
79 * given platform. Allocation of IRQs are either static through the CPU
80 * vector map, or dynamic in the case of board mux vectors or MSI.
81 *
82 * As this is a central point for all IRQ controllers on the system,
83 * each of the available sources are mapped out here. This combined with
84 * sparseirq makes it quite trivial to keep the vector map tightly packed
85 * when dynamically creating IRQs, as well as tying in to otherwise
86 * unused irq_desc positions in the sparse array.
87 */
88 static DECLARE_BITMAP(intc_irq_map, NR_IRQS);
89 static DEFINE_SPINLOCK(vector_lock);
90
91 #ifdef CONFIG_SMP
92 #define IS_SMP(x) x.smp
93 #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
94 #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
95 #else
96 #define IS_SMP(x) 0
97 #define INTC_REG(d, x, c) (d->reg[(x)])
98 #define SMP_NR(d, x) 1
99 #endif
100
101 static unsigned int intc_prio_level[NR_IRQS]; /* for now */
102 static unsigned int default_prio_level = 2; /* 2 - 16 */
103 static unsigned long ack_handle[NR_IRQS];
104 #ifdef CONFIG_INTC_BALANCING
105 static unsigned long dist_handle[NR_IRQS];
106 #endif
107
108 static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
109 {
110 struct irq_chip *chip = get_irq_chip(irq);
111 return container_of(chip, struct intc_desc_int, chip);
112 }
113
114 static unsigned long intc_phys_to_virt(struct intc_desc_int *d,
115 unsigned long address)
116 {
117 struct intc_window *window;
118 int k;
119
120 /* scan through physical windows and convert address */
121 for (k = 0; k < d->nr_windows; k++) {
122 window = d->window + k;
123
124 if (address < window->phys)
125 continue;
126
127 if (address >= (window->phys + window->size))
128 continue;
129
130 address -= window->phys;
131 address += (unsigned long)window->virt;
132
133 return address;
134 }
135
136 /* no windows defined, register must be 1:1 mapped virt:phys */
137 return address;
138 }
139
140 static unsigned int intc_get_reg(struct intc_desc_int *d, unsigned long address)
141 {
142 unsigned int k;
143
144 address = intc_phys_to_virt(d, address);
145
146 for (k = 0; k < d->nr_reg; k++) {
147 if (d->reg[k] == address)
148 return k;
149 }
150
151 BUG();
152 return 0;
153 }
154
155 static inline unsigned int set_field(unsigned int value,
156 unsigned int field_value,
157 unsigned int handle)
158 {
159 unsigned int width = _INTC_WIDTH(handle);
160 unsigned int shift = _INTC_SHIFT(handle);
161
162 value &= ~(((1 << width) - 1) << shift);
163 value |= field_value << shift;
164 return value;
165 }
166
167 static void write_8(unsigned long addr, unsigned long h, unsigned long data)
168 {
169 __raw_writeb(set_field(0, data, h), addr);
170 (void)__raw_readb(addr); /* Defeat write posting */
171 }
172
173 static void write_16(unsigned long addr, unsigned long h, unsigned long data)
174 {
175 __raw_writew(set_field(0, data, h), addr);
176 (void)__raw_readw(addr); /* Defeat write posting */
177 }
178
179 static void write_32(unsigned long addr, unsigned long h, unsigned long data)
180 {
181 __raw_writel(set_field(0, data, h), addr);
182 (void)__raw_readl(addr); /* Defeat write posting */
183 }
184
185 static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
186 {
187 unsigned long flags;
188 local_irq_save(flags);
189 __raw_writeb(set_field(__raw_readb(addr), data, h), addr);
190 (void)__raw_readb(addr); /* Defeat write posting */
191 local_irq_restore(flags);
192 }
193
194 static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
195 {
196 unsigned long flags;
197 local_irq_save(flags);
198 __raw_writew(set_field(__raw_readw(addr), data, h), addr);
199 (void)__raw_readw(addr); /* Defeat write posting */
200 local_irq_restore(flags);
201 }
202
203 static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
204 {
205 unsigned long flags;
206 local_irq_save(flags);
207 __raw_writel(set_field(__raw_readl(addr), data, h), addr);
208 (void)__raw_readl(addr); /* Defeat write posting */
209 local_irq_restore(flags);
210 }
211
212 enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
213
214 static void (*intc_reg_fns[])(unsigned long addr,
215 unsigned long h,
216 unsigned long data) = {
217 [REG_FN_WRITE_BASE + 0] = write_8,
218 [REG_FN_WRITE_BASE + 1] = write_16,
219 [REG_FN_WRITE_BASE + 3] = write_32,
220 [REG_FN_MODIFY_BASE + 0] = modify_8,
221 [REG_FN_MODIFY_BASE + 1] = modify_16,
222 [REG_FN_MODIFY_BASE + 3] = modify_32,
223 };
224
225 enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
226 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
227 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
228 MODE_PRIO_REG, /* Priority value written to enable interrupt */
229 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
230 };
231
232 static void intc_mode_field(unsigned long addr,
233 unsigned long handle,
234 void (*fn)(unsigned long,
235 unsigned long,
236 unsigned long),
237 unsigned int irq)
238 {
239 fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
240 }
241
242 static void intc_mode_zero(unsigned long addr,
243 unsigned long handle,
244 void (*fn)(unsigned long,
245 unsigned long,
246 unsigned long),
247 unsigned int irq)
248 {
249 fn(addr, handle, 0);
250 }
251
252 static void intc_mode_prio(unsigned long addr,
253 unsigned long handle,
254 void (*fn)(unsigned long,
255 unsigned long,
256 unsigned long),
257 unsigned int irq)
258 {
259 fn(addr, handle, intc_prio_level[irq]);
260 }
261
262 static void (*intc_enable_fns[])(unsigned long addr,
263 unsigned long handle,
264 void (*fn)(unsigned long,
265 unsigned long,
266 unsigned long),
267 unsigned int irq) = {
268 [MODE_ENABLE_REG] = intc_mode_field,
269 [MODE_MASK_REG] = intc_mode_zero,
270 [MODE_DUAL_REG] = intc_mode_field,
271 [MODE_PRIO_REG] = intc_mode_prio,
272 [MODE_PCLR_REG] = intc_mode_prio,
273 };
274
275 static void (*intc_disable_fns[])(unsigned long addr,
276 unsigned long handle,
277 void (*fn)(unsigned long,
278 unsigned long,
279 unsigned long),
280 unsigned int irq) = {
281 [MODE_ENABLE_REG] = intc_mode_zero,
282 [MODE_MASK_REG] = intc_mode_field,
283 [MODE_DUAL_REG] = intc_mode_field,
284 [MODE_PRIO_REG] = intc_mode_zero,
285 [MODE_PCLR_REG] = intc_mode_field,
286 };
287
288 #ifdef CONFIG_INTC_BALANCING
289 static inline void intc_balancing_enable(unsigned int irq)
290 {
291 struct intc_desc_int *d = get_intc_desc(irq);
292 unsigned long handle = dist_handle[irq];
293 unsigned long addr;
294
295 if (irq_balancing_disabled(irq) || !handle)
296 return;
297
298 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
299 intc_reg_fns[_INTC_FN(handle)](addr, handle, 1);
300 }
301
302 static inline void intc_balancing_disable(unsigned int irq)
303 {
304 struct intc_desc_int *d = get_intc_desc(irq);
305 unsigned long handle = dist_handle[irq];
306 unsigned long addr;
307
308 if (irq_balancing_disabled(irq) || !handle)
309 return;
310
311 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
312 intc_reg_fns[_INTC_FN(handle)](addr, handle, 0);
313 }
314
315 static unsigned int intc_dist_data(struct intc_desc *desc,
316 struct intc_desc_int *d,
317 intc_enum enum_id)
318 {
319 struct intc_mask_reg *mr = desc->hw.mask_regs;
320 unsigned int i, j, fn, mode;
321 unsigned long reg_e, reg_d;
322
323 for (i = 0; mr && enum_id && i < desc->hw.nr_mask_regs; i++) {
324 mr = desc->hw.mask_regs + i;
325
326 /*
327 * Skip this entry if there's no auto-distribution
328 * register associated with it.
329 */
330 if (!mr->dist_reg)
331 continue;
332
333 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
334 if (mr->enum_ids[j] != enum_id)
335 continue;
336
337 fn = REG_FN_MODIFY_BASE;
338 mode = MODE_ENABLE_REG;
339 reg_e = mr->dist_reg;
340 reg_d = mr->dist_reg;
341
342 fn += (mr->reg_width >> 3) - 1;
343 return _INTC_MK(fn, mode,
344 intc_get_reg(d, reg_e),
345 intc_get_reg(d, reg_d),
346 1,
347 (mr->reg_width - 1) - j);
348 }
349 }
350
351 /*
352 * It's possible we've gotten here with no distribution options
353 * available for the IRQ in question, so we just skip over those.
354 */
355 return 0;
356 }
357 #else
358 static inline void intc_balancing_enable(unsigned int irq)
359 {
360 }
361
362 static inline void intc_balancing_disable(unsigned int irq)
363 {
364 }
365 #endif
366
367 static inline void _intc_enable(unsigned int irq, unsigned long handle)
368 {
369 struct intc_desc_int *d = get_intc_desc(irq);
370 unsigned long addr;
371 unsigned int cpu;
372
373 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
374 #ifdef CONFIG_SMP
375 if (!cpumask_test_cpu(cpu, irq_to_desc(irq)->affinity))
376 continue;
377 #endif
378 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
379 intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
380 [_INTC_FN(handle)], irq);
381 }
382
383 intc_balancing_enable(irq);
384 }
385
386 static void intc_enable(unsigned int irq)
387 {
388 _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
389 }
390
391 static void intc_disable(unsigned int irq)
392 {
393 struct intc_desc_int *d = get_intc_desc(irq);
394 unsigned long handle = (unsigned long)get_irq_chip_data(irq);
395 unsigned long addr;
396 unsigned int cpu;
397
398 intc_balancing_disable(irq);
399
400 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
401 #ifdef CONFIG_SMP
402 if (!cpumask_test_cpu(cpu, irq_to_desc(irq)->affinity))
403 continue;
404 #endif
405 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
406 intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
407 [_INTC_FN(handle)], irq);
408 }
409 }
410
411 static void (*intc_enable_noprio_fns[])(unsigned long addr,
412 unsigned long handle,
413 void (*fn)(unsigned long,
414 unsigned long,
415 unsigned long),
416 unsigned int irq) = {
417 [MODE_ENABLE_REG] = intc_mode_field,
418 [MODE_MASK_REG] = intc_mode_zero,
419 [MODE_DUAL_REG] = intc_mode_field,
420 [MODE_PRIO_REG] = intc_mode_field,
421 [MODE_PCLR_REG] = intc_mode_field,
422 };
423
424 static void intc_enable_disable(struct intc_desc_int *d,
425 unsigned long handle, int do_enable)
426 {
427 unsigned long addr;
428 unsigned int cpu;
429 void (*fn)(unsigned long, unsigned long,
430 void (*)(unsigned long, unsigned long, unsigned long),
431 unsigned int);
432
433 if (do_enable) {
434 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
435 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
436 fn = intc_enable_noprio_fns[_INTC_MODE(handle)];
437 fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
438 }
439 } else {
440 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
441 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
442 fn = intc_disable_fns[_INTC_MODE(handle)];
443 fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
444 }
445 }
446 }
447
448 static int intc_set_wake(unsigned int irq, unsigned int on)
449 {
450 return 0; /* allow wakeup, but setup hardware in intc_suspend() */
451 }
452
453 #ifdef CONFIG_SMP
454 /*
455 * This is held with the irq desc lock held, so we don't require any
456 * additional locking here at the intc desc level. The affinity mask is
457 * later tested in the enable/disable paths.
458 */
459 static int intc_set_affinity(unsigned int irq, const struct cpumask *cpumask)
460 {
461 if (!cpumask_intersects(cpumask, cpu_online_mask))
462 return -1;
463
464 cpumask_copy(irq_to_desc(irq)->affinity, cpumask);
465
466 return 0;
467 }
468 #endif
469
470 static void intc_mask_ack(unsigned int irq)
471 {
472 struct intc_desc_int *d = get_intc_desc(irq);
473 unsigned long handle = ack_handle[irq];
474 unsigned long addr;
475
476 intc_disable(irq);
477
478 /* read register and write zero only to the associated bit */
479 if (handle) {
480 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
481 switch (_INTC_FN(handle)) {
482 case REG_FN_MODIFY_BASE + 0: /* 8bit */
483 __raw_readb(addr);
484 __raw_writeb(0xff ^ set_field(0, 1, handle), addr);
485 break;
486 case REG_FN_MODIFY_BASE + 1: /* 16bit */
487 __raw_readw(addr);
488 __raw_writew(0xffff ^ set_field(0, 1, handle), addr);
489 break;
490 case REG_FN_MODIFY_BASE + 3: /* 32bit */
491 __raw_readl(addr);
492 __raw_writel(0xffffffff ^ set_field(0, 1, handle), addr);
493 break;
494 default:
495 BUG();
496 break;
497 }
498 }
499 }
500
501 static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
502 unsigned int nr_hp,
503 unsigned int irq)
504 {
505 int i;
506
507 /*
508 * this doesn't scale well, but...
509 *
510 * this function should only be used for cerain uncommon
511 * operations such as intc_set_priority() and intc_set_sense()
512 * and in those rare cases performance doesn't matter that much.
513 * keeping the memory footprint low is more important.
514 *
515 * one rather simple way to speed this up and still keep the
516 * memory footprint down is to make sure the array is sorted
517 * and then perform a bisect to lookup the irq.
518 */
519 for (i = 0; i < nr_hp; i++) {
520 if ((hp + i)->irq != irq)
521 continue;
522
523 return hp + i;
524 }
525
526 return NULL;
527 }
528
529 int intc_set_priority(unsigned int irq, unsigned int prio)
530 {
531 struct intc_desc_int *d = get_intc_desc(irq);
532 struct intc_handle_int *ihp;
533
534 if (!intc_prio_level[irq] || prio <= 1)
535 return -EINVAL;
536
537 ihp = intc_find_irq(d->prio, d->nr_prio, irq);
538 if (ihp) {
539 if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
540 return -EINVAL;
541
542 intc_prio_level[irq] = prio;
543
544 /*
545 * only set secondary masking method directly
546 * primary masking method is using intc_prio_level[irq]
547 * priority level will be set during next enable()
548 */
549 if (_INTC_FN(ihp->handle) != REG_FN_ERR)
550 _intc_enable(irq, ihp->handle);
551 }
552 return 0;
553 }
554
555 #define VALID(x) (x | 0x80)
556
557 static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
558 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
559 [IRQ_TYPE_EDGE_RISING] = VALID(1),
560 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
561 /* SH7706, SH7707 and SH7709 do not support high level triggered */
562 #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
563 !defined(CONFIG_CPU_SUBTYPE_SH7709)
564 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
565 #endif
566 };
567
568 static int intc_set_sense(unsigned int irq, unsigned int type)
569 {
570 struct intc_desc_int *d = get_intc_desc(irq);
571 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
572 struct intc_handle_int *ihp;
573 unsigned long addr;
574
575 if (!value)
576 return -EINVAL;
577
578 ihp = intc_find_irq(d->sense, d->nr_sense, irq);
579 if (ihp) {
580 addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
581 intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
582 }
583 return 0;
584 }
585
586 static intc_enum __init intc_grp_id(struct intc_desc *desc,
587 intc_enum enum_id)
588 {
589 struct intc_group *g = desc->hw.groups;
590 unsigned int i, j;
591
592 for (i = 0; g && enum_id && i < desc->hw.nr_groups; i++) {
593 g = desc->hw.groups + i;
594
595 for (j = 0; g->enum_ids[j]; j++) {
596 if (g->enum_ids[j] != enum_id)
597 continue;
598
599 return g->enum_id;
600 }
601 }
602
603 return 0;
604 }
605
606 static unsigned int __init _intc_mask_data(struct intc_desc *desc,
607 struct intc_desc_int *d,
608 intc_enum enum_id,
609 unsigned int *reg_idx,
610 unsigned int *fld_idx)
611 {
612 struct intc_mask_reg *mr = desc->hw.mask_regs;
613 unsigned int fn, mode;
614 unsigned long reg_e, reg_d;
615
616 while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) {
617 mr = desc->hw.mask_regs + *reg_idx;
618
619 for (; *fld_idx < ARRAY_SIZE(mr->enum_ids); (*fld_idx)++) {
620 if (mr->enum_ids[*fld_idx] != enum_id)
621 continue;
622
623 if (mr->set_reg && mr->clr_reg) {
624 fn = REG_FN_WRITE_BASE;
625 mode = MODE_DUAL_REG;
626 reg_e = mr->clr_reg;
627 reg_d = mr->set_reg;
628 } else {
629 fn = REG_FN_MODIFY_BASE;
630 if (mr->set_reg) {
631 mode = MODE_ENABLE_REG;
632 reg_e = mr->set_reg;
633 reg_d = mr->set_reg;
634 } else {
635 mode = MODE_MASK_REG;
636 reg_e = mr->clr_reg;
637 reg_d = mr->clr_reg;
638 }
639 }
640
641 fn += (mr->reg_width >> 3) - 1;
642 return _INTC_MK(fn, mode,
643 intc_get_reg(d, reg_e),
644 intc_get_reg(d, reg_d),
645 1,
646 (mr->reg_width - 1) - *fld_idx);
647 }
648
649 *fld_idx = 0;
650 (*reg_idx)++;
651 }
652
653 return 0;
654 }
655
656 static unsigned int __init intc_mask_data(struct intc_desc *desc,
657 struct intc_desc_int *d,
658 intc_enum enum_id, int do_grps)
659 {
660 unsigned int i = 0;
661 unsigned int j = 0;
662 unsigned int ret;
663
664 ret = _intc_mask_data(desc, d, enum_id, &i, &j);
665 if (ret)
666 return ret;
667
668 if (do_grps)
669 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
670
671 return 0;
672 }
673
674 static unsigned int __init _intc_prio_data(struct intc_desc *desc,
675 struct intc_desc_int *d,
676 intc_enum enum_id,
677 unsigned int *reg_idx,
678 unsigned int *fld_idx)
679 {
680 struct intc_prio_reg *pr = desc->hw.prio_regs;
681 unsigned int fn, n, mode, bit;
682 unsigned long reg_e, reg_d;
683
684 while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) {
685 pr = desc->hw.prio_regs + *reg_idx;
686
687 for (; *fld_idx < ARRAY_SIZE(pr->enum_ids); (*fld_idx)++) {
688 if (pr->enum_ids[*fld_idx] != enum_id)
689 continue;
690
691 if (pr->set_reg && pr->clr_reg) {
692 fn = REG_FN_WRITE_BASE;
693 mode = MODE_PCLR_REG;
694 reg_e = pr->set_reg;
695 reg_d = pr->clr_reg;
696 } else {
697 fn = REG_FN_MODIFY_BASE;
698 mode = MODE_PRIO_REG;
699 if (!pr->set_reg)
700 BUG();
701 reg_e = pr->set_reg;
702 reg_d = pr->set_reg;
703 }
704
705 fn += (pr->reg_width >> 3) - 1;
706 n = *fld_idx + 1;
707
708 BUG_ON(n * pr->field_width > pr->reg_width);
709
710 bit = pr->reg_width - (n * pr->field_width);
711
712 return _INTC_MK(fn, mode,
713 intc_get_reg(d, reg_e),
714 intc_get_reg(d, reg_d),
715 pr->field_width, bit);
716 }
717
718 *fld_idx = 0;
719 (*reg_idx)++;
720 }
721
722 return 0;
723 }
724
725 static unsigned int __init intc_prio_data(struct intc_desc *desc,
726 struct intc_desc_int *d,
727 intc_enum enum_id, int do_grps)
728 {
729 unsigned int i = 0;
730 unsigned int j = 0;
731 unsigned int ret;
732
733 ret = _intc_prio_data(desc, d, enum_id, &i, &j);
734 if (ret)
735 return ret;
736
737 if (do_grps)
738 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
739
740 return 0;
741 }
742
743 static void __init intc_enable_disable_enum(struct intc_desc *desc,
744 struct intc_desc_int *d,
745 intc_enum enum_id, int enable)
746 {
747 unsigned int i, j, data;
748
749 /* go through and enable/disable all mask bits */
750 i = j = 0;
751 do {
752 data = _intc_mask_data(desc, d, enum_id, &i, &j);
753 if (data)
754 intc_enable_disable(d, data, enable);
755 j++;
756 } while (data);
757
758 /* go through and enable/disable all priority fields */
759 i = j = 0;
760 do {
761 data = _intc_prio_data(desc, d, enum_id, &i, &j);
762 if (data)
763 intc_enable_disable(d, data, enable);
764
765 j++;
766 } while (data);
767 }
768
769 static unsigned int __init intc_ack_data(struct intc_desc *desc,
770 struct intc_desc_int *d,
771 intc_enum enum_id)
772 {
773 struct intc_mask_reg *mr = desc->hw.ack_regs;
774 unsigned int i, j, fn, mode;
775 unsigned long reg_e, reg_d;
776
777 for (i = 0; mr && enum_id && i < desc->hw.nr_ack_regs; i++) {
778 mr = desc->hw.ack_regs + i;
779
780 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
781 if (mr->enum_ids[j] != enum_id)
782 continue;
783
784 fn = REG_FN_MODIFY_BASE;
785 mode = MODE_ENABLE_REG;
786 reg_e = mr->set_reg;
787 reg_d = mr->set_reg;
788
789 fn += (mr->reg_width >> 3) - 1;
790 return _INTC_MK(fn, mode,
791 intc_get_reg(d, reg_e),
792 intc_get_reg(d, reg_d),
793 1,
794 (mr->reg_width - 1) - j);
795 }
796 }
797
798 return 0;
799 }
800
801 static unsigned int __init intc_sense_data(struct intc_desc *desc,
802 struct intc_desc_int *d,
803 intc_enum enum_id)
804 {
805 struct intc_sense_reg *sr = desc->hw.sense_regs;
806 unsigned int i, j, fn, bit;
807
808 for (i = 0; sr && enum_id && i < desc->hw.nr_sense_regs; i++) {
809 sr = desc->hw.sense_regs + i;
810
811 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
812 if (sr->enum_ids[j] != enum_id)
813 continue;
814
815 fn = REG_FN_MODIFY_BASE;
816 fn += (sr->reg_width >> 3) - 1;
817
818 BUG_ON((j + 1) * sr->field_width > sr->reg_width);
819
820 bit = sr->reg_width - ((j + 1) * sr->field_width);
821
822 return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
823 0, sr->field_width, bit);
824 }
825 }
826
827 return 0;
828 }
829
830 static void __init intc_register_irq(struct intc_desc *desc,
831 struct intc_desc_int *d,
832 intc_enum enum_id,
833 unsigned int irq)
834 {
835 struct intc_handle_int *hp;
836 unsigned int data[2], primary;
837
838 /*
839 * Register the IRQ position with the global IRQ map
840 */
841 set_bit(irq, intc_irq_map);
842
843 /*
844 * Prefer single interrupt source bitmap over other combinations:
845 *
846 * 1. bitmap, single interrupt source
847 * 2. priority, single interrupt source
848 * 3. bitmap, multiple interrupt sources (groups)
849 * 4. priority, multiple interrupt sources (groups)
850 */
851 data[0] = intc_mask_data(desc, d, enum_id, 0);
852 data[1] = intc_prio_data(desc, d, enum_id, 0);
853
854 primary = 0;
855 if (!data[0] && data[1])
856 primary = 1;
857
858 if (!data[0] && !data[1])
859 pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n",
860 irq, irq2evt(irq));
861
862 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
863 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
864
865 if (!data[primary])
866 primary ^= 1;
867
868 BUG_ON(!data[primary]); /* must have primary masking method */
869
870 disable_irq_nosync(irq);
871 set_irq_chip_and_handler_name(irq, &d->chip,
872 handle_level_irq, "level");
873 set_irq_chip_data(irq, (void *)data[primary]);
874
875 /*
876 * set priority level
877 * - this needs to be at least 2 for 5-bit priorities on 7780
878 */
879 intc_prio_level[irq] = default_prio_level;
880
881 /* enable secondary masking method if present */
882 if (data[!primary])
883 _intc_enable(irq, data[!primary]);
884
885 /* add irq to d->prio list if priority is available */
886 if (data[1]) {
887 hp = d->prio + d->nr_prio;
888 hp->irq = irq;
889 hp->handle = data[1];
890
891 if (primary) {
892 /*
893 * only secondary priority should access registers, so
894 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
895 */
896 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
897 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
898 }
899 d->nr_prio++;
900 }
901
902 /* add irq to d->sense list if sense is available */
903 data[0] = intc_sense_data(desc, d, enum_id);
904 if (data[0]) {
905 (d->sense + d->nr_sense)->irq = irq;
906 (d->sense + d->nr_sense)->handle = data[0];
907 d->nr_sense++;
908 }
909
910 /* irq should be disabled by default */
911 d->chip.mask(irq);
912
913 if (desc->hw.ack_regs)
914 ack_handle[irq] = intc_ack_data(desc, d, enum_id);
915
916 #ifdef CONFIG_INTC_BALANCING
917 if (desc->hw.mask_regs)
918 dist_handle[irq] = intc_dist_data(desc, d, enum_id);
919 #endif
920
921 #ifdef CONFIG_ARM
922 set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */
923 #endif
924 }
925
926 static unsigned int __init save_reg(struct intc_desc_int *d,
927 unsigned int cnt,
928 unsigned long value,
929 unsigned int smp)
930 {
931 if (value) {
932 value = intc_phys_to_virt(d, value);
933
934 d->reg[cnt] = value;
935 #ifdef CONFIG_SMP
936 d->smp[cnt] = smp;
937 #endif
938 return 1;
939 }
940
941 return 0;
942 }
943
944 static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
945 {
946 generic_handle_irq((unsigned int)get_irq_data(irq));
947 }
948
949 int __init register_intc_controller(struct intc_desc *desc)
950 {
951 unsigned int i, k, smp;
952 struct intc_hw_desc *hw = &desc->hw;
953 struct intc_desc_int *d;
954 struct resource *res;
955
956 pr_info("Registered controller '%s' with %u IRQs\n",
957 desc->name, hw->nr_vectors);
958
959 d = kzalloc(sizeof(*d), GFP_NOWAIT);
960 if (!d)
961 goto err0;
962
963 INIT_LIST_HEAD(&d->list);
964 list_add(&d->list, &intc_list);
965
966 if (desc->num_resources) {
967 d->nr_windows = desc->num_resources;
968 d->window = kzalloc(d->nr_windows * sizeof(*d->window),
969 GFP_NOWAIT);
970 if (!d->window)
971 goto err1;
972
973 for (k = 0; k < d->nr_windows; k++) {
974 res = desc->resource + k;
975 WARN_ON(resource_type(res) != IORESOURCE_MEM);
976 d->window[k].phys = res->start;
977 d->window[k].size = resource_size(res);
978 d->window[k].virt = ioremap_nocache(res->start,
979 resource_size(res));
980 if (!d->window[k].virt)
981 goto err2;
982 }
983 }
984
985 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
986 #ifdef CONFIG_INTC_BALANCING
987 if (d->nr_reg)
988 d->nr_reg += hw->nr_mask_regs;
989 #endif
990 d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
991 d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
992 d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
993
994 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
995 if (!d->reg)
996 goto err2;
997
998 #ifdef CONFIG_SMP
999 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
1000 if (!d->smp)
1001 goto err3;
1002 #endif
1003 k = 0;
1004
1005 if (hw->mask_regs) {
1006 for (i = 0; i < hw->nr_mask_regs; i++) {
1007 smp = IS_SMP(hw->mask_regs[i]);
1008 k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
1009 k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
1010 #ifdef CONFIG_INTC_BALANCING
1011 k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0);
1012 #endif
1013 }
1014 }
1015
1016 if (hw->prio_regs) {
1017 d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
1018 GFP_NOWAIT);
1019 if (!d->prio)
1020 goto err4;
1021
1022 for (i = 0; i < hw->nr_prio_regs; i++) {
1023 smp = IS_SMP(hw->prio_regs[i]);
1024 k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
1025 k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
1026 }
1027 }
1028
1029 if (hw->sense_regs) {
1030 d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
1031 GFP_NOWAIT);
1032 if (!d->sense)
1033 goto err5;
1034
1035 for (i = 0; i < hw->nr_sense_regs; i++)
1036 k += save_reg(d, k, hw->sense_regs[i].reg, 0);
1037 }
1038
1039 d->chip.name = desc->name;
1040 d->chip.mask = intc_disable;
1041 d->chip.unmask = intc_enable;
1042 d->chip.mask_ack = intc_disable;
1043 d->chip.enable = intc_enable;
1044 d->chip.disable = intc_disable;
1045 d->chip.shutdown = intc_disable;
1046 d->chip.set_type = intc_set_sense;
1047 d->chip.set_wake = intc_set_wake;
1048 #ifdef CONFIG_SMP
1049 d->chip.set_affinity = intc_set_affinity;
1050 #endif
1051
1052 if (hw->ack_regs) {
1053 for (i = 0; i < hw->nr_ack_regs; i++)
1054 k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
1055
1056 d->chip.mask_ack = intc_mask_ack;
1057 }
1058
1059 /* disable bits matching force_disable before registering irqs */
1060 if (desc->force_disable)
1061 intc_enable_disable_enum(desc, d, desc->force_disable, 0);
1062
1063 /* disable bits matching force_enable before registering irqs */
1064 if (desc->force_enable)
1065 intc_enable_disable_enum(desc, d, desc->force_enable, 0);
1066
1067 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
1068
1069 /* register the vectors one by one */
1070 for (i = 0; i < hw->nr_vectors; i++) {
1071 struct intc_vect *vect = hw->vectors + i;
1072 unsigned int irq = evt2irq(vect->vect);
1073 struct irq_desc *irq_desc;
1074
1075 if (!vect->enum_id)
1076 continue;
1077
1078 irq_desc = irq_to_desc_alloc_node(irq, numa_node_id());
1079 if (unlikely(!irq_desc)) {
1080 pr_err("can't get irq_desc for %d\n", irq);
1081 continue;
1082 }
1083
1084 intc_register_irq(desc, d, vect->enum_id, irq);
1085
1086 for (k = i + 1; k < hw->nr_vectors; k++) {
1087 struct intc_vect *vect2 = hw->vectors + k;
1088 unsigned int irq2 = evt2irq(vect2->vect);
1089
1090 if (vect->enum_id != vect2->enum_id)
1091 continue;
1092
1093 /*
1094 * In the case of multi-evt handling and sparse
1095 * IRQ support, each vector still needs to have
1096 * its own backing irq_desc.
1097 */
1098 irq_desc = irq_to_desc_alloc_node(irq2, numa_node_id());
1099 if (unlikely(!irq_desc)) {
1100 pr_err("can't get irq_desc for %d\n", irq2);
1101 continue;
1102 }
1103
1104 vect2->enum_id = 0;
1105
1106 /* redirect this interrupts to the first one */
1107 set_irq_chip(irq2, &dummy_irq_chip);
1108 set_irq_chained_handler(irq2, intc_redirect_irq);
1109 set_irq_data(irq2, (void *)irq);
1110 }
1111 }
1112
1113 /* enable bits matching force_enable after registering irqs */
1114 if (desc->force_enable)
1115 intc_enable_disable_enum(desc, d, desc->force_enable, 1);
1116
1117 return 0;
1118 err5:
1119 kfree(d->prio);
1120 err4:
1121 #ifdef CONFIG_SMP
1122 kfree(d->smp);
1123 err3:
1124 #endif
1125 kfree(d->reg);
1126 err2:
1127 for (k = 0; k < d->nr_windows; k++)
1128 if (d->window[k].virt)
1129 iounmap(d->window[k].virt);
1130
1131 kfree(d->window);
1132 err1:
1133 kfree(d);
1134 err0:
1135 pr_err("unable to allocate INTC memory\n");
1136
1137 return -ENOMEM;
1138 }
1139
1140 #ifdef CONFIG_INTC_USERIMASK
1141 static void __iomem *uimask;
1142
1143 int register_intc_userimask(unsigned long addr)
1144 {
1145 if (unlikely(uimask))
1146 return -EBUSY;
1147
1148 uimask = ioremap_nocache(addr, SZ_4K);
1149 if (unlikely(!uimask))
1150 return -ENOMEM;
1151
1152 pr_info("userimask support registered for levels 0 -> %d\n",
1153 default_prio_level - 1);
1154
1155 return 0;
1156 }
1157
1158 static ssize_t
1159 show_intc_userimask(struct sysdev_class *cls,
1160 struct sysdev_class_attribute *attr, char *buf)
1161 {
1162 return sprintf(buf, "%d\n", (__raw_readl(uimask) >> 4) & 0xf);
1163 }
1164
1165 static ssize_t
1166 store_intc_userimask(struct sysdev_class *cls,
1167 struct sysdev_class_attribute *attr,
1168 const char *buf, size_t count)
1169 {
1170 unsigned long level;
1171
1172 level = simple_strtoul(buf, NULL, 10);
1173
1174 /*
1175 * Minimal acceptable IRQ levels are in the 2 - 16 range, but
1176 * these are chomped so as to not interfere with normal IRQs.
1177 *
1178 * Level 1 is a special case on some CPUs in that it's not
1179 * directly settable, but given that USERIMASK cuts off below a
1180 * certain level, we don't care about this limitation here.
1181 * Level 0 on the other hand equates to user masking disabled.
1182 *
1183 * We use default_prio_level as a cut off so that only special
1184 * case opt-in IRQs can be mangled.
1185 */
1186 if (level >= default_prio_level)
1187 return -EINVAL;
1188
1189 __raw_writel(0xa5 << 24 | level << 4, uimask);
1190
1191 return count;
1192 }
1193
1194 static SYSDEV_CLASS_ATTR(userimask, S_IRUSR | S_IWUSR,
1195 show_intc_userimask, store_intc_userimask);
1196 #endif
1197
1198 static ssize_t
1199 show_intc_name(struct sys_device *dev, struct sysdev_attribute *attr, char *buf)
1200 {
1201 struct intc_desc_int *d;
1202
1203 d = container_of(dev, struct intc_desc_int, sysdev);
1204
1205 return sprintf(buf, "%s\n", d->chip.name);
1206 }
1207
1208 static SYSDEV_ATTR(name, S_IRUGO, show_intc_name, NULL);
1209
1210 static int intc_suspend(struct sys_device *dev, pm_message_t state)
1211 {
1212 struct intc_desc_int *d;
1213 struct irq_desc *desc;
1214 int irq;
1215
1216 /* get intc controller associated with this sysdev */
1217 d = container_of(dev, struct intc_desc_int, sysdev);
1218
1219 switch (state.event) {
1220 case PM_EVENT_ON:
1221 if (d->state.event != PM_EVENT_FREEZE)
1222 break;
1223 for_each_irq_desc(irq, desc) {
1224 if (desc->handle_irq == intc_redirect_irq)
1225 continue;
1226 if (desc->chip != &d->chip)
1227 continue;
1228 if (desc->status & IRQ_DISABLED)
1229 intc_disable(irq);
1230 else
1231 intc_enable(irq);
1232 }
1233 break;
1234 case PM_EVENT_FREEZE:
1235 /* nothing has to be done */
1236 break;
1237 case PM_EVENT_SUSPEND:
1238 /* enable wakeup irqs belonging to this intc controller */
1239 for_each_irq_desc(irq, desc) {
1240 if ((desc->status & IRQ_WAKEUP) && (desc->chip == &d->chip))
1241 intc_enable(irq);
1242 }
1243 break;
1244 }
1245 d->state = state;
1246
1247 return 0;
1248 }
1249
1250 static int intc_resume(struct sys_device *dev)
1251 {
1252 return intc_suspend(dev, PMSG_ON);
1253 }
1254
1255 static struct sysdev_class intc_sysdev_class = {
1256 .name = "intc",
1257 .suspend = intc_suspend,
1258 .resume = intc_resume,
1259 };
1260
1261 /* register this intc as sysdev to allow suspend/resume */
1262 static int __init register_intc_sysdevs(void)
1263 {
1264 struct intc_desc_int *d;
1265 int error;
1266 int id = 0;
1267
1268 error = sysdev_class_register(&intc_sysdev_class);
1269 #ifdef CONFIG_INTC_USERIMASK
1270 if (!error && uimask)
1271 error = sysdev_class_create_file(&intc_sysdev_class,
1272 &attr_userimask);
1273 #endif
1274 if (!error) {
1275 list_for_each_entry(d, &intc_list, list) {
1276 d->sysdev.id = id;
1277 d->sysdev.cls = &intc_sysdev_class;
1278 error = sysdev_register(&d->sysdev);
1279 if (error == 0)
1280 error = sysdev_create_file(&d->sysdev,
1281 &attr_name);
1282 if (error)
1283 break;
1284
1285 id++;
1286 }
1287 }
1288
1289 if (error)
1290 pr_err("sysdev registration error\n");
1291
1292 return error;
1293 }
1294 device_initcall(register_intc_sysdevs);
1295
1296 /*
1297 * Dynamic IRQ allocation and deallocation
1298 */
1299 unsigned int create_irq_nr(unsigned int irq_want, int node)
1300 {
1301 unsigned int irq = 0, new;
1302 unsigned long flags;
1303 struct irq_desc *desc;
1304
1305 spin_lock_irqsave(&vector_lock, flags);
1306
1307 /*
1308 * First try the wanted IRQ
1309 */
1310 if (test_and_set_bit(irq_want, intc_irq_map) == 0) {
1311 new = irq_want;
1312 } else {
1313 /* .. then fall back to scanning. */
1314 new = find_first_zero_bit(intc_irq_map, nr_irqs);
1315 if (unlikely(new == nr_irqs))
1316 goto out_unlock;
1317
1318 __set_bit(new, intc_irq_map);
1319 }
1320
1321 desc = irq_to_desc_alloc_node(new, node);
1322 if (unlikely(!desc)) {
1323 pr_err("can't get irq_desc for %d\n", new);
1324 goto out_unlock;
1325 }
1326
1327 desc = move_irq_desc(desc, node);
1328 irq = new;
1329
1330 out_unlock:
1331 spin_unlock_irqrestore(&vector_lock, flags);
1332
1333 if (irq > 0) {
1334 dynamic_irq_init(irq);
1335 #ifdef CONFIG_ARM
1336 set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */
1337 #endif
1338 }
1339
1340 return irq;
1341 }
1342
1343 int create_irq(void)
1344 {
1345 int nid = cpu_to_node(smp_processor_id());
1346 int irq;
1347
1348 irq = create_irq_nr(NR_IRQS_LEGACY, nid);
1349 if (irq == 0)
1350 irq = -1;
1351
1352 return irq;
1353 }
1354
1355 void destroy_irq(unsigned int irq)
1356 {
1357 unsigned long flags;
1358
1359 dynamic_irq_cleanup(irq);
1360
1361 spin_lock_irqsave(&vector_lock, flags);
1362 __clear_bit(irq, intc_irq_map);
1363 spin_unlock_irqrestore(&vector_lock, flags);
1364 }
1365
1366 int reserve_irq_vector(unsigned int irq)
1367 {
1368 unsigned long flags;
1369 int ret = 0;
1370
1371 spin_lock_irqsave(&vector_lock, flags);
1372 if (test_and_set_bit(irq, intc_irq_map))
1373 ret = -EBUSY;
1374 spin_unlock_irqrestore(&vector_lock, flags);
1375
1376 return ret;
1377 }
1378
1379 void reserve_irq_legacy(void)
1380 {
1381 unsigned long flags;
1382 int i, j;
1383
1384 spin_lock_irqsave(&vector_lock, flags);
1385 j = find_first_bit(intc_irq_map, nr_irqs);
1386 for (i = 0; i < j; i++)
1387 __set_bit(i, intc_irq_map);
1388 spin_unlock_irqrestore(&vector_lock, flags);
1389 }
Tomato firmware and modifications.