2 * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family
3 * of PCI-SCSI IO processors.
5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
7 * This driver is derived from the Linux sym53c8xx driver.
8 * Copyright (C) 1998-2000 Gerard Roudier
10 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
11 * a port of the FreeBSD ncr driver to Linux-1.2.13.
13 * The original ncr driver has been written for 386bsd and FreeBSD by
14 * Wolfgang Stanglmeier <wolf@cologne.de>
15 * Stefan Esser <se@mi.Uni-Koeln.de>
16 * Copyright (C) 1994 Wolfgang Stanglmeier
18 * Other major contributions:
20 * NVRAM detection and reading.
21 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
23 *-----------------------------------------------------------------------------
25 * This program is free software; you can redistribute it and/or modify
26 * it under the terms of the GNU General Public License as published by
27 * the Free Software Foundation; either version 2 of the License, or
28 * (at your option) any later version.
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
41 * Scripts for SYMBIOS-Processor
43 * We have to know the offsets of all labels before we reach
44 * them (for forward jumps). Therefore we declare a struct
45 * here. If you make changes inside the script,
47 * DONT FORGET TO CHANGE THE LENGTHS HERE!
51 * Script fragments which are loaded into the on-chip RAM
52 * of 825A, 875, 876, 895, 895A, 896 and 1010 chips.
53 * Must not exceed 4K bytes.
57 u32 getjob_begin
[ 4];
59 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
64 #if SYM_CONF_DMA_ADDRESSING_MODE == 2
65 u32 is_dmap_dirty
[ 4];
70 #ifdef SYM_CONF_IARB_SUPPORT
81 u32 datai_done_wsr
[ 20];
83 u32 datao_done_wss
[ 6];
88 #ifdef SYM_CONF_IARB_SUPPORT
97 u32 complete_error
[ 4];
100 u32 disconnect
[ 12];
101 #ifdef SYM_CONF_IARB_SUPPORT
106 #ifdef SYM_CONF_IARB_SUPPORT
111 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
116 u32 reselected
[ 22];
117 u32 resel_scntl4
[ 20];
119 #if SYM_CONF_MAX_TASK*4 > 512
121 #elif SYM_CONF_MAX_TASK*4 > 256
128 u32 resel_no_tag
[ 6];
129 u32 data_in
[SYM_CONF_MAX_SG
* 2];
131 u32 data_out
[SYM_CONF_MAX_SG
* 2];
134 u32 pm0_data_out
[ 6];
135 u32 pm0_data_end
[ 6];
137 u32 pm1_data_out
[ 6];
138 u32 pm1_data_end
[ 6];
142 * Script fragments which stay in main memory for all chips
143 * except for chips that support 8K on-chip RAM.
148 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
149 u32 sel_for_abort
[ 18];
151 u32 sel_for_abort
[ 16];
153 u32 sel_for_abort_1
[ 2];
154 u32 msg_in_etc
[ 12];
155 u32 msg_received
[ 4];
156 u32 msg_weird_seen
[ 4];
157 u32 msg_extended
[ 20];
168 u32 nego_bad_phase
[ 4];
170 u32 msg_out_done
[ 4];
172 u32 data_ovrun1
[ 22];
173 u32 data_ovrun2
[ 8];
174 u32 abort_resel
[ 16];
175 u32 resend_ident
[ 4];
176 u32 ident_break
[ 4];
177 u32 ident_break_atn
[ 4];
179 u32 resel_bad_lun
[ 4];
181 u32 bad_i_t_l_q
[ 4];
187 u32 pm_save_end
[ 4];
191 u32 pm_wsr_handle
[ 38];
192 u32 wsr_ma_helper
[ 4];
197 u32 pm0_data_addr
[ 1];
198 u32 pm1_data_addr
[ 1];
205 * Script fragments used at initialisations.
206 * Only runs out of main memory.
213 static struct SYM_FWA_SCR SYM_FWA_SCR
= {
214 /*--------------------------< START >----------------------------*/ {
217 * Will be patched with a NO_OP if LED
218 * not needed or not desired.
220 SCR_REG_REG (gpreg
, SCR_AND
, 0xfe),
225 SCR_FROM_REG (ctest2
),
228 * Stop here if the C code wants to perform
229 * some error recovery procedure manually.
230 * (Indicate this by setting SEM in ISTAT)
232 SCR_FROM_REG (istat
),
235 * Report to the C code the next position in
236 * the start queue the SCRIPTS will schedule.
237 * The C code must not change SCRATCHA.
239 SCR_LOAD_ABS (scratcha
, 4),
241 SCR_INT
^ IFTRUE (MASK (SEM
, SEM
)),
244 * Start the next job.
246 * @DSA = start point for this job.
247 * SCRATCHA = address of this job in the start queue.
249 * We will restore startpos with SCRATCHA if we fails the
250 * arbitration or if it is the idle job.
252 * The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS
253 * is a critical path. If it is partially executed, it then
254 * may happen that the job address is not yet in the DSA
255 * and the next queue position points to the next JOB.
257 SCR_LOAD_ABS (dsa
, 4),
259 SCR_LOAD_REL (temp
, 4),
261 }/*-------------------------< GETJOB_BEGIN >---------------------*/,{
262 SCR_STORE_ABS (temp
, 4),
264 SCR_LOAD_REL (dsa
, 4),
266 }/*-------------------------< GETJOB_END >-----------------------*/,{
267 SCR_LOAD_REL (temp
, 4),
271 }/*-------------------------< SELECT >---------------------------*/,{
273 * DSA contains the address of a scheduled
276 * SCRATCHA contains the address of the start queue
277 * entry which points to the next job.
279 * Set Initiator mode.
281 * (Target mode is left as an exercise for the reader)
283 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
288 * And try to select this target.
290 SCR_SEL_TBL_ATN
^ offsetof (struct sym_dsb
, select
),
293 * Now there are 4 possibilities:
295 * (1) The chip loses arbitration.
296 * This is ok, because it will try again,
297 * when the bus becomes idle.
298 * (But beware of the timeout function!)
300 * (2) The chip is reselected.
301 * Then the script processor takes the jump
302 * to the RESELECT label.
304 * (3) The chip wins arbitration.
305 * Then it will execute SCRIPTS instruction until
306 * the next instruction that checks SCSI phase.
307 * Then will stop and wait for selection to be
308 * complete or selection time-out to occur.
310 * After having won arbitration, the SCRIPTS
311 * processor is able to execute instructions while
312 * the SCSI core is performing SCSI selection.
315 * Initialize the status registers
317 SCR_LOAD_REL (scr0
, 4),
318 offsetof (struct sym_ccb
, phys
.head
.status
),
320 * We may need help from CPU if the DMA segment
321 * registers aren't up-to-date for this IO.
322 * Patched with NOOP for chips that donnot
323 * support DAC addressing.
325 #if SYM_CONF_DMA_ADDRESSING_MODE == 2
326 }/*-------------------------< IS_DMAP_DIRTY >--------------------*/,{
327 SCR_FROM_REG (HX_REG
),
329 SCR_INT
^ IFTRUE (MASK (HX_DMAP_DIRTY
, HX_DMAP_DIRTY
)),
332 }/*-------------------------< WF_SEL_DONE >----------------------*/,{
333 SCR_INT
^ IFFALSE (WHEN (SCR_MSG_OUT
)),
334 SIR_SEL_ATN_NO_MSG_OUT
,
335 }/*-------------------------< SEL_DONE >-------------------------*/,{
336 SCR_LOAD_REL (scntl3
, 1),
337 offsetof(struct sym_dsb
, select
.sel_scntl3
),
338 }/*-------------------------< SEND_IDENT >-----------------------*/,{
340 * Selection complete.
341 * Send the IDENTIFY and possibly the TAG message
342 * and negotiation message if present.
344 SCR_MOVE_TBL
^ SCR_MSG_OUT
,
345 offsetof (struct sym_dsb
, smsg
),
346 }/*-------------------------< SELECT2 >--------------------------*/,{
347 #ifdef SYM_CONF_IARB_SUPPORT
349 * Set IMMEDIATE ARBITRATION if we have been given
350 * a hint to do so. (Some job to do after this one).
352 SCR_FROM_REG (HF_REG
),
354 SCR_JUMPR
^ IFFALSE (MASK (HF_HINT_IARB
, HF_HINT_IARB
)),
356 SCR_REG_REG (scntl1
, SCR_OR
, IARB
),
360 * Anticipate the COMMAND phase.
361 * This is the PHASE we expect at this point.
363 SCR_JUMP
^ IFFALSE (WHEN (SCR_COMMAND
)),
364 PADDR_A (sel_no_cmd
),
365 }/*-------------------------< COMMAND >--------------------------*/,{
367 * ... and send the command
369 SCR_MOVE_TBL
^ SCR_COMMAND
,
370 offsetof (struct sym_dsb
, cmd
),
371 }/*-------------------------< DISPATCH >-------------------------*/,{
373 * MSG_IN is the only phase that shall be
374 * entered at least once for each (re)selection.
375 * So we test it first.
377 SCR_JUMP
^ IFTRUE (WHEN (SCR_MSG_IN
)),
379 SCR_JUMP
^ IFTRUE (IF (SCR_DATA_OUT
)),
380 PADDR_A (datao_phase
),
381 SCR_JUMP
^ IFTRUE (IF (SCR_DATA_IN
)),
382 PADDR_A (datai_phase
),
383 SCR_JUMP
^ IFTRUE (IF (SCR_STATUS
)),
385 SCR_JUMP
^ IFTRUE (IF (SCR_COMMAND
)),
387 SCR_JUMP
^ IFTRUE (IF (SCR_MSG_OUT
)),
390 * Discard as many illegal phases as
391 * required and tell the C code about.
393 SCR_JUMPR
^ IFFALSE (WHEN (SCR_ILG_OUT
)),
395 SCR_MOVE_ABS (1) ^ SCR_ILG_OUT
,
397 SCR_JUMPR
^ IFTRUE (WHEN (SCR_ILG_OUT
)),
399 SCR_JUMPR
^ IFFALSE (WHEN (SCR_ILG_IN
)),
401 SCR_MOVE_ABS (1) ^ SCR_ILG_IN
,
403 SCR_JUMPR
^ IFTRUE (WHEN (SCR_ILG_IN
)),
409 }/*-------------------------< SEL_NO_CMD >-----------------------*/,{
411 * The target does not switch to command
412 * phase after IDENTIFY has been sent.
414 * If it stays in MSG OUT phase send it
415 * the IDENTIFY again.
417 SCR_JUMP
^ IFTRUE (WHEN (SCR_MSG_OUT
)),
418 PADDR_B (resend_ident
),
420 * If target does not switch to MSG IN phase
421 * and we sent a negotiation, assert the
422 * failure immediately.
424 SCR_JUMP
^ IFTRUE (WHEN (SCR_MSG_IN
)),
426 SCR_FROM_REG (HS_REG
),
428 SCR_INT
^ IFTRUE (DATA (HS_NEGOTIATE
)),
431 * Jump to dispatcher.
435 }/*-------------------------< INIT >-----------------------------*/,{
437 * Wait for the SCSI RESET signal to be
438 * inactive before restarting operations,
439 * since the chip may hang on SEL_ATN
440 * if SCSI RESET is active.
442 SCR_FROM_REG (sstat0
),
444 SCR_JUMPR
^ IFTRUE (MASK (IRST
, IRST
)),
448 }/*-------------------------< CLRACK >---------------------------*/,{
450 * Terminate possible pending message phase.
456 }/*-------------------------< DATAI_DONE >-----------------------*/,{
458 * Save current pointer to LASTP.
460 SCR_STORE_REL (temp
, 4),
461 offsetof (struct sym_ccb
, phys
.head
.lastp
),
463 * If the SWIDE is not full, jump to dispatcher.
464 * We anticipate a STATUS phase.
466 SCR_FROM_REG (scntl2
),
468 SCR_JUMP
^ IFTRUE (MASK (WSR
, WSR
)),
469 PADDR_A (datai_done_wsr
),
470 SCR_JUMP
^ IFTRUE (WHEN (SCR_STATUS
)),
474 }/*-------------------------< DATAI_DONE_WSR >-------------------*/,{
477 * Clear this condition.
479 SCR_REG_REG (scntl2
, SCR_OR
, WSR
),
482 * We are expecting an IGNORE RESIDUE message
483 * from the device, otherwise we are in data
484 * overrun condition. Check against MSG_IN phase.
486 SCR_INT
^ IFFALSE (WHEN (SCR_MSG_IN
)),
488 SCR_JUMP
^ IFFALSE (WHEN (SCR_MSG_IN
)),
491 * We are in MSG_IN phase,
492 * Read the first byte of the message.
493 * If it is not an IGNORE RESIDUE message,
494 * signal overrun and jump to message
497 SCR_MOVE_ABS (1) ^ SCR_MSG_IN
,
499 SCR_INT
^ IFFALSE (DATA (M_IGN_RESIDUE
)),
501 SCR_JUMP
^ IFFALSE (DATA (M_IGN_RESIDUE
)),
504 * We got the message we expected.
505 * Read the 2nd byte, and jump to dispatcher.
509 SCR_MOVE_ABS (1) ^ SCR_MSG_IN
,
515 }/*-------------------------< DATAO_DONE >-----------------------*/,{
517 * Save current pointer to LASTP.
519 SCR_STORE_REL (temp
, 4),
520 offsetof (struct sym_ccb
, phys
.head
.lastp
),
522 * If the SODL is not full jump to dispatcher.
523 * We anticipate a STATUS phase.
525 SCR_FROM_REG (scntl2
),
527 SCR_JUMP
^ IFTRUE (MASK (WSS
, WSS
)),
528 PADDR_A (datao_done_wss
),
529 SCR_JUMP
^ IFTRUE (WHEN (SCR_STATUS
)),
533 }/*-------------------------< DATAO_DONE_WSS >-------------------*/,{
535 * The SODL is full, clear this condition.
537 SCR_REG_REG (scntl2
, SCR_OR
, WSS
),
540 * And signal a DATA UNDERRUN condition
547 }/*-------------------------< DATAI_PHASE >----------------------*/,{
549 * Jump to current pointer.
551 SCR_LOAD_REL (temp
, 4),
552 offsetof (struct sym_ccb
, phys
.head
.lastp
),
555 }/*-------------------------< DATAO_PHASE >----------------------*/,{
556 SCR_REG_REG (scntl4
, SCR_OR
, (XCLKH_DT
|XCLKH_ST
)),
559 * Jump to current pointer.
561 SCR_LOAD_REL (temp
, 4),
562 offsetof (struct sym_ccb
, phys
.head
.lastp
),
565 }/*-------------------------< MSG_IN >---------------------------*/,{
567 * Get the first byte of the message.
569 * The script processor doesn't negate the
570 * ACK signal after this transfer.
572 SCR_MOVE_ABS (1) ^ SCR_MSG_IN
,
574 }/*-------------------------< MSG_IN2 >--------------------------*/,{
576 * Check first against 1 byte messages
577 * that we handle from SCRIPTS.
579 SCR_JUMP
^ IFTRUE (DATA (M_COMPLETE
)),
581 SCR_JUMP
^ IFTRUE (DATA (M_DISCONNECT
)),
582 PADDR_A (disconnect
),
583 SCR_JUMP
^ IFTRUE (DATA (M_SAVE_DP
)),
585 SCR_JUMP
^ IFTRUE (DATA (M_RESTORE_DP
)),
586 PADDR_A (restore_dp
),
588 * We handle all other messages from the
589 * C code, so no need to waste on-chip RAM
593 PADDR_B (msg_in_etc
),
594 }/*-------------------------< STATUS >---------------------------*/,{
598 SCR_MOVE_ABS (1) ^ SCR_STATUS
,
600 #ifdef SYM_CONF_IARB_SUPPORT
602 * If STATUS is not GOOD, clear IMMEDIATE ARBITRATION,
603 * since we may have to tamper the start queue from
606 SCR_JUMPR
^ IFTRUE (DATA (S_GOOD
)),
608 SCR_REG_REG (scntl1
, SCR_AND
, ~IARB
),
612 * save status to scsi_status.
617 SCR_LOAD_REG (HS_REG
, HS_COMPLETE
),
620 * Anticipate the MESSAGE PHASE for
621 * the TASK COMPLETE message.
623 SCR_JUMP
^ IFTRUE (WHEN (SCR_MSG_IN
)),
627 }/*-------------------------< COMPLETE >-------------------------*/,{
631 * When we terminate the cycle by clearing ACK,
632 * the target may disconnect immediately.
634 * We don't want to be told of an "unexpected disconnect",
635 * so we disable this feature.
637 SCR_REG_REG (scntl2
, SCR_AND
, 0x7f),
640 * Terminate cycle ...
642 SCR_CLR (SCR_ACK
|SCR_ATN
),
645 * ... and wait for the disconnect.
649 }/*-------------------------< COMPLETE2 >------------------------*/,{
653 SCR_STORE_REL (scr0
, 4),
654 offsetof (struct sym_ccb
, phys
.head
.status
),
656 * Some bridges may reorder DMA writes to memory.
657 * We donnot want the CPU to deal with completions
658 * without all the posted write having been flushed
659 * to memory. This DUMMY READ should flush posted
660 * buffers prior to the CPU having to deal with
663 SCR_LOAD_REL (scr0
, 4), /* DUMMY READ */
664 offsetof (struct sym_ccb
, phys
.head
.status
),
667 * If command resulted in not GOOD status,
668 * call the C code if needed.
670 SCR_FROM_REG (SS_REG
),
672 SCR_CALL
^ IFFALSE (DATA (S_GOOD
)),
673 PADDR_B (bad_status
),
675 * If we performed an auto-sense, call
676 * the C code to synchronyze task aborts
677 * with UNIT ATTENTION conditions.
679 SCR_FROM_REG (HF_REG
),
681 SCR_JUMP
^ IFFALSE (MASK (0 ,(HF_SENSE
|HF_EXT_ERR
))),
682 PADDR_A (complete_error
),
683 }/*-------------------------< DONE >-----------------------------*/,{
685 * Copy the DSA to the DONE QUEUE and
686 * signal completion to the host.
687 * If we are interrupted between DONE
688 * and DONE_END, we must reset, otherwise
689 * the completed CCB may be lost.
691 SCR_STORE_ABS (dsa
, 4),
693 SCR_LOAD_ABS (dsa
, 4),
695 SCR_LOAD_ABS (scratcha
, 4),
697 SCR_STORE_REL (scratcha
, 4),
700 * The instruction below reads the DONE QUEUE next
701 * free position from memory.
702 * In addition it ensures that all PCI posted writes
703 * are flushed and so the DSA value of the done
704 * CCB is visible by the CPU before INTFLY is raised.
706 SCR_LOAD_REL (scratcha
, 4),
710 SCR_STORE_ABS (scratcha
, 4),
712 }/*-------------------------< DONE_END >-------------------------*/,{
715 }/*-------------------------< COMPLETE_ERROR >-------------------*/,{
716 SCR_LOAD_ABS (scratcha
, 4),
720 }/*-------------------------< SAVE_DP >--------------------------*/,{
722 * Clear ACK immediately.
723 * No need to delay it.
728 * Keep track we received a SAVE DP, so
729 * we will switch to the other PM context
730 * on the next PM since the DP may point
731 * to the current PM context.
733 SCR_REG_REG (HF_REG
, SCR_OR
, HF_DP_SAVED
),
737 * Copy LASTP to SAVEP.
739 SCR_LOAD_REL (scratcha
, 4),
740 offsetof (struct sym_ccb
, phys
.head
.lastp
),
741 SCR_STORE_REL (scratcha
, 4),
742 offsetof (struct sym_ccb
, phys
.head
.savep
),
744 * Anticipate the MESSAGE PHASE for
745 * the DISCONNECT message.
747 SCR_JUMP
^ IFTRUE (WHEN (SCR_MSG_IN
)),
751 }/*-------------------------< RESTORE_DP >-----------------------*/,{
753 * Clear ACK immediately.
754 * No need to delay it.
759 * Copy SAVEP to LASTP.
761 SCR_LOAD_REL (scratcha
, 4),
762 offsetof (struct sym_ccb
, phys
.head
.savep
),
763 SCR_STORE_REL (scratcha
, 4),
764 offsetof (struct sym_ccb
, phys
.head
.lastp
),
767 }/*-------------------------< DISCONNECT >-----------------------*/,{
771 * disable the "unexpected disconnect" feature,
772 * and remove the ACK signal.
774 SCR_REG_REG (scntl2
, SCR_AND
, 0x7f),
776 SCR_CLR (SCR_ACK
|SCR_ATN
),
779 * Wait for the disconnect.
784 * Status is: DISCONNECTED.
786 SCR_LOAD_REG (HS_REG
, HS_DISCONNECT
),
791 SCR_STORE_REL (scr0
, 4),
792 offsetof (struct sym_ccb
, phys
.head
.status
),
795 }/*-------------------------< IDLE >-----------------------------*/,{
798 * Switch the LED off and wait for reselect.
799 * Will be patched with a NO_OP if LED
800 * not needed or not desired.
802 SCR_REG_REG (gpreg
, SCR_OR
, 0x01),
804 #ifdef SYM_CONF_IARB_SUPPORT
808 }/*-------------------------< UNGETJOB >-------------------------*/,{
809 #ifdef SYM_CONF_IARB_SUPPORT
811 * Set IMMEDIATE ARBITRATION, for the next time.
812 * This will give us better chance to win arbitration
813 * for the job we just wanted to do.
815 SCR_REG_REG (scntl1
, SCR_OR
, IARB
),
819 * We are not able to restart the SCRIPTS if we are
820 * interrupted and these instruction haven't been
821 * all executed. BTW, this is very unlikely to
822 * happen, but we check that from the C code.
824 SCR_LOAD_REG (dsa
, 0xff),
826 SCR_STORE_ABS (scratcha
, 4),
828 }/*-------------------------< RESELECT >-------------------------*/,{
829 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
831 * Make sure we are in initiator mode.
837 * Sleep waiting for a reselection.
841 }/*-------------------------< RESELECTED >-----------------------*/,{
844 * Will be patched with a NO_OP if LED
845 * not needed or not desired.
847 SCR_REG_REG (gpreg
, SCR_AND
, 0xfe),
850 * load the target id into the sdid
852 SCR_REG_SFBR (ssid
, SCR_AND
, 0x8F),
857 * Load the target control block address
859 SCR_LOAD_ABS (dsa
, 4),
861 SCR_SFBR_REG (dsa
, SCR_SHL
, 0),
863 SCR_REG_REG (dsa
, SCR_SHL
, 0),
865 SCR_REG_REG (dsa
, SCR_AND
, 0x3c),
867 SCR_LOAD_REL (dsa
, 4),
870 * We expect MESSAGE IN phase.
871 * If not, get help from the C code.
873 SCR_INT
^ IFFALSE (WHEN (SCR_MSG_IN
)),
876 * Load the legacy synchronous transfer registers.
878 SCR_LOAD_REL (scntl3
, 1),
879 offsetof(struct sym_tcb
, head
.wval
),
880 SCR_LOAD_REL (sxfer
, 1),
881 offsetof(struct sym_tcb
, head
.sval
),
882 }/*-------------------------< RESEL_SCNTL4 >---------------------*/,{
884 * The C1010 uses a new synchronous timing scheme.
885 * Will be patched with a NO_OP if not a C1010.
887 SCR_LOAD_REL (scntl4
, 1),
888 offsetof(struct sym_tcb
, head
.uval
),
890 * Get the IDENTIFY message.
892 SCR_MOVE_ABS (1) ^ SCR_MSG_IN
,
895 * If IDENTIFY LUN #0, use a faster path
896 * to find the LCB structure.
898 SCR_JUMP
^ IFTRUE (MASK (0x80, 0xbf)),
899 PADDR_A (resel_lun0
),
901 * If message isn't an IDENTIFY,
902 * tell the C code about.
904 SCR_INT
^ IFFALSE (MASK (0x80, 0x80)),
905 SIR_RESEL_NO_IDENTIFY
,
907 * It is an IDENTIFY message,
908 * Load the LUN control block address.
910 SCR_LOAD_REL (dsa
, 4),
911 offsetof(struct sym_tcb
, head
.luntbl_sa
),
912 SCR_SFBR_REG (dsa
, SCR_SHL
, 0),
914 SCR_REG_REG (dsa
, SCR_SHL
, 0),
916 SCR_REG_REG (dsa
, SCR_AND
, 0xfc),
918 SCR_LOAD_REL (dsa
, 4),
922 }/*-------------------------< RESEL_LUN0 >-----------------------*/,{
924 * LUN 0 special case (but usual one :))
926 SCR_LOAD_REL (dsa
, 4),
927 offsetof(struct sym_tcb
, head
.lun0_sa
),
929 * Jump indirectly to the reselect action for this LUN.
931 SCR_LOAD_REL (temp
, 4),
932 offsetof(struct sym_lcb
, head
.resel_sa
),
935 /* In normal situations, we jump to RESEL_TAG or RESEL_NO_TAG */
936 }/*-------------------------< RESEL_TAG >------------------------*/,{
938 * ACK the IDENTIFY previously received.
943 * It shall be a tagged command.
945 * The C code will deal with errors.
946 * Aggressive optimization, isn't it? :)
948 SCR_MOVE_ABS (2) ^ SCR_MSG_IN
,
951 * Load the pointer to the tagged task
952 * table for this LUN.
954 SCR_LOAD_REL (dsa
, 4),
955 offsetof(struct sym_lcb
, head
.itlq_tbl_sa
),
957 * The SIDL still contains the TAG value.
958 * Aggressive optimization, isn't it? :):)
960 SCR_REG_SFBR (sidl
, SCR_SHL
, 0),
962 #if SYM_CONF_MAX_TASK*4 > 512
963 SCR_JUMPR
^ IFFALSE (CARRYSET
),
965 SCR_REG_REG (dsa1
, SCR_OR
, 2),
967 SCR_REG_REG (sfbr
, SCR_SHL
, 0),
969 SCR_JUMPR
^ IFFALSE (CARRYSET
),
971 SCR_REG_REG (dsa1
, SCR_OR
, 1),
973 #elif SYM_CONF_MAX_TASK*4 > 256
974 SCR_JUMPR
^ IFFALSE (CARRYSET
),
976 SCR_REG_REG (dsa1
, SCR_OR
, 1),
980 * Retrieve the DSA of this task.
981 * JUMP indirectly to the restart point of the CCB.
983 SCR_SFBR_REG (dsa
, SCR_AND
, 0xfc),
985 SCR_LOAD_REL (dsa
, 4),
987 SCR_LOAD_REL (temp
, 4),
988 offsetof(struct sym_ccb
, phys
.head
.go
.restart
),
991 /* In normal situations we branch to RESEL_DSA */
992 }/*-------------------------< RESEL_DSA >------------------------*/,{
994 * ACK the IDENTIFY or TAG previously received.
998 }/*-------------------------< RESEL_DSA1 >-----------------------*/,{
1000 * Initialize the status registers
1002 SCR_LOAD_REL (scr0
, 4),
1003 offsetof (struct sym_ccb
, phys
.head
.status
),
1005 * Jump to dispatcher.
1009 }/*-------------------------< RESEL_NO_TAG >---------------------*/,{
1011 * Load the DSA with the unique ITL task.
1013 SCR_LOAD_REL (dsa
, 4),
1014 offsetof(struct sym_lcb
, head
.itl_task_sa
),
1016 * JUMP indirectly to the restart point of the CCB.
1018 SCR_LOAD_REL (temp
, 4),
1019 offsetof(struct sym_ccb
, phys
.head
.go
.restart
),
1022 /* In normal situations we branch to RESEL_DSA */
1023 }/*-------------------------< DATA_IN >--------------------------*/,{
1025 * Because the size depends on the
1026 * #define SYM_CONF_MAX_SG parameter,
1027 * it is filled in at runtime.
1029 * ##===========< i=0; i<SYM_CONF_MAX_SG >=========
1030 * || SCR_CHMOV_TBL ^ SCR_DATA_IN,
1031 * || offsetof (struct sym_dsb, data[ i]),
1032 * ##==========================================
1035 }/*-------------------------< DATA_IN2 >-------------------------*/,{
1037 PADDR_A (datai_done
),
1039 PADDR_B (data_ovrun
),
1040 }/*-------------------------< DATA_OUT >-------------------------*/,{
1042 * Because the size depends on the
1043 * #define SYM_CONF_MAX_SG parameter,
1044 * it is filled in at runtime.
1046 * ##===========< i=0; i<SYM_CONF_MAX_SG >=========
1047 * || SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1048 * || offsetof (struct sym_dsb, data[ i]),
1049 * ##==========================================
1052 }/*-------------------------< DATA_OUT2 >------------------------*/,{
1054 PADDR_A (datao_done
),
1056 PADDR_B (data_ovrun
),
1057 }/*-------------------------< PM0_DATA >-------------------------*/,{
1059 * Read our host flags to SFBR, so we will be able
1060 * to check against the data direction we expect.
1062 SCR_FROM_REG (HF_REG
),
1065 * Check against actual DATA PHASE.
1067 SCR_JUMP
^ IFFALSE (WHEN (SCR_DATA_IN
)),
1068 PADDR_A (pm0_data_out
),
1070 * Actual phase is DATA IN.
1071 * Check against expected direction.
1073 SCR_JUMP
^ IFFALSE (MASK (HF_DATA_IN
, HF_DATA_IN
)),
1074 PADDR_B (data_ovrun
),
1076 * Keep track we are moving data from the
1077 * PM0 DATA mini-script.
1079 SCR_REG_REG (HF_REG
, SCR_OR
, HF_IN_PM0
),
1082 * Move the data to memory.
1084 SCR_CHMOV_TBL
^ SCR_DATA_IN
,
1085 offsetof (struct sym_ccb
, phys
.pm0
.sg
),
1087 PADDR_A (pm0_data_end
),
1088 }/*-------------------------< PM0_DATA_OUT >---------------------*/,{
1090 * Actual phase is DATA OUT.
1091 * Check against expected direction.
1093 SCR_JUMP
^ IFTRUE (MASK (HF_DATA_IN
, HF_DATA_IN
)),
1094 PADDR_B (data_ovrun
),
1096 * Keep track we are moving data from the
1097 * PM0 DATA mini-script.
1099 SCR_REG_REG (HF_REG
, SCR_OR
, HF_IN_PM0
),
1102 * Move the data from memory.
1104 SCR_CHMOV_TBL
^ SCR_DATA_OUT
,
1105 offsetof (struct sym_ccb
, phys
.pm0
.sg
),
1106 }/*-------------------------< PM0_DATA_END >---------------------*/,{
1108 * Clear the flag that told we were moving
1109 * data from the PM0 DATA mini-script.
1111 SCR_REG_REG (HF_REG
, SCR_AND
, (~HF_IN_PM0
)),
1114 * Return to the previous DATA script which
1115 * is guaranteed by design (if no bug) to be
1116 * the main DATA script for this transfer.
1118 SCR_LOAD_REL (temp
, 4),
1119 offsetof (struct sym_ccb
, phys
.pm0
.ret
),
1122 }/*-------------------------< PM1_DATA >-------------------------*/,{
1124 * Read our host flags to SFBR, so we will be able
1125 * to check against the data direction we expect.
1127 SCR_FROM_REG (HF_REG
),
1130 * Check against actual DATA PHASE.
1132 SCR_JUMP
^ IFFALSE (WHEN (SCR_DATA_IN
)),
1133 PADDR_A (pm1_data_out
),
1135 * Actual phase is DATA IN.
1136 * Check against expected direction.
1138 SCR_JUMP
^ IFFALSE (MASK (HF_DATA_IN
, HF_DATA_IN
)),
1139 PADDR_B (data_ovrun
),
1141 * Keep track we are moving data from the
1142 * PM1 DATA mini-script.
1144 SCR_REG_REG (HF_REG
, SCR_OR
, HF_IN_PM1
),
1147 * Move the data to memory.
1149 SCR_CHMOV_TBL
^ SCR_DATA_IN
,
1150 offsetof (struct sym_ccb
, phys
.pm1
.sg
),
1152 PADDR_A (pm1_data_end
),
1153 }/*-------------------------< PM1_DATA_OUT >---------------------*/,{
1155 * Actual phase is DATA OUT.
1156 * Check against expected direction.
1158 SCR_JUMP
^ IFTRUE (MASK (HF_DATA_IN
, HF_DATA_IN
)),
1159 PADDR_B (data_ovrun
),
1161 * Keep track we are moving data from the
1162 * PM1 DATA mini-script.
1164 SCR_REG_REG (HF_REG
, SCR_OR
, HF_IN_PM1
),
1167 * Move the data from memory.
1169 SCR_CHMOV_TBL
^ SCR_DATA_OUT
,
1170 offsetof (struct sym_ccb
, phys
.pm1
.sg
),
1171 }/*-------------------------< PM1_DATA_END >---------------------*/,{
1173 * Clear the flag that told we were moving
1174 * data from the PM1 DATA mini-script.
1176 SCR_REG_REG (HF_REG
, SCR_AND
, (~HF_IN_PM1
)),
1179 * Return to the previous DATA script which
1180 * is guaranteed by design (if no bug) to be
1181 * the main DATA script for this transfer.
1183 SCR_LOAD_REL (temp
, 4),
1184 offsetof (struct sym_ccb
, phys
.pm1
.ret
),
1187 }/*-------------------------<>-----------------------------------*/
1190 static struct SYM_FWB_SCR SYM_FWB_SCR
= {
1191 /*--------------------------< START64 >--------------------------*/ {
1193 * SCRIPT entry point for the 895A, 896 and 1010.
1194 * For now, there is no specific stuff for those
1195 * chips at this point, but this may come.
1199 }/*-------------------------< NO_DATA >--------------------------*/,{
1201 PADDR_B (data_ovrun
),
1202 }/*-------------------------< SEL_FOR_ABORT >--------------------*/,{
1204 * We are jumped here by the C code, if we have
1205 * some target to reset or some disconnected
1206 * job to abort. Since error recovery is a serious
1207 * busyness, we will really reset the SCSI BUS, if
1208 * case of a SCSI interrupt occurring in this path.
1210 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
1212 * Set initiator mode.
1218 * And try to select this target.
1220 SCR_SEL_TBL_ATN
^ offsetof (struct sym_hcb
, abrt_sel
),
1223 * Wait for the selection to complete or
1224 * the selection to time out.
1226 SCR_JUMPR
^ IFFALSE (WHEN (SCR_MSG_OUT
)),
1232 SIR_TARGET_SELECTED
,
1234 * The C code should let us continue here.
1235 * Send the 'kiss of death' message.
1236 * We expect an immediate disconnect once
1237 * the target has eaten the message.
1239 SCR_REG_REG (scntl2
, SCR_AND
, 0x7f),
1241 SCR_MOVE_TBL
^ SCR_MSG_OUT
,
1242 offsetof (struct sym_hcb
, abrt_tbl
),
1243 SCR_CLR (SCR_ACK
|SCR_ATN
),
1248 * Tell the C code that we are done.
1252 }/*-------------------------< SEL_FOR_ABORT_1 >------------------*/,{
1254 * Jump at scheduler.
1258 }/*-------------------------< MSG_IN_ETC >-----------------------*/,{
1260 * If it is an EXTENDED (variable size message)
1263 SCR_JUMP
^ IFTRUE (DATA (M_EXTENDED
)),
1264 PADDR_B (msg_extended
),
1266 * Let the C code handle any other
1269 SCR_JUMP
^ IFTRUE (MASK (0x00, 0xf0)),
1270 PADDR_B (msg_received
),
1271 SCR_JUMP
^ IFTRUE (MASK (0x10, 0xf0)),
1272 PADDR_B (msg_received
),
1274 * We donnot handle 2 bytes messages from SCRIPTS.
1275 * So, let the C code deal with these ones too.
1277 SCR_JUMP
^ IFFALSE (MASK (0x20, 0xf0)),
1278 PADDR_B (msg_weird_seen
),
1281 SCR_MOVE_ABS (1) ^ SCR_MSG_IN
,
1283 }/*-------------------------< MSG_RECEIVED >---------------------*/,{
1284 SCR_LOAD_REL (scratcha
, 4), /* DUMMY READ */
1288 }/*-------------------------< MSG_WEIRD_SEEN >-------------------*/,{
1289 SCR_LOAD_REL (scratcha
, 4), /* DUMMY READ */
1293 }/*-------------------------< MSG_EXTENDED >---------------------*/,{
1295 * Clear ACK and get the next byte
1296 * assumed to be the message length.
1300 SCR_MOVE_ABS (1) ^ SCR_MSG_IN
,
1303 * Try to catch some unlikely situations as 0 length
1304 * or too large the length.
1306 SCR_JUMP
^ IFTRUE (DATA (0)),
1307 PADDR_B (msg_weird_seen
),
1308 SCR_TO_REG (scratcha
),
1310 SCR_REG_REG (sfbr
, SCR_ADD
, (256-8)),
1312 SCR_JUMP
^ IFTRUE (CARRYSET
),
1313 PADDR_B (msg_weird_seen
),
1315 * We donnot handle extended messages from SCRIPTS.
1316 * Read the amount of data correponding to the
1317 * message length and call the C code.
1319 SCR_STORE_REL (scratcha
, 1),
1320 offsetof (struct sym_dsb
, smsg_ext
.size
),
1323 SCR_MOVE_TBL
^ SCR_MSG_IN
,
1324 offsetof (struct sym_dsb
, smsg_ext
),
1326 PADDR_B (msg_received
),
1327 }/*-------------------------< MSG_BAD >--------------------------*/,{
1329 * unimplemented message - reject it.
1337 }/*-------------------------< MSG_WEIRD >------------------------*/,{
1339 * weird message received
1340 * ignore all MSG IN phases and reject it.
1346 }/*-------------------------< MSG_WEIRD1 >-----------------------*/,{
1349 SCR_JUMP
^ IFFALSE (WHEN (SCR_MSG_IN
)),
1351 SCR_MOVE_ABS (1) ^ SCR_MSG_IN
,
1354 PADDR_B (msg_weird1
),
1355 }/*-------------------------< WDTR_RESP >------------------------*/,{
1357 * let the target fetch our answer.
1363 SCR_JUMP
^ IFFALSE (WHEN (SCR_MSG_OUT
)),
1364 PADDR_B (nego_bad_phase
),
1365 }/*-------------------------< SEND_WDTR >------------------------*/,{
1367 * Send the M_X_WIDE_REQ
1369 SCR_MOVE_ABS (4) ^ SCR_MSG_OUT
,
1372 PADDR_B (msg_out_done
),
1373 }/*-------------------------< SDTR_RESP >------------------------*/,{
1375 * let the target fetch our answer.
1381 SCR_JUMP
^ IFFALSE (WHEN (SCR_MSG_OUT
)),
1382 PADDR_B (nego_bad_phase
),
1383 }/*-------------------------< SEND_SDTR >------------------------*/,{
1385 * Send the M_X_SYNC_REQ
1387 SCR_MOVE_ABS (5) ^ SCR_MSG_OUT
,
1390 PADDR_B (msg_out_done
),
1391 }/*-------------------------< PPR_RESP >-------------------------*/,{
1393 * let the target fetch our answer.
1399 SCR_JUMP
^ IFFALSE (WHEN (SCR_MSG_OUT
)),
1400 PADDR_B (nego_bad_phase
),
1401 }/*-------------------------< SEND_PPR >-------------------------*/,{
1403 * Send the M_X_PPR_REQ
1405 SCR_MOVE_ABS (8) ^ SCR_MSG_OUT
,
1408 PADDR_B (msg_out_done
),
1409 }/*-------------------------< NEGO_BAD_PHASE >-------------------*/,{
1414 }/*-------------------------< MSG_OUT >--------------------------*/,{
1416 * The target requests a message.
1417 * We donnot send messages that may
1418 * require the device to go to bus free.
1420 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT
,
1423 * ... wait for the next phase
1424 * if it's a message out, send it again, ...
1426 SCR_JUMP
^ IFTRUE (WHEN (SCR_MSG_OUT
)),
1428 }/*-------------------------< MSG_OUT_DONE >---------------------*/,{
1430 * Let the C code be aware of the
1431 * sent message and clear the message.
1436 * ... and process the next phase
1440 }/*-------------------------< DATA_OVRUN >-----------------------*/,{
1442 * Use scratcha to count the extra bytes.
1444 SCR_LOAD_ABS (scratcha
, 4),
1446 }/*-------------------------< DATA_OVRUN1 >----------------------*/,{
1448 * The target may want to transfer too much data.
1450 * If phase is DATA OUT write 1 byte and count it.
1452 SCR_JUMPR
^ IFFALSE (WHEN (SCR_DATA_OUT
)),
1454 SCR_CHMOV_ABS (1) ^ SCR_DATA_OUT
,
1457 PADDR_B (data_ovrun2
),
1459 * If WSR is set, clear this condition, and
1462 SCR_FROM_REG (scntl2
),
1464 SCR_JUMPR
^ IFFALSE (MASK (WSR
, WSR
)),
1466 SCR_REG_REG (scntl2
, SCR_OR
, WSR
),
1469 PADDR_B (data_ovrun2
),
1471 * Finally check against DATA IN phase.
1472 * Signal data overrun to the C code
1473 * and jump to dispatcher if not so.
1474 * Read 1 byte otherwise and count it.
1476 SCR_JUMPR
^ IFTRUE (WHEN (SCR_DATA_IN
)),
1482 SCR_CHMOV_ABS (1) ^ SCR_DATA_IN
,
1484 }/*-------------------------< DATA_OVRUN2 >----------------------*/,{
1487 * This will allow to return a negative
1490 SCR_REG_REG (scratcha
, SCR_ADD
, 0x01),
1492 SCR_REG_REG (scratcha1
, SCR_ADDC
, 0),
1494 SCR_REG_REG (scratcha2
, SCR_ADDC
, 0),
1497 * .. and repeat as required.
1500 PADDR_B (data_ovrun1
),
1501 }/*-------------------------< ABORT_RESEL >----------------------*/,{
1507 * send the abort/abortag/reset message
1508 * we expect an immediate disconnect
1510 SCR_REG_REG (scntl2
, SCR_AND
, 0x7f),
1512 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT
,
1514 SCR_CLR (SCR_ACK
|SCR_ATN
),
1522 }/*-------------------------< RESEND_IDENT >---------------------*/,{
1524 * The target stays in MSG OUT phase after having acked
1525 * Identify [+ Tag [+ Extended message ]]. Targets shall
1526 * behave this way on parity error.
1527 * We must send it again all the messages.
1529 SCR_SET (SCR_ATN
), /* Shall be asserted 2 deskew delays before the */
1530 0, /* 1rst ACK = 90 ns. Hope the chip isn't too fast */
1532 PADDR_A (send_ident
),
1533 }/*-------------------------< IDENT_BREAK >----------------------*/,{
1538 }/*-------------------------< IDENT_BREAK_ATN >------------------*/,{
1543 }/*-------------------------< SDATA_IN >-------------------------*/,{
1544 SCR_CHMOV_TBL
^ SCR_DATA_IN
,
1545 offsetof (struct sym_dsb
, sense
),
1547 PADDR_A (datai_done
),
1549 PADDR_B (data_ovrun
),
1550 }/*-------------------------< RESEL_BAD_LUN >--------------------*/,{
1552 * Message is an IDENTIFY, but lun is unknown.
1553 * Signal problem to C code for logging the event.
1554 * Send a M_ABORT to clear all pending tasks.
1559 PADDR_B (abort_resel
),
1560 }/*-------------------------< BAD_I_T_L >------------------------*/,{
1562 * We donnot have a task for that I_T_L.
1563 * Signal problem to C code for logging the event.
1564 * Send a M_ABORT message.
1567 SIR_RESEL_BAD_I_T_L
,
1569 PADDR_B (abort_resel
),
1570 }/*-------------------------< BAD_I_T_L_Q >----------------------*/,{
1572 * We donnot have a task that matches the tag.
1573 * Signal problem to C code for logging the event.
1574 * Send a M_ABORTTAG message.
1577 SIR_RESEL_BAD_I_T_L_Q
,
1579 PADDR_B (abort_resel
),
1580 }/*-------------------------< BAD_STATUS >-----------------------*/,{
1582 * Anything different from INTERMEDIATE
1583 * CONDITION MET should be a bad SCSI status,
1584 * given that GOOD status has already been tested.
1587 SCR_LOAD_ABS (scratcha
, 4),
1589 SCR_INT
^ IFFALSE (DATA (S_COND_MET
)),
1590 SIR_BAD_SCSI_STATUS
,
1593 }/*-------------------------< PM_HANDLE >------------------------*/,{
1595 * Phase mismatch handling.
1597 * Since we have to deal with 2 SCSI data pointers
1598 * (current and saved), we need at least 2 contexts.
1599 * Each context (pm0 and pm1) has a saved area, a
1600 * SAVE mini-script and a DATA phase mini-script.
1603 * Get the PM handling flags.
1605 SCR_FROM_REG (HF_REG
),
1608 * If no flags (1rst PM for example), avoid
1609 * all the below heavy flags testing.
1610 * This makes the normal case a bit faster.
1612 SCR_JUMP
^ IFTRUE (MASK (0, (HF_IN_PM0
| HF_IN_PM1
| HF_DP_SAVED
))),
1613 PADDR_B (pm_handle1
),
1615 * If we received a SAVE DP, switch to the
1616 * other PM context since the savep may point
1617 * to the current PM context.
1619 SCR_JUMPR
^ IFFALSE (MASK (HF_DP_SAVED
, HF_DP_SAVED
)),
1621 SCR_REG_REG (sfbr
, SCR_XOR
, HF_ACT_PM
),
1624 * If we have been interrupt in a PM DATA mini-script,
1625 * we take the return address from the corresponding
1627 * This ensure the return address always points to the
1628 * main DATA script for this transfer.
1630 SCR_JUMP
^ IFTRUE (MASK (0, (HF_IN_PM0
| HF_IN_PM1
))),
1631 PADDR_B (pm_handle1
),
1632 SCR_JUMPR
^ IFFALSE (MASK (HF_IN_PM0
, HF_IN_PM0
)),
1634 SCR_LOAD_REL (ia
, 4),
1635 offsetof(struct sym_ccb
, phys
.pm0
.ret
),
1638 SCR_LOAD_REL (ia
, 4),
1639 offsetof(struct sym_ccb
, phys
.pm1
.ret
),
1642 }/*-------------------------< PM_HANDLE1 >-----------------------*/,{
1645 * Update the return address so that it
1646 * will point after the interrupted MOVE.
1648 SCR_REG_REG (ia
, SCR_ADD
, 8),
1650 SCR_REG_REG (ia1
, SCR_ADDC
, 0),
1652 }/*-------------------------< PM_SAVE >--------------------------*/,{
1654 * Clear all the flags that told us if we were
1655 * interrupted in a PM DATA mini-script and/or
1656 * we received a SAVE DP.
1658 SCR_SFBR_REG (HF_REG
, SCR_AND
, (~(HF_IN_PM0
|HF_IN_PM1
|HF_DP_SAVED
))),
1661 * Choose the current PM context.
1663 SCR_JUMP
^ IFTRUE (MASK (HF_ACT_PM
, HF_ACT_PM
)),
1665 }/*-------------------------< PM0_SAVE >-------------------------*/,{
1666 SCR_STORE_REL (ia
, 4),
1667 offsetof(struct sym_ccb
, phys
.pm0
.ret
),
1669 * If WSR bit is set, either UA and RBC may
1670 * have to be changed whether the device wants
1671 * to ignore this residue or not.
1673 SCR_FROM_REG (scntl2
),
1675 SCR_CALL
^ IFTRUE (MASK (WSR
, WSR
)),
1676 PADDR_B (pm_wsr_handle
),
1678 * Save the remaining byte count, the updated
1679 * address and the return address.
1681 SCR_STORE_REL (rbc
, 4),
1682 offsetof(struct sym_ccb
, phys
.pm0
.sg
.size
),
1683 SCR_STORE_REL (ua
, 4),
1684 offsetof(struct sym_ccb
, phys
.pm0
.sg
.addr
),
1686 * Set the current pointer at the PM0 DATA mini-script.
1688 SCR_LOAD_ABS (ia
, 4),
1689 PADDR_B (pm0_data_addr
),
1690 }/*-------------------------< PM_SAVE_END >----------------------*/,{
1691 SCR_STORE_REL (ia
, 4),
1692 offsetof(struct sym_ccb
, phys
.head
.lastp
),
1695 }/*-------------------------< PM1_SAVE >-------------------------*/,{
1696 SCR_STORE_REL (ia
, 4),
1697 offsetof(struct sym_ccb
, phys
.pm1
.ret
),
1699 * If WSR bit is set, either UA and RBC may
1700 * have to be changed whether the device wants
1701 * to ignore this residue or not.
1703 SCR_FROM_REG (scntl2
),
1705 SCR_CALL
^ IFTRUE (MASK (WSR
, WSR
)),
1706 PADDR_B (pm_wsr_handle
),
1708 * Save the remaining byte count, the updated
1709 * address and the return address.
1711 SCR_STORE_REL (rbc
, 4),
1712 offsetof(struct sym_ccb
, phys
.pm1
.sg
.size
),
1713 SCR_STORE_REL (ua
, 4),
1714 offsetof(struct sym_ccb
, phys
.pm1
.sg
.addr
),
1716 * Set the current pointer at the PM1 DATA mini-script.
1718 SCR_LOAD_ABS (ia
, 4),
1719 PADDR_B (pm1_data_addr
),
1721 PADDR_B (pm_save_end
),
1722 }/*-------------------------< PM_WSR_HANDLE >--------------------*/,{
1724 * Phase mismatch handling from SCRIPT with WSR set.
1725 * Such a condition can occur if the chip wants to
1726 * execute a CHMOV(size > 1) when the WSR bit is
1727 * set and the target changes PHASE.
1729 * We must move the residual byte to memory.
1731 * UA contains bit 0..31 of the address to
1732 * move the residual byte.
1733 * Move it to the table indirect.
1735 SCR_STORE_REL (ua
, 4),
1736 offsetof (struct sym_ccb
, phys
.wresid
.addr
),
1738 * Increment UA (move address to next position).
1740 SCR_REG_REG (ua
, SCR_ADD
, 1),
1742 SCR_REG_REG (ua1
, SCR_ADDC
, 0),
1744 SCR_REG_REG (ua2
, SCR_ADDC
, 0),
1746 SCR_REG_REG (ua3
, SCR_ADDC
, 0),
1749 * Compute SCRATCHA as:
1750 * - size to transfer = 1 byte.
1751 * - bit 24..31 = high address bit [32...39].
1753 SCR_LOAD_ABS (scratcha
, 4),
1755 SCR_REG_REG (scratcha
, SCR_OR
, 1),
1757 SCR_FROM_REG (rbc3
),
1759 SCR_TO_REG (scratcha3
),
1762 * Move this value to the table indirect.
1764 SCR_STORE_REL (scratcha
, 4),
1765 offsetof (struct sym_ccb
, phys
.wresid
.size
),
1767 * Wait for a valid phase.
1768 * While testing with bogus QUANTUM drives, the C1010
1769 * sometimes raised a spurious phase mismatch with
1770 * WSR and the CHMOV(1) triggered another PM.
1771 * Waiting explicitly for the PHASE seemed to avoid
1772 * the nested phase mismatch. Btw, this didn't happen
1773 * using my IBM drives.
1775 SCR_JUMPR
^ IFFALSE (WHEN (SCR_DATA_IN
)),
1778 * Perform the move of the residual byte.
1780 SCR_CHMOV_TBL
^ SCR_DATA_IN
,
1781 offsetof (struct sym_ccb
, phys
.wresid
),
1783 * We can now handle the phase mismatch with UA fixed.
1784 * RBC[0..23]=0 is a special case that does not require
1785 * a PM context. The C code also checks against this.
1789 SCR_RETURN
^ IFFALSE (DATA (0)),
1791 SCR_FROM_REG (rbc1
),
1793 SCR_RETURN
^ IFFALSE (DATA (0)),
1795 SCR_FROM_REG (rbc2
),
1797 SCR_RETURN
^ IFFALSE (DATA (0)),
1801 * Not only we donnot need a PM context, but this would
1802 * lead to a bogus CHMOV(0). This condition means that
1803 * the residual was the last byte to move from this CHMOV.
1804 * So, we just have to move the current data script pointer
1805 * (i.e. TEMP) to the SCRIPTS address following the
1806 * interrupted CHMOV and jump to dispatcher.
1807 * IA contains the data pointer to save.
1810 PADDR_B (pm_save_end
),
1811 }/*-------------------------< WSR_MA_HELPER >--------------------*/,{
1813 * Helper for the C code when WSR bit is set.
1814 * Perform the move of the residual byte.
1816 SCR_CHMOV_TBL
^ SCR_DATA_IN
,
1817 offsetof (struct sym_ccb
, phys
.wresid
),
1821 }/*-------------------------< ZERO >-----------------------------*/,{
1823 }/*-------------------------< SCRATCH >--------------------------*/,{
1825 }/*-------------------------< PM0_DATA_ADDR >--------------------*/,{
1827 }/*-------------------------< PM1_DATA_ADDR >--------------------*/,{
1829 }/*-------------------------< DONE_POS >-------------------------*/,{
1831 }/*-------------------------< STARTPOS >-------------------------*/,{
1833 }/*-------------------------< TARGTBL >--------------------------*/,{
1835 }/*-------------------------<>-----------------------------------*/
1838 static struct SYM_FWZ_SCR SYM_FWZ_SCR
= {
1839 /*-------------------------< SNOOPTEST >------------------------*/{
1841 * Read the variable from memory.
1843 SCR_LOAD_REL (scratcha
, 4),
1844 offsetof(struct sym_hcb
, scratch
),
1846 * Write the variable to memory.
1848 SCR_STORE_REL (temp
, 4),
1849 offsetof(struct sym_hcb
, scratch
),
1851 * Read back the variable from memory.
1853 SCR_LOAD_REL (temp
, 4),
1854 offsetof(struct sym_hcb
, scratch
),
1855 }/*-------------------------< SNOOPEND >-------------------------*/,{
1861 }/*-------------------------<>-----------------------------------*/