?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / scsi / qla2xxx / qla_nx.h
blob15559cab39f8761ea4e75e19658e476011e012be
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_NX_H
8 #define __QLA_NX_H
9
10 /*
11 * Following are the states of the Phantom. Phantom will set them and
12 * Host will read to check if the fields are correct.
13 */
14 #define PHAN_INITIALIZE_FAILED 0xffff
15 #define PHAN_INITIALIZE_COMPLETE 0xff01
16
17 /* Host writes the following to notify that it has done the init-handshake */
18 #define PHAN_INITIALIZE_ACK 0xf00f
19 #define PHAN_PEG_RCV_INITIALIZED 0xff01
20
21 /*CRB_RELATED*/
22 #define QLA82XX_CRB_BASE QLA82XX_CAM_RAM(0x200)
23 #define QLA82XX_REG(X) (QLA82XX_CRB_BASE+(X))
24
25 #define CRB_CMDPEG_STATE QLA82XX_REG(0x50)
26 #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c)
27 #define BOOT_LOADER_DIMM_STATUS QLA82XX_REG(0x54)
28 #define CRB_DMA_SHIFT QLA82XX_REG(0xcc)
29
30 #define QLA82XX_HW_H0_CH_HUB_ADR 0x05
31 #define QLA82XX_HW_H1_CH_HUB_ADR 0x0E
32 #define QLA82XX_HW_H2_CH_HUB_ADR 0x03
33 #define QLA82XX_HW_H3_CH_HUB_ADR 0x01
34 #define QLA82XX_HW_H4_CH_HUB_ADR 0x06
35 #define QLA82XX_HW_H5_CH_HUB_ADR 0x07
36 #define QLA82XX_HW_H6_CH_HUB_ADR 0x08
37
38 /* Hub 0 */
39 #define QLA82XX_HW_MN_CRB_AGT_ADR 0x15
40 #define QLA82XX_HW_MS_CRB_AGT_ADR 0x25
41
42 /* Hub 1 */
43 #define QLA82XX_HW_PS_CRB_AGT_ADR 0x73
44 #define QLA82XX_HW_QMS_CRB_AGT_ADR 0x00
45 #define QLA82XX_HW_RPMX3_CRB_AGT_ADR 0x0b
46 #define QLA82XX_HW_SQGS0_CRB_AGT_ADR 0x01
47 #define QLA82XX_HW_SQGS1_CRB_AGT_ADR 0x02
48 #define QLA82XX_HW_SQGS2_CRB_AGT_ADR 0x03
49 #define QLA82XX_HW_SQGS3_CRB_AGT_ADR 0x04
50 #define QLA82XX_HW_C2C0_CRB_AGT_ADR 0x58
51 #define QLA82XX_HW_C2C1_CRB_AGT_ADR 0x59
52 #define QLA82XX_HW_C2C2_CRB_AGT_ADR 0x5a
53 #define QLA82XX_HW_RPMX2_CRB_AGT_ADR 0x0a
54 #define QLA82XX_HW_RPMX4_CRB_AGT_ADR 0x0c
55 #define QLA82XX_HW_RPMX7_CRB_AGT_ADR 0x0f
56 #define QLA82XX_HW_RPMX9_CRB_AGT_ADR 0x12
57 #define QLA82XX_HW_SMB_CRB_AGT_ADR 0x18
58
59 /* Hub 2 */
60 #define QLA82XX_HW_NIU_CRB_AGT_ADR 0x31
61 #define QLA82XX_HW_I2C0_CRB_AGT_ADR 0x19
62 #define QLA82XX_HW_I2C1_CRB_AGT_ADR 0x29
63
64 #define QLA82XX_HW_SN_CRB_AGT_ADR 0x10
65 #define QLA82XX_HW_I2Q_CRB_AGT_ADR 0x20
66 #define QLA82XX_HW_LPC_CRB_AGT_ADR 0x22
67 #define QLA82XX_HW_ROMUSB_CRB_AGT_ADR 0x21
68 #define QLA82XX_HW_QM_CRB_AGT_ADR 0x66
69 #define QLA82XX_HW_SQG0_CRB_AGT_ADR 0x60
70 #define QLA82XX_HW_SQG1_CRB_AGT_ADR 0x61
71 #define QLA82XX_HW_SQG2_CRB_AGT_ADR 0x62
72 #define QLA82XX_HW_SQG3_CRB_AGT_ADR 0x63
73 #define QLA82XX_HW_RPMX1_CRB_AGT_ADR 0x09
74 #define QLA82XX_HW_RPMX5_CRB_AGT_ADR 0x0d
75 #define QLA82XX_HW_RPMX6_CRB_AGT_ADR 0x0e
76 #define QLA82XX_HW_RPMX8_CRB_AGT_ADR 0x11
77
78 /* Hub 3 */
79 #define QLA82XX_HW_PH_CRB_AGT_ADR 0x1A
80 #define QLA82XX_HW_SRE_CRB_AGT_ADR 0x50
81 #define QLA82XX_HW_EG_CRB_AGT_ADR 0x51
82 #define QLA82XX_HW_RPMX0_CRB_AGT_ADR 0x08
83
84 /* Hub 4 */
85 #define QLA82XX_HW_PEGN0_CRB_AGT_ADR 0x40
86 #define QLA82XX_HW_PEGN1_CRB_AGT_ADR 0x41
87 #define QLA82XX_HW_PEGN2_CRB_AGT_ADR 0x42
88 #define QLA82XX_HW_PEGN3_CRB_AGT_ADR 0x43
89 #define QLA82XX_HW_PEGNI_CRB_AGT_ADR 0x44
90 #define QLA82XX_HW_PEGND_CRB_AGT_ADR 0x45
91 #define QLA82XX_HW_PEGNC_CRB_AGT_ADR 0x46
92 #define QLA82XX_HW_PEGR0_CRB_AGT_ADR 0x47
93 #define QLA82XX_HW_PEGR1_CRB_AGT_ADR 0x48
94 #define QLA82XX_HW_PEGR2_CRB_AGT_ADR 0x49
95 #define QLA82XX_HW_PEGR3_CRB_AGT_ADR 0x4a
96 #define QLA82XX_HW_PEGN4_CRB_AGT_ADR 0x4b
97
98 /* Hub 5 */
99 #define QLA82XX_HW_PEGS0_CRB_AGT_ADR 0x40
100 #define QLA82XX_HW_PEGS1_CRB_AGT_ADR 0x41
101 #define QLA82XX_HW_PEGS2_CRB_AGT_ADR 0x42
102 #define QLA82XX_HW_PEGS3_CRB_AGT_ADR 0x43
103 #define QLA82XX_HW_PEGSI_CRB_AGT_ADR 0x44
104 #define QLA82XX_HW_PEGSD_CRB_AGT_ADR 0x45
105 #define QLA82XX_HW_PEGSC_CRB_AGT_ADR 0x46
106
107 /* Hub 6 */
108 #define QLA82XX_HW_CAS0_CRB_AGT_ADR 0x46
109 #define QLA82XX_HW_CAS1_CRB_AGT_ADR 0x47
110 #define QLA82XX_HW_CAS2_CRB_AGT_ADR 0x48
111 #define QLA82XX_HW_CAS3_CRB_AGT_ADR 0x49
112 #define QLA82XX_HW_NCM_CRB_AGT_ADR 0x16
113 #define QLA82XX_HW_TMR_CRB_AGT_ADR 0x17
114 #define QLA82XX_HW_XDMA_CRB_AGT_ADR 0x05
115 #define QLA82XX_HW_OCM0_CRB_AGT_ADR 0x06
116 #define QLA82XX_HW_OCM1_CRB_AGT_ADR 0x07
117
118 /* This field defines PCI/X adr [25:20] of agents on the CRB */
119 /* */
120 #define QLA82XX_HW_PX_MAP_CRB_PH 0
121 #define QLA82XX_HW_PX_MAP_CRB_PS 1
122 #define QLA82XX_HW_PX_MAP_CRB_MN 2
123 #define QLA82XX_HW_PX_MAP_CRB_MS 3
124 #define QLA82XX_HW_PX_MAP_CRB_SRE 5
125 #define QLA82XX_HW_PX_MAP_CRB_NIU 6
126 #define QLA82XX_HW_PX_MAP_CRB_QMN 7
127 #define QLA82XX_HW_PX_MAP_CRB_SQN0 8
128 #define QLA82XX_HW_PX_MAP_CRB_SQN1 9
129 #define QLA82XX_HW_PX_MAP_CRB_SQN2 10
130 #define QLA82XX_HW_PX_MAP_CRB_SQN3 11
131 #define QLA82XX_HW_PX_MAP_CRB_QMS 12
132 #define QLA82XX_HW_PX_MAP_CRB_SQS0 13
133 #define QLA82XX_HW_PX_MAP_CRB_SQS1 14
134 #define QLA82XX_HW_PX_MAP_CRB_SQS2 15
135 #define QLA82XX_HW_PX_MAP_CRB_SQS3 16
136 #define QLA82XX_HW_PX_MAP_CRB_PGN0 17
137 #define QLA82XX_HW_PX_MAP_CRB_PGN1 18
138 #define QLA82XX_HW_PX_MAP_CRB_PGN2 19
139 #define QLA82XX_HW_PX_MAP_CRB_PGN3 20
140 #define QLA82XX_HW_PX_MAP_CRB_PGN4 QLA82XX_HW_PX_MAP_CRB_SQS2
141 #define QLA82XX_HW_PX_MAP_CRB_PGND 21
142 #define QLA82XX_HW_PX_MAP_CRB_PGNI 22
143 #define QLA82XX_HW_PX_MAP_CRB_PGS0 23
144 #define QLA82XX_HW_PX_MAP_CRB_PGS1 24
145 #define QLA82XX_HW_PX_MAP_CRB_PGS2 25
146 #define QLA82XX_HW_PX_MAP_CRB_PGS3 26
147 #define QLA82XX_HW_PX_MAP_CRB_PGSD 27
148 #define QLA82XX_HW_PX_MAP_CRB_PGSI 28
149 #define QLA82XX_HW_PX_MAP_CRB_SN 29
150 #define QLA82XX_HW_PX_MAP_CRB_EG 31
151 #define QLA82XX_HW_PX_MAP_CRB_PH2 32
152 #define QLA82XX_HW_PX_MAP_CRB_PS2 33
153 #define QLA82XX_HW_PX_MAP_CRB_CAM 34
154 #define QLA82XX_HW_PX_MAP_CRB_CAS0 35
155 #define QLA82XX_HW_PX_MAP_CRB_CAS1 36
156 #define QLA82XX_HW_PX_MAP_CRB_CAS2 37
157 #define QLA82XX_HW_PX_MAP_CRB_C2C0 38
158 #define QLA82XX_HW_PX_MAP_CRB_C2C1 39
159 #define QLA82XX_HW_PX_MAP_CRB_TIMR 40
160 #define QLA82XX_HW_PX_MAP_CRB_RPMX1 42
161 #define QLA82XX_HW_PX_MAP_CRB_RPMX2 43
162 #define QLA82XX_HW_PX_MAP_CRB_RPMX3 44
163 #define QLA82XX_HW_PX_MAP_CRB_RPMX4 45
164 #define QLA82XX_HW_PX_MAP_CRB_RPMX5 46
165 #define QLA82XX_HW_PX_MAP_CRB_RPMX6 47
166 #define QLA82XX_HW_PX_MAP_CRB_RPMX7 48
167 #define QLA82XX_HW_PX_MAP_CRB_XDMA 49
168 #define QLA82XX_HW_PX_MAP_CRB_I2Q 50
169 #define QLA82XX_HW_PX_MAP_CRB_ROMUSB 51
170 #define QLA82XX_HW_PX_MAP_CRB_CAS3 52
171 #define QLA82XX_HW_PX_MAP_CRB_RPMX0 53
172 #define QLA82XX_HW_PX_MAP_CRB_RPMX8 54
173 #define QLA82XX_HW_PX_MAP_CRB_RPMX9 55
174 #define QLA82XX_HW_PX_MAP_CRB_OCM0 56
175 #define QLA82XX_HW_PX_MAP_CRB_OCM1 57
176 #define QLA82XX_HW_PX_MAP_CRB_SMB 58
177 #define QLA82XX_HW_PX_MAP_CRB_I2C0 59
178 #define QLA82XX_HW_PX_MAP_CRB_I2C1 60
179 #define QLA82XX_HW_PX_MAP_CRB_LPC 61
180 #define QLA82XX_HW_PX_MAP_CRB_PGNC 62
181 #define QLA82XX_HW_PX_MAP_CRB_PGR0 63
182 #define QLA82XX_HW_PX_MAP_CRB_PGR1 4
183 #define QLA82XX_HW_PX_MAP_CRB_PGR2 30
184 #define QLA82XX_HW_PX_MAP_CRB_PGR3 41
185
186 /* This field defines CRB adr [31:20] of the agents */
187 /* */
188
189 #define QLA82XX_HW_CRB_HUB_AGT_ADR_MN ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
190 QLA82XX_HW_MN_CRB_AGT_ADR)
191 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PH ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
192 QLA82XX_HW_PH_CRB_AGT_ADR)
193 #define QLA82XX_HW_CRB_HUB_AGT_ADR_MS ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
194 QLA82XX_HW_MS_CRB_AGT_ADR)
195 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
196 QLA82XX_HW_PS_CRB_AGT_ADR)
197 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
198 QLA82XX_HW_SS_CRB_AGT_ADR)
199 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
200 QLA82XX_HW_RPMX3_CRB_AGT_ADR)
201 #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
202 QLA82XX_HW_QMS_CRB_AGT_ADR)
203 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
204 QLA82XX_HW_SQGS0_CRB_AGT_ADR)
205 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
206 QLA82XX_HW_SQGS1_CRB_AGT_ADR)
207 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
208 QLA82XX_HW_SQGS2_CRB_AGT_ADR)
209 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
210 QLA82XX_HW_SQGS3_CRB_AGT_ADR)
211 #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
212 QLA82XX_HW_C2C0_CRB_AGT_ADR)
213 #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
214 QLA82XX_HW_C2C1_CRB_AGT_ADR)
215 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
216 QLA82XX_HW_RPMX2_CRB_AGT_ADR)
217 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
218 QLA82XX_HW_RPMX4_CRB_AGT_ADR)
219 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
220 QLA82XX_HW_RPMX7_CRB_AGT_ADR)
221 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
222 QLA82XX_HW_RPMX9_CRB_AGT_ADR)
223 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SMB ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
224 QLA82XX_HW_SMB_CRB_AGT_ADR)
225 #define QLA82XX_HW_CRB_HUB_AGT_ADR_NIU ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
226 QLA82XX_HW_NIU_CRB_AGT_ADR)
227 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
228 QLA82XX_HW_I2C0_CRB_AGT_ADR)
229 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
230 QLA82XX_HW_I2C1_CRB_AGT_ADR)
231 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SRE ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
232 QLA82XX_HW_SRE_CRB_AGT_ADR)
233 #define QLA82XX_HW_CRB_HUB_AGT_ADR_EG ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
234 QLA82XX_HW_EG_CRB_AGT_ADR)
235 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
236 QLA82XX_HW_RPMX0_CRB_AGT_ADR)
237 #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMN ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
238 QLA82XX_HW_QM_CRB_AGT_ADR)
239 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
240 QLA82XX_HW_SQG0_CRB_AGT_ADR)
241 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
242 QLA82XX_HW_SQG1_CRB_AGT_ADR)
243 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
244 QLA82XX_HW_SQG2_CRB_AGT_ADR)
245 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
246 QLA82XX_HW_SQG3_CRB_AGT_ADR)
247 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
248 QLA82XX_HW_RPMX1_CRB_AGT_ADR)
249 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
250 QLA82XX_HW_RPMX5_CRB_AGT_ADR)
251 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
252 QLA82XX_HW_RPMX6_CRB_AGT_ADR)
253 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
254 QLA82XX_HW_RPMX8_CRB_AGT_ADR)
255 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
256 QLA82XX_HW_CAS0_CRB_AGT_ADR)
257 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
258 QLA82XX_HW_CAS1_CRB_AGT_ADR)
259 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
260 QLA82XX_HW_CAS2_CRB_AGT_ADR)
261 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
262 QLA82XX_HW_CAS3_CRB_AGT_ADR)
263 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
264 QLA82XX_HW_PEGNI_CRB_AGT_ADR)
265 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGND ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
266 QLA82XX_HW_PEGND_CRB_AGT_ADR)
267 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
268 QLA82XX_HW_PEGN0_CRB_AGT_ADR)
269 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
270 QLA82XX_HW_PEGN1_CRB_AGT_ADR)
271 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
272 QLA82XX_HW_PEGN2_CRB_AGT_ADR)
273 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
274 QLA82XX_HW_PEGN3_CRB_AGT_ADR)
275 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
276 QLA82XX_HW_PEGN4_CRB_AGT_ADR)
277 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
278 QLA82XX_HW_PEGNC_CRB_AGT_ADR)
279 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
280 QLA82XX_HW_PEGR0_CRB_AGT_ADR)
281 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
282 QLA82XX_HW_PEGR1_CRB_AGT_ADR)
283 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
284 QLA82XX_HW_PEGR2_CRB_AGT_ADR)
285 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
286 QLA82XX_HW_PEGR3_CRB_AGT_ADR)
287 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
288 QLA82XX_HW_PEGSI_CRB_AGT_ADR)
289 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSD ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
290 QLA82XX_HW_PEGSD_CRB_AGT_ADR)
291 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
292 QLA82XX_HW_PEGS0_CRB_AGT_ADR)
293 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
294 QLA82XX_HW_PEGS1_CRB_AGT_ADR)
295 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
296 QLA82XX_HW_PEGS2_CRB_AGT_ADR)
297 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
298 QLA82XX_HW_PEGS3_CRB_AGT_ADR)
299 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSC ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
300 QLA82XX_HW_PEGSC_CRB_AGT_ADR)
301 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAM ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
302 QLA82XX_HW_NCM_CRB_AGT_ADR)
303 #define QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
304 QLA82XX_HW_TMR_CRB_AGT_ADR)
305 #define QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
306 QLA82XX_HW_XDMA_CRB_AGT_ADR)
307 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SN ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
308 QLA82XX_HW_SN_CRB_AGT_ADR)
309 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
310 QLA82XX_HW_I2Q_CRB_AGT_ADR)
311 #define QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
312 QLA82XX_HW_ROMUSB_CRB_AGT_ADR)
313 #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
314 QLA82XX_HW_OCM0_CRB_AGT_ADR)
315 #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM1 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
316 QLA82XX_HW_OCM1_CRB_AGT_ADR)
317 #define QLA82XX_HW_CRB_HUB_AGT_ADR_LPC ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
318 QLA82XX_HW_LPC_CRB_AGT_ADR)
319
320 #define ROMUSB_GLB (QLA82XX_CRB_ROMUSB + 0x00000)
321 #define QLA82XX_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
322 #define QLA82XX_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
323 #define QLA82XX_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
324 #define QLA82XX_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
325 #define QLA82XX_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
326 #define QLA82XX_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
327 #define QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
328 #define QLA82XX_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
329
330 #define ROMUSB_ROM (QLA82XX_CRB_ROMUSB + 0x10000)
331 #define QLA82XX_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
332 #define QLA82XX_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
333
334 /* Lock IDs for ROM lock */
335 #define ROM_LOCK_DRIVER 0x0d417340
336
337 #define QLA82XX_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */
338 #define QLA82XX_PCI_CRB_WINDOW(A) \
339 (QLA82XX_PCI_CRBSPACE + (A)*QLA82XX_PCI_CRB_WINDOWSIZE)
340 #define QLA82XX_CRB_C2C_0 \
341 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C0)
342 #define QLA82XX_CRB_C2C_1 \
343 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C1)
344 #define QLA82XX_CRB_C2C_2 \
345 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C2)
346 #define QLA82XX_CRB_CAM \
347 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAM)
348 #define QLA82XX_CRB_CASPER \
349 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS)
350 #define QLA82XX_CRB_CASPER_0 \
351 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS0)
352 #define QLA82XX_CRB_CASPER_1 \
353 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS1)
354 #define QLA82XX_CRB_CASPER_2 \
355 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS2)
356 #define QLA82XX_CRB_DDR_MD \
357 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MS)
358 #define QLA82XX_CRB_DDR_NET \
359 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MN)
360 #define QLA82XX_CRB_EPG \
361 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_EG)
362 #define QLA82XX_CRB_I2Q \
363 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2Q)
364 #define QLA82XX_CRB_NIU \
365 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_NIU)
366
367 #define QLA82XX_CRB_PCIX_HOST \
368 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH)
369 #define QLA82XX_CRB_PCIX_HOST2 \
370 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH2)
371 #define QLA82XX_CRB_PCIX_MD \
372 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS)
373 #define QLA82XX_CRB_PCIE \
374 QLA82XX_CRB_PCIX_MD
375
376 /* window 1 pcie slot */
377 #define QLA82XX_CRB_PCIE2 \
378 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS2)
379 #define QLA82XX_CRB_PEG_MD_0 \
380 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS0)
381 #define QLA82XX_CRB_PEG_MD_1 \
382 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS1)
383 #define QLA82XX_CRB_PEG_MD_2 \
384 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS2)
385 #define QLA82XX_CRB_PEG_MD_3 \
386 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)
387 #define QLA82XX_CRB_PEG_MD_3 \
388 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)
389 #define QLA82XX_CRB_PEG_MD_D \
390 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSD)
391 #define QLA82XX_CRB_PEG_MD_I \
392 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSI)
393 #define QLA82XX_CRB_PEG_NET_0 \
394 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN0)
395 #define QLA82XX_CRB_PEG_NET_1 \
396 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN1)
397 #define QLA82XX_CRB_PEG_NET_2 \
398 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN2)
399 #define QLA82XX_CRB_PEG_NET_3 \
400 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN3)
401 #define QLA82XX_CRB_PEG_NET_4 \
402 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN4)
403 #define QLA82XX_CRB_PEG_NET_D \
404 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGND)
405 #define QLA82XX_CRB_PEG_NET_I \
406 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGNI)
407 #define QLA82XX_CRB_PQM_MD \
408 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMS)
409 #define QLA82XX_CRB_PQM_NET \
410 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMN)
411 #define QLA82XX_CRB_QDR_MD \
412 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SS)
413 #define QLA82XX_CRB_QDR_NET \
414 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SN)
415 #define QLA82XX_CRB_ROMUSB \
416 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_ROMUSB)
417 #define QLA82XX_CRB_RPMX_0 \
418 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX0)
419 #define QLA82XX_CRB_RPMX_1 \
420 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX1)
421 #define QLA82XX_CRB_RPMX_2 \
422 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX2)
423 #define QLA82XX_CRB_RPMX_3 \
424 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX3)
425 #define QLA82XX_CRB_RPMX_4 \
426 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX4)
427 #define QLA82XX_CRB_RPMX_5 \
428 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX5)
429 #define QLA82XX_CRB_RPMX_6 \
430 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX6)
431 #define QLA82XX_CRB_RPMX_7 \
432 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX7)
433 #define QLA82XX_CRB_SQM_MD_0 \
434 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS0)
435 #define QLA82XX_CRB_SQM_MD_1 \
436 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS1)
437 #define QLA82XX_CRB_SQM_MD_2 \
438 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS2)
439 #define QLA82XX_CRB_SQM_MD_3 \
440 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS3)
441 #define QLA82XX_CRB_SQM_NET_0 \
442 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN0)
443 #define QLA82XX_CRB_SQM_NET_1 \
444 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN1)
445 #define QLA82XX_CRB_SQM_NET_2 \
446 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN2)
447 #define QLA82XX_CRB_SQM_NET_3 \
448 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN3)
449 #define QLA82XX_CRB_SRE \
450 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SRE)
451 #define QLA82XX_CRB_TIMER \
452 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_TIMR)
453 #define QLA82XX_CRB_XDMA \
454 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_XDMA)
455 #define QLA82XX_CRB_I2C0 \
456 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C0)
457 #define QLA82XX_CRB_I2C1 \
458 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C1)
459 #define QLA82XX_CRB_OCM0 \
460 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_OCM0)
461 #define QLA82XX_CRB_SMB \
462 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SMB)
463 #define QLA82XX_CRB_MAX \
464 QLA82XX_PCI_CRB_WINDOW(64)
465
466 /*
467 * ====================== BASE ADDRESSES ON-CHIP ======================
468 * Base addresses of major components on-chip.
469 * ====================== BASE ADDRESSES ON-CHIP ======================
470 */
471 #define QLA82XX_ADDR_DDR_NET (0x0000000000000000ULL)
472 #define QLA82XX_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
473
474 /* Imbus address bit used to indicate a host address. This bit is
475 * eliminated by the pcie bar and bar select before presentation
476 * over pcie. */
477 /* host memory via IMBUS */
478 #define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL)
479 #define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL)
480 #define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
481 #define QLA82XX_ADDR_OCM0 (0x0000000200000000ULL)
482 #define QLA82XX_ADDR_OCM0_MAX (0x00000002000fffffULL)
483 #define QLA82XX_ADDR_OCM1 (0x0000000200400000ULL)
484 #define QLA82XX_ADDR_OCM1_MAX (0x00000002004fffffULL)
485 #define QLA82XX_ADDR_QDR_NET (0x0000000300000000ULL)
486
487 #define QLA82XX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)
488 #define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
489
490 #define QLA82XX_PCI_CRBSPACE (unsigned long)0x06000000
491 #define QLA82XX_PCI_DIRECT_CRB (unsigned long)0x04400000
492 #define QLA82XX_PCI_CAMQM (unsigned long)0x04800000
493 #define QLA82XX_PCI_CAMQM_MAX (unsigned long)0x04ffffff
494 #define QLA82XX_PCI_DDR_NET (unsigned long)0x00000000
495 #define QLA82XX_PCI_QDR_NET (unsigned long)0x04000000
496 #define QLA82XX_PCI_QDR_NET_MAX (unsigned long)0x043fffff
497
498 /*
499 * Register offsets for MN
500 */
501 #define MIU_CONTROL (0x000)
502 #define MIU_TAG (0x004)
503 #define MIU_TEST_AGT_CTRL (0x090)
504 #define MIU_TEST_AGT_ADDR_LO (0x094)
505 #define MIU_TEST_AGT_ADDR_HI (0x098)
506 #define MIU_TEST_AGT_WRDATA_LO (0x0a0)
507 #define MIU_TEST_AGT_WRDATA_HI (0x0a4)
508 #define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i)))
509 #define MIU_TEST_AGT_RDDATA_LO (0x0a8)
510 #define MIU_TEST_AGT_RDDATA_HI (0x0ac)
511 #define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i)))
512 #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
513 #define MIU_TEST_AGT_UPPER_ADDR(off) (0)
514
515 /* MIU_TEST_AGT_CTRL flags. work for SIU as well */
516 #define MIU_TA_CTL_START 1
517 #define MIU_TA_CTL_ENABLE 2
518 #define MIU_TA_CTL_WRITE 4
519 #define MIU_TA_CTL_BUSY 8
520
521 /*CAM RAM */
522 # define QLA82XX_CAM_RAM_BASE (QLA82XX_CRB_CAM + 0x02000)
523 # define QLA82XX_CAM_RAM(reg) (QLA82XX_CAM_RAM_BASE + (reg))
524
525 #define QLA82XX_PEG_TUNE_MN_SPD_ZEROED 0x80000000
526 #define QLA82XX_BOOT_LOADER_MN_ISSUE 0xff00ffff
527 #define QLA82XX_PORT_MODE_ADDR (QLA82XX_CAM_RAM(0x24))
528 #define QLA82XX_PEG_HALT_STATUS1 (QLA82XX_CAM_RAM(0xa8))
529 #define QLA82XX_PEG_HALT_STATUS2 (QLA82XX_CAM_RAM(0xac))
530 #define QLA82XX_PEG_ALIVE_COUNTER (QLA82XX_CAM_RAM(0xb0))
531
532 #define QLA82XX_CAMRAM_DB1 (QLA82XX_CAM_RAM(0x1b8))
533 #define QLA82XX_CAMRAM_DB2 (QLA82XX_CAM_RAM(0x1bc))
534
535 #define HALT_STATUS_UNRECOVERABLE 0x80000000
536 #define HALT_STATUS_RECOVERABLE 0x40000000
537
538 /* Driver Coexistence Defines */
539 #define QLA82XX_CRB_DRV_ACTIVE (QLA82XX_CAM_RAM(0x138))
540 #define QLA82XX_CRB_DEV_STATE (QLA82XX_CAM_RAM(0x140))
541 #define QLA82XX_CRB_DRV_STATE (QLA82XX_CAM_RAM(0x144))
542 #define QLA82XX_CRB_DRV_SCRATCH (QLA82XX_CAM_RAM(0x148))
543 #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c))
544 #define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174))
545
546 /* Every driver should use these Device State */
547 #define QLA82XX_DEV_COLD 1
548 #define QLA82XX_DEV_INITIALIZING 2
549 #define QLA82XX_DEV_READY 3
550 #define QLA82XX_DEV_NEED_RESET 4
551 #define QLA82XX_DEV_NEED_QUIESCENT 5
552 #define QLA82XX_DEV_FAILED 6
553 #define QLA82XX_DEV_QUIESCENT 7
554 #define MAX_STATES 8 /* Increment if new state added */
555
556 #define QLA82XX_IDC_VERSION 1
557 #define QLA82XX_ROM_DEV_INIT_TIMEOUT 30
558 #define QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT 10
559
560 #define QLA82XX_ROM_LOCK_ID (QLA82XX_CAM_RAM(0x100))
561 #define QLA82XX_CRB_WIN_LOCK_ID (QLA82XX_CAM_RAM(0x124))
562 #define QLA82XX_FW_VERSION_MAJOR (QLA82XX_CAM_RAM(0x150))
563 #define QLA82XX_FW_VERSION_MINOR (QLA82XX_CAM_RAM(0x154))
564 #define QLA82XX_FW_VERSION_SUB (QLA82XX_CAM_RAM(0x158))
565 #define QLA82XX_PCIE_REG(reg) (QLA82XX_CRB_PCIE + (reg))
566
567 #define PCIE_CHICKEN3 (0x120c8)
568 #define PCIE_SETUP_FUNCTION (0x12040)
569 #define PCIE_SETUP_FUNCTION2 (0x12048)
570
571 #define QLA82XX_PCIX_PS_REG(reg) (QLA82XX_CRB_PCIX_MD + (reg))
572 #define QLA82XX_PCIX_PS2_REG(reg) (QLA82XX_CRB_PCIE2 + (reg))
573
574 #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */
575 #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */
576 #define PCIE_SEM5_LOCK (0x1c028) /* Coexistence lock */
577 #define PCIE_SEM5_UNLOCK (0x1c02c) /* Coexistence unlock */
578 #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */
579 #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/
580
581 /* Different drive state */
582 #define QLA82XX_DRVST_NOT_RDY 0
583 #define QLA82XX_DRVST_RST_RDY 1
584 #define QLA82XX_DRVST_QSNT_RDY 2
585
586 /*
587 * The PCI VendorID and DeviceID for our board.
588 */
589 #define PCI_DEVICE_ID_QLOGIC_ISP8021 0x8021
590
591 #define QLA82XX_MSIX_TBL_SPACE 8192
592 #define QLA82XX_PCI_REG_MSIX_TBL 0x44
593 #define QLA82XX_PCI_MSIX_CONTROL 0x40
594
595 struct crb_128M_2M_sub_block_map {
596 unsigned valid;
597 unsigned start_128M;
598 unsigned end_128M;
599 unsigned start_2M;
600 };
601
602 struct crb_128M_2M_block_map {
603 struct crb_128M_2M_sub_block_map sub_block[16];
604 };
605
606 struct crb_addr_pair {
607 long addr;
608 long data;
609 };
610
611 #define ADDR_ERROR ((unsigned long) 0xffffffff)
612 #define MAX_CTL_CHECK 1000
613
614 /***************************************************************************
615 * PCI related defines.
616 **************************************************************************/
617
618 /*
619 * Interrupt related defines.
620 */
621 #define PCIX_TARGET_STATUS (0x10118)
622 #define PCIX_TARGET_STATUS_F1 (0x10160)
623 #define PCIX_TARGET_STATUS_F2 (0x10164)
624 #define PCIX_TARGET_STATUS_F3 (0x10168)
625 #define PCIX_TARGET_STATUS_F4 (0x10360)
626 #define PCIX_TARGET_STATUS_F5 (0x10364)
627 #define PCIX_TARGET_STATUS_F6 (0x10368)
628 #define PCIX_TARGET_STATUS_F7 (0x1036c)
629
630 #define PCIX_TARGET_MASK (0x10128)
631 #define PCIX_TARGET_MASK_F1 (0x10170)
632 #define PCIX_TARGET_MASK_F2 (0x10174)
633 #define PCIX_TARGET_MASK_F3 (0x10178)
634 #define PCIX_TARGET_MASK_F4 (0x10370)
635 #define PCIX_TARGET_MASK_F5 (0x10374)
636 #define PCIX_TARGET_MASK_F6 (0x10378)
637 #define PCIX_TARGET_MASK_F7 (0x1037c)
638
639 /*
640 * Message Signaled Interrupts
641 */
642 #define PCIX_MSI_F0 (0x13000)
643 #define PCIX_MSI_F1 (0x13004)
644 #define PCIX_MSI_F2 (0x13008)
645 #define PCIX_MSI_F3 (0x1300c)
646 #define PCIX_MSI_F4 (0x13010)
647 #define PCIX_MSI_F5 (0x13014)
648 #define PCIX_MSI_F6 (0x13018)
649 #define PCIX_MSI_F7 (0x1301c)
650 #define PCIX_MSI_F(FUNC) (0x13000 + ((FUNC) * 4))
651 #define PCIX_INT_VECTOR (0x10100)
652 #define PCIX_INT_MASK (0x10104)
653
654 /*
655 * Interrupt state machine and other bits.
656 */
657 #define PCIE_MISCCFG_RC (0x1206c)
658
659 #define ISR_INT_TARGET_STATUS \
660 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS))
661 #define ISR_INT_TARGET_STATUS_F1 \
662 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))
663 #define ISR_INT_TARGET_STATUS_F2 \
664 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))
665 #define ISR_INT_TARGET_STATUS_F3 \
666 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
667 #define ISR_INT_TARGET_STATUS_F4 \
668 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
669 #define ISR_INT_TARGET_STATUS_F5 \
670 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
671 #define ISR_INT_TARGET_STATUS_F6 \
672 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
673 #define ISR_INT_TARGET_STATUS_F7 \
674 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
675
676 #define ISR_INT_TARGET_MASK \
677 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK))
678 #define ISR_INT_TARGET_MASK_F1 \
679 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F1))
680 #define ISR_INT_TARGET_MASK_F2 \
681 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
682 #define ISR_INT_TARGET_MASK_F3 \
683 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
684 #define ISR_INT_TARGET_MASK_F4 \
685 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
686 #define ISR_INT_TARGET_MASK_F5 \
687 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
688 #define ISR_INT_TARGET_MASK_F6 \
689 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
690 #define ISR_INT_TARGET_MASK_F7 \
691 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
692
693 #define ISR_INT_VECTOR \
694 (QLA82XX_PCIX_PS_REG(PCIX_INT_VECTOR))
695 #define ISR_INT_MASK \
696 (QLA82XX_PCIX_PS_REG(PCIX_INT_MASK))
697 #define ISR_INT_STATE_REG \
698 (QLA82XX_PCIX_PS_REG(PCIE_MISCCFG_RC))
699
700 #define ISR_MSI_INT_TRIGGER(FUNC) \
701 (QLA82XX_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
702
703 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)
704 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
705
706 /*
707 * PCI Interrupt Vector Values.
708 */
709 #define PCIX_INT_VECTOR_BIT_F0 0x0080
710 #define PCIX_INT_VECTOR_BIT_F1 0x0100
711 #define PCIX_INT_VECTOR_BIT_F2 0x0200
712 #define PCIX_INT_VECTOR_BIT_F3 0x0400
713 #define PCIX_INT_VECTOR_BIT_F4 0x0800
714 #define PCIX_INT_VECTOR_BIT_F5 0x1000
715 #define PCIX_INT_VECTOR_BIT_F6 0x2000
716 #define PCIX_INT_VECTOR_BIT_F7 0x4000
717
718 struct qla82xx_legacy_intr_set {
719 uint32_t int_vec_bit;
720 uint32_t tgt_status_reg;
721 uint32_t tgt_mask_reg;
722 uint32_t pci_int_reg;
723 };
724
725 #define QLA82XX_LEGACY_INTR_CONFIG \
726 { \
727 { \
728 .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \
729 .tgt_status_reg = ISR_INT_TARGET_STATUS, \
730 .tgt_mask_reg = ISR_INT_TARGET_MASK, \
731 .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \
732 \
733 { \
734 .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \
735 .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \
736 .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \
737 .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \
738 \
739 { \
740 .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \
741 .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \
742 .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \
743 .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \
744 \
745 { \
746 .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \
747 .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \
748 .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \
749 .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \
750 \
751 { \
752 .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \
753 .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \
754 .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \
755 .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \
756 \
757 { \
758 .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \
759 .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \
760 .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \
761 .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \
762 \
763 { \
764 .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \
765 .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \
766 .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \
767 .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \
768 \
769 { \
770 .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \
771 .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \
772 .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \
773 .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \
774 }
775
776 #define BRDCFG_START 0x4000
777 #define BOOTLD_START 0x10000
778 #define IMAGE_START 0x100000
779 #define FLASH_ADDR_START 0x43000
780
781 /* Magic number to let user know flash is programmed */
782 #define QLA82XX_BDINFO_MAGIC 0x12345678
783 #define QLA82XX_FW_MAGIC_OFFSET (BRDCFG_START + 0x128)
784 #define FW_SIZE_OFFSET (0x3e840c)
785 #define QLA82XX_FW_MIN_SIZE 0x3fffff
786
787 /* UNIFIED ROMIMAGE START */
788 #define QLA82XX_URI_FW_MIN_SIZE 0xc8000
789 #define QLA82XX_URI_DIR_SECT_PRODUCT_TBL 0x0
790 #define QLA82XX_URI_DIR_SECT_BOOTLD 0x6
791 #define QLA82XX_URI_DIR_SECT_FW 0x7
792
793 /* Offsets */
794 #define QLA82XX_URI_CHIP_REV_OFF 10
795 #define QLA82XX_URI_FLAGS_OFF 11
796 #define QLA82XX_URI_BIOS_VERSION_OFF 12
797 #define QLA82XX_URI_BOOTLD_IDX_OFF 27
798 #define QLA82XX_URI_FIRMWARE_IDX_OFF 29
799
800 struct qla82xx_uri_table_desc{
801 uint32_t findex;
802 uint32_t num_entries;
803 uint32_t entry_size;
804 uint32_t reserved[5];
805 };
806
807 struct qla82xx_uri_data_desc{
808 uint32_t findex;
809 uint32_t size;
810 uint32_t reserved[5];
811 };
812
813 /* UNIFIED ROMIMAGE END */
814
815 #define QLA82XX_UNIFIED_ROMIMAGE 3
816 #define QLA82XX_FLASH_ROMIMAGE 4
817 #define QLA82XX_UNKNOWN_ROMIMAGE 0xff
818
819 #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0)
820 #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4)
821
822 #ifndef readq
823 static inline u64 readq(void __iomem *addr)
824 {
825 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
826 }
827 #endif
828
829 #ifndef writeq
830 static inline void writeq(u64 val, void __iomem *addr)
831 {
832 writel(((u32) (val)), (addr));
833 writel(((u32) (val >> 32)), (addr + 4));
834 }
835 #endif
836
837 /* Request and response queue size */
838 #define REQUEST_ENTRY_CNT_82XX 128 /* Number of request entries. */
839 #define RESPONSE_ENTRY_CNT_82XX 128 /* Number of response entries.*/
840
841 /*
842 * ISP 8021 I/O Register Set structure definitions.
843 */
844 struct device_reg_82xx {
845 uint32_t req_q_out[64]; /* Request Queue out-Pointer (64 * 4) */
846 uint32_t rsp_q_in[64]; /* Response Queue In-Pointer. */
847 uint32_t rsp_q_out[64]; /* Response Queue Out-Pointer. */
848
849 uint16_t mailbox_in[32]; /* Mail box In registers */
850 uint16_t unused_1[32];
851 uint32_t hint; /* Host interrupt register */
852 #define HINT_MBX_INT_PENDING BIT_0
853 uint16_t unused_2[62];
854 uint16_t mailbox_out[32]; /* Mail box Out registers */
855 uint32_t unused_3[48];
856
857 uint32_t host_status; /* host status */
858 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
859 #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
860 uint32_t host_int; /* Interrupt status. */
861 #define ISRX_NX_RISC_INT BIT_0 /* RISC interrupt. */
862 };
863
864 struct fcp_cmnd {
865 struct scsi_lun lun;
866 uint8_t crn;
867 uint8_t task_attribute;
868 uint8_t task_management;
869 uint8_t additional_cdb_len;
870 uint8_t cdb[260]; /* 256 for CDB len and 4 for FCP_DL */
871 };
872
873 struct dsd_dma {
874 struct list_head list;
875 dma_addr_t dsd_list_dma;
876 void *dsd_addr;
877 };
878
879 #define QLA_DSDS_PER_IOCB 37
880 #define QLA_DSD_SIZE 12
881 struct ct6_dsd {
882 uint16_t fcp_cmnd_len;
883 dma_addr_t fcp_cmnd_dma;
884 struct fcp_cmnd *fcp_cmnd;
885 int dsd_use_cnt;
886 struct list_head dsd_list;
887 };
888
889 #define MBC_TOGGLE_INTERRUPT 0x10
890
891 /* Flash offset */
892 #define FLT_REG_BOOTLOAD_82XX 0x72
893 #define FLT_REG_BOOT_CODE_82XX 0x78
894 #define FLT_REG_FW_82XX 0x74
895 #define FLT_REG_GOLD_FW_82XX 0x75
896 #define FLT_REG_VPD_82XX 0x81
897
898 #define FA_VPD_SIZE_82XX 0x400
899
900 #define FA_FLASH_LAYOUT_ADDR_82 0xFC400
901
902 /******************************************************************************
903 *
904 * Definitions specific to M25P flash
905 *
906 *******************************************************************************
907 * Instructions
908 */
909 #define M25P_INSTR_WREN 0x06
910 #define M25P_INSTR_WRDI 0x04
911 #define M25P_INSTR_RDID 0x9f
912 #define M25P_INSTR_RDSR 0x05
913 #define M25P_INSTR_WRSR 0x01
914 #define M25P_INSTR_READ 0x03
915 #define M25P_INSTR_FAST_READ 0x0b
916 #define M25P_INSTR_PP 0x02
917 #define M25P_INSTR_SE 0xd8
918 #define M25P_INSTR_BE 0xc7
919 #define M25P_INSTR_DP 0xb9
920 #define M25P_INSTR_RES 0xab
921
922 #endif
Tomato firmware and modifications.