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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / scsi / mvsas / mv_defs.h
blobaaa378622add49aa60c83d7169d56b8843bef1cb
1 /*
2 * Marvell 88SE64xx/88SE94xx const head file
3 *
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
6 *
7 * This file is licensed under GPLv2.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; version 2 of the
12 * License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA
23 */
24
25 #ifndef _MV_DEFS_H_
26 #define _MV_DEFS_H_
27
28 #define PCI_DEVICE_ID_ARECA_1300 0x1300
29 #define PCI_DEVICE_ID_ARECA_1320 0x1320
30
31 enum chip_flavors {
32 chip_6320,
33 chip_6440,
34 chip_6485,
35 chip_9480,
36 chip_9180,
37 chip_1300,
38 chip_1320
39 };
40
41 /* driver compile-time configuration */
42 enum driver_configuration {
43 MVS_SLOTS = 512, /* command slots */
44 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
45 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
46 /* software requires power-of-2
47 ring size */
48 MVS_SOC_SLOTS = 64,
49 MVS_SOC_TX_RING_SZ = MVS_SOC_SLOTS * 2,
50 MVS_SOC_RX_RING_SZ = MVS_SOC_SLOTS * 2,
51
52 MVS_SLOT_BUF_SZ = 8192, /* cmd tbl + IU + status + PRD */
53 MVS_SSP_CMD_SZ = 64, /* SSP command table buffer size */
54 MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */
55 MVS_OAF_SZ = 64, /* Open address frame buffer size */
56 MVS_QUEUE_SIZE = 32, /* Support Queue depth */
57 MVS_CAN_QUEUE = MVS_SLOTS - 2, /* SCSI Queue depth */
58 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
59 };
60
61 /* unchangeable hardware details */
62 enum hardware_details {
63 MVS_MAX_PHYS = 8, /* max. possible phys */
64 MVS_MAX_PORTS = 8, /* max. possible ports */
65 MVS_SOC_PHYS = 4, /* soc phys */
66 MVS_SOC_PORTS = 4, /* soc phys */
67 MVS_MAX_DEVICES = 1024, /* max supported device */
68 };
69
70 /* peripheral registers (BAR2) */
71 enum peripheral_registers {
72 SPI_CTL = 0x10, /* EEPROM control */
73 SPI_CMD = 0x14, /* EEPROM command */
74 SPI_DATA = 0x18, /* EEPROM data */
75 };
76
77 enum peripheral_register_bits {
78 TWSI_RDY = (1U << 7), /* EEPROM interface ready */
79 TWSI_RD = (1U << 4), /* EEPROM read access */
80
81 SPI_ADDR_MASK = 0x3ffff, /* bits 17:0 */
82 };
83
84 enum hw_register_bits {
85 /* MVS_GBL_CTL */
86 INT_EN = (1U << 1), /* Global int enable */
87 HBA_RST = (1U << 0), /* HBA reset */
88
89 /* MVS_GBL_INT_STAT */
90 INT_XOR = (1U << 4), /* XOR engine event */
91 INT_SAS_SATA = (1U << 0), /* SAS/SATA event */
92
93 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
94 SATA_TARGET = (1U << 16), /* port0 SATA target enable */
95 MODE_AUTO_DET_PORT7 = (1U << 15), /* port0 SAS/SATA autodetect */
96 MODE_AUTO_DET_PORT6 = (1U << 14),
97 MODE_AUTO_DET_PORT5 = (1U << 13),
98 MODE_AUTO_DET_PORT4 = (1U << 12),
99 MODE_AUTO_DET_PORT3 = (1U << 11),
100 MODE_AUTO_DET_PORT2 = (1U << 10),
101 MODE_AUTO_DET_PORT1 = (1U << 9),
102 MODE_AUTO_DET_PORT0 = (1U << 8),
103 MODE_AUTO_DET_EN = MODE_AUTO_DET_PORT0 | MODE_AUTO_DET_PORT1 |
104 MODE_AUTO_DET_PORT2 | MODE_AUTO_DET_PORT3 |
105 MODE_AUTO_DET_PORT4 | MODE_AUTO_DET_PORT5 |
106 MODE_AUTO_DET_PORT6 | MODE_AUTO_DET_PORT7,
107 MODE_SAS_PORT7_MASK = (1U << 7), /* port0 SAS(1), SATA(0) mode */
108 MODE_SAS_PORT6_MASK = (1U << 6),
109 MODE_SAS_PORT5_MASK = (1U << 5),
110 MODE_SAS_PORT4_MASK = (1U << 4),
111 MODE_SAS_PORT3_MASK = (1U << 3),
112 MODE_SAS_PORT2_MASK = (1U << 2),
113 MODE_SAS_PORT1_MASK = (1U << 1),
114 MODE_SAS_PORT0_MASK = (1U << 0),
115 MODE_SAS_SATA = MODE_SAS_PORT0_MASK | MODE_SAS_PORT1_MASK |
116 MODE_SAS_PORT2_MASK | MODE_SAS_PORT3_MASK |
117 MODE_SAS_PORT4_MASK | MODE_SAS_PORT5_MASK |
118 MODE_SAS_PORT6_MASK | MODE_SAS_PORT7_MASK,
119
120 /* SAS_MODE value may be
121 * dictated (in hw) by values
122 * of SATA_TARGET & AUTO_DET
123 */
124
125 /* MVS_TX_CFG */
126 TX_EN = (1U << 16), /* Enable TX */
127 TX_RING_SZ_MASK = 0xfff, /* TX ring size, bits 11:0 */
128
129 /* MVS_RX_CFG */
130 RX_EN = (1U << 16), /* Enable RX */
131 RX_RING_SZ_MASK = 0xfff, /* RX ring size, bits 11:0 */
132
133 /* MVS_INT_COAL */
134 COAL_EN = (1U << 16), /* Enable int coalescing */
135
136 /* MVS_INT_STAT, MVS_INT_MASK */
137 CINT_I2C = (1U << 31), /* I2C event */
138 CINT_SW0 = (1U << 30), /* software event 0 */
139 CINT_SW1 = (1U << 29), /* software event 1 */
140 CINT_PRD_BC = (1U << 28), /* PRD BC err for read cmd */
141 CINT_DMA_PCIE = (1U << 27), /* DMA to PCIE timeout */
142 CINT_MEM = (1U << 26), /* int mem parity err */
143 CINT_I2C_SLAVE = (1U << 25), /* slave I2C event */
144 CINT_SRS = (1U << 3), /* SRS event */
145 CINT_CI_STOP = (1U << 1), /* cmd issue stopped */
146 CINT_DONE = (1U << 0), /* cmd completion */
147
148 /* shl for ports 1-3 */
149 CINT_PORT_STOPPED = (1U << 16), /* port0 stopped */
150 CINT_PORT = (1U << 8), /* port0 event */
151 CINT_PORT_MASK_OFFSET = 8,
152 CINT_PORT_MASK = (0xFF << CINT_PORT_MASK_OFFSET),
153 CINT_PHY_MASK_OFFSET = 4,
154 CINT_PHY_MASK = (0x0F << CINT_PHY_MASK_OFFSET),
155
156 /* TX (delivery) ring bits */
157 TXQ_CMD_SHIFT = 29,
158 TXQ_CMD_SSP = 1, /* SSP protocol */
159 TXQ_CMD_SMP = 2, /* SMP protocol */
160 TXQ_CMD_STP = 3, /* STP/SATA protocol */
161 TXQ_CMD_SSP_FREE_LIST = 4, /* add to SSP targ free list */
162 TXQ_CMD_SLOT_RESET = 7, /* reset command slot */
163 TXQ_MODE_I = (1U << 28), /* mode: 0=target,1=initiator */
164 TXQ_MODE_TARGET = 0,
165 TXQ_MODE_INITIATOR = 1,
166 TXQ_PRIO_HI = (1U << 27), /* priority: 0=normal, 1=high */
167 TXQ_PRI_NORMAL = 0,
168 TXQ_PRI_HIGH = 1,
169 TXQ_SRS_SHIFT = 20, /* SATA register set */
170 TXQ_SRS_MASK = 0x7f,
171 TXQ_PHY_SHIFT = 12, /* PHY bitmap */
172 TXQ_PHY_MASK = 0xff,
173 TXQ_SLOT_MASK = 0xfff, /* slot number */
174
175 /* RX (completion) ring bits */
176 RXQ_GOOD = (1U << 23), /* Response good */
177 RXQ_SLOT_RESET = (1U << 21), /* Slot reset complete */
178 RXQ_CMD_RX = (1U << 20), /* target cmd received */
179 RXQ_ATTN = (1U << 19), /* attention */
180 RXQ_RSP = (1U << 18), /* response frame xfer'd */
181 RXQ_ERR = (1U << 17), /* err info rec xfer'd */
182 RXQ_DONE = (1U << 16), /* cmd complete */
183 RXQ_SLOT_MASK = 0xfff, /* slot number */
184
185 /* mvs_cmd_hdr bits */
186 MCH_PRD_LEN_SHIFT = 16, /* 16-bit PRD table len */
187 MCH_SSP_FR_TYPE_SHIFT = 13, /* SSP frame type */
188
189 /* SSP initiator only */
190 MCH_SSP_FR_CMD = 0x0, /* COMMAND frame */
191
192 /* SSP initiator or target */
193 MCH_SSP_FR_TASK = 0x1, /* TASK frame */
194
195 /* SSP target only */
196 MCH_SSP_FR_XFER_RDY = 0x4, /* XFER_RDY frame */
197 MCH_SSP_FR_RESP = 0x5, /* RESPONSE frame */
198 MCH_SSP_FR_READ = 0x6, /* Read DATA frame(s) */
199 MCH_SSP_FR_READ_RESP = 0x7, /* ditto, plus RESPONSE */
200
201 MCH_SSP_MODE_PASSTHRU = 1,
202 MCH_SSP_MODE_NORMAL = 0,
203 MCH_PASSTHRU = (1U << 12), /* pass-through (SSP) */
204 MCH_FBURST = (1U << 11), /* first burst (SSP) */
205 MCH_CHK_LEN = (1U << 10), /* chk xfer len (SSP) */
206 MCH_RETRY = (1U << 9), /* tport layer retry (SSP) */
207 MCH_PROTECTION = (1U << 8), /* protection info rec (SSP) */
208 MCH_RESET = (1U << 7), /* Reset (STP/SATA) */
209 MCH_FPDMA = (1U << 6), /* First party DMA (STP/SATA) */
210 MCH_ATAPI = (1U << 5), /* ATAPI (STP/SATA) */
211 MCH_BIST = (1U << 4), /* BIST activate (STP/SATA) */
212 MCH_PMP_MASK = 0xf, /* PMP from cmd FIS (STP/SATA)*/
213
214 CCTL_RST = (1U << 5), /* port logic reset */
215
216 /* 0(LSB first), 1(MSB first) */
217 CCTL_ENDIAN_DATA = (1U << 3), /* PRD data */
218 CCTL_ENDIAN_RSP = (1U << 2), /* response frame */
219 CCTL_ENDIAN_OPEN = (1U << 1), /* open address frame */
220 CCTL_ENDIAN_CMD = (1U << 0), /* command table */
221
222 /* MVS_Px_SER_CTLSTAT (per-phy control) */
223 PHY_SSP_RST = (1U << 3), /* reset SSP link layer */
224 PHY_BCAST_CHG = (1U << 2), /* broadcast(change) notif */
225 PHY_RST_HARD = (1U << 1), /* hard reset + phy reset */
226 PHY_RST = (1U << 0), /* phy reset */
227 PHY_READY_MASK = (1U << 20),
228
229 /* MVS_Px_INT_STAT, MVS_Px_INT_MASK (per-phy events) */
230 PHYEV_DEC_ERR = (1U << 24), /* Phy Decoding Error */
231 PHYEV_DCDR_ERR = (1U << 23), /* STP Deocder Error */
232 PHYEV_CRC_ERR = (1U << 22), /* STP CRC Error */
233 PHYEV_UNASSOC_FIS = (1U << 19), /* unassociated FIS rx'd */
234 PHYEV_AN = (1U << 18), /* SATA async notification */
235 PHYEV_BIST_ACT = (1U << 17), /* BIST activate FIS */
236 PHYEV_SIG_FIS = (1U << 16), /* signature FIS */
237 PHYEV_POOF = (1U << 12), /* phy ready from 1 -> 0 */
238 PHYEV_IU_BIG = (1U << 11), /* IU too long err */
239 PHYEV_IU_SMALL = (1U << 10), /* IU too short err */
240 PHYEV_UNK_TAG = (1U << 9), /* unknown tag */
241 PHYEV_BROAD_CH = (1U << 8), /* broadcast(CHANGE) */
242 PHYEV_COMWAKE = (1U << 7), /* COMWAKE rx'd */
243 PHYEV_PORT_SEL = (1U << 6), /* port selector present */
244 PHYEV_HARD_RST = (1U << 5), /* hard reset rx'd */
245 PHYEV_ID_TMOUT = (1U << 4), /* identify timeout */
246 PHYEV_ID_FAIL = (1U << 3), /* identify failed */
247 PHYEV_ID_DONE = (1U << 2), /* identify done */
248 PHYEV_HARD_RST_DONE = (1U << 1), /* hard reset done */
249 PHYEV_RDY_CH = (1U << 0), /* phy ready changed state */
250
251 /* MVS_PCS */
252 PCS_EN_SATA_REG_SHIFT = (16), /* Enable SATA Register Set */
253 PCS_EN_PORT_XMT_SHIFT = (12), /* Enable Port Transmit */
254 PCS_EN_PORT_XMT_SHIFT2 = (8), /* For 6485 */
255 PCS_SATA_RETRY = (1U << 8), /* retry ctl FIS on R_ERR */
256 PCS_RSP_RX_EN = (1U << 7), /* raw response rx */
257 PCS_SATA_RETRY_2 = (1U << 6), /* For 9180 */
258 PCS_SELF_CLEAR = (1U << 5), /* self-clearing int mode */
259 PCS_FIS_RX_EN = (1U << 4), /* FIS rx enable */
260 PCS_CMD_STOP_ERR = (1U << 3), /* cmd stop-on-err enable */
261 PCS_CMD_RST = (1U << 1), /* reset cmd issue */
262 PCS_CMD_EN = (1U << 0), /* enable cmd issue */
263
264 /* Port n Attached Device Info */
265 PORT_DEV_SSP_TRGT = (1U << 19),
266 PORT_DEV_SMP_TRGT = (1U << 18),
267 PORT_DEV_STP_TRGT = (1U << 17),
268 PORT_DEV_SSP_INIT = (1U << 11),
269 PORT_DEV_SMP_INIT = (1U << 10),
270 PORT_DEV_STP_INIT = (1U << 9),
271 PORT_PHY_ID_MASK = (0xFFU << 24),
272 PORT_SSP_TRGT_MASK = (0x1U << 19),
273 PORT_SSP_INIT_MASK = (0x1U << 11),
274 PORT_DEV_TRGT_MASK = (0x7U << 17),
275 PORT_DEV_INIT_MASK = (0x7U << 9),
276 PORT_DEV_TYPE_MASK = (0x7U << 0),
277
278 /* Port n PHY Status */
279 PHY_RDY = (1U << 2),
280 PHY_DW_SYNC = (1U << 1),
281 PHY_OOB_DTCTD = (1U << 0),
282
283 /* VSR */
284 /* PHYMODE 6 (CDB) */
285 PHY_MODE6_LATECLK = (1U << 29), /* Lock Clock */
286 PHY_MODE6_DTL_SPEED = (1U << 27), /* Digital Loop Speed */
287 PHY_MODE6_FC_ORDER = (1U << 26), /* Fibre Channel Mode Order*/
288 PHY_MODE6_MUCNT_EN = (1U << 24), /* u Count Enable */
289 PHY_MODE6_SEL_MUCNT_LEN = (1U << 22), /* Training Length Select */
290 PHY_MODE6_SELMUPI = (1U << 20), /* Phase Multi Select (init) */
291 PHY_MODE6_SELMUPF = (1U << 18), /* Phase Multi Select (final) */
292 PHY_MODE6_SELMUFF = (1U << 16), /* Freq Loop Multi Sel(final) */
293 PHY_MODE6_SELMUFI = (1U << 14), /* Freq Loop Multi Sel(init) */
294 PHY_MODE6_FREEZE_LOOP = (1U << 12), /* Freeze Rx CDR Loop */
295 PHY_MODE6_INT_RXFOFFS = (1U << 3), /* Rx CDR Freq Loop Enable */
296 PHY_MODE6_FRC_RXFOFFS = (1U << 2), /* Initial Rx CDR Offset */
297 PHY_MODE6_STAU_0D8 = (1U << 1), /* Rx CDR Freq Loop Saturate */
298 PHY_MODE6_RXSAT_DIS = (1U << 0), /* Saturate Ctl */
299 };
300
301 /* SAS/SATA configuration port registers, aka phy registers */
302 enum sas_sata_config_port_regs {
303 PHYR_IDENTIFY = 0x00, /* info for IDENTIFY frame */
304 PHYR_ADDR_LO = 0x04, /* my SAS address (low) */
305 PHYR_ADDR_HI = 0x08, /* my SAS address (high) */
306 PHYR_ATT_DEV_INFO = 0x0C, /* attached device info */
307 PHYR_ATT_ADDR_LO = 0x10, /* attached dev SAS addr (low) */
308 PHYR_ATT_ADDR_HI = 0x14, /* attached dev SAS addr (high) */
309 PHYR_SATA_CTL = 0x18, /* SATA control */
310 PHYR_PHY_STAT = 0x1C, /* PHY status */
311 PHYR_SATA_SIG0 = 0x20, /*port SATA signature FIS(Byte 0-3) */
312 PHYR_SATA_SIG1 = 0x24, /*port SATA signature FIS(Byte 4-7) */
313 PHYR_SATA_SIG2 = 0x28, /*port SATA signature FIS(Byte 8-11) */
314 PHYR_SATA_SIG3 = 0x2c, /*port SATA signature FIS(Byte 12-15) */
315 PHYR_R_ERR_COUNT = 0x30, /* port R_ERR count register */
316 PHYR_CRC_ERR_COUNT = 0x34, /* port CRC error count register */
317 PHYR_WIDE_PORT = 0x38, /* wide port participating */
318 PHYR_CURRENT0 = 0x80, /* current connection info 0 */
319 PHYR_CURRENT1 = 0x84, /* current connection info 1 */
320 PHYR_CURRENT2 = 0x88, /* current connection info 2 */
321 CONFIG_ID_FRAME0 = 0x100, /* Port device ID frame register 0 */
322 CONFIG_ID_FRAME1 = 0x104, /* Port device ID frame register 1 */
323 CONFIG_ID_FRAME2 = 0x108, /* Port device ID frame register 2 */
324 CONFIG_ID_FRAME3 = 0x10c, /* Port device ID frame register 3 */
325 CONFIG_ID_FRAME4 = 0x110, /* Port device ID frame register 4 */
326 CONFIG_ID_FRAME5 = 0x114, /* Port device ID frame register 5 */
327 CONFIG_ID_FRAME6 = 0x118, /* Port device ID frame register 6 */
328 CONFIG_ATT_ID_FRAME0 = 0x11c, /* attached ID frame register 0 */
329 CONFIG_ATT_ID_FRAME1 = 0x120, /* attached ID frame register 1 */
330 CONFIG_ATT_ID_FRAME2 = 0x124, /* attached ID frame register 2 */
331 CONFIG_ATT_ID_FRAME3 = 0x128, /* attached ID frame register 3 */
332 CONFIG_ATT_ID_FRAME4 = 0x12c, /* attached ID frame register 4 */
333 CONFIG_ATT_ID_FRAME5 = 0x130, /* attached ID frame register 5 */
334 CONFIG_ATT_ID_FRAME6 = 0x134, /* attached ID frame register 6 */
335 };
336
337 enum sas_cmd_port_registers {
338 CMD_CMRST_OOB_DET = 0x100, /* COMRESET OOB detect register */
339 CMD_CMWK_OOB_DET = 0x104, /* COMWAKE OOB detect register */
340 CMD_CMSAS_OOB_DET = 0x108, /* COMSAS OOB detect register */
341 CMD_BRST_OOB_DET = 0x10c, /* burst OOB detect register */
342 CMD_OOB_SPACE = 0x110, /* OOB space control register */
343 CMD_OOB_BURST = 0x114, /* OOB burst control register */
344 CMD_PHY_TIMER = 0x118, /* PHY timer control register */
345 CMD_PHY_CONFIG0 = 0x11c, /* PHY config register 0 */
346 CMD_PHY_CONFIG1 = 0x120, /* PHY config register 1 */
347 CMD_SAS_CTL0 = 0x124, /* SAS control register 0 */
348 CMD_SAS_CTL1 = 0x128, /* SAS control register 1 */
349 CMD_SAS_CTL2 = 0x12c, /* SAS control register 2 */
350 CMD_SAS_CTL3 = 0x130, /* SAS control register 3 */
351 CMD_ID_TEST = 0x134, /* ID test register */
352 CMD_PL_TIMER = 0x138, /* PL timer register */
353 CMD_WD_TIMER = 0x13c, /* WD timer register */
354 CMD_PORT_SEL_COUNT = 0x140, /* port selector count register */
355 CMD_APP_MEM_CTL = 0x144, /* Application Memory Control */
356 CMD_XOR_MEM_CTL = 0x148, /* XOR Block Memory Control */
357 CMD_DMA_MEM_CTL = 0x14c, /* DMA Block Memory Control */
358 CMD_PORT_MEM_CTL0 = 0x150, /* Port Memory Control 0 */
359 CMD_PORT_MEM_CTL1 = 0x154, /* Port Memory Control 1 */
360 CMD_SATA_PORT_MEM_CTL0 = 0x158, /* SATA Port Memory Control 0 */
361 CMD_SATA_PORT_MEM_CTL1 = 0x15c, /* SATA Port Memory Control 1 */
362 CMD_XOR_MEM_BIST_CTL = 0x160, /* XOR Memory BIST Control */
363 CMD_XOR_MEM_BIST_STAT = 0x164, /* XOR Memroy BIST Status */
364 CMD_DMA_MEM_BIST_CTL = 0x168, /* DMA Memory BIST Control */
365 CMD_DMA_MEM_BIST_STAT = 0x16c, /* DMA Memory BIST Status */
366 CMD_PORT_MEM_BIST_CTL = 0x170, /* Port Memory BIST Control */
367 CMD_PORT_MEM_BIST_STAT0 = 0x174, /* Port Memory BIST Status 0 */
368 CMD_PORT_MEM_BIST_STAT1 = 0x178, /* Port Memory BIST Status 1 */
369 CMD_STP_MEM_BIST_CTL = 0x17c, /* STP Memory BIST Control */
370 CMD_STP_MEM_BIST_STAT0 = 0x180, /* STP Memory BIST Status 0 */
371 CMD_STP_MEM_BIST_STAT1 = 0x184, /* STP Memory BIST Status 1 */
372 CMD_RESET_COUNT = 0x188, /* Reset Count */
373 CMD_MONTR_DATA_SEL = 0x18C, /* Monitor Data/Select */
374 CMD_PLL_PHY_CONFIG = 0x190, /* PLL/PHY Configuration */
375 CMD_PHY_CTL = 0x194, /* PHY Control and Status */
376 CMD_PHY_TEST_COUNT0 = 0x198, /* Phy Test Count 0 */
377 CMD_PHY_TEST_COUNT1 = 0x19C, /* Phy Test Count 1 */
378 CMD_PHY_TEST_COUNT2 = 0x1A0, /* Phy Test Count 2 */
379 CMD_APP_ERR_CONFIG = 0x1A4, /* Application Error Configuration */
380 CMD_PND_FIFO_CTL0 = 0x1A8, /* Pending FIFO Control 0 */
381 CMD_HOST_CTL = 0x1AC, /* Host Control Status */
382 CMD_HOST_WR_DATA = 0x1B0, /* Host Write Data */
383 CMD_HOST_RD_DATA = 0x1B4, /* Host Read Data */
384 CMD_PHY_MODE_21 = 0x1B8, /* Phy Mode 21 */
385 CMD_SL_MODE0 = 0x1BC, /* SL Mode 0 */
386 CMD_SL_MODE1 = 0x1C0, /* SL Mode 1 */
387 CMD_PND_FIFO_CTL1 = 0x1C4, /* Pending FIFO Control 1 */
388 };
389
390 enum mvs_info_flags {
391 MVF_MSI = (1U << 0), /* MSI is enabled */
392 MVF_PHY_PWR_FIX = (1U << 1),
393 MVF_FLAG_SOC = (1U << 2), /* SoC integrated controllers */
394 };
395
396 enum mvs_event_flags {
397 PHY_PLUG_EVENT = (3U),
398 PHY_PLUG_IN = (1U << 0), /* phy plug in */
399 PHY_PLUG_OUT = (1U << 1), /* phy plug out */
400 };
401
402 enum mvs_port_type {
403 PORT_TGT_MASK = (1U << 5),
404 PORT_INIT_PORT = (1U << 4),
405 PORT_TGT_PORT = (1U << 3),
406 PORT_INIT_TGT_PORT = (PORT_INIT_PORT | PORT_TGT_PORT),
407 PORT_TYPE_SAS = (1U << 1),
408 PORT_TYPE_SATA = (1U << 0),
409 };
410
411 /* Command Table Format */
412 enum ct_format {
413 /* SSP */
414 SSP_F_H = 0x00,
415 SSP_F_IU = 0x18,
416 SSP_F_MAX = 0x4D,
417 /* STP */
418 STP_CMD_FIS = 0x00,
419 STP_ATAPI_CMD = 0x40,
420 STP_F_MAX = 0x10,
421 /* SMP */
422 SMP_F_T = 0x00,
423 SMP_F_DEP = 0x01,
424 SMP_F_MAX = 0x101,
425 };
426
427 enum status_buffer {
428 SB_EIR_OFF = 0x00, /* Error Information Record */
429 SB_RFB_OFF = 0x08, /* Response Frame Buffer */
430 SB_RFB_MAX = 0x400, /* RFB size*/
431 };
432
433 enum error_info_rec {
434 CMD_ISS_STPD = (1U << 31), /* Cmd Issue Stopped */
435 CMD_PI_ERR = (1U << 30), /* Protection info error. see flags2 */
436 RSP_OVER = (1U << 29), /* rsp buffer overflow */
437 RETRY_LIM = (1U << 28), /* FIS/frame retry limit exceeded */
438 UNK_FIS = (1U << 27), /* unknown FIS */
439 DMA_TERM = (1U << 26), /* DMA terminate primitive rx'd */
440 SYNC_ERR = (1U << 25), /* SYNC rx'd during frame xmit */
441 TFILE_ERR = (1U << 24), /* SATA taskfile Error bit set */
442 R_ERR = (1U << 23), /* SATA returned R_ERR prim */
443 RD_OFS = (1U << 20), /* Read DATA frame invalid offset */
444 XFER_RDY_OFS = (1U << 19), /* XFER_RDY offset error */
445 UNEXP_XFER_RDY = (1U << 18), /* unexpected XFER_RDY error */
446 DATA_OVER_UNDER = (1U << 16), /* data overflow/underflow */
447 INTERLOCK = (1U << 15), /* interlock error */
448 NAK = (1U << 14), /* NAK rx'd */
449 ACK_NAK_TO = (1U << 13), /* ACK/NAK timeout */
450 CXN_CLOSED = (1U << 12), /* cxn closed w/out ack/nak */
451 OPEN_TO = (1U << 11), /* I_T nexus lost, open cxn timeout */
452 PATH_BLOCKED = (1U << 10), /* I_T nexus lost, pathway blocked */
453 NO_DEST = (1U << 9), /* I_T nexus lost, no destination */
454 STP_RES_BSY = (1U << 8), /* STP resources busy */
455 BREAK = (1U << 7), /* break received */
456 BAD_DEST = (1U << 6), /* bad destination */
457 BAD_PROTO = (1U << 5), /* protocol not supported */
458 BAD_RATE = (1U << 4), /* cxn rate not supported */
459 WRONG_DEST = (1U << 3), /* wrong destination error */
460 CREDIT_TO = (1U << 2), /* credit timeout */
461 WDOG_TO = (1U << 1), /* watchdog timeout */
462 BUF_PAR = (1U << 0), /* buffer parity error */
463 };
464
465 enum error_info_rec_2 {
466 SLOT_BSY_ERR = (1U << 31), /* Slot Busy Error */
467 GRD_CHK_ERR = (1U << 14), /* Guard Check Error */
468 APP_CHK_ERR = (1U << 13), /* Application Check error */
469 REF_CHK_ERR = (1U << 12), /* Reference Check Error */
470 USR_BLK_NM = (1U << 0), /* User Block Number */
471 };
472
473 enum pci_cfg_register_bits {
474 PCTL_PWR_OFF = (0xFU << 24),
475 PCTL_COM_ON = (0xFU << 20),
476 PCTL_LINK_RST = (0xFU << 16),
477 PCTL_LINK_OFFS = (16),
478 PCTL_PHY_DSBL = (0xFU << 12),
479 PCTL_PHY_DSBL_OFFS = (12),
480 PRD_REQ_SIZE = (0x4000),
481 PRD_REQ_MASK = (0x00007000),
482 PLS_NEG_LINK_WD = (0x3FU << 4),
483 PLS_NEG_LINK_WD_OFFS = 4,
484 PLS_LINK_SPD = (0x0FU << 0),
485 PLS_LINK_SPD_OFFS = 0,
486 };
487
488 enum open_frame_protocol {
489 PROTOCOL_SMP = 0x0,
490 PROTOCOL_SSP = 0x1,
491 PROTOCOL_STP = 0x2,
492 };
493
494 /* define for response frame datapres field */
495 enum datapres_field {
496 NO_DATA = 0,
497 RESPONSE_DATA = 1,
498 SENSE_DATA = 2,
499 };
500
501 /* define task management IU */
502 struct mvs_tmf_task{
503 u8 tmf;
504 u16 tag_of_task_to_be_managed;
505 };
506 #endif
Tomato firmware and modifications.