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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / scsi / gdth.c
blob4cf7ffa2dad37b24e3a186c5bdbddf553363988f
1 /************************************************************************
2 * Linux driver for *
3 * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
4 * Intel Corporation: Storage RAID Controllers *
5 * *
6 * gdth.c *
7 * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
8 * Copyright (C) 2002-04 Intel Corporation *
9 * Copyright (C) 2003-06 Adaptec Inc. *
10 * <achim_leubner@adaptec.com> *
11 * *
12 * Additions/Fixes: *
13 * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
14 * Johannes Dinner <johannes_dinner@adaptec.com> *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published *
18 * by the Free Software Foundation; either version 2 of the License, *
19 * or (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this kernel; if not, write to the Free Software *
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
29 * *
30 * Linux kernel 2.6.x supported *
31 * *
32 ************************************************************************/
33
34 /* All GDT Disk Array Controllers are fully supported by this driver.
35 * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
36 * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
37 * list of all controller types.
38 *
39 * If you have one or more GDT3000/3020 EISA controllers with
40 * controller BIOS disabled, you have to set the IRQ values with the
41 * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
42 * the IRQ values for the EISA controllers.
43 *
44 * After the optional list of IRQ values, other possible
45 * command line options are:
46 * disable:Y disable driver
47 * disable:N enable driver
48 * reserve_mode:0 reserve no drives for the raw service
49 * reserve_mode:1 reserve all not init., removable drives
50 * reserve_mode:2 reserve all not init. drives
51 * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
52 * h- controller no., b- channel no.,
53 * t- target ID, l- LUN
54 * reverse_scan:Y reverse scan order for PCI controllers
55 * reverse_scan:N scan PCI controllers like BIOS
56 * max_ids:x x - target ID count per channel (1..MAXID)
57 * rescan:Y rescan all channels/IDs
58 * rescan:N use all devices found until now
59 * hdr_channel:x x - number of virtual bus for host drives
60 * shared_access:Y disable driver reserve/release protocol to
61 * access a shared resource from several nodes,
62 * appropriate controller firmware required
63 * shared_access:N enable driver reserve/release protocol
64 * probe_eisa_isa:Y scan for EISA/ISA controllers
65 * probe_eisa_isa:N do not scan for EISA/ISA controllers
66 * force_dma32:Y use only 32 bit DMA mode
67 * force_dma32:N use 64 bit DMA mode, if supported
68 *
69 * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
70 * max_ids:127,rescan:N,hdr_channel:0,
71 * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
72 * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
73 *
74 * When loading the gdth driver as a module, the same options are available.
75 * You can set the IRQs with "IRQ=...". However, the syntax to specify the
76 * options changes slightly. You must replace all ',' between options
77 * with ' ' and all ':' with '=' and you must use
78 * '1' in place of 'Y' and '0' in place of 'N'.
79 *
80 * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
81 * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
82 * probe_eisa_isa=0 force_dma32=0"
83 * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
84 */
85
86 /* The meaning of the Scsi_Pointer members in this driver is as follows:
87 * ptr: Chaining
88 * this_residual: unused
89 * buffer: unused
90 * dma_handle: unused
91 * buffers_residual: unused
92 * Status: unused
93 * Message: unused
94 * have_data_in: unused
95 * sent_command: unused
96 * phase: unused
97 */
98
99
100 /* interrupt coalescing */
101 /* #define INT_COAL */
102
103 /* statistics */
104 #define GDTH_STATISTICS
105
106 #include <linux/module.h>
107
108 #include <linux/version.h>
109 #include <linux/kernel.h>
110 #include <linux/types.h>
111 #include <linux/pci.h>
112 #include <linux/string.h>
113 #include <linux/ctype.h>
114 #include <linux/ioport.h>
115 #include <linux/delay.h>
116 #include <linux/interrupt.h>
117 #include <linux/in.h>
118 #include <linux/proc_fs.h>
119 #include <linux/time.h>
120 #include <linux/timer.h>
121 #include <linux/dma-mapping.h>
122 #include <linux/list.h>
123 #include <linux/smp_lock.h>
124 #include <linux/slab.h>
125
126 #ifdef GDTH_RTC
127 #include <linux/mc146818rtc.h>
128 #endif
129 #include <linux/reboot.h>
130
131 #include <asm/dma.h>
132 #include <asm/system.h>
133 #include <asm/io.h>
134 #include <asm/uaccess.h>
135 #include <linux/spinlock.h>
136 #include <linux/blkdev.h>
137 #include <linux/scatterlist.h>
138
139 #include "scsi.h"
140 #include <scsi/scsi_host.h>
141 #include "gdth.h"
142
143 static void gdth_delay(int milliseconds);
144 static void gdth_eval_mapping(u32 size, u32 *cyls, int *heads, int *secs);
145 static irqreturn_t gdth_interrupt(int irq, void *dev_id);
146 static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
147 int gdth_from_wait, int* pIndex);
148 static int gdth_sync_event(gdth_ha_str *ha, int service, u8 index,
149 Scsi_Cmnd *scp);
150 static int gdth_async_event(gdth_ha_str *ha);
151 static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
152
153 static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 priority);
154 static void gdth_next(gdth_ha_str *ha);
155 static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 b);
156 static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
157 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, u16 source,
158 u16 idx, gdth_evt_data *evt);
159 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
160 static void gdth_readapp_event(gdth_ha_str *ha, u8 application,
161 gdth_evt_str *estr);
162 static void gdth_clear_events(void);
163
164 static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
165 char *buffer, u16 count);
166 static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
167 static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u16 hdrive);
168
169 static void gdth_enable_int(gdth_ha_str *ha);
170 static int gdth_test_busy(gdth_ha_str *ha);
171 static int gdth_get_cmd_index(gdth_ha_str *ha);
172 static void gdth_release_event(gdth_ha_str *ha);
173 static int gdth_wait(gdth_ha_str *ha, int index,u32 time);
174 static int gdth_internal_cmd(gdth_ha_str *ha, u8 service, u16 opcode,
175 u32 p1, u64 p2,u64 p3);
176 static int gdth_search_drives(gdth_ha_str *ha);
177 static int gdth_analyse_hdrive(gdth_ha_str *ha, u16 hdrive);
178
179 static const char *gdth_ctr_name(gdth_ha_str *ha);
180
181 static int gdth_open(struct inode *inode, struct file *filep);
182 static int gdth_close(struct inode *inode, struct file *filep);
183 static long gdth_unlocked_ioctl(struct file *filep, unsigned int cmd,
184 unsigned long arg);
185
186 static void gdth_flush(gdth_ha_str *ha);
187 static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
188 static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
189 struct gdth_cmndinfo *cmndinfo);
190 static void gdth_scsi_done(struct scsi_cmnd *scp);
191
192 #ifdef DEBUG_GDTH
193 static u8 DebugState = DEBUG_GDTH;
194
195 #ifdef __SERIAL__
196 #define MAX_SERBUF 160
197 static void ser_init(void);
198 static void ser_puts(char *str);
199 static void ser_putc(char c);
200 static int ser_printk(const char *fmt, ...);
201 static char strbuf[MAX_SERBUF+1];
202 #ifdef __COM2__
203 #define COM_BASE 0x2f8
204 #else
205 #define COM_BASE 0x3f8
206 #endif
207 static void ser_init()
208 {
209 unsigned port=COM_BASE;
210
211 outb(0x80,port+3);
212 outb(0,port+1);
213 /* 19200 Baud, if 9600: outb(12,port) */
214 outb(6, port);
215 outb(3,port+3);
216 outb(0,port+1);
217 /*
218 ser_putc('I');
219 ser_putc(' ');
220 */
221 }
222
223 static void ser_puts(char *str)
224 {
225 char *ptr;
226
227 ser_init();
228 for (ptr=str;*ptr;++ptr)
229 ser_putc(*ptr);
230 }
231
232 static void ser_putc(char c)
233 {
234 unsigned port=COM_BASE;
235
236 while ((inb(port+5) & 0x20)==0);
237 outb(c,port);
238 if (c==0x0a)
239 {
240 while ((inb(port+5) & 0x20)==0);
241 outb(0x0d,port);
242 }
243 }
244
245 static int ser_printk(const char *fmt, ...)
246 {
247 va_list args;
248 int i;
249
250 va_start(args,fmt);
251 i = vsprintf(strbuf,fmt,args);
252 ser_puts(strbuf);
253 va_end(args);
254 return i;
255 }
256
257 #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
258 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
259 #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
260
261 #else /* !__SERIAL__ */
262 #define TRACE(a) {if (DebugState==1) {printk a;}}
263 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
264 #define TRACE3(a) {if (DebugState!=0) {printk a;}}
265 #endif
266
267 #else /* !DEBUG */
268 #define TRACE(a)
269 #define TRACE2(a)
270 #define TRACE3(a)
271 #endif
272
273 #ifdef GDTH_STATISTICS
274 static u32 max_rq=0, max_index=0, max_sg=0;
275 #ifdef INT_COAL
276 static u32 max_int_coal=0;
277 #endif
278 static u32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
279 static struct timer_list gdth_timer;
280 #endif
281
282 #define PTR2USHORT(a) (u16)(unsigned long)(a)
283 #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
284 #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
285
286 #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
287
288 #ifdef CONFIG_ISA
289 static u8 gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
290 #endif
291 #if defined(CONFIG_EISA) || defined(CONFIG_ISA)
292 static u8 gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
293 #endif
294 static u8 gdth_polling; /* polling if TRUE */
295 static int gdth_ctr_count = 0; /* controller count */
296 static LIST_HEAD(gdth_instances); /* controller list */
297 static u8 gdth_write_through = FALSE; /* write through */
298 static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
299 static int elastidx;
300 static int eoldidx;
301 static int major;
302
303 #define DIN 1 /* IN data direction */
304 #define DOU 2 /* OUT data direction */
305 #define DNO DIN /* no data transfer */
306 #define DUN DIN /* unknown data direction */
307 static u8 gdth_direction_tab[0x100] = {
308 DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
309 DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
310 DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
311 DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
312 DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
313 DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
314 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
315 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
316 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
317 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
318 DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
319 DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
320 DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
321 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
322 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
323 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
324 };
325
326 /* LILO and modprobe/insmod parameters */
327 /* IRQ list for GDT3000/3020 EISA controllers */
328 static int irq[MAXHA] __initdata =
329 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
330 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
331 /* disable driver flag */
332 static int disable __initdata = 0;
333 /* reserve flag */
334 static int reserve_mode = 1;
335 /* reserve list */
336 static int reserve_list[MAX_RES_ARGS] =
337 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
338 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
339 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
340 /* scan order for PCI controllers */
341 static int reverse_scan = 0;
342 /* virtual channel for the host drives */
343 static int hdr_channel = 0;
344 /* max. IDs per channel */
345 static int max_ids = MAXID;
346 /* rescan all IDs */
347 static int rescan = 0;
348 /* shared access */
349 static int shared_access = 1;
350 /* enable support for EISA and ISA controllers */
351 static int probe_eisa_isa = 0;
352 /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
353 static int force_dma32 = 0;
354
355 /* parameters for modprobe/insmod */
356 module_param_array(irq, int, NULL, 0);
357 module_param(disable, int, 0);
358 module_param(reserve_mode, int, 0);
359 module_param_array(reserve_list, int, NULL, 0);
360 module_param(reverse_scan, int, 0);
361 module_param(hdr_channel, int, 0);
362 module_param(max_ids, int, 0);
363 module_param(rescan, int, 0);
364 module_param(shared_access, int, 0);
365 module_param(probe_eisa_isa, int, 0);
366 module_param(force_dma32, int, 0);
367 MODULE_AUTHOR("Achim Leubner");
368 MODULE_LICENSE("GPL");
369
370 /* ioctl interface */
371 static const struct file_operations gdth_fops = {
372 .unlocked_ioctl = gdth_unlocked_ioctl,
373 .open = gdth_open,
374 .release = gdth_close,
375 };
376
377 #include "gdth_proc.h"
378 #include "gdth_proc.c"
379
380 static gdth_ha_str *gdth_find_ha(int hanum)
381 {
382 gdth_ha_str *ha;
383
384 list_for_each_entry(ha, &gdth_instances, list)
385 if (hanum == ha->hanum)
386 return ha;
387
388 return NULL;
389 }
390
391 static struct gdth_cmndinfo *gdth_get_cmndinfo(gdth_ha_str *ha)
392 {
393 struct gdth_cmndinfo *priv = NULL;
394 unsigned long flags;
395 int i;
396
397 spin_lock_irqsave(&ha->smp_lock, flags);
398
399 for (i=0; i<GDTH_MAXCMDS; ++i) {
400 if (ha->cmndinfo[i].index == 0) {
401 priv = &ha->cmndinfo[i];
402 memset(priv, 0, sizeof(*priv));
403 priv->index = i+1;
404 break;
405 }
406 }
407
408 spin_unlock_irqrestore(&ha->smp_lock, flags);
409
410 return priv;
411 }
412
413 static void gdth_put_cmndinfo(struct gdth_cmndinfo *priv)
414 {
415 BUG_ON(!priv);
416 priv->index = 0;
417 }
418
419 static void gdth_delay(int milliseconds)
420 {
421 if (milliseconds == 0) {
422 udelay(1);
423 } else {
424 mdelay(milliseconds);
425 }
426 }
427
428 static void gdth_scsi_done(struct scsi_cmnd *scp)
429 {
430 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
431 int internal_command = cmndinfo->internal_command;
432
433 TRACE2(("gdth_scsi_done()\n"));
434
435 gdth_put_cmndinfo(cmndinfo);
436 scp->host_scribble = NULL;
437
438 if (internal_command)
439 complete((struct completion *)scp->request);
440 else
441 scp->scsi_done(scp);
442 }
443
444 int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
445 int timeout, u32 *info)
446 {
447 gdth_ha_str *ha = shost_priv(sdev->host);
448 Scsi_Cmnd *scp;
449 struct gdth_cmndinfo cmndinfo;
450 DECLARE_COMPLETION_ONSTACK(wait);
451 int rval;
452
453 scp = kzalloc(sizeof(*scp), GFP_KERNEL);
454 if (!scp)
455 return -ENOMEM;
456
457 scp->sense_buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
458 if (!scp->sense_buffer) {
459 kfree(scp);
460 return -ENOMEM;
461 }
462
463 scp->device = sdev;
464 memset(&cmndinfo, 0, sizeof(cmndinfo));
465
466 /* use request field to save the ptr. to completion struct. */
467 scp->request = (struct request *)&wait;
468 scp->cmd_len = 12;
469 scp->cmnd = cmnd;
470 cmndinfo.priority = IOCTL_PRI;
471 cmndinfo.internal_cmd_str = gdtcmd;
472 cmndinfo.internal_command = 1;
473
474 TRACE(("__gdth_execute() cmd 0x%x\n", scp->cmnd[0]));
475 __gdth_queuecommand(ha, scp, &cmndinfo);
476
477 wait_for_completion(&wait);
478
479 rval = cmndinfo.status;
480 if (info)
481 *info = cmndinfo.info;
482 kfree(scp->sense_buffer);
483 kfree(scp);
484 return rval;
485 }
486
487 int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
488 int timeout, u32 *info)
489 {
490 struct scsi_device *sdev = scsi_get_host_dev(shost);
491 int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
492
493 scsi_free_host_dev(sdev);
494 return rval;
495 }
496
497 static void gdth_eval_mapping(u32 size, u32 *cyls, int *heads, int *secs)
498 {
499 *cyls = size /HEADS/SECS;
500 if (*cyls <= MAXCYLS) {
501 *heads = HEADS;
502 *secs = SECS;
503 } else { /* too high for 64*32 */
504 *cyls = size /MEDHEADS/MEDSECS;
505 if (*cyls <= MAXCYLS) {
506 *heads = MEDHEADS;
507 *secs = MEDSECS;
508 } else { /* too high for 127*63 */
509 *cyls = size /BIGHEADS/BIGSECS;
510 *heads = BIGHEADS;
511 *secs = BIGSECS;
512 }
513 }
514 }
515
516 /* controller search and initialization functions */
517 #ifdef CONFIG_EISA
518 static int __init gdth_search_eisa(u16 eisa_adr)
519 {
520 u32 id;
521
522 TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
523 id = inl(eisa_adr+ID0REG);
524 if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
525 if ((inb(eisa_adr+EISAREG) & 8) == 0)
526 return 0; /* not EISA configured */
527 return 1;
528 }
529 if (id == GDT3_ID) /* GDT3000 */
530 return 1;
531
532 return 0;
533 }
534 #endif /* CONFIG_EISA */
535
536 #ifdef CONFIG_ISA
537 static int __init gdth_search_isa(u32 bios_adr)
538 {
539 void __iomem *addr;
540 u32 id;
541
542 TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
543 if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(u32))) != NULL) {
544 id = readl(addr);
545 iounmap(addr);
546 if (id == GDT2_ID) /* GDT2000 */
547 return 1;
548 }
549 return 0;
550 }
551 #endif /* CONFIG_ISA */
552
553 #ifdef CONFIG_PCI
554
555 static bool gdth_search_vortex(u16 device)
556 {
557 if (device <= PCI_DEVICE_ID_VORTEX_GDT6555)
558 return true;
559 if (device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP &&
560 device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP)
561 return true;
562 if (device == PCI_DEVICE_ID_VORTEX_GDTNEWRX ||
563 device == PCI_DEVICE_ID_VORTEX_GDTNEWRX2)
564 return true;
565 return false;
566 }
567
568 static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out);
569 static int gdth_pci_init_one(struct pci_dev *pdev,
570 const struct pci_device_id *ent);
571 static void gdth_pci_remove_one(struct pci_dev *pdev);
572 static void gdth_remove_one(gdth_ha_str *ha);
573
574 /* Vortex only makes RAID controllers.
575 * We do not really want to specify all 550 ids here, so wildcard match.
576 */
577 static const struct pci_device_id gdthtable[] = {
578 { PCI_VDEVICE(VORTEX, PCI_ANY_ID) },
579 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC) },
580 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC_XSCALE) },
581 { } /* terminate list */
582 };
583 MODULE_DEVICE_TABLE(pci, gdthtable);
584
585 static struct pci_driver gdth_pci_driver = {
586 .name = "gdth",
587 .id_table = gdthtable,
588 .probe = gdth_pci_init_one,
589 .remove = gdth_pci_remove_one,
590 };
591
592 static void __devexit gdth_pci_remove_one(struct pci_dev *pdev)
593 {
594 gdth_ha_str *ha = pci_get_drvdata(pdev);
595
596 pci_set_drvdata(pdev, NULL);
597
598 list_del(&ha->list);
599 gdth_remove_one(ha);
600
601 pci_disable_device(pdev);
602 }
603
604 static int __devinit gdth_pci_init_one(struct pci_dev *pdev,
605 const struct pci_device_id *ent)
606 {
607 u16 vendor = pdev->vendor;
608 u16 device = pdev->device;
609 unsigned long base0, base1, base2;
610 int rc;
611 gdth_pci_str gdth_pcistr;
612 gdth_ha_str *ha = NULL;
613
614 TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
615 gdth_ctr_count, vendor, device));
616
617 memset(&gdth_pcistr, 0, sizeof(gdth_pcistr));
618
619 if (vendor == PCI_VENDOR_ID_VORTEX && !gdth_search_vortex(device))
620 return -ENODEV;
621
622 rc = pci_enable_device(pdev);
623 if (rc)
624 return rc;
625
626 if (gdth_ctr_count >= MAXHA)
627 return -EBUSY;
628
629 /* GDT PCI controller found, resources are already in pdev */
630 gdth_pcistr.pdev = pdev;
631 base0 = pci_resource_flags(pdev, 0);
632 base1 = pci_resource_flags(pdev, 1);
633 base2 = pci_resource_flags(pdev, 2);
634 if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
635 device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
636 if (!(base0 & IORESOURCE_MEM))
637 return -ENODEV;
638 gdth_pcistr.dpmem = pci_resource_start(pdev, 0);
639 } else { /* GDT6110, GDT6120, .. */
640 if (!(base0 & IORESOURCE_MEM) ||
641 !(base2 & IORESOURCE_MEM) ||
642 !(base1 & IORESOURCE_IO))
643 return -ENODEV;
644 gdth_pcistr.dpmem = pci_resource_start(pdev, 2);
645 gdth_pcistr.io = pci_resource_start(pdev, 1);
646 }
647 TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
648 gdth_pcistr.pdev->bus->number,
649 PCI_SLOT(gdth_pcistr.pdev->devfn),
650 gdth_pcistr.irq,
651 gdth_pcistr.dpmem));
652
653 rc = gdth_pci_probe_one(&gdth_pcistr, &ha);
654 if (rc)
655 return rc;
656
657 return 0;
658 }
659 #endif /* CONFIG_PCI */
660
661 #ifdef CONFIG_EISA
662 static int __init gdth_init_eisa(u16 eisa_adr,gdth_ha_str *ha)
663 {
664 u32 retries,id;
665 u8 prot_ver,eisacf,i,irq_found;
666
667 TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
668
669 /* disable board interrupts, deinitialize services */
670 outb(0xff,eisa_adr+EDOORREG);
671 outb(0x00,eisa_adr+EDENABREG);
672 outb(0x00,eisa_adr+EINTENABREG);
673
674 outb(0xff,eisa_adr+LDOORREG);
675 retries = INIT_RETRIES;
676 gdth_delay(20);
677 while (inb(eisa_adr+EDOORREG) != 0xff) {
678 if (--retries == 0) {
679 printk("GDT-EISA: Initialization error (DEINIT failed)\n");
680 return 0;
681 }
682 gdth_delay(1);
683 TRACE2(("wait for DEINIT: retries=%d\n",retries));
684 }
685 prot_ver = inb(eisa_adr+MAILBOXREG);
686 outb(0xff,eisa_adr+EDOORREG);
687 if (prot_ver != PROTOCOL_VERSION) {
688 printk("GDT-EISA: Illegal protocol version\n");
689 return 0;
690 }
691 ha->bmic = eisa_adr;
692 ha->brd_phys = (u32)eisa_adr >> 12;
693
694 outl(0,eisa_adr+MAILBOXREG);
695 outl(0,eisa_adr+MAILBOXREG+4);
696 outl(0,eisa_adr+MAILBOXREG+8);
697 outl(0,eisa_adr+MAILBOXREG+12);
698
699 /* detect IRQ */
700 if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
701 ha->oem_id = OEM_ID_ICP;
702 ha->type = GDT_EISA;
703 ha->stype = id;
704 outl(1,eisa_adr+MAILBOXREG+8);
705 outb(0xfe,eisa_adr+LDOORREG);
706 retries = INIT_RETRIES;
707 gdth_delay(20);
708 while (inb(eisa_adr+EDOORREG) != 0xfe) {
709 if (--retries == 0) {
710 printk("GDT-EISA: Initialization error (get IRQ failed)\n");
711 return 0;
712 }
713 gdth_delay(1);
714 }
715 ha->irq = inb(eisa_adr+MAILBOXREG);
716 outb(0xff,eisa_adr+EDOORREG);
717 TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
718 /* check the result */
719 if (ha->irq == 0) {
720 TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
721 for (i = 0, irq_found = FALSE;
722 i < MAXHA && irq[i] != 0xff; ++i) {
723 if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
724 irq_found = TRUE;
725 break;
726 }
727 }
728 if (irq_found) {
729 ha->irq = irq[i];
730 irq[i] = 0;
731 printk("GDT-EISA: Can not detect controller IRQ,\n");
732 printk("Use IRQ setting from command line (IRQ = %d)\n",
733 ha->irq);
734 } else {
735 printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
736 printk("the controller BIOS or use command line parameters\n");
737 return 0;
738 }
739 }
740 } else {
741 eisacf = inb(eisa_adr+EISAREG) & 7;
742 if (eisacf > 4) /* level triggered */
743 eisacf -= 4;
744 ha->irq = gdth_irq_tab[eisacf];
745 ha->oem_id = OEM_ID_ICP;
746 ha->type = GDT_EISA;
747 ha->stype = id;
748 }
749
750 ha->dma64_support = 0;
751 return 1;
752 }
753 #endif /* CONFIG_EISA */
754
755 #ifdef CONFIG_ISA
756 static int __init gdth_init_isa(u32 bios_adr,gdth_ha_str *ha)
757 {
758 register gdt2_dpram_str __iomem *dp2_ptr;
759 int i;
760 u8 irq_drq,prot_ver;
761 u32 retries;
762
763 TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
764
765 ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
766 if (ha->brd == NULL) {
767 printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
768 return 0;
769 }
770 dp2_ptr = ha->brd;
771 writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
772 /* reset interface area */
773 memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
774 if (readl(&dp2_ptr->u) != 0) {
775 printk("GDT-ISA: Initialization error (DPMEM write error)\n");
776 iounmap(ha->brd);
777 return 0;
778 }
779
780 /* disable board interrupts, read DRQ and IRQ */
781 writeb(0xff, &dp2_ptr->io.irqdel);
782 writeb(0x00, &dp2_ptr->io.irqen);
783 writeb(0x00, &dp2_ptr->u.ic.S_Status);
784 writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
785
786 irq_drq = readb(&dp2_ptr->io.rq);
787 for (i=0; i<3; ++i) {
788 if ((irq_drq & 1)==0)
789 break;
790 irq_drq >>= 1;
791 }
792 ha->drq = gdth_drq_tab[i];
793
794 irq_drq = readb(&dp2_ptr->io.rq) >> 3;
795 for (i=1; i<5; ++i) {
796 if ((irq_drq & 1)==0)
797 break;
798 irq_drq >>= 1;
799 }
800 ha->irq = gdth_irq_tab[i];
801
802 /* deinitialize services */
803 writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
804 writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
805 writeb(0, &dp2_ptr->io.event);
806 retries = INIT_RETRIES;
807 gdth_delay(20);
808 while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
809 if (--retries == 0) {
810 printk("GDT-ISA: Initialization error (DEINIT failed)\n");
811 iounmap(ha->brd);
812 return 0;
813 }
814 gdth_delay(1);
815 }
816 prot_ver = (u8)readl(&dp2_ptr->u.ic.S_Info[0]);
817 writeb(0, &dp2_ptr->u.ic.Status);
818 writeb(0xff, &dp2_ptr->io.irqdel);
819 if (prot_ver != PROTOCOL_VERSION) {
820 printk("GDT-ISA: Illegal protocol version\n");
821 iounmap(ha->brd);
822 return 0;
823 }
824
825 ha->oem_id = OEM_ID_ICP;
826 ha->type = GDT_ISA;
827 ha->ic_all_size = sizeof(dp2_ptr->u);
828 ha->stype= GDT2_ID;
829 ha->brd_phys = bios_adr >> 4;
830
831 /* special request to controller BIOS */
832 writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
833 writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
834 writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
835 writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
836 writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
837 writeb(0, &dp2_ptr->io.event);
838 retries = INIT_RETRIES;
839 gdth_delay(20);
840 while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
841 if (--retries == 0) {
842 printk("GDT-ISA: Initialization error\n");
843 iounmap(ha->brd);
844 return 0;
845 }
846 gdth_delay(1);
847 }
848 writeb(0, &dp2_ptr->u.ic.Status);
849 writeb(0xff, &dp2_ptr->io.irqdel);
850
851 ha->dma64_support = 0;
852 return 1;
853 }
854 #endif /* CONFIG_ISA */
855
856 #ifdef CONFIG_PCI
857 static int __devinit gdth_init_pci(struct pci_dev *pdev, gdth_pci_str *pcistr,
858 gdth_ha_str *ha)
859 {
860 register gdt6_dpram_str __iomem *dp6_ptr;
861 register gdt6c_dpram_str __iomem *dp6c_ptr;
862 register gdt6m_dpram_str __iomem *dp6m_ptr;
863 u32 retries;
864 u8 prot_ver;
865 u16 command;
866 int i, found = FALSE;
867
868 TRACE(("gdth_init_pci()\n"));
869
870 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
871 ha->oem_id = OEM_ID_INTEL;
872 else
873 ha->oem_id = OEM_ID_ICP;
874 ha->brd_phys = (pdev->bus->number << 8) | (pdev->devfn & 0xf8);
875 ha->stype = (u32)pdev->device;
876 ha->irq = pdev->irq;
877 ha->pdev = pdev;
878
879 if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
880 TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
881 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
882 if (ha->brd == NULL) {
883 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
884 return 0;
885 }
886 /* check and reset interface area */
887 dp6_ptr = ha->brd;
888 writel(DPMEM_MAGIC, &dp6_ptr->u);
889 if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
890 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
891 pcistr->dpmem);
892 found = FALSE;
893 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
894 iounmap(ha->brd);
895 ha->brd = ioremap(i, sizeof(u16));
896 if (ha->brd == NULL) {
897 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
898 return 0;
899 }
900 if (readw(ha->brd) != 0xffff) {
901 TRACE2(("init_pci_old() address 0x%x busy\n", i));
902 continue;
903 }
904 iounmap(ha->brd);
905 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
906 ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
907 if (ha->brd == NULL) {
908 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
909 return 0;
910 }
911 dp6_ptr = ha->brd;
912 writel(DPMEM_MAGIC, &dp6_ptr->u);
913 if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
914 printk("GDT-PCI: Use free address at 0x%x\n", i);
915 found = TRUE;
916 break;
917 }
918 }
919 if (!found) {
920 printk("GDT-PCI: No free address found!\n");
921 iounmap(ha->brd);
922 return 0;
923 }
924 }
925 memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
926 if (readl(&dp6_ptr->u) != 0) {
927 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
928 iounmap(ha->brd);
929 return 0;
930 }
931
932 /* disable board interrupts, deinit services */
933 writeb(0xff, &dp6_ptr->io.irqdel);
934 writeb(0x00, &dp6_ptr->io.irqen);
935 writeb(0x00, &dp6_ptr->u.ic.S_Status);
936 writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
937
938 writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
939 writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
940 writeb(0, &dp6_ptr->io.event);
941 retries = INIT_RETRIES;
942 gdth_delay(20);
943 while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
944 if (--retries == 0) {
945 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
946 iounmap(ha->brd);
947 return 0;
948 }
949 gdth_delay(1);
950 }
951 prot_ver = (u8)readl(&dp6_ptr->u.ic.S_Info[0]);
952 writeb(0, &dp6_ptr->u.ic.S_Status);
953 writeb(0xff, &dp6_ptr->io.irqdel);
954 if (prot_ver != PROTOCOL_VERSION) {
955 printk("GDT-PCI: Illegal protocol version\n");
956 iounmap(ha->brd);
957 return 0;
958 }
959
960 ha->type = GDT_PCI;
961 ha->ic_all_size = sizeof(dp6_ptr->u);
962
963 /* special command to controller BIOS */
964 writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
965 writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
966 writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
967 writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
968 writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
969 writeb(0, &dp6_ptr->io.event);
970 retries = INIT_RETRIES;
971 gdth_delay(20);
972 while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
973 if (--retries == 0) {
974 printk("GDT-PCI: Initialization error\n");
975 iounmap(ha->brd);
976 return 0;
977 }
978 gdth_delay(1);
979 }
980 writeb(0, &dp6_ptr->u.ic.S_Status);
981 writeb(0xff, &dp6_ptr->io.irqdel);
982
983 ha->dma64_support = 0;
984
985 } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
986 ha->plx = (gdt6c_plx_regs *)pcistr->io;
987 TRACE2(("init_pci_new() dpmem %lx irq %d\n",
988 pcistr->dpmem,ha->irq));
989 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
990 if (ha->brd == NULL) {
991 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
992 iounmap(ha->brd);
993 return 0;
994 }
995 /* check and reset interface area */
996 dp6c_ptr = ha->brd;
997 writel(DPMEM_MAGIC, &dp6c_ptr->u);
998 if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
999 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1000 pcistr->dpmem);
1001 found = FALSE;
1002 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1003 iounmap(ha->brd);
1004 ha->brd = ioremap(i, sizeof(u16));
1005 if (ha->brd == NULL) {
1006 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1007 return 0;
1008 }
1009 if (readw(ha->brd) != 0xffff) {
1010 TRACE2(("init_pci_plx() address 0x%x busy\n", i));
1011 continue;
1012 }
1013 iounmap(ha->brd);
1014 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_2, i);
1015 ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
1016 if (ha->brd == NULL) {
1017 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1018 return 0;
1019 }
1020 dp6c_ptr = ha->brd;
1021 writel(DPMEM_MAGIC, &dp6c_ptr->u);
1022 if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
1023 printk("GDT-PCI: Use free address at 0x%x\n", i);
1024 found = TRUE;
1025 break;
1026 }
1027 }
1028 if (!found) {
1029 printk("GDT-PCI: No free address found!\n");
1030 iounmap(ha->brd);
1031 return 0;
1032 }
1033 }
1034 memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
1035 if (readl(&dp6c_ptr->u) != 0) {
1036 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1037 iounmap(ha->brd);
1038 return 0;
1039 }
1040
1041 /* disable board interrupts, deinit services */
1042 outb(0x00,PTR2USHORT(&ha->plx->control1));
1043 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
1044
1045 writeb(0x00, &dp6c_ptr->u.ic.S_Status);
1046 writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
1047
1048 writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
1049 writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
1050
1051 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1052
1053 retries = INIT_RETRIES;
1054 gdth_delay(20);
1055 while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
1056 if (--retries == 0) {
1057 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1058 iounmap(ha->brd);
1059 return 0;
1060 }
1061 gdth_delay(1);
1062 }
1063 prot_ver = (u8)readl(&dp6c_ptr->u.ic.S_Info[0]);
1064 writeb(0, &dp6c_ptr->u.ic.Status);
1065 if (prot_ver != PROTOCOL_VERSION) {
1066 printk("GDT-PCI: Illegal protocol version\n");
1067 iounmap(ha->brd);
1068 return 0;
1069 }
1070
1071 ha->type = GDT_PCINEW;
1072 ha->ic_all_size = sizeof(dp6c_ptr->u);
1073
1074 /* special command to controller BIOS */
1075 writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
1076 writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
1077 writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
1078 writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
1079 writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
1080
1081 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1082
1083 retries = INIT_RETRIES;
1084 gdth_delay(20);
1085 while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
1086 if (--retries == 0) {
1087 printk("GDT-PCI: Initialization error\n");
1088 iounmap(ha->brd);
1089 return 0;
1090 }
1091 gdth_delay(1);
1092 }
1093 writeb(0, &dp6c_ptr->u.ic.S_Status);
1094
1095 ha->dma64_support = 0;
1096
1097 } else { /* MPR */
1098 TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1099 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
1100 if (ha->brd == NULL) {
1101 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1102 return 0;
1103 }
1104
1105 /* manipulate config. space to enable DPMEM, start RP controller */
1106 pci_read_config_word(pdev, PCI_COMMAND, &command);
1107 command |= 6;
1108 pci_write_config_word(pdev, PCI_COMMAND, command);
1109 if (pci_resource_start(pdev, 8) == 1UL)
1110 pci_resource_start(pdev, 8) = 0UL;
1111 i = 0xFEFF0001UL;
1112 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, i);
1113 gdth_delay(1);
1114 pci_write_config_dword(pdev, PCI_ROM_ADDRESS,
1115 pci_resource_start(pdev, 8));
1116
1117 dp6m_ptr = ha->brd;
1118
1119 /* Ensure that it is safe to access the non HW portions of DPMEM.
1120 * Aditional check needed for Xscale based RAID controllers */
1121 while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
1122 gdth_delay(1);
1123
1124 /* check and reset interface area */
1125 writel(DPMEM_MAGIC, &dp6m_ptr->u);
1126 if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
1127 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1128 pcistr->dpmem);
1129 found = FALSE;
1130 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1131 iounmap(ha->brd);
1132 ha->brd = ioremap(i, sizeof(u16));
1133 if (ha->brd == NULL) {
1134 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1135 return 0;
1136 }
1137 if (readw(ha->brd) != 0xffff) {
1138 TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
1139 continue;
1140 }
1141 iounmap(ha->brd);
1142 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
1143 ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
1144 if (ha->brd == NULL) {
1145 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1146 return 0;
1147 }
1148 dp6m_ptr = ha->brd;
1149 writel(DPMEM_MAGIC, &dp6m_ptr->u);
1150 if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
1151 printk("GDT-PCI: Use free address at 0x%x\n", i);
1152 found = TRUE;
1153 break;
1154 }
1155 }
1156 if (!found) {
1157 printk("GDT-PCI: No free address found!\n");
1158 iounmap(ha->brd);
1159 return 0;
1160 }
1161 }
1162 memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
1163
1164 /* disable board interrupts, deinit services */
1165 writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
1166 &dp6m_ptr->i960r.edoor_en_reg);
1167 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1168 writeb(0x00, &dp6m_ptr->u.ic.S_Status);
1169 writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
1170
1171 writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
1172 writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
1173 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1174 retries = INIT_RETRIES;
1175 gdth_delay(20);
1176 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
1177 if (--retries == 0) {
1178 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1179 iounmap(ha->brd);
1180 return 0;
1181 }
1182 gdth_delay(1);
1183 }
1184 prot_ver = (u8)readl(&dp6m_ptr->u.ic.S_Info[0]);
1185 writeb(0, &dp6m_ptr->u.ic.S_Status);
1186 if (prot_ver != PROTOCOL_VERSION) {
1187 printk("GDT-PCI: Illegal protocol version\n");
1188 iounmap(ha->brd);
1189 return 0;
1190 }
1191
1192 ha->type = GDT_PCIMPR;
1193 ha->ic_all_size = sizeof(dp6m_ptr->u);
1194
1195 /* special command to controller BIOS */
1196 writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
1197 writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
1198 writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
1199 writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
1200 writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
1201 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1202 retries = INIT_RETRIES;
1203 gdth_delay(20);
1204 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
1205 if (--retries == 0) {
1206 printk("GDT-PCI: Initialization error\n");
1207 iounmap(ha->brd);
1208 return 0;
1209 }
1210 gdth_delay(1);
1211 }
1212 writeb(0, &dp6m_ptr->u.ic.S_Status);
1213
1214 /* read FW version to detect 64-bit DMA support */
1215 writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
1216 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1217 retries = INIT_RETRIES;
1218 gdth_delay(20);
1219 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
1220 if (--retries == 0) {
1221 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1222 iounmap(ha->brd);
1223 return 0;
1224 }
1225 gdth_delay(1);
1226 }
1227 prot_ver = (u8)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
1228 writeb(0, &dp6m_ptr->u.ic.S_Status);
1229 if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
1230 ha->dma64_support = 0;
1231 else
1232 ha->dma64_support = 1;
1233 }
1234
1235 return 1;
1236 }
1237 #endif /* CONFIG_PCI */
1238
1239 /* controller protocol functions */
1240
1241 static void __devinit gdth_enable_int(gdth_ha_str *ha)
1242 {
1243 unsigned long flags;
1244 gdt2_dpram_str __iomem *dp2_ptr;
1245 gdt6_dpram_str __iomem *dp6_ptr;
1246 gdt6m_dpram_str __iomem *dp6m_ptr;
1247
1248 TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
1249 spin_lock_irqsave(&ha->smp_lock, flags);
1250
1251 if (ha->type == GDT_EISA) {
1252 outb(0xff, ha->bmic + EDOORREG);
1253 outb(0xff, ha->bmic + EDENABREG);
1254 outb(0x01, ha->bmic + EINTENABREG);
1255 } else if (ha->type == GDT_ISA) {
1256 dp2_ptr = ha->brd;
1257 writeb(1, &dp2_ptr->io.irqdel);
1258 writeb(0, &dp2_ptr->u.ic.Cmd_Index);
1259 writeb(1, &dp2_ptr->io.irqen);
1260 } else if (ha->type == GDT_PCI) {
1261 dp6_ptr = ha->brd;
1262 writeb(1, &dp6_ptr->io.irqdel);
1263 writeb(0, &dp6_ptr->u.ic.Cmd_Index);
1264 writeb(1, &dp6_ptr->io.irqen);
1265 } else if (ha->type == GDT_PCINEW) {
1266 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
1267 outb(0x03, PTR2USHORT(&ha->plx->control1));
1268 } else if (ha->type == GDT_PCIMPR) {
1269 dp6m_ptr = ha->brd;
1270 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1271 writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
1272 &dp6m_ptr->i960r.edoor_en_reg);
1273 }
1274 spin_unlock_irqrestore(&ha->smp_lock, flags);
1275 }
1276
1277 /* return IStatus if interrupt was from this card else 0 */
1278 static u8 gdth_get_status(gdth_ha_str *ha)
1279 {
1280 u8 IStatus = 0;
1281
1282 TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count));
1283
1284 if (ha->type == GDT_EISA)
1285 IStatus = inb((u16)ha->bmic + EDOORREG);
1286 else if (ha->type == GDT_ISA)
1287 IStatus =
1288 readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1289 else if (ha->type == GDT_PCI)
1290 IStatus =
1291 readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1292 else if (ha->type == GDT_PCINEW)
1293 IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
1294 else if (ha->type == GDT_PCIMPR)
1295 IStatus =
1296 readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
1297
1298 return IStatus;
1299 }
1300
1301 static int gdth_test_busy(gdth_ha_str *ha)
1302 {
1303 register int gdtsema0 = 0;
1304
1305 TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
1306
1307 if (ha->type == GDT_EISA)
1308 gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
1309 else if (ha->type == GDT_ISA)
1310 gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1311 else if (ha->type == GDT_PCI)
1312 gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1313 else if (ha->type == GDT_PCINEW)
1314 gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
1315 else if (ha->type == GDT_PCIMPR)
1316 gdtsema0 =
1317 (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1318
1319 return (gdtsema0 & 1);
1320 }
1321
1322
1323 static int gdth_get_cmd_index(gdth_ha_str *ha)
1324 {
1325 int i;
1326
1327 TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
1328
1329 for (i=0; i<GDTH_MAXCMDS; ++i) {
1330 if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
1331 ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
1332 ha->cmd_tab[i].service = ha->pccb->Service;
1333 ha->pccb->CommandIndex = (u32)i+2;
1334 return (i+2);
1335 }
1336 }
1337 return 0;
1338 }
1339
1340
1341 static void gdth_set_sema0(gdth_ha_str *ha)
1342 {
1343 TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
1344
1345 if (ha->type == GDT_EISA) {
1346 outb(1, ha->bmic + SEMA0REG);
1347 } else if (ha->type == GDT_ISA) {
1348 writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1349 } else if (ha->type == GDT_PCI) {
1350 writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1351 } else if (ha->type == GDT_PCINEW) {
1352 outb(1, PTR2USHORT(&ha->plx->sema0_reg));
1353 } else if (ha->type == GDT_PCIMPR) {
1354 writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1355 }
1356 }
1357
1358
1359 static void gdth_copy_command(gdth_ha_str *ha)
1360 {
1361 register gdth_cmd_str *cmd_ptr;
1362 register gdt6m_dpram_str __iomem *dp6m_ptr;
1363 register gdt6c_dpram_str __iomem *dp6c_ptr;
1364 gdt6_dpram_str __iomem *dp6_ptr;
1365 gdt2_dpram_str __iomem *dp2_ptr;
1366 u16 cp_count,dp_offset,cmd_no;
1367
1368 TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
1369
1370 cp_count = ha->cmd_len;
1371 dp_offset= ha->cmd_offs_dpmem;
1372 cmd_no = ha->cmd_cnt;
1373 cmd_ptr = ha->pccb;
1374
1375 ++ha->cmd_cnt;
1376 if (ha->type == GDT_EISA)
1377 return; /* no DPMEM, no copy */
1378
1379 /* set cpcount dword aligned */
1380 if (cp_count & 3)
1381 cp_count += (4 - (cp_count & 3));
1382
1383 ha->cmd_offs_dpmem += cp_count;
1384
1385 /* set offset and service, copy command to DPMEM */
1386 if (ha->type == GDT_ISA) {
1387 dp2_ptr = ha->brd;
1388 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1389 &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
1390 writew((u16)cmd_ptr->Service,
1391 &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
1392 memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1393 } else if (ha->type == GDT_PCI) {
1394 dp6_ptr = ha->brd;
1395 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1396 &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
1397 writew((u16)cmd_ptr->Service,
1398 &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
1399 memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1400 } else if (ha->type == GDT_PCINEW) {
1401 dp6c_ptr = ha->brd;
1402 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1403 &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
1404 writew((u16)cmd_ptr->Service,
1405 &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
1406 memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1407 } else if (ha->type == GDT_PCIMPR) {
1408 dp6m_ptr = ha->brd;
1409 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1410 &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
1411 writew((u16)cmd_ptr->Service,
1412 &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
1413 memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1414 }
1415 }
1416
1417
1418 static void gdth_release_event(gdth_ha_str *ha)
1419 {
1420 TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
1421
1422 #ifdef GDTH_STATISTICS
1423 {
1424 u32 i,j;
1425 for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
1426 if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
1427 ++i;
1428 }
1429 if (max_index < i) {
1430 max_index = i;
1431 TRACE3(("GDT: max_index = %d\n",(u16)i));
1432 }
1433 }
1434 #endif
1435
1436 if (ha->pccb->OpCode == GDT_INIT)
1437 ha->pccb->Service |= 0x80;
1438
1439 if (ha->type == GDT_EISA) {
1440 if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
1441 outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
1442 outb(ha->pccb->Service, ha->bmic + LDOORREG);
1443 } else if (ha->type == GDT_ISA) {
1444 writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
1445 } else if (ha->type == GDT_PCI) {
1446 writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
1447 } else if (ha->type == GDT_PCINEW) {
1448 outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
1449 } else if (ha->type == GDT_PCIMPR) {
1450 writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
1451 }
1452 }
1453
1454 static int gdth_wait(gdth_ha_str *ha, int index, u32 time)
1455 {
1456 int answer_found = FALSE;
1457 int wait_index = 0;
1458
1459 TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
1460
1461 if (index == 0)
1462 return 1; /* no wait required */
1463
1464 do {
1465 __gdth_interrupt(ha, true, &wait_index);
1466 if (wait_index == index) {
1467 answer_found = TRUE;
1468 break;
1469 }
1470 gdth_delay(1);
1471 } while (--time);
1472
1473 while (gdth_test_busy(ha))
1474 gdth_delay(0);
1475
1476 return (answer_found);
1477 }
1478
1479
1480 static int gdth_internal_cmd(gdth_ha_str *ha, u8 service, u16 opcode,
1481 u32 p1, u64 p2, u64 p3)
1482 {
1483 register gdth_cmd_str *cmd_ptr;
1484 int retries,index;
1485
1486 TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
1487
1488 cmd_ptr = ha->pccb;
1489 memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
1490
1491 /* make command */
1492 for (retries = INIT_RETRIES;;) {
1493 cmd_ptr->Service = service;
1494 cmd_ptr->RequestBuffer = INTERNAL_CMND;
1495 if (!(index=gdth_get_cmd_index(ha))) {
1496 TRACE(("GDT: No free command index found\n"));
1497 return 0;
1498 }
1499 gdth_set_sema0(ha);
1500 cmd_ptr->OpCode = opcode;
1501 cmd_ptr->BoardNode = LOCALBOARD;
1502 if (service == CACHESERVICE) {
1503 if (opcode == GDT_IOCTL) {
1504 cmd_ptr->u.ioctl.subfunc = p1;
1505 cmd_ptr->u.ioctl.channel = (u32)p2;
1506 cmd_ptr->u.ioctl.param_size = (u16)p3;
1507 cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
1508 } else {
1509 if (ha->cache_feat & GDT_64BIT) {
1510 cmd_ptr->u.cache64.DeviceNo = (u16)p1;
1511 cmd_ptr->u.cache64.BlockNo = p2;
1512 } else {
1513 cmd_ptr->u.cache.DeviceNo = (u16)p1;
1514 cmd_ptr->u.cache.BlockNo = (u32)p2;
1515 }
1516 }
1517 } else if (service == SCSIRAWSERVICE) {
1518 if (ha->raw_feat & GDT_64BIT) {
1519 cmd_ptr->u.raw64.direction = p1;
1520 cmd_ptr->u.raw64.bus = (u8)p2;
1521 cmd_ptr->u.raw64.target = (u8)p3;
1522 cmd_ptr->u.raw64.lun = (u8)(p3 >> 8);
1523 } else {
1524 cmd_ptr->u.raw.direction = p1;
1525 cmd_ptr->u.raw.bus = (u8)p2;
1526 cmd_ptr->u.raw.target = (u8)p3;
1527 cmd_ptr->u.raw.lun = (u8)(p3 >> 8);
1528 }
1529 } else if (service == SCREENSERVICE) {
1530 if (opcode == GDT_REALTIME) {
1531 *(u32 *)&cmd_ptr->u.screen.su.data[0] = p1;
1532 *(u32 *)&cmd_ptr->u.screen.su.data[4] = (u32)p2;
1533 *(u32 *)&cmd_ptr->u.screen.su.data[8] = (u32)p3;
1534 }
1535 }
1536 ha->cmd_len = sizeof(gdth_cmd_str);
1537 ha->cmd_offs_dpmem = 0;
1538 ha->cmd_cnt = 0;
1539 gdth_copy_command(ha);
1540 gdth_release_event(ha);
1541 gdth_delay(20);
1542 if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
1543 printk("GDT: Initialization error (timeout service %d)\n",service);
1544 return 0;
1545 }
1546 if (ha->status != S_BSY || --retries == 0)
1547 break;
1548 gdth_delay(1);
1549 }
1550
1551 return (ha->status != S_OK ? 0:1);
1552 }
1553
1554
1555 /* search for devices */
1556
1557 static int __devinit gdth_search_drives(gdth_ha_str *ha)
1558 {
1559 u16 cdev_cnt, i;
1560 int ok;
1561 u32 bus_no, drv_cnt, drv_no, j;
1562 gdth_getch_str *chn;
1563 gdth_drlist_str *drl;
1564 gdth_iochan_str *ioc;
1565 gdth_raw_iochan_str *iocr;
1566 gdth_arcdl_str *alst;
1567 gdth_alist_str *alst2;
1568 gdth_oem_str_ioctl *oemstr;
1569 #ifdef INT_COAL
1570 gdth_perf_modes *pmod;
1571 #endif
1572
1573 #ifdef GDTH_RTC
1574 u8 rtc[12];
1575 unsigned long flags;
1576 #endif
1577
1578 TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
1579 ok = 0;
1580
1581 /* initialize controller services, at first: screen service */
1582 ha->screen_feat = 0;
1583 if (!force_dma32) {
1584 ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
1585 if (ok)
1586 ha->screen_feat = GDT_64BIT;
1587 }
1588 if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
1589 ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
1590 if (!ok) {
1591 printk("GDT-HA %d: Initialization error screen service (code %d)\n",
1592 ha->hanum, ha->status);
1593 return 0;
1594 }
1595 TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
1596
1597 #ifdef GDTH_RTC
1598 /* read realtime clock info, send to controller */
1599 /* 1. wait for the falling edge of update flag */
1600 spin_lock_irqsave(&rtc_lock, flags);
1601 for (j = 0; j < 1000000; ++j)
1602 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
1603 break;
1604 for (j = 0; j < 1000000; ++j)
1605 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
1606 break;
1607 /* 2. read info */
1608 do {
1609 for (j = 0; j < 12; ++j)
1610 rtc[j] = CMOS_READ(j);
1611 } while (rtc[0] != CMOS_READ(0));
1612 spin_unlock_irqrestore(&rtc_lock, flags);
1613 TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(u32 *)&rtc[0],
1614 *(u32 *)&rtc[4], *(u32 *)&rtc[8]));
1615 /* 3. send to controller firmware */
1616 gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(u32 *)&rtc[0],
1617 *(u32 *)&rtc[4], *(u32 *)&rtc[8]);
1618 #endif
1619
1620 /* unfreeze all IOs */
1621 gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
1622
1623 /* initialize cache service */
1624 ha->cache_feat = 0;
1625 if (!force_dma32) {
1626 ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
1627 0, 0);
1628 if (ok)
1629 ha->cache_feat = GDT_64BIT;
1630 }
1631 if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
1632 ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
1633 if (!ok) {
1634 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1635 ha->hanum, ha->status);
1636 return 0;
1637 }
1638 TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
1639 cdev_cnt = (u16)ha->info;
1640 ha->fw_vers = ha->service;
1641
1642 #ifdef INT_COAL
1643 if (ha->type == GDT_PCIMPR) {
1644 /* set perf. modes */
1645 pmod = (gdth_perf_modes *)ha->pscratch;
1646 pmod->version = 1;
1647 pmod->st_mode = 1; /* enable one status buffer */
1648 *((u64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
1649 pmod->st_buff_indx1 = COALINDEX;
1650 pmod->st_buff_addr2 = 0;
1651 pmod->st_buff_u_addr2 = 0;
1652 pmod->st_buff_indx2 = 0;
1653 pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
1654 pmod->cmd_mode = 0; // disable all cmd buffers
1655 pmod->cmd_buff_addr1 = 0;
1656 pmod->cmd_buff_u_addr1 = 0;
1657 pmod->cmd_buff_indx1 = 0;
1658 pmod->cmd_buff_addr2 = 0;
1659 pmod->cmd_buff_u_addr2 = 0;
1660 pmod->cmd_buff_indx2 = 0;
1661 pmod->cmd_buff_size = 0;
1662 pmod->reserved1 = 0;
1663 pmod->reserved2 = 0;
1664 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
1665 INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
1666 printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
1667 }
1668 }
1669 #endif
1670
1671 /* detect number of buses - try new IOCTL */
1672 iocr = (gdth_raw_iochan_str *)ha->pscratch;
1673 iocr->hdr.version = 0xffffffff;
1674 iocr->hdr.list_entries = MAXBUS;
1675 iocr->hdr.first_chan = 0;
1676 iocr->hdr.last_chan = MAXBUS-1;
1677 iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
1678 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
1679 INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
1680 TRACE2(("IOCHAN_RAW_DESC supported!\n"));
1681 ha->bus_cnt = iocr->hdr.chan_count;
1682 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1683 if (iocr->list[bus_no].proc_id < MAXID)
1684 ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
1685 else
1686 ha->bus_id[bus_no] = 0xff;
1687 }
1688 } else {
1689 /* old method */
1690 chn = (gdth_getch_str *)ha->pscratch;
1691 for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
1692 chn->channel_no = bus_no;
1693 if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1694 SCSI_CHAN_CNT | L_CTRL_PATTERN,
1695 IO_CHANNEL | INVALID_CHANNEL,
1696 sizeof(gdth_getch_str))) {
1697 if (bus_no == 0) {
1698 printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
1699 ha->hanum, ha->status);
1700 return 0;
1701 }
1702 break;
1703 }
1704 if (chn->siop_id < MAXID)
1705 ha->bus_id[bus_no] = chn->siop_id;
1706 else
1707 ha->bus_id[bus_no] = 0xff;
1708 }
1709 ha->bus_cnt = (u8)bus_no;
1710 }
1711 TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
1712
1713 /* read cache configuration */
1714 if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
1715 INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
1716 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1717 ha->hanum, ha->status);
1718 return 0;
1719 }
1720 ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
1721 TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
1722 ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
1723 ha->cpar.write_back,ha->cpar.block_size));
1724
1725 /* read board info and features */
1726 ha->more_proc = FALSE;
1727 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
1728 INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
1729 memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
1730 sizeof(gdth_binfo_str));
1731 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
1732 INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
1733 TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
1734 ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
1735 ha->more_proc = TRUE;
1736 }
1737 } else {
1738 TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
1739 strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
1740 }
1741 TRACE2(("Controller name: %s\n",ha->binfo.type_string));
1742
1743 /* read more informations */
1744 if (ha->more_proc) {
1745 /* physical drives, channel addresses */
1746 ioc = (gdth_iochan_str *)ha->pscratch;
1747 ioc->hdr.version = 0xffffffff;
1748 ioc->hdr.list_entries = MAXBUS;
1749 ioc->hdr.first_chan = 0;
1750 ioc->hdr.last_chan = MAXBUS-1;
1751 ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
1752 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
1753 INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
1754 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1755 ha->raw[bus_no].address = ioc->list[bus_no].address;
1756 ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
1757 }
1758 } else {
1759 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1760 ha->raw[bus_no].address = IO_CHANNEL;
1761 ha->raw[bus_no].local_no = bus_no;
1762 }
1763 }
1764 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1765 chn = (gdth_getch_str *)ha->pscratch;
1766 chn->channel_no = ha->raw[bus_no].local_no;
1767 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1768 SCSI_CHAN_CNT | L_CTRL_PATTERN,
1769 ha->raw[bus_no].address | INVALID_CHANNEL,
1770 sizeof(gdth_getch_str))) {
1771 ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
1772 TRACE2(("Channel %d: %d phys. drives\n",
1773 bus_no,chn->drive_cnt));
1774 }
1775 if (ha->raw[bus_no].pdev_cnt > 0) {
1776 drl = (gdth_drlist_str *)ha->pscratch;
1777 drl->sc_no = ha->raw[bus_no].local_no;
1778 drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
1779 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1780 SCSI_DR_LIST | L_CTRL_PATTERN,
1781 ha->raw[bus_no].address | INVALID_CHANNEL,
1782 sizeof(gdth_drlist_str))) {
1783 for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
1784 ha->raw[bus_no].id_list[j] = drl->sc_list[j];
1785 } else {
1786 ha->raw[bus_no].pdev_cnt = 0;
1787 }
1788 }
1789 }
1790
1791 /* logical drives */
1792 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
1793 INVALID_CHANNEL,sizeof(u32))) {
1794 drv_cnt = *(u32 *)ha->pscratch;
1795 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
1796 INVALID_CHANNEL,drv_cnt * sizeof(u32))) {
1797 for (j = 0; j < drv_cnt; ++j) {
1798 drv_no = ((u32 *)ha->pscratch)[j];
1799 if (drv_no < MAX_LDRIVES) {
1800 ha->hdr[drv_no].is_logdrv = TRUE;
1801 TRACE2(("Drive %d is log. drive\n",drv_no));
1802 }
1803 }
1804 }
1805 alst = (gdth_arcdl_str *)ha->pscratch;
1806 alst->entries_avail = MAX_LDRIVES;
1807 alst->first_entry = 0;
1808 alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
1809 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1810 ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
1811 INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
1812 (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
1813 for (j = 0; j < alst->entries_init; ++j) {
1814 ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
1815 ha->hdr[j].is_master = alst->list[j].is_master;
1816 ha->hdr[j].is_parity = alst->list[j].is_parity;
1817 ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
1818 ha->hdr[j].master_no = alst->list[j].cd_handle;
1819 }
1820 } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1821 ARRAY_DRV_LIST | LA_CTRL_PATTERN,
1822 0, 35 * sizeof(gdth_alist_str))) {
1823 for (j = 0; j < 35; ++j) {
1824 alst2 = &((gdth_alist_str *)ha->pscratch)[j];
1825 ha->hdr[j].is_arraydrv = alst2->is_arrayd;
1826 ha->hdr[j].is_master = alst2->is_master;
1827 ha->hdr[j].is_parity = alst2->is_parity;
1828 ha->hdr[j].is_hotfix = alst2->is_hotfix;
1829 ha->hdr[j].master_no = alst2->cd_handle;
1830 }
1831 }
1832 }
1833 }
1834
1835 /* initialize raw service */
1836 ha->raw_feat = 0;
1837 if (!force_dma32) {
1838 ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
1839 if (ok)
1840 ha->raw_feat = GDT_64BIT;
1841 }
1842 if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
1843 ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
1844 if (!ok) {
1845 printk("GDT-HA %d: Initialization error raw service (code %d)\n",
1846 ha->hanum, ha->status);
1847 return 0;
1848 }
1849 TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
1850
1851 /* set/get features raw service (scatter/gather) */
1852 if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
1853 0, 0)) {
1854 TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
1855 if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
1856 TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
1857 ha->info));
1858 ha->raw_feat |= (u16)ha->info;
1859 }
1860 }
1861
1862 /* set/get features cache service (equal to raw service) */
1863 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
1864 SCATTER_GATHER,0)) {
1865 TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
1866 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
1867 TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
1868 ha->info));
1869 ha->cache_feat |= (u16)ha->info;
1870 }
1871 }
1872
1873 /* reserve drives for raw service */
1874 if (reserve_mode != 0) {
1875 gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
1876 reserve_mode == 1 ? 1 : 3, 0, 0);
1877 TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
1878 ha->status));
1879 }
1880 for (i = 0; i < MAX_RES_ARGS; i += 4) {
1881 if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
1882 reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
1883 TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
1884 reserve_list[i], reserve_list[i+1],
1885 reserve_list[i+2], reserve_list[i+3]));
1886 if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
1887 reserve_list[i+1], reserve_list[i+2] |
1888 (reserve_list[i+3] << 8))) {
1889 printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
1890 ha->hanum, ha->status);
1891 }
1892 }
1893 }
1894
1895 /* Determine OEM string using IOCTL */
1896 oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
1897 oemstr->params.ctl_version = 0x01;
1898 oemstr->params.buffer_size = sizeof(oemstr->text);
1899 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1900 CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
1901 sizeof(gdth_oem_str_ioctl))) {
1902 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
1903 printk("GDT-HA %d: Vendor: %s Name: %s\n",
1904 ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
1905 /* Save the Host Drive inquiry data */
1906 strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
1907 sizeof(ha->oem_name));
1908 } else {
1909 /* Old method, based on PCI ID */
1910 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
1911 printk("GDT-HA %d: Name: %s\n",
1912 ha->hanum, ha->binfo.type_string);
1913 if (ha->oem_id == OEM_ID_INTEL)
1914 strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
1915 else
1916 strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
1917 }
1918
1919 /* scanning for host drives */
1920 for (i = 0; i < cdev_cnt; ++i)
1921 gdth_analyse_hdrive(ha, i);
1922
1923 TRACE(("gdth_search_drives() OK\n"));
1924 return 1;
1925 }
1926
1927 static int gdth_analyse_hdrive(gdth_ha_str *ha, u16 hdrive)
1928 {
1929 u32 drv_cyls;
1930 int drv_hds, drv_secs;
1931
1932 TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
1933 if (hdrive >= MAX_HDRIVES)
1934 return 0;
1935
1936 if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
1937 return 0;
1938 ha->hdr[hdrive].present = TRUE;
1939 ha->hdr[hdrive].size = ha->info;
1940
1941 /* evaluate mapping (sectors per head, heads per cylinder) */
1942 ha->hdr[hdrive].size &= ~SECS32;
1943 if (ha->info2 == 0) {
1944 gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
1945 } else {
1946 drv_hds = ha->info2 & 0xff;
1947 drv_secs = (ha->info2 >> 8) & 0xff;
1948 drv_cyls = (u32)ha->hdr[hdrive].size / drv_hds / drv_secs;
1949 }
1950 ha->hdr[hdrive].heads = (u8)drv_hds;
1951 ha->hdr[hdrive].secs = (u8)drv_secs;
1952 /* round size */
1953 ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
1954
1955 if (ha->cache_feat & GDT_64BIT) {
1956 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
1957 && ha->info2 != 0) {
1958 ha->hdr[hdrive].size = ((u64)ha->info2 << 32) | ha->info;
1959 }
1960 }
1961 TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
1962 hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
1963
1964 /* get informations about device */
1965 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
1966 TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
1967 hdrive,ha->info));
1968 ha->hdr[hdrive].devtype = (u16)ha->info;
1969 }
1970
1971 /* cluster info */
1972 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
1973 TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
1974 hdrive,ha->info));
1975 if (!shared_access)
1976 ha->hdr[hdrive].cluster_type = (u8)ha->info;
1977 }
1978
1979 /* R/W attributes */
1980 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
1981 TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
1982 hdrive,ha->info));
1983 ha->hdr[hdrive].rw_attribs = (u8)ha->info;
1984 }
1985
1986 return 1;
1987 }
1988
1989
1990 /* command queueing/sending functions */
1991
1992 static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 priority)
1993 {
1994 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
1995 register Scsi_Cmnd *pscp;
1996 register Scsi_Cmnd *nscp;
1997 unsigned long flags;
1998
1999 TRACE(("gdth_putq() priority %d\n",priority));
2000 spin_lock_irqsave(&ha->smp_lock, flags);
2001
2002 if (!cmndinfo->internal_command)
2003 cmndinfo->priority = priority;
2004
2005 if (ha->req_first==NULL) {
2006 ha->req_first = scp; /* queue was empty */
2007 scp->SCp.ptr = NULL;
2008 } else { /* queue not empty */
2009 pscp = ha->req_first;
2010 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2011 /* priority: 0-highest,..,0xff-lowest */
2012 while (nscp && gdth_cmnd_priv(nscp)->priority <= priority) {
2013 pscp = nscp;
2014 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2015 }
2016 pscp->SCp.ptr = (char *)scp;
2017 scp->SCp.ptr = (char *)nscp;
2018 }
2019 spin_unlock_irqrestore(&ha->smp_lock, flags);
2020
2021 #ifdef GDTH_STATISTICS
2022 flags = 0;
2023 for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
2024 ++flags;
2025 if (max_rq < flags) {
2026 max_rq = flags;
2027 TRACE3(("GDT: max_rq = %d\n",(u16)max_rq));
2028 }
2029 #endif
2030 }
2031
2032 static void gdth_next(gdth_ha_str *ha)
2033 {
2034 register Scsi_Cmnd *pscp;
2035 register Scsi_Cmnd *nscp;
2036 u8 b, t, l, firsttime;
2037 u8 this_cmd, next_cmd;
2038 unsigned long flags = 0;
2039 int cmd_index;
2040
2041 TRACE(("gdth_next() hanum %d\n", ha->hanum));
2042 if (!gdth_polling)
2043 spin_lock_irqsave(&ha->smp_lock, flags);
2044
2045 ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
2046 this_cmd = firsttime = TRUE;
2047 next_cmd = gdth_polling ? FALSE:TRUE;
2048 cmd_index = 0;
2049
2050 for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
2051 struct gdth_cmndinfo *nscp_cmndinfo = gdth_cmnd_priv(nscp);
2052 if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
2053 pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2054 if (!nscp_cmndinfo->internal_command) {
2055 b = nscp->device->channel;
2056 t = nscp->device->id;
2057 l = nscp->device->lun;
2058 if (nscp_cmndinfo->priority >= DEFAULT_PRI) {
2059 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2060 (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
2061 continue;
2062 }
2063 } else
2064 b = t = l = 0;
2065
2066 if (firsttime) {
2067 if (gdth_test_busy(ha)) { /* controller busy ? */
2068 TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
2069 if (!gdth_polling) {
2070 spin_unlock_irqrestore(&ha->smp_lock, flags);
2071 return;
2072 }
2073 while (gdth_test_busy(ha))
2074 gdth_delay(1);
2075 }
2076 firsttime = FALSE;
2077 }
2078
2079 if (!nscp_cmndinfo->internal_command) {
2080 if (nscp_cmndinfo->phase == -1) {
2081 nscp_cmndinfo->phase = CACHESERVICE; /* default: cache svc. */
2082 if (nscp->cmnd[0] == TEST_UNIT_READY) {
2083 TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
2084 b, t, l));
2085 /* TEST_UNIT_READY -> set scan mode */
2086 if ((ha->scan_mode & 0x0f) == 0) {
2087 if (b == 0 && t == 0 && l == 0) {
2088 ha->scan_mode |= 1;
2089 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2090 }
2091 } else if ((ha->scan_mode & 0x0f) == 1) {
2092 if (b == 0 && ((t == 0 && l == 1) ||
2093 (t == 1 && l == 0))) {
2094 nscp_cmndinfo->OpCode = GDT_SCAN_START;
2095 nscp_cmndinfo->phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
2096 | SCSIRAWSERVICE;
2097 ha->scan_mode = 0x12;
2098 TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
2099 ha->scan_mode));
2100 } else {
2101 ha->scan_mode &= 0x10;
2102 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2103 }
2104 } else if (ha->scan_mode == 0x12) {
2105 if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
2106 nscp_cmndinfo->phase = SCSIRAWSERVICE;
2107 nscp_cmndinfo->OpCode = GDT_SCAN_END;
2108 ha->scan_mode &= 0x10;
2109 TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
2110 ha->scan_mode));
2111 }
2112 }
2113 }
2114 if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
2115 nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
2116 (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
2117 /* always GDT_CLUST_INFO! */
2118 nscp_cmndinfo->OpCode = GDT_CLUST_INFO;
2119 }
2120 }
2121 }
2122
2123 if (nscp_cmndinfo->OpCode != -1) {
2124 if ((nscp_cmndinfo->phase & 0xff) == CACHESERVICE) {
2125 if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2126 this_cmd = FALSE;
2127 next_cmd = FALSE;
2128 } else if ((nscp_cmndinfo->phase & 0xff) == SCSIRAWSERVICE) {
2129 if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
2130 this_cmd = FALSE;
2131 next_cmd = FALSE;
2132 } else {
2133 memset((char*)nscp->sense_buffer,0,16);
2134 nscp->sense_buffer[0] = 0x70;
2135 nscp->sense_buffer[2] = NOT_READY;
2136 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2137 if (!nscp_cmndinfo->wait_for_completion)
2138 nscp_cmndinfo->wait_for_completion++;
2139 else
2140 gdth_scsi_done(nscp);
2141 }
2142 } else if (gdth_cmnd_priv(nscp)->internal_command) {
2143 if (!(cmd_index=gdth_special_cmd(ha, nscp)))
2144 this_cmd = FALSE;
2145 next_cmd = FALSE;
2146 } else if (b != ha->virt_bus) {
2147 if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
2148 !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
2149 this_cmd = FALSE;
2150 else
2151 ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
2152 } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
2153 TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
2154 nscp->cmnd[0], b, t, l));
2155 nscp->result = DID_BAD_TARGET << 16;
2156 if (!nscp_cmndinfo->wait_for_completion)
2157 nscp_cmndinfo->wait_for_completion++;
2158 else
2159 gdth_scsi_done(nscp);
2160 } else {
2161 switch (nscp->cmnd[0]) {
2162 case TEST_UNIT_READY:
2163 case INQUIRY:
2164 case REQUEST_SENSE:
2165 case READ_CAPACITY:
2166 case VERIFY:
2167 case START_STOP:
2168 case MODE_SENSE:
2169 case SERVICE_ACTION_IN:
2170 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2171 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2172 nscp->cmnd[4],nscp->cmnd[5]));
2173 if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
2174 /* return UNIT_ATTENTION */
2175 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2176 nscp->cmnd[0], t));
2177 ha->hdr[t].media_changed = FALSE;
2178 memset((char*)nscp->sense_buffer,0,16);
2179 nscp->sense_buffer[0] = 0x70;
2180 nscp->sense_buffer[2] = UNIT_ATTENTION;
2181 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2182 if (!nscp_cmndinfo->wait_for_completion)
2183 nscp_cmndinfo->wait_for_completion++;
2184 else
2185 gdth_scsi_done(nscp);
2186 } else if (gdth_internal_cache_cmd(ha, nscp))
2187 gdth_scsi_done(nscp);
2188 break;
2189
2190 case ALLOW_MEDIUM_REMOVAL:
2191 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2192 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2193 nscp->cmnd[4],nscp->cmnd[5]));
2194 if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
2195 TRACE(("Prevent r. nonremov. drive->do nothing\n"));
2196 nscp->result = DID_OK << 16;
2197 nscp->sense_buffer[0] = 0;
2198 if (!nscp_cmndinfo->wait_for_completion)
2199 nscp_cmndinfo->wait_for_completion++;
2200 else
2201 gdth_scsi_done(nscp);
2202 } else {
2203 nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
2204 TRACE(("Prevent/allow r. %d rem. drive %d\n",
2205 nscp->cmnd[4],nscp->cmnd[3]));
2206 if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2207 this_cmd = FALSE;
2208 }
2209 break;
2210
2211 case RESERVE:
2212 case RELEASE:
2213 TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
2214 "RESERVE" : "RELEASE"));
2215 if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2216 this_cmd = FALSE;
2217 break;
2218
2219 case READ_6:
2220 case WRITE_6:
2221 case READ_10:
2222 case WRITE_10:
2223 case READ_16:
2224 case WRITE_16:
2225 if (ha->hdr[t].media_changed) {
2226 /* return UNIT_ATTENTION */
2227 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2228 nscp->cmnd[0], t));
2229 ha->hdr[t].media_changed = FALSE;
2230 memset((char*)nscp->sense_buffer,0,16);
2231 nscp->sense_buffer[0] = 0x70;
2232 nscp->sense_buffer[2] = UNIT_ATTENTION;
2233 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2234 if (!nscp_cmndinfo->wait_for_completion)
2235 nscp_cmndinfo->wait_for_completion++;
2236 else
2237 gdth_scsi_done(nscp);
2238 } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
2239 this_cmd = FALSE;
2240 break;
2241
2242 default:
2243 TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
2244 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2245 nscp->cmnd[4],nscp->cmnd[5]));
2246 printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
2247 ha->hanum, nscp->cmnd[0]);
2248 nscp->result = DID_ABORT << 16;
2249 if (!nscp_cmndinfo->wait_for_completion)
2250 nscp_cmndinfo->wait_for_completion++;
2251 else
2252 gdth_scsi_done(nscp);
2253 break;
2254 }
2255 }
2256
2257 if (!this_cmd)
2258 break;
2259 if (nscp == ha->req_first)
2260 ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
2261 else
2262 pscp->SCp.ptr = nscp->SCp.ptr;
2263 if (!next_cmd)
2264 break;
2265 }
2266
2267 if (ha->cmd_cnt > 0) {
2268 gdth_release_event(ha);
2269 }
2270
2271 if (!gdth_polling)
2272 spin_unlock_irqrestore(&ha->smp_lock, flags);
2273
2274 if (gdth_polling && ha->cmd_cnt > 0) {
2275 if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
2276 printk("GDT-HA %d: Command %d timed out !\n",
2277 ha->hanum, cmd_index);
2278 }
2279 }
2280
2281 /*
2282 * gdth_copy_internal_data() - copy to/from a buffer onto a scsi_cmnd's
2283 * buffers, kmap_atomic() as needed.
2284 */
2285 static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
2286 char *buffer, u16 count)
2287 {
2288 u16 cpcount,i, max_sg = scsi_sg_count(scp);
2289 u16 cpsum,cpnow;
2290 struct scatterlist *sl;
2291 char *address;
2292
2293 cpcount = min_t(u16, count, scsi_bufflen(scp));
2294
2295 if (cpcount) {
2296 cpsum=0;
2297 scsi_for_each_sg(scp, sl, max_sg, i) {
2298 unsigned long flags;
2299 cpnow = (u16)sl->length;
2300 TRACE(("copy_internal() now %d sum %d count %d %d\n",
2301 cpnow, cpsum, cpcount, scsi_bufflen(scp)));
2302 if (cpsum+cpnow > cpcount)
2303 cpnow = cpcount - cpsum;
2304 cpsum += cpnow;
2305 if (!sg_page(sl)) {
2306 printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
2307 ha->hanum);
2308 return;
2309 }
2310 local_irq_save(flags);
2311 address = kmap_atomic(sg_page(sl), KM_BIO_SRC_IRQ) + sl->offset;
2312 memcpy(address, buffer, cpnow);
2313 flush_dcache_page(sg_page(sl));
2314 kunmap_atomic(address, KM_BIO_SRC_IRQ);
2315 local_irq_restore(flags);
2316 if (cpsum == cpcount)
2317 break;
2318 buffer += cpnow;
2319 }
2320 } else if (count) {
2321 printk("GDT-HA %d: SCSI command with no buffers but data transfer expected!\n",
2322 ha->hanum);
2323 WARN_ON(1);
2324 }
2325 }
2326
2327 static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
2328 {
2329 u8 t;
2330 gdth_inq_data inq;
2331 gdth_rdcap_data rdc;
2332 gdth_sense_data sd;
2333 gdth_modep_data mpd;
2334 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
2335
2336 t = scp->device->id;
2337 TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
2338 scp->cmnd[0],t));
2339
2340 scp->result = DID_OK << 16;
2341 scp->sense_buffer[0] = 0;
2342
2343 switch (scp->cmnd[0]) {
2344 case TEST_UNIT_READY:
2345 case VERIFY:
2346 case START_STOP:
2347 TRACE2(("Test/Verify/Start hdrive %d\n",t));
2348 break;
2349
2350 case INQUIRY:
2351 TRACE2(("Inquiry hdrive %d devtype %d\n",
2352 t,ha->hdr[t].devtype));
2353 inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
2354 /* you can here set all disks to removable, if you want to do
2355 a flush using the ALLOW_MEDIUM_REMOVAL command */
2356 inq.modif_rmb = 0x00;
2357 if ((ha->hdr[t].devtype & 1) ||
2358 (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
2359 inq.modif_rmb = 0x80;
2360 inq.version = 2;
2361 inq.resp_aenc = 2;
2362 inq.add_length= 32;
2363 strcpy(inq.vendor,ha->oem_name);
2364 sprintf(inq.product,"Host Drive #%02d",t);
2365 strcpy(inq.revision," ");
2366 gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data));
2367 break;
2368
2369 case REQUEST_SENSE:
2370 TRACE2(("Request sense hdrive %d\n",t));
2371 sd.errorcode = 0x70;
2372 sd.segno = 0x00;
2373 sd.key = NO_SENSE;
2374 sd.info = 0;
2375 sd.add_length= 0;
2376 gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data));
2377 break;
2378
2379 case MODE_SENSE:
2380 TRACE2(("Mode sense hdrive %d\n",t));
2381 memset((char*)&mpd,0,sizeof(gdth_modep_data));
2382 mpd.hd.data_length = sizeof(gdth_modep_data);
2383 mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
2384 mpd.hd.bd_length = sizeof(mpd.bd);
2385 mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
2386 mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
2387 mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
2388 gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data));
2389 break;
2390
2391 case READ_CAPACITY:
2392 TRACE2(("Read capacity hdrive %d\n",t));
2393 if (ha->hdr[t].size > (u64)0xffffffff)
2394 rdc.last_block_no = 0xffffffff;
2395 else
2396 rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
2397 rdc.block_length = cpu_to_be32(SECTOR_SIZE);
2398 gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data));
2399 break;
2400
2401 case SERVICE_ACTION_IN:
2402 if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
2403 (ha->cache_feat & GDT_64BIT)) {
2404 gdth_rdcap16_data rdc16;
2405
2406 TRACE2(("Read capacity (16) hdrive %d\n",t));
2407 rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
2408 rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
2409 gdth_copy_internal_data(ha, scp, (char*)&rdc16,
2410 sizeof(gdth_rdcap16_data));
2411 } else {
2412 scp->result = DID_ABORT << 16;
2413 }
2414 break;
2415
2416 default:
2417 TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
2418 break;
2419 }
2420
2421 if (!cmndinfo->wait_for_completion)
2422 cmndinfo->wait_for_completion++;
2423 else
2424 return 1;
2425
2426 return 0;
2427 }
2428
2429 static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u16 hdrive)
2430 {
2431 register gdth_cmd_str *cmdp;
2432 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
2433 u32 cnt, blockcnt;
2434 u64 no, blockno;
2435 int i, cmd_index, read_write, sgcnt, mode64;
2436
2437 cmdp = ha->pccb;
2438 TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
2439 scp->cmnd[0],scp->cmd_len,hdrive));
2440
2441 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2442 return 0;
2443
2444 mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
2445 /* test for READ_16, WRITE_16 if !mode64 ? ---
2446 not required, should not occur due to error return on
2447 READ_CAPACITY_16 */
2448
2449 cmdp->Service = CACHESERVICE;
2450 cmdp->RequestBuffer = scp;
2451 /* search free command index */
2452 if (!(cmd_index=gdth_get_cmd_index(ha))) {
2453 TRACE(("GDT: No free command index found\n"));
2454 return 0;
2455 }
2456 /* if it's the first command, set command semaphore */
2457 if (ha->cmd_cnt == 0)
2458 gdth_set_sema0(ha);
2459
2460 /* fill command */
2461 read_write = 0;
2462 if (cmndinfo->OpCode != -1)
2463 cmdp->OpCode = cmndinfo->OpCode; /* special cache cmd. */
2464 else if (scp->cmnd[0] == RESERVE)
2465 cmdp->OpCode = GDT_RESERVE_DRV;
2466 else if (scp->cmnd[0] == RELEASE)
2467 cmdp->OpCode = GDT_RELEASE_DRV;
2468 else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
2469 if (scp->cmnd[4] & 1) /* prevent ? */
2470 cmdp->OpCode = GDT_MOUNT;
2471 else if (scp->cmnd[3] & 1) /* removable drive ? */
2472 cmdp->OpCode = GDT_UNMOUNT;
2473 else
2474 cmdp->OpCode = GDT_FLUSH;
2475 } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
2476 scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
2477 ) {
2478 read_write = 1;
2479 if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
2480 (ha->cache_feat & GDT_WR_THROUGH)))
2481 cmdp->OpCode = GDT_WRITE_THR;
2482 else
2483 cmdp->OpCode = GDT_WRITE;
2484 } else {
2485 read_write = 2;
2486 cmdp->OpCode = GDT_READ;
2487 }
2488
2489 cmdp->BoardNode = LOCALBOARD;
2490 if (mode64) {
2491 cmdp->u.cache64.DeviceNo = hdrive;
2492 cmdp->u.cache64.BlockNo = 1;
2493 cmdp->u.cache64.sg_canz = 0;
2494 } else {
2495 cmdp->u.cache.DeviceNo = hdrive;
2496 cmdp->u.cache.BlockNo = 1;
2497 cmdp->u.cache.sg_canz = 0;
2498 }
2499
2500 if (read_write) {
2501 if (scp->cmd_len == 16) {
2502 memcpy(&no, &scp->cmnd[2], sizeof(u64));
2503 blockno = be64_to_cpu(no);
2504 memcpy(&cnt, &scp->cmnd[10], sizeof(u32));
2505 blockcnt = be32_to_cpu(cnt);
2506 } else if (scp->cmd_len == 10) {
2507 memcpy(&no, &scp->cmnd[2], sizeof(u32));
2508 blockno = be32_to_cpu(no);
2509 memcpy(&cnt, &scp->cmnd[7], sizeof(u16));
2510 blockcnt = be16_to_cpu(cnt);
2511 } else {
2512 memcpy(&no, &scp->cmnd[0], sizeof(u32));
2513 blockno = be32_to_cpu(no) & 0x001fffffUL;
2514 blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
2515 }
2516 if (mode64) {
2517 cmdp->u.cache64.BlockNo = blockno;
2518 cmdp->u.cache64.BlockCnt = blockcnt;
2519 } else {
2520 cmdp->u.cache.BlockNo = (u32)blockno;
2521 cmdp->u.cache.BlockCnt = blockcnt;
2522 }
2523
2524 if (scsi_bufflen(scp)) {
2525 cmndinfo->dma_dir = (read_write == 1 ?
2526 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2527 sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
2528 cmndinfo->dma_dir);
2529 if (mode64) {
2530 struct scatterlist *sl;
2531
2532 cmdp->u.cache64.DestAddr= (u64)-1;
2533 cmdp->u.cache64.sg_canz = sgcnt;
2534 scsi_for_each_sg(scp, sl, sgcnt, i) {
2535 cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2536 #ifdef GDTH_DMA_STATISTICS
2537 if (cmdp->u.cache64.sg_lst[i].sg_ptr > (u64)0xffffffff)
2538 ha->dma64_cnt++;
2539 else
2540 ha->dma32_cnt++;
2541 #endif
2542 cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
2543 }
2544 } else {
2545 struct scatterlist *sl;
2546
2547 cmdp->u.cache.DestAddr= 0xffffffff;
2548 cmdp->u.cache.sg_canz = sgcnt;
2549 scsi_for_each_sg(scp, sl, sgcnt, i) {
2550 cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
2551 #ifdef GDTH_DMA_STATISTICS
2552 ha->dma32_cnt++;
2553 #endif
2554 cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
2555 }
2556 }
2557
2558 #ifdef GDTH_STATISTICS
2559 if (max_sg < (u32)sgcnt) {
2560 max_sg = (u32)sgcnt;
2561 TRACE3(("GDT: max_sg = %d\n",max_sg));
2562 }
2563 #endif
2564
2565 }
2566 }
2567 /* evaluate command size, check space */
2568 if (mode64) {
2569 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2570 cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
2571 cmdp->u.cache64.sg_lst[0].sg_ptr,
2572 cmdp->u.cache64.sg_lst[0].sg_len));
2573 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2574 cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
2575 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
2576 (u16)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
2577 } else {
2578 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2579 cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
2580 cmdp->u.cache.sg_lst[0].sg_ptr,
2581 cmdp->u.cache.sg_lst[0].sg_len));
2582 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2583 cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
2584 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
2585 (u16)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
2586 }
2587 if (ha->cmd_len & 3)
2588 ha->cmd_len += (4 - (ha->cmd_len & 3));
2589
2590 if (ha->cmd_cnt > 0) {
2591 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2592 ha->ic_all_size) {
2593 TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
2594 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2595 return 0;
2596 }
2597 }
2598
2599 /* copy command */
2600 gdth_copy_command(ha);
2601 return cmd_index;
2602 }
2603
2604 static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 b)
2605 {
2606 register gdth_cmd_str *cmdp;
2607 u16 i;
2608 dma_addr_t sense_paddr;
2609 int cmd_index, sgcnt, mode64;
2610 u8 t,l;
2611 struct page *page;
2612 unsigned long offset;
2613 struct gdth_cmndinfo *cmndinfo;
2614
2615 t = scp->device->id;
2616 l = scp->device->lun;
2617 cmdp = ha->pccb;
2618 TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
2619 scp->cmnd[0],b,t,l));
2620
2621 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2622 return 0;
2623
2624 mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
2625
2626 cmdp->Service = SCSIRAWSERVICE;
2627 cmdp->RequestBuffer = scp;
2628 /* search free command index */
2629 if (!(cmd_index=gdth_get_cmd_index(ha))) {
2630 TRACE(("GDT: No free command index found\n"));
2631 return 0;
2632 }
2633 /* if it's the first command, set command semaphore */
2634 if (ha->cmd_cnt == 0)
2635 gdth_set_sema0(ha);
2636
2637 cmndinfo = gdth_cmnd_priv(scp);
2638 /* fill command */
2639 if (cmndinfo->OpCode != -1) {
2640 cmdp->OpCode = cmndinfo->OpCode; /* special raw cmd. */
2641 cmdp->BoardNode = LOCALBOARD;
2642 if (mode64) {
2643 cmdp->u.raw64.direction = (cmndinfo->phase >> 8);
2644 TRACE2(("special raw cmd 0x%x param 0x%x\n",
2645 cmdp->OpCode, cmdp->u.raw64.direction));
2646 /* evaluate command size */
2647 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
2648 } else {
2649 cmdp->u.raw.direction = (cmndinfo->phase >> 8);
2650 TRACE2(("special raw cmd 0x%x param 0x%x\n",
2651 cmdp->OpCode, cmdp->u.raw.direction));
2652 /* evaluate command size */
2653 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
2654 }
2655
2656 } else {
2657 page = virt_to_page(scp->sense_buffer);
2658 offset = (unsigned long)scp->sense_buffer & ~PAGE_MASK;
2659 sense_paddr = pci_map_page(ha->pdev,page,offset,
2660 16,PCI_DMA_FROMDEVICE);
2661
2662 cmndinfo->sense_paddr = sense_paddr;
2663 cmdp->OpCode = GDT_WRITE; /* always */
2664 cmdp->BoardNode = LOCALBOARD;
2665 if (mode64) {
2666 cmdp->u.raw64.reserved = 0;
2667 cmdp->u.raw64.mdisc_time = 0;
2668 cmdp->u.raw64.mcon_time = 0;
2669 cmdp->u.raw64.clen = scp->cmd_len;
2670 cmdp->u.raw64.target = t;
2671 cmdp->u.raw64.lun = l;
2672 cmdp->u.raw64.bus = b;
2673 cmdp->u.raw64.priority = 0;
2674 cmdp->u.raw64.sdlen = scsi_bufflen(scp);
2675 cmdp->u.raw64.sense_len = 16;
2676 cmdp->u.raw64.sense_data = sense_paddr;
2677 cmdp->u.raw64.direction =
2678 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
2679 memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
2680 cmdp->u.raw64.sg_ranz = 0;
2681 } else {
2682 cmdp->u.raw.reserved = 0;
2683 cmdp->u.raw.mdisc_time = 0;
2684 cmdp->u.raw.mcon_time = 0;
2685 cmdp->u.raw.clen = scp->cmd_len;
2686 cmdp->u.raw.target = t;
2687 cmdp->u.raw.lun = l;
2688 cmdp->u.raw.bus = b;
2689 cmdp->u.raw.priority = 0;
2690 cmdp->u.raw.link_p = 0;
2691 cmdp->u.raw.sdlen = scsi_bufflen(scp);
2692 cmdp->u.raw.sense_len = 16;
2693 cmdp->u.raw.sense_data = sense_paddr;
2694 cmdp->u.raw.direction =
2695 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
2696 memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
2697 cmdp->u.raw.sg_ranz = 0;
2698 }
2699
2700 if (scsi_bufflen(scp)) {
2701 cmndinfo->dma_dir = PCI_DMA_BIDIRECTIONAL;
2702 sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
2703 cmndinfo->dma_dir);
2704 if (mode64) {
2705 struct scatterlist *sl;
2706
2707 cmdp->u.raw64.sdata = (u64)-1;
2708 cmdp->u.raw64.sg_ranz = sgcnt;
2709 scsi_for_each_sg(scp, sl, sgcnt, i) {
2710 cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2711 #ifdef GDTH_DMA_STATISTICS
2712 if (cmdp->u.raw64.sg_lst[i].sg_ptr > (u64)0xffffffff)
2713 ha->dma64_cnt++;
2714 else
2715 ha->dma32_cnt++;
2716 #endif
2717 cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
2718 }
2719 } else {
2720 struct scatterlist *sl;
2721
2722 cmdp->u.raw.sdata = 0xffffffff;
2723 cmdp->u.raw.sg_ranz = sgcnt;
2724 scsi_for_each_sg(scp, sl, sgcnt, i) {
2725 cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
2726 #ifdef GDTH_DMA_STATISTICS
2727 ha->dma32_cnt++;
2728 #endif
2729 cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
2730 }
2731 }
2732
2733 #ifdef GDTH_STATISTICS
2734 if (max_sg < sgcnt) {
2735 max_sg = sgcnt;
2736 TRACE3(("GDT: max_sg = %d\n",sgcnt));
2737 }
2738 #endif
2739
2740 }
2741 if (mode64) {
2742 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2743 cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
2744 cmdp->u.raw64.sg_lst[0].sg_ptr,
2745 cmdp->u.raw64.sg_lst[0].sg_len));
2746 /* evaluate command size */
2747 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
2748 (u16)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
2749 } else {
2750 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2751 cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
2752 cmdp->u.raw.sg_lst[0].sg_ptr,
2753 cmdp->u.raw.sg_lst[0].sg_len));
2754 /* evaluate command size */
2755 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
2756 (u16)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
2757 }
2758 }
2759 /* check space */
2760 if (ha->cmd_len & 3)
2761 ha->cmd_len += (4 - (ha->cmd_len & 3));
2762
2763 if (ha->cmd_cnt > 0) {
2764 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2765 ha->ic_all_size) {
2766 TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
2767 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2768 return 0;
2769 }
2770 }
2771
2772 /* copy command */
2773 gdth_copy_command(ha);
2774 return cmd_index;
2775 }
2776
2777 static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
2778 {
2779 register gdth_cmd_str *cmdp;
2780 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
2781 int cmd_index;
2782
2783 cmdp= ha->pccb;
2784 TRACE2(("gdth_special_cmd(): "));
2785
2786 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2787 return 0;
2788
2789 *cmdp = *cmndinfo->internal_cmd_str;
2790 cmdp->RequestBuffer = scp;
2791
2792 /* search free command index */
2793 if (!(cmd_index=gdth_get_cmd_index(ha))) {
2794 TRACE(("GDT: No free command index found\n"));
2795 return 0;
2796 }
2797
2798 /* if it's the first command, set command semaphore */
2799 if (ha->cmd_cnt == 0)
2800 gdth_set_sema0(ha);
2801
2802 /* evaluate command size, check space */
2803 if (cmdp->OpCode == GDT_IOCTL) {
2804 TRACE2(("IOCTL\n"));
2805 ha->cmd_len =
2806 GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(u64);
2807 } else if (cmdp->Service == CACHESERVICE) {
2808 TRACE2(("cache command %d\n",cmdp->OpCode));
2809 if (ha->cache_feat & GDT_64BIT)
2810 ha->cmd_len =
2811 GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
2812 else
2813 ha->cmd_len =
2814 GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
2815 } else if (cmdp->Service == SCSIRAWSERVICE) {
2816 TRACE2(("raw command %d\n",cmdp->OpCode));
2817 if (ha->raw_feat & GDT_64BIT)
2818 ha->cmd_len =
2819 GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
2820 else
2821 ha->cmd_len =
2822 GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
2823 }
2824
2825 if (ha->cmd_len & 3)
2826 ha->cmd_len += (4 - (ha->cmd_len & 3));
2827
2828 if (ha->cmd_cnt > 0) {
2829 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2830 ha->ic_all_size) {
2831 TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
2832 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2833 return 0;
2834 }
2835 }
2836
2837 /* copy command */
2838 gdth_copy_command(ha);
2839 return cmd_index;
2840 }
2841
2842
2843 /* Controller event handling functions */
2844 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, u16 source,
2845 u16 idx, gdth_evt_data *evt)
2846 {
2847 gdth_evt_str *e;
2848 struct timeval tv;
2849
2850 /* no GDTH_LOCK_HA() ! */
2851 TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
2852 if (source == 0) /* no source -> no event */
2853 return NULL;
2854
2855 if (ebuffer[elastidx].event_source == source &&
2856 ebuffer[elastidx].event_idx == idx &&
2857 ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
2858 !memcmp((char *)&ebuffer[elastidx].event_data.eu,
2859 (char *)&evt->eu, evt->size)) ||
2860 (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
2861 !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
2862 (char *)&evt->event_string)))) {
2863 e = &ebuffer[elastidx];
2864 do_gettimeofday(&tv);
2865 e->last_stamp = tv.tv_sec;
2866 ++e->same_count;
2867 } else {
2868 if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
2869 ++elastidx;
2870 if (elastidx == MAX_EVENTS)
2871 elastidx = 0;
2872 if (elastidx == eoldidx) { /* reached mark ? */
2873 ++eoldidx;
2874 if (eoldidx == MAX_EVENTS)
2875 eoldidx = 0;
2876 }
2877 }
2878 e = &ebuffer[elastidx];
2879 e->event_source = source;
2880 e->event_idx = idx;
2881 do_gettimeofday(&tv);
2882 e->first_stamp = e->last_stamp = tv.tv_sec;
2883 e->same_count = 1;
2884 e->event_data = *evt;
2885 e->application = 0;
2886 }
2887 return e;
2888 }
2889
2890 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
2891 {
2892 gdth_evt_str *e;
2893 int eindex;
2894 unsigned long flags;
2895
2896 TRACE2(("gdth_read_event() handle %d\n", handle));
2897 spin_lock_irqsave(&ha->smp_lock, flags);
2898 if (handle == -1)
2899 eindex = eoldidx;
2900 else
2901 eindex = handle;
2902 estr->event_source = 0;
2903
2904 if (eindex < 0 || eindex >= MAX_EVENTS) {
2905 spin_unlock_irqrestore(&ha->smp_lock, flags);
2906 return eindex;
2907 }
2908 e = &ebuffer[eindex];
2909 if (e->event_source != 0) {
2910 if (eindex != elastidx) {
2911 if (++eindex == MAX_EVENTS)
2912 eindex = 0;
2913 } else {
2914 eindex = -1;
2915 }
2916 memcpy(estr, e, sizeof(gdth_evt_str));
2917 }
2918 spin_unlock_irqrestore(&ha->smp_lock, flags);
2919 return eindex;
2920 }
2921
2922 static void gdth_readapp_event(gdth_ha_str *ha,
2923 u8 application, gdth_evt_str *estr)
2924 {
2925 gdth_evt_str *e;
2926 int eindex;
2927 unsigned long flags;
2928 u8 found = FALSE;
2929
2930 TRACE2(("gdth_readapp_event() app. %d\n", application));
2931 spin_lock_irqsave(&ha->smp_lock, flags);
2932 eindex = eoldidx;
2933 for (;;) {
2934 e = &ebuffer[eindex];
2935 if (e->event_source == 0)
2936 break;
2937 if ((e->application & application) == 0) {
2938 e->application |= application;
2939 found = TRUE;
2940 break;
2941 }
2942 if (eindex == elastidx)
2943 break;
2944 if (++eindex == MAX_EVENTS)
2945 eindex = 0;
2946 }
2947 if (found)
2948 memcpy(estr, e, sizeof(gdth_evt_str));
2949 else
2950 estr->event_source = 0;
2951 spin_unlock_irqrestore(&ha->smp_lock, flags);
2952 }
2953
2954 static void gdth_clear_events(void)
2955 {
2956 TRACE(("gdth_clear_events()"));
2957
2958 eoldidx = elastidx = 0;
2959 ebuffer[0].event_source = 0;
2960 }
2961
2962
2963 /* SCSI interface functions */
2964
2965 static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
2966 int gdth_from_wait, int* pIndex)
2967 {
2968 gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
2969 gdt6_dpram_str __iomem *dp6_ptr;
2970 gdt2_dpram_str __iomem *dp2_ptr;
2971 Scsi_Cmnd *scp;
2972 int rval, i;
2973 u8 IStatus;
2974 u16 Service;
2975 unsigned long flags = 0;
2976 #ifdef INT_COAL
2977 int coalesced = FALSE;
2978 int next = FALSE;
2979 gdth_coal_status *pcs = NULL;
2980 int act_int_coal = 0;
2981 #endif
2982
2983 TRACE(("gdth_interrupt() IRQ %d\n", ha->irq));
2984
2985 /* if polling and not from gdth_wait() -> return */
2986 if (gdth_polling) {
2987 if (!gdth_from_wait) {
2988 return IRQ_HANDLED;
2989 }
2990 }
2991
2992 if (!gdth_polling)
2993 spin_lock_irqsave(&ha->smp_lock, flags);
2994
2995 /* search controller */
2996 IStatus = gdth_get_status(ha);
2997 if (IStatus == 0) {
2998 /* spurious interrupt */
2999 if (!gdth_polling)
3000 spin_unlock_irqrestore(&ha->smp_lock, flags);
3001 return IRQ_HANDLED;
3002 }
3003
3004 #ifdef GDTH_STATISTICS
3005 ++act_ints;
3006 #endif
3007
3008 #ifdef INT_COAL
3009 /* See if the fw is returning coalesced status */
3010 if (IStatus == COALINDEX) {
3011 /* Coalesced status. Setup the initial status
3012 buffer pointer and flags */
3013 pcs = ha->coal_stat;
3014 coalesced = TRUE;
3015 next = TRUE;
3016 }
3017
3018 do {
3019 if (coalesced) {
3020 /* For coalesced requests all status
3021 information is found in the status buffer */
3022 IStatus = (u8)(pcs->status & 0xff);
3023 }
3024 #endif
3025
3026 if (ha->type == GDT_EISA) {
3027 if (IStatus & 0x80) { /* error flag */
3028 IStatus &= ~0x80;
3029 ha->status = inw(ha->bmic + MAILBOXREG+8);
3030 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3031 } else /* no error */
3032 ha->status = S_OK;
3033 ha->info = inl(ha->bmic + MAILBOXREG+12);
3034 ha->service = inw(ha->bmic + MAILBOXREG+10);
3035 ha->info2 = inl(ha->bmic + MAILBOXREG+4);
3036
3037 outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
3038 outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
3039 } else if (ha->type == GDT_ISA) {
3040 dp2_ptr = ha->brd;
3041 if (IStatus & 0x80) { /* error flag */
3042 IStatus &= ~0x80;
3043 ha->status = readw(&dp2_ptr->u.ic.Status);
3044 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3045 } else /* no error */
3046 ha->status = S_OK;
3047 ha->info = readl(&dp2_ptr->u.ic.Info[0]);
3048 ha->service = readw(&dp2_ptr->u.ic.Service);
3049 ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
3050
3051 writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
3052 writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
3053 writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
3054 } else if (ha->type == GDT_PCI) {
3055 dp6_ptr = ha->brd;
3056 if (IStatus & 0x80) { /* error flag */
3057 IStatus &= ~0x80;
3058 ha->status = readw(&dp6_ptr->u.ic.Status);
3059 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3060 } else /* no error */
3061 ha->status = S_OK;
3062 ha->info = readl(&dp6_ptr->u.ic.Info[0]);
3063 ha->service = readw(&dp6_ptr->u.ic.Service);
3064 ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
3065
3066 writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
3067 writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
3068 writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
3069 } else if (ha->type == GDT_PCINEW) {
3070 if (IStatus & 0x80) { /* error flag */
3071 IStatus &= ~0x80;
3072 ha->status = inw(PTR2USHORT(&ha->plx->status));
3073 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3074 } else
3075 ha->status = S_OK;
3076 ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
3077 ha->service = inw(PTR2USHORT(&ha->plx->service));
3078 ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
3079
3080 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
3081 outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
3082 } else if (ha->type == GDT_PCIMPR) {
3083 dp6m_ptr = ha->brd;
3084 if (IStatus & 0x80) { /* error flag */
3085 IStatus &= ~0x80;
3086 #ifdef INT_COAL
3087 if (coalesced)
3088 ha->status = pcs->ext_status & 0xffff;
3089 else
3090 #endif
3091 ha->status = readw(&dp6m_ptr->i960r.status);
3092 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3093 } else /* no error */
3094 ha->status = S_OK;
3095 #ifdef INT_COAL
3096 /* get information */
3097 if (coalesced) {
3098 ha->info = pcs->info0;
3099 ha->info2 = pcs->info1;
3100 ha->service = (pcs->ext_status >> 16) & 0xffff;
3101 } else
3102 #endif
3103 {
3104 ha->info = readl(&dp6m_ptr->i960r.info[0]);
3105 ha->service = readw(&dp6m_ptr->i960r.service);
3106 ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
3107 }
3108 /* event string */
3109 if (IStatus == ASYNCINDEX) {
3110 if (ha->service != SCREENSERVICE &&
3111 (ha->fw_vers & 0xff) >= 0x1a) {
3112 ha->dvr.severity = readb
3113 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
3114 for (i = 0; i < 256; ++i) {
3115 ha->dvr.event_string[i] = readb
3116 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
3117 if (ha->dvr.event_string[i] == 0)
3118 break;
3119 }
3120 }
3121 }
3122 #ifdef INT_COAL
3123 /* Make sure that non coalesced interrupts get cleared
3124 before being handled by gdth_async_event/gdth_sync_event */
3125 if (!coalesced)
3126 #endif
3127 {
3128 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3129 writeb(0, &dp6m_ptr->i960r.sema1_reg);
3130 }
3131 } else {
3132 TRACE2(("gdth_interrupt() unknown controller type\n"));
3133 if (!gdth_polling)
3134 spin_unlock_irqrestore(&ha->smp_lock, flags);
3135 return IRQ_HANDLED;
3136 }
3137
3138 TRACE(("gdth_interrupt() index %d stat %d info %d\n",
3139 IStatus,ha->status,ha->info));
3140
3141 if (gdth_from_wait) {
3142 *pIndex = (int)IStatus;
3143 }
3144
3145 if (IStatus == ASYNCINDEX) {
3146 TRACE2(("gdth_interrupt() async. event\n"));
3147 gdth_async_event(ha);
3148 if (!gdth_polling)
3149 spin_unlock_irqrestore(&ha->smp_lock, flags);
3150 gdth_next(ha);
3151 return IRQ_HANDLED;
3152 }
3153
3154 if (IStatus == SPEZINDEX) {
3155 TRACE2(("Service unknown or not initialized !\n"));
3156 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3157 ha->dvr.eu.driver.ionode = ha->hanum;
3158 gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
3159 if (!gdth_polling)
3160 spin_unlock_irqrestore(&ha->smp_lock, flags);
3161 return IRQ_HANDLED;
3162 }
3163 scp = ha->cmd_tab[IStatus-2].cmnd;
3164 Service = ha->cmd_tab[IStatus-2].service;
3165 ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
3166 if (scp == UNUSED_CMND) {
3167 TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
3168 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3169 ha->dvr.eu.driver.ionode = ha->hanum;
3170 ha->dvr.eu.driver.index = IStatus;
3171 gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
3172 if (!gdth_polling)
3173 spin_unlock_irqrestore(&ha->smp_lock, flags);
3174 return IRQ_HANDLED;
3175 }
3176 if (scp == INTERNAL_CMND) {
3177 TRACE(("gdth_interrupt() answer to internal command\n"));
3178 if (!gdth_polling)
3179 spin_unlock_irqrestore(&ha->smp_lock, flags);
3180 return IRQ_HANDLED;
3181 }
3182
3183 TRACE(("gdth_interrupt() sync. status\n"));
3184 rval = gdth_sync_event(ha,Service,IStatus,scp);
3185 if (!gdth_polling)
3186 spin_unlock_irqrestore(&ha->smp_lock, flags);
3187 if (rval == 2) {
3188 gdth_putq(ha, scp, gdth_cmnd_priv(scp)->priority);
3189 } else if (rval == 1) {
3190 gdth_scsi_done(scp);
3191 }
3192
3193 #ifdef INT_COAL
3194 if (coalesced) {
3195 /* go to the next status in the status buffer */
3196 ++pcs;
3197 #ifdef GDTH_STATISTICS
3198 ++act_int_coal;
3199 if (act_int_coal > max_int_coal) {
3200 max_int_coal = act_int_coal;
3201 printk("GDT: max_int_coal = %d\n",(u16)max_int_coal);
3202 }
3203 #endif
3204 /* see if there is another status */
3205 if (pcs->status == 0)
3206 /* Stop the coalesce loop */
3207 next = FALSE;
3208 }
3209 } while (next);
3210
3211 /* coalescing only for new GDT_PCIMPR controllers available */
3212 if (ha->type == GDT_PCIMPR && coalesced) {
3213 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3214 writeb(0, &dp6m_ptr->i960r.sema1_reg);
3215 }
3216 #endif
3217
3218 gdth_next(ha);
3219 return IRQ_HANDLED;
3220 }
3221
3222 static irqreturn_t gdth_interrupt(int irq, void *dev_id)
3223 {
3224 gdth_ha_str *ha = dev_id;
3225
3226 return __gdth_interrupt(ha, false, NULL);
3227 }
3228
3229 static int gdth_sync_event(gdth_ha_str *ha, int service, u8 index,
3230 Scsi_Cmnd *scp)
3231 {
3232 gdth_msg_str *msg;
3233 gdth_cmd_str *cmdp;
3234 u8 b, t;
3235 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
3236
3237 cmdp = ha->pccb;
3238 TRACE(("gdth_sync_event() serv %d status %d\n",
3239 service,ha->status));
3240
3241 if (service == SCREENSERVICE) {
3242 msg = ha->pmsg;
3243 TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
3244 msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
3245 if (msg->msg_len > MSGLEN+1)
3246 msg->msg_len = MSGLEN+1;
3247 if (msg->msg_len)
3248 if (!(msg->msg_answer && msg->msg_ext)) {
3249 msg->msg_text[msg->msg_len] = '\0';
3250 printk("%s",msg->msg_text);
3251 }
3252
3253 if (msg->msg_ext && !msg->msg_answer) {
3254 while (gdth_test_busy(ha))
3255 gdth_delay(0);
3256 cmdp->Service = SCREENSERVICE;
3257 cmdp->RequestBuffer = SCREEN_CMND;
3258 gdth_get_cmd_index(ha);
3259 gdth_set_sema0(ha);
3260 cmdp->OpCode = GDT_READ;
3261 cmdp->BoardNode = LOCALBOARD;
3262 cmdp->u.screen.reserved = 0;
3263 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3264 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3265 ha->cmd_offs_dpmem = 0;
3266 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3267 + sizeof(u64);
3268 ha->cmd_cnt = 0;
3269 gdth_copy_command(ha);
3270 gdth_release_event(ha);
3271 return 0;
3272 }
3273
3274 if (msg->msg_answer && msg->msg_alen) {
3275 /* default answers (getchar() not possible) */
3276 if (msg->msg_alen == 1) {
3277 msg->msg_alen = 0;
3278 msg->msg_len = 1;
3279 msg->msg_text[0] = 0;
3280 } else {
3281 msg->msg_alen -= 2;
3282 msg->msg_len = 2;
3283 msg->msg_text[0] = 1;
3284 msg->msg_text[1] = 0;
3285 }
3286 msg->msg_ext = 0;
3287 msg->msg_answer = 0;
3288 while (gdth_test_busy(ha))
3289 gdth_delay(0);
3290 cmdp->Service = SCREENSERVICE;
3291 cmdp->RequestBuffer = SCREEN_CMND;
3292 gdth_get_cmd_index(ha);
3293 gdth_set_sema0(ha);
3294 cmdp->OpCode = GDT_WRITE;
3295 cmdp->BoardNode = LOCALBOARD;
3296 cmdp->u.screen.reserved = 0;
3297 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3298 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3299 ha->cmd_offs_dpmem = 0;
3300 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3301 + sizeof(u64);
3302 ha->cmd_cnt = 0;
3303 gdth_copy_command(ha);
3304 gdth_release_event(ha);
3305 return 0;
3306 }
3307 printk("\n");
3308
3309 } else {
3310 b = scp->device->channel;
3311 t = scp->device->id;
3312 if (cmndinfo->OpCode == -1 && b != ha->virt_bus) {
3313 ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
3314 }
3315 /* cache or raw service */
3316 if (ha->status == S_BSY) {
3317 TRACE2(("Controller busy -> retry !\n"));
3318 if (cmndinfo->OpCode == GDT_MOUNT)
3319 cmndinfo->OpCode = GDT_CLUST_INFO;
3320 /* retry */
3321 return 2;
3322 }
3323 if (scsi_bufflen(scp))
3324 pci_unmap_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
3325 cmndinfo->dma_dir);
3326
3327 if (cmndinfo->sense_paddr)
3328 pci_unmap_page(ha->pdev, cmndinfo->sense_paddr, 16,
3329 PCI_DMA_FROMDEVICE);
3330
3331 if (ha->status == S_OK) {
3332 cmndinfo->status = S_OK;
3333 cmndinfo->info = ha->info;
3334 if (cmndinfo->OpCode != -1) {
3335 TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
3336 cmndinfo->OpCode));
3337 /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
3338 if (cmndinfo->OpCode == GDT_CLUST_INFO) {
3339 ha->hdr[t].cluster_type = (u8)ha->info;
3340 if (!(ha->hdr[t].cluster_type &
3341 CLUSTER_MOUNTED)) {
3342 /* NOT MOUNTED -> MOUNT */
3343 cmndinfo->OpCode = GDT_MOUNT;
3344 if (ha->hdr[t].cluster_type &
3345 CLUSTER_RESERVED) {
3346 /* cluster drive RESERVED (on the other node) */
3347 cmndinfo->phase = -2; /* reservation conflict */
3348 }
3349 } else {
3350 cmndinfo->OpCode = -1;
3351 }
3352 } else {
3353 if (cmndinfo->OpCode == GDT_MOUNT) {
3354 ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
3355 ha->hdr[t].media_changed = TRUE;
3356 } else if (cmndinfo->OpCode == GDT_UNMOUNT) {
3357 ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
3358 ha->hdr[t].media_changed = TRUE;
3359 }
3360 cmndinfo->OpCode = -1;
3361 }
3362 /* retry */
3363 cmndinfo->priority = HIGH_PRI;
3364 return 2;
3365 } else {
3366 /* RESERVE/RELEASE ? */
3367 if (scp->cmnd[0] == RESERVE) {
3368 ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
3369 } else if (scp->cmnd[0] == RELEASE) {
3370 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3371 }
3372 scp->result = DID_OK << 16;
3373 scp->sense_buffer[0] = 0;
3374 }
3375 } else {
3376 cmndinfo->status = ha->status;
3377 cmndinfo->info = ha->info;
3378
3379 if (cmndinfo->OpCode != -1) {
3380 TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
3381 cmndinfo->OpCode, ha->status));
3382 if (cmndinfo->OpCode == GDT_SCAN_START ||
3383 cmndinfo->OpCode == GDT_SCAN_END) {
3384 cmndinfo->OpCode = -1;
3385 /* retry */
3386 cmndinfo->priority = HIGH_PRI;
3387 return 2;
3388 }
3389 memset((char*)scp->sense_buffer,0,16);
3390 scp->sense_buffer[0] = 0x70;
3391 scp->sense_buffer[2] = NOT_READY;
3392 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3393 } else if (service == CACHESERVICE) {
3394 if (ha->status == S_CACHE_UNKNOWN &&
3395 (ha->hdr[t].cluster_type &
3396 CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
3397 /* bus reset -> force GDT_CLUST_INFO */
3398 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3399 }
3400 memset((char*)scp->sense_buffer,0,16);
3401 if (ha->status == (u16)S_CACHE_RESERV) {
3402 scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
3403 } else {
3404 scp->sense_buffer[0] = 0x70;
3405 scp->sense_buffer[2] = NOT_READY;
3406 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3407 }
3408 if (!cmndinfo->internal_command) {
3409 ha->dvr.size = sizeof(ha->dvr.eu.sync);
3410 ha->dvr.eu.sync.ionode = ha->hanum;
3411 ha->dvr.eu.sync.service = service;
3412 ha->dvr.eu.sync.status = ha->status;
3413 ha->dvr.eu.sync.info = ha->info;
3414 ha->dvr.eu.sync.hostdrive = t;
3415 if (ha->status >= 0x8000)
3416 gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
3417 else
3418 gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
3419 }
3420 } else {
3421 /* sense buffer filled from controller firmware (DMA) */
3422 if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
3423 scp->result = DID_BAD_TARGET << 16;
3424 } else {
3425 scp->result = (DID_OK << 16) | ha->info;
3426 }
3427 }
3428 }
3429 if (!cmndinfo->wait_for_completion)
3430 cmndinfo->wait_for_completion++;
3431 else
3432 return 1;
3433 }
3434
3435 return 0;
3436 }
3437
3438 static char *async_cache_tab[] = {
3439 /* 0*/ "\011\000\002\002\002\004\002\006\004"
3440 "GDT HA %u, service %u, async. status %u/%lu unknown",
3441 /* 1*/ "\011\000\002\002\002\004\002\006\004"
3442 "GDT HA %u, service %u, async. status %u/%lu unknown",
3443 /* 2*/ "\005\000\002\006\004"
3444 "GDT HA %u, Host Drive %lu not ready",
3445 /* 3*/ "\005\000\002\006\004"
3446 "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3447 /* 4*/ "\005\000\002\006\004"
3448 "GDT HA %u, mirror update on Host Drive %lu failed",
3449 /* 5*/ "\005\000\002\006\004"
3450 "GDT HA %u, Mirror Drive %lu failed",
3451 /* 6*/ "\005\000\002\006\004"
3452 "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3453 /* 7*/ "\005\000\002\006\004"
3454 "GDT HA %u, Host Drive %lu write protected",
3455 /* 8*/ "\005\000\002\006\004"
3456 "GDT HA %u, media changed in Host Drive %lu",
3457 /* 9*/ "\005\000\002\006\004"
3458 "GDT HA %u, Host Drive %lu is offline",
3459 /*10*/ "\005\000\002\006\004"
3460 "GDT HA %u, media change of Mirror Drive %lu",
3461 /*11*/ "\005\000\002\006\004"
3462 "GDT HA %u, Mirror Drive %lu is write protected",
3463 /*12*/ "\005\000\002\006\004"
3464 "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
3465 /*13*/ "\007\000\002\006\002\010\002"
3466 "GDT HA %u, Array Drive %u: Cache Drive %u failed",
3467 /*14*/ "\005\000\002\006\002"
3468 "GDT HA %u, Array Drive %u: FAIL state entered",
3469 /*15*/ "\005\000\002\006\002"
3470 "GDT HA %u, Array Drive %u: error",
3471 /*16*/ "\007\000\002\006\002\010\002"
3472 "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
3473 /*17*/ "\005\000\002\006\002"
3474 "GDT HA %u, Array Drive %u: parity build failed",
3475 /*18*/ "\005\000\002\006\002"
3476 "GDT HA %u, Array Drive %u: drive rebuild failed",
3477 /*19*/ "\005\000\002\010\002"
3478 "GDT HA %u, Test of Hot Fix %u failed",
3479 /*20*/ "\005\000\002\006\002"
3480 "GDT HA %u, Array Drive %u: drive build finished successfully",
3481 /*21*/ "\005\000\002\006\002"
3482 "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
3483 /*22*/ "\007\000\002\006\002\010\002"
3484 "GDT HA %u, Array Drive %u: Hot Fix %u activated",
3485 /*23*/ "\005\000\002\006\002"
3486 "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
3487 /*24*/ "\005\000\002\010\002"
3488 "GDT HA %u, mirror update on Cache Drive %u completed",
3489 /*25*/ "\005\000\002\010\002"
3490 "GDT HA %u, mirror update on Cache Drive %lu failed",
3491 /*26*/ "\005\000\002\006\002"
3492 "GDT HA %u, Array Drive %u: drive rebuild started",
3493 /*27*/ "\005\000\002\012\001"
3494 "GDT HA %u, Fault bus %u: SHELF OK detected",
3495 /*28*/ "\005\000\002\012\001"
3496 "GDT HA %u, Fault bus %u: SHELF not OK detected",
3497 /*29*/ "\007\000\002\012\001\013\001"
3498 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
3499 /*30*/ "\007\000\002\012\001\013\001"
3500 "GDT HA %u, Fault bus %u, ID %u: new disk detected",
3501 /*31*/ "\007\000\002\012\001\013\001"
3502 "GDT HA %u, Fault bus %u, ID %u: old disk detected",
3503 /*32*/ "\007\000\002\012\001\013\001"
3504 "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
3505 /*33*/ "\007\000\002\012\001\013\001"
3506 "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
3507 /*34*/ "\011\000\002\012\001\013\001\006\004"
3508 "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
3509 /*35*/ "\007\000\002\012\001\013\001"
3510 "GDT HA %u, Fault bus %u, ID %u: disk write protected",
3511 /*36*/ "\007\000\002\012\001\013\001"
3512 "GDT HA %u, Fault bus %u, ID %u: disk not available",
3513 /*37*/ "\007\000\002\012\001\006\004"
3514 "GDT HA %u, Fault bus %u: swap detected (%lu)",
3515 /*38*/ "\007\000\002\012\001\013\001"
3516 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
3517 /*39*/ "\007\000\002\012\001\013\001"
3518 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
3519 /*40*/ "\007\000\002\012\001\013\001"
3520 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
3521 /*41*/ "\007\000\002\012\001\013\001"
3522 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
3523 /*42*/ "\005\000\002\006\002"
3524 "GDT HA %u, Array Drive %u: drive build started",
3525 /*43*/ "\003\000\002"
3526 "GDT HA %u, DRAM parity error detected",
3527 /*44*/ "\005\000\002\006\002"
3528 "GDT HA %u, Mirror Drive %u: update started",
3529 /*45*/ "\007\000\002\006\002\010\002"
3530 "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
3531 /*46*/ "\005\000\002\006\002"
3532 "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
3533 /*47*/ "\005\000\002\006\002"
3534 "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
3535 /*48*/ "\005\000\002\006\002"
3536 "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
3537 /*49*/ "\005\000\002\006\002"
3538 "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
3539 /*50*/ "\007\000\002\012\001\013\001"
3540 "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
3541 /*51*/ "\005\000\002\006\002"
3542 "GDT HA %u, Array Drive %u: expand started",
3543 /*52*/ "\005\000\002\006\002"
3544 "GDT HA %u, Array Drive %u: expand finished successfully",
3545 /*53*/ "\005\000\002\006\002"
3546 "GDT HA %u, Array Drive %u: expand failed",
3547 /*54*/ "\003\000\002"
3548 "GDT HA %u, CPU temperature critical",
3549 /*55*/ "\003\000\002"
3550 "GDT HA %u, CPU temperature OK",
3551 /*56*/ "\005\000\002\006\004"
3552 "GDT HA %u, Host drive %lu created",
3553 /*57*/ "\005\000\002\006\002"
3554 "GDT HA %u, Array Drive %u: expand restarted",
3555 /*58*/ "\005\000\002\006\002"
3556 "GDT HA %u, Array Drive %u: expand stopped",
3557 /*59*/ "\005\000\002\010\002"
3558 "GDT HA %u, Mirror Drive %u: drive build quited",
3559 /*60*/ "\005\000\002\006\002"
3560 "GDT HA %u, Array Drive %u: parity build quited",
3561 /*61*/ "\005\000\002\006\002"
3562 "GDT HA %u, Array Drive %u: drive rebuild quited",
3563 /*62*/ "\005\000\002\006\002"
3564 "GDT HA %u, Array Drive %u: parity verify started",
3565 /*63*/ "\005\000\002\006\002"
3566 "GDT HA %u, Array Drive %u: parity verify done",
3567 /*64*/ "\005\000\002\006\002"
3568 "GDT HA %u, Array Drive %u: parity verify failed",
3569 /*65*/ "\005\000\002\006\002"
3570 "GDT HA %u, Array Drive %u: parity error detected",
3571 /*66*/ "\005\000\002\006\002"
3572 "GDT HA %u, Array Drive %u: parity verify quited",
3573 /*67*/ "\005\000\002\006\002"
3574 "GDT HA %u, Host Drive %u reserved",
3575 /*68*/ "\005\000\002\006\002"
3576 "GDT HA %u, Host Drive %u mounted and released",
3577 /*69*/ "\005\000\002\006\002"
3578 "GDT HA %u, Host Drive %u released",
3579 /*70*/ "\003\000\002"
3580 "GDT HA %u, DRAM error detected and corrected with ECC",
3581 /*71*/ "\003\000\002"
3582 "GDT HA %u, Uncorrectable DRAM error detected with ECC",
3583 /*72*/ "\011\000\002\012\001\013\001\014\001"
3584 "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
3585 /*73*/ "\005\000\002\006\002"
3586 "GDT HA %u, Host drive %u resetted locally",
3587 /*74*/ "\005\000\002\006\002"
3588 "GDT HA %u, Host drive %u resetted remotely",
3589 /*75*/ "\003\000\002"
3590 "GDT HA %u, async. status 75 unknown",
3591 };
3592
3593
3594 static int gdth_async_event(gdth_ha_str *ha)
3595 {
3596 gdth_cmd_str *cmdp;
3597 int cmd_index;
3598
3599 cmdp= ha->pccb;
3600 TRACE2(("gdth_async_event() ha %d serv %d\n",
3601 ha->hanum, ha->service));
3602
3603 if (ha->service == SCREENSERVICE) {
3604 if (ha->status == MSG_REQUEST) {
3605 while (gdth_test_busy(ha))
3606 gdth_delay(0);
3607 cmdp->Service = SCREENSERVICE;
3608 cmdp->RequestBuffer = SCREEN_CMND;
3609 cmd_index = gdth_get_cmd_index(ha);
3610 gdth_set_sema0(ha);
3611 cmdp->OpCode = GDT_READ;
3612 cmdp->BoardNode = LOCALBOARD;
3613 cmdp->u.screen.reserved = 0;
3614 cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
3615 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3616 ha->cmd_offs_dpmem = 0;
3617 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3618 + sizeof(u64);
3619 ha->cmd_cnt = 0;
3620 gdth_copy_command(ha);
3621 if (ha->type == GDT_EISA)
3622 printk("[EISA slot %d] ",(u16)ha->brd_phys);
3623 else if (ha->type == GDT_ISA)
3624 printk("[DPMEM 0x%4X] ",(u16)ha->brd_phys);
3625 else
3626 printk("[PCI %d/%d] ",(u16)(ha->brd_phys>>8),
3627 (u16)((ha->brd_phys>>3)&0x1f));
3628 gdth_release_event(ha);
3629 }
3630
3631 } else {
3632 if (ha->type == GDT_PCIMPR &&
3633 (ha->fw_vers & 0xff) >= 0x1a) {
3634 ha->dvr.size = 0;
3635 ha->dvr.eu.async.ionode = ha->hanum;
3636 ha->dvr.eu.async.status = ha->status;
3637 /* severity and event_string already set! */
3638 } else {
3639 ha->dvr.size = sizeof(ha->dvr.eu.async);
3640 ha->dvr.eu.async.ionode = ha->hanum;
3641 ha->dvr.eu.async.service = ha->service;
3642 ha->dvr.eu.async.status = ha->status;
3643 ha->dvr.eu.async.info = ha->info;
3644 *(u32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
3645 }
3646 gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
3647 gdth_log_event( &ha->dvr, NULL );
3648
3649 /* new host drive from expand? */
3650 if (ha->service == CACHESERVICE && ha->status == 56) {
3651 TRACE2(("gdth_async_event(): new host drive %d created\n",
3652 (u16)ha->info));
3653 /* gdth_analyse_hdrive(hanum, (u16)ha->info); */
3654 }
3655 }
3656 return 1;
3657 }
3658
3659 static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
3660 {
3661 gdth_stackframe stack;
3662 char *f = NULL;
3663 int i,j;
3664
3665 TRACE2(("gdth_log_event()\n"));
3666 if (dvr->size == 0) {
3667 if (buffer == NULL) {
3668 printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
3669 } else {
3670 sprintf(buffer,"Adapter %d: %s\n",
3671 dvr->eu.async.ionode,dvr->event_string);
3672 }
3673 } else if (dvr->eu.async.service == CACHESERVICE &&
3674 INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
3675 TRACE2(("GDT: Async. event cache service, event no.: %d\n",
3676 dvr->eu.async.status));
3677
3678 f = async_cache_tab[dvr->eu.async.status];
3679
3680 /* i: parameter to push, j: stack element to fill */
3681 for (j=0,i=1; i < f[0]; i+=2) {
3682 switch (f[i+1]) {
3683 case 4:
3684 stack.b[j++] = *(u32*)&dvr->eu.stream[(int)f[i]];
3685 break;
3686 case 2:
3687 stack.b[j++] = *(u16*)&dvr->eu.stream[(int)f[i]];
3688 break;
3689 case 1:
3690 stack.b[j++] = *(u8*)&dvr->eu.stream[(int)f[i]];
3691 break;
3692 default:
3693 break;
3694 }
3695 }
3696
3697 if (buffer == NULL) {
3698 printk(&f[(int)f[0]],stack);
3699 printk("\n");
3700 } else {
3701 sprintf(buffer,&f[(int)f[0]],stack);
3702 }
3703
3704 } else {
3705 if (buffer == NULL) {
3706 printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
3707 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
3708 } else {
3709 sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
3710 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
3711 }
3712 }
3713 }
3714
3715 #ifdef GDTH_STATISTICS
3716 static u8 gdth_timer_running;
3717
3718 static void gdth_timeout(unsigned long data)
3719 {
3720 u32 i;
3721 Scsi_Cmnd *nscp;
3722 gdth_ha_str *ha;
3723 unsigned long flags;
3724
3725 if(unlikely(list_empty(&gdth_instances))) {
3726 gdth_timer_running = 0;
3727 return;
3728 }
3729
3730 ha = list_first_entry(&gdth_instances, gdth_ha_str, list);
3731 spin_lock_irqsave(&ha->smp_lock, flags);
3732
3733 for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
3734 if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
3735 ++act_stats;
3736
3737 for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
3738 ++act_rq;
3739
3740 TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
3741 act_ints, act_ios, act_stats, act_rq));
3742 act_ints = act_ios = 0;
3743
3744 gdth_timer.expires = jiffies + 30 * HZ;
3745 add_timer(&gdth_timer);
3746 spin_unlock_irqrestore(&ha->smp_lock, flags);
3747 }
3748
3749 static void gdth_timer_init(void)
3750 {
3751 if (gdth_timer_running)
3752 return;
3753 gdth_timer_running = 1;
3754 TRACE2(("gdth_detect(): Initializing timer !\n"));
3755 gdth_timer.expires = jiffies + HZ;
3756 gdth_timer.data = 0L;
3757 gdth_timer.function = gdth_timeout;
3758 add_timer(&gdth_timer);
3759 }
3760 #else
3761 static inline void gdth_timer_init(void)
3762 {
3763 }
3764 #endif
3765
3766 static void __init internal_setup(char *str,int *ints)
3767 {
3768 int i, argc;
3769 char *cur_str, *argv;
3770
3771 TRACE2(("internal_setup() str %s ints[0] %d\n",
3772 str ? str:"NULL", ints ? ints[0]:0));
3773
3774 /* read irq[] from ints[] */
3775 if (ints) {
3776 argc = ints[0];
3777 if (argc > 0) {
3778 if (argc > MAXHA)
3779 argc = MAXHA;
3780 for (i = 0; i < argc; ++i)
3781 irq[i] = ints[i+1];
3782 }
3783 }
3784
3785 /* analyse string */
3786 argv = str;
3787 while (argv && (cur_str = strchr(argv, ':'))) {
3788 int val = 0, c = *++cur_str;
3789
3790 if (c == 'n' || c == 'N')
3791 val = 0;
3792 else if (c == 'y' || c == 'Y')
3793 val = 1;
3794 else
3795 val = (int)simple_strtoul(cur_str, NULL, 0);
3796
3797 if (!strncmp(argv, "disable:", 8))
3798 disable = val;
3799 else if (!strncmp(argv, "reserve_mode:", 13))
3800 reserve_mode = val;
3801 else if (!strncmp(argv, "reverse_scan:", 13))
3802 reverse_scan = val;
3803 else if (!strncmp(argv, "hdr_channel:", 12))
3804 hdr_channel = val;
3805 else if (!strncmp(argv, "max_ids:", 8))
3806 max_ids = val;
3807 else if (!strncmp(argv, "rescan:", 7))
3808 rescan = val;
3809 else if (!strncmp(argv, "shared_access:", 14))
3810 shared_access = val;
3811 else if (!strncmp(argv, "probe_eisa_isa:", 15))
3812 probe_eisa_isa = val;
3813 else if (!strncmp(argv, "reserve_list:", 13)) {
3814 reserve_list[0] = val;
3815 for (i = 1; i < MAX_RES_ARGS; i++) {
3816 cur_str = strchr(cur_str, ',');
3817 if (!cur_str)
3818 break;
3819 if (!isdigit((int)*++cur_str)) {
3820 --cur_str;
3821 break;
3822 }
3823 reserve_list[i] =
3824 (int)simple_strtoul(cur_str, NULL, 0);
3825 }
3826 if (!cur_str)
3827 break;
3828 argv = ++cur_str;
3829 continue;
3830 }
3831
3832 if ((argv = strchr(argv, ',')))
3833 ++argv;
3834 }
3835 }
3836
3837 int __init option_setup(char *str)
3838 {
3839 int ints[MAXHA];
3840 char *cur = str;
3841 int i = 1;
3842
3843 TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
3844
3845 while (cur && isdigit(*cur) && i < MAXHA) {
3846 ints[i++] = simple_strtoul(cur, NULL, 0);
3847 if ((cur = strchr(cur, ',')) != NULL) cur++;
3848 }
3849
3850 ints[0] = i - 1;
3851 internal_setup(cur, ints);
3852 return 1;
3853 }
3854
3855 static const char *gdth_ctr_name(gdth_ha_str *ha)
3856 {
3857 TRACE2(("gdth_ctr_name()\n"));
3858
3859 if (ha->type == GDT_EISA) {
3860 switch (ha->stype) {
3861 case GDT3_ID:
3862 return("GDT3000/3020");
3863 case GDT3A_ID:
3864 return("GDT3000A/3020A/3050A");
3865 case GDT3B_ID:
3866 return("GDT3000B/3010A");
3867 }
3868 } else if (ha->type == GDT_ISA) {
3869 return("GDT2000/2020");
3870 } else if (ha->type == GDT_PCI) {
3871 switch (ha->pdev->device) {
3872 case PCI_DEVICE_ID_VORTEX_GDT60x0:
3873 return("GDT6000/6020/6050");
3874 case PCI_DEVICE_ID_VORTEX_GDT6000B:
3875 return("GDT6000B/6010");
3876 }
3877 }
3878 /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
3879
3880 return("");
3881 }
3882
3883 static const char *gdth_info(struct Scsi_Host *shp)
3884 {
3885 gdth_ha_str *ha = shost_priv(shp);
3886
3887 TRACE2(("gdth_info()\n"));
3888 return ((const char *)ha->binfo.type_string);
3889 }
3890
3891 static enum blk_eh_timer_return gdth_timed_out(struct scsi_cmnd *scp)
3892 {
3893 gdth_ha_str *ha = shost_priv(scp->device->host);
3894 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
3895 u8 b, t;
3896 unsigned long flags;
3897 enum blk_eh_timer_return retval = BLK_EH_NOT_HANDLED;
3898
3899 TRACE(("%s() cmd 0x%x\n", scp->cmnd[0], __func__));
3900 b = scp->device->channel;
3901 t = scp->device->id;
3902
3903 /*
3904 * We don't really honor the command timeout, but we try to
3905 * honor 6 times of the actual command timeout! So reset the
3906 * timer if this is less than 6th timeout on this command!
3907 */
3908 if (++cmndinfo->timeout_count < 6)
3909 retval = BLK_EH_RESET_TIMER;
3910
3911 /* Reset the timeout if it is locked IO */
3912 spin_lock_irqsave(&ha->smp_lock, flags);
3913 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha, b)].lock) ||
3914 (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock)) {
3915 TRACE2(("%s(): locked IO, reset timeout\n", __func__));
3916 retval = BLK_EH_RESET_TIMER;
3917 }
3918 spin_unlock_irqrestore(&ha->smp_lock, flags);
3919
3920 return retval;
3921 }
3922
3923
3924 static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
3925 {
3926 gdth_ha_str *ha = shost_priv(scp->device->host);
3927 int i;
3928 unsigned long flags;
3929 Scsi_Cmnd *cmnd;
3930 u8 b;
3931
3932 TRACE2(("gdth_eh_bus_reset()\n"));
3933
3934 b = scp->device->channel;
3935
3936 /* clear command tab */
3937 spin_lock_irqsave(&ha->smp_lock, flags);
3938 for (i = 0; i < GDTH_MAXCMDS; ++i) {
3939 cmnd = ha->cmd_tab[i].cmnd;
3940 if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
3941 ha->cmd_tab[i].cmnd = UNUSED_CMND;
3942 }
3943 spin_unlock_irqrestore(&ha->smp_lock, flags);
3944
3945 if (b == ha->virt_bus) {
3946 /* host drives */
3947 for (i = 0; i < MAX_HDRIVES; ++i) {
3948 if (ha->hdr[i].present) {
3949 spin_lock_irqsave(&ha->smp_lock, flags);
3950 gdth_polling = TRUE;
3951 while (gdth_test_busy(ha))
3952 gdth_delay(0);
3953 if (gdth_internal_cmd(ha, CACHESERVICE,
3954 GDT_CLUST_RESET, i, 0, 0))
3955 ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
3956 gdth_polling = FALSE;
3957 spin_unlock_irqrestore(&ha->smp_lock, flags);
3958 }
3959 }
3960 } else {
3961 /* raw devices */
3962 spin_lock_irqsave(&ha->smp_lock, flags);
3963 for (i = 0; i < MAXID; ++i)
3964 ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
3965 gdth_polling = TRUE;
3966 while (gdth_test_busy(ha))
3967 gdth_delay(0);
3968 gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
3969 BUS_L2P(ha,b), 0, 0);
3970 gdth_polling = FALSE;
3971 spin_unlock_irqrestore(&ha->smp_lock, flags);
3972 }
3973 return SUCCESS;
3974 }
3975
3976 static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
3977 {
3978 u8 b, t;
3979 gdth_ha_str *ha = shost_priv(sdev->host);
3980 struct scsi_device *sd;
3981 unsigned capacity;
3982
3983 sd = sdev;
3984 capacity = cap;
3985 b = sd->channel;
3986 t = sd->id;
3987 TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
3988
3989 if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
3990 /* raw device or host drive without mapping information */
3991 TRACE2(("Evaluate mapping\n"));
3992 gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
3993 } else {
3994 ip[0] = ha->hdr[t].heads;
3995 ip[1] = ha->hdr[t].secs;
3996 ip[2] = capacity / ip[0] / ip[1];
3997 }
3998
3999 TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
4000 ip[0],ip[1],ip[2]));
4001 return 0;
4002 }
4003
4004
4005 static int gdth_queuecommand(struct scsi_cmnd *scp,
4006 void (*done)(struct scsi_cmnd *))
4007 {
4008 gdth_ha_str *ha = shost_priv(scp->device->host);
4009 struct gdth_cmndinfo *cmndinfo;
4010
4011 TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
4012
4013 cmndinfo = gdth_get_cmndinfo(ha);
4014 BUG_ON(!cmndinfo);
4015
4016 scp->scsi_done = done;
4017 cmndinfo->timeout_count = 0;
4018 cmndinfo->priority = DEFAULT_PRI;
4019
4020 return __gdth_queuecommand(ha, scp, cmndinfo);
4021 }
4022
4023 static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
4024 struct gdth_cmndinfo *cmndinfo)
4025 {
4026 scp->host_scribble = (unsigned char *)cmndinfo;
4027 cmndinfo->wait_for_completion = 1;
4028 cmndinfo->phase = -1;
4029 cmndinfo->OpCode = -1;
4030
4031 #ifdef GDTH_STATISTICS
4032 ++act_ios;
4033 #endif
4034
4035 gdth_putq(ha, scp, cmndinfo->priority);
4036 gdth_next(ha);
4037 return 0;
4038 }
4039
4040
4041 static int gdth_open(struct inode *inode, struct file *filep)
4042 {
4043 gdth_ha_str *ha;
4044
4045 lock_kernel();
4046 list_for_each_entry(ha, &gdth_instances, list) {
4047 if (!ha->sdev)
4048 ha->sdev = scsi_get_host_dev(ha->shost);
4049 }
4050 unlock_kernel();
4051
4052 TRACE(("gdth_open()\n"));
4053 return 0;
4054 }
4055
4056 static int gdth_close(struct inode *inode, struct file *filep)
4057 {
4058 TRACE(("gdth_close()\n"));
4059 return 0;
4060 }
4061
4062 static int ioc_event(void __user *arg)
4063 {
4064 gdth_ioctl_event evt;
4065 gdth_ha_str *ha;
4066 unsigned long flags;
4067
4068 if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)))
4069 return -EFAULT;
4070 ha = gdth_find_ha(evt.ionode);
4071 if (!ha)
4072 return -EFAULT;
4073
4074 if (evt.erase == 0xff) {
4075 if (evt.event.event_source == ES_TEST)
4076 evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
4077 else if (evt.event.event_source == ES_DRIVER)
4078 evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
4079 else if (evt.event.event_source == ES_SYNC)
4080 evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
4081 else
4082 evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
4083 spin_lock_irqsave(&ha->smp_lock, flags);
4084 gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
4085 &evt.event.event_data);
4086 spin_unlock_irqrestore(&ha->smp_lock, flags);
4087 } else if (evt.erase == 0xfe) {
4088 gdth_clear_events();
4089 } else if (evt.erase == 0) {
4090 evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
4091 } else {
4092 gdth_readapp_event(ha, evt.erase, &evt.event);
4093 }
4094 if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
4095 return -EFAULT;
4096 return 0;
4097 }
4098
4099 static int ioc_lockdrv(void __user *arg)
4100 {
4101 gdth_ioctl_lockdrv ldrv;
4102 u8 i, j;
4103 unsigned long flags;
4104 gdth_ha_str *ha;
4105
4106 if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)))
4107 return -EFAULT;
4108 ha = gdth_find_ha(ldrv.ionode);
4109 if (!ha)
4110 return -EFAULT;
4111
4112 for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
4113 j = ldrv.drives[i];
4114 if (j >= MAX_HDRIVES || !ha->hdr[j].present)
4115 continue;
4116 if (ldrv.lock) {
4117 spin_lock_irqsave(&ha->smp_lock, flags);
4118 ha->hdr[j].lock = 1;
4119 spin_unlock_irqrestore(&ha->smp_lock, flags);
4120 gdth_wait_completion(ha, ha->bus_cnt, j);
4121 } else {
4122 spin_lock_irqsave(&ha->smp_lock, flags);
4123 ha->hdr[j].lock = 0;
4124 spin_unlock_irqrestore(&ha->smp_lock, flags);
4125 gdth_next(ha);
4126 }
4127 }
4128 return 0;
4129 }
4130
4131 static int ioc_resetdrv(void __user *arg, char *cmnd)
4132 {
4133 gdth_ioctl_reset res;
4134 gdth_cmd_str cmd;
4135 gdth_ha_str *ha;
4136 int rval;
4137
4138 if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
4139 res.number >= MAX_HDRIVES)
4140 return -EFAULT;
4141 ha = gdth_find_ha(res.ionode);
4142 if (!ha)
4143 return -EFAULT;
4144
4145 if (!ha->hdr[res.number].present)
4146 return 0;
4147 memset(&cmd, 0, sizeof(gdth_cmd_str));
4148 cmd.Service = CACHESERVICE;
4149 cmd.OpCode = GDT_CLUST_RESET;
4150 if (ha->cache_feat & GDT_64BIT)
4151 cmd.u.cache64.DeviceNo = res.number;
4152 else
4153 cmd.u.cache.DeviceNo = res.number;
4154
4155 rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
4156 if (rval < 0)
4157 return rval;
4158 res.status = rval;
4159
4160 if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
4161 return -EFAULT;
4162 return 0;
4163 }
4164
4165 static int ioc_general(void __user *arg, char *cmnd)
4166 {
4167 gdth_ioctl_general gen;
4168 char *buf = NULL;
4169 u64 paddr;
4170 gdth_ha_str *ha;
4171 int rval;
4172
4173 if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
4174 return -EFAULT;
4175 ha = gdth_find_ha(gen.ionode);
4176 if (!ha)
4177 return -EFAULT;
4178
4179 if (gen.data_len > INT_MAX)
4180 return -EINVAL;
4181 if (gen.sense_len > INT_MAX)
4182 return -EINVAL;
4183 if (gen.data_len + gen.sense_len > INT_MAX)
4184 return -EINVAL;
4185
4186 if (gen.data_len + gen.sense_len != 0) {
4187 if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
4188 FALSE, &paddr)))
4189 return -EFAULT;
4190 if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
4191 gen.data_len + gen.sense_len)) {
4192 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4193 return -EFAULT;
4194 }
4195
4196 if (gen.command.OpCode == GDT_IOCTL) {
4197 gen.command.u.ioctl.p_param = paddr;
4198 } else if (gen.command.Service == CACHESERVICE) {
4199 if (ha->cache_feat & GDT_64BIT) {
4200 /* copy elements from 32-bit IOCTL structure */
4201 gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
4202 gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
4203 gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
4204 /* addresses */
4205 if (ha->cache_feat & SCATTER_GATHER) {
4206 gen.command.u.cache64.DestAddr = (u64)-1;
4207 gen.command.u.cache64.sg_canz = 1;
4208 gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
4209 gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
4210 gen.command.u.cache64.sg_lst[1].sg_len = 0;
4211 } else {
4212 gen.command.u.cache64.DestAddr = paddr;
4213 gen.command.u.cache64.sg_canz = 0;
4214 }
4215 } else {
4216 if (ha->cache_feat & SCATTER_GATHER) {
4217 gen.command.u.cache.DestAddr = 0xffffffff;
4218 gen.command.u.cache.sg_canz = 1;
4219 gen.command.u.cache.sg_lst[0].sg_ptr = (u32)paddr;
4220 gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
4221 gen.command.u.cache.sg_lst[1].sg_len = 0;
4222 } else {
4223 gen.command.u.cache.DestAddr = paddr;
4224 gen.command.u.cache.sg_canz = 0;
4225 }
4226 }
4227 } else if (gen.command.Service == SCSIRAWSERVICE) {
4228 if (ha->raw_feat & GDT_64BIT) {
4229 /* copy elements from 32-bit IOCTL structure */
4230 char cmd[16];
4231 gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
4232 gen.command.u.raw64.bus = gen.command.u.raw.bus;
4233 gen.command.u.raw64.lun = gen.command.u.raw.lun;
4234 gen.command.u.raw64.target = gen.command.u.raw.target;
4235 memcpy(cmd, gen.command.u.raw.cmd, 16);
4236 memcpy(gen.command.u.raw64.cmd, cmd, 16);
4237 gen.command.u.raw64.clen = gen.command.u.raw.clen;
4238 gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
4239 gen.command.u.raw64.direction = gen.command.u.raw.direction;
4240 /* addresses */
4241 if (ha->raw_feat & SCATTER_GATHER) {
4242 gen.command.u.raw64.sdata = (u64)-1;
4243 gen.command.u.raw64.sg_ranz = 1;
4244 gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
4245 gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
4246 gen.command.u.raw64.sg_lst[1].sg_len = 0;
4247 } else {
4248 gen.command.u.raw64.sdata = paddr;
4249 gen.command.u.raw64.sg_ranz = 0;
4250 }
4251 gen.command.u.raw64.sense_data = paddr + gen.data_len;
4252 } else {
4253 if (ha->raw_feat & SCATTER_GATHER) {
4254 gen.command.u.raw.sdata = 0xffffffff;
4255 gen.command.u.raw.sg_ranz = 1;
4256 gen.command.u.raw.sg_lst[0].sg_ptr = (u32)paddr;
4257 gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
4258 gen.command.u.raw.sg_lst[1].sg_len = 0;
4259 } else {
4260 gen.command.u.raw.sdata = paddr;
4261 gen.command.u.raw.sg_ranz = 0;
4262 }
4263 gen.command.u.raw.sense_data = (u32)paddr + gen.data_len;
4264 }
4265 } else {
4266 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4267 return -EFAULT;
4268 }
4269 }
4270
4271 rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
4272 if (rval < 0)
4273 return rval;
4274 gen.status = rval;
4275
4276 if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
4277 gen.data_len + gen.sense_len)) {
4278 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4279 return -EFAULT;
4280 }
4281 if (copy_to_user(arg, &gen,
4282 sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
4283 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4284 return -EFAULT;
4285 }
4286 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
4287 return 0;
4288 }
4289
4290 static int ioc_hdrlist(void __user *arg, char *cmnd)
4291 {
4292 gdth_ioctl_rescan *rsc;
4293 gdth_cmd_str *cmd;
4294 gdth_ha_str *ha;
4295 u8 i;
4296 int rc = -ENOMEM;
4297 u32 cluster_type = 0;
4298
4299 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
4300 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
4301 if (!rsc || !cmd)
4302 goto free_fail;
4303
4304 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
4305 (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
4306 rc = -EFAULT;
4307 goto free_fail;
4308 }
4309 memset(cmd, 0, sizeof(gdth_cmd_str));
4310
4311 for (i = 0; i < MAX_HDRIVES; ++i) {
4312 if (!ha->hdr[i].present) {
4313 rsc->hdr_list[i].bus = 0xff;
4314 continue;
4315 }
4316 rsc->hdr_list[i].bus = ha->virt_bus;
4317 rsc->hdr_list[i].target = i;
4318 rsc->hdr_list[i].lun = 0;
4319 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
4320 if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
4321 cmd->Service = CACHESERVICE;
4322 cmd->OpCode = GDT_CLUST_INFO;
4323 if (ha->cache_feat & GDT_64BIT)
4324 cmd->u.cache64.DeviceNo = i;
4325 else
4326 cmd->u.cache.DeviceNo = i;
4327 if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
4328 rsc->hdr_list[i].cluster_type = cluster_type;
4329 }
4330 }
4331
4332 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
4333 rc = -EFAULT;
4334 else
4335 rc = 0;
4336
4337 free_fail:
4338 kfree(rsc);
4339 kfree(cmd);
4340 return rc;
4341 }
4342
4343 static int ioc_rescan(void __user *arg, char *cmnd)
4344 {
4345 gdth_ioctl_rescan *rsc;
4346 gdth_cmd_str *cmd;
4347 u16 i, status, hdr_cnt;
4348 u32 info;
4349 int cyls, hds, secs;
4350 int rc = -ENOMEM;
4351 unsigned long flags;
4352 gdth_ha_str *ha;
4353
4354 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
4355 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
4356 if (!cmd || !rsc)
4357 goto free_fail;
4358
4359 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
4360 (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
4361 rc = -EFAULT;
4362 goto free_fail;
4363 }
4364 memset(cmd, 0, sizeof(gdth_cmd_str));
4365
4366 if (rsc->flag == 0) {
4367 /* old method: re-init. cache service */
4368 cmd->Service = CACHESERVICE;
4369 if (ha->cache_feat & GDT_64BIT) {
4370 cmd->OpCode = GDT_X_INIT_HOST;
4371 cmd->u.cache64.DeviceNo = LINUX_OS;
4372 } else {
4373 cmd->OpCode = GDT_INIT;
4374 cmd->u.cache.DeviceNo = LINUX_OS;
4375 }
4376
4377 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4378 i = 0;
4379 hdr_cnt = (status == S_OK ? (u16)info : 0);
4380 } else {
4381 i = rsc->hdr_no;
4382 hdr_cnt = i + 1;
4383 }
4384
4385 for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
4386 cmd->Service = CACHESERVICE;
4387 cmd->OpCode = GDT_INFO;
4388 if (ha->cache_feat & GDT_64BIT)
4389 cmd->u.cache64.DeviceNo = i;
4390 else
4391 cmd->u.cache.DeviceNo = i;
4392
4393 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4394
4395 spin_lock_irqsave(&ha->smp_lock, flags);
4396 rsc->hdr_list[i].bus = ha->virt_bus;
4397 rsc->hdr_list[i].target = i;
4398 rsc->hdr_list[i].lun = 0;
4399 if (status != S_OK) {
4400 ha->hdr[i].present = FALSE;
4401 } else {
4402 ha->hdr[i].present = TRUE;
4403 ha->hdr[i].size = info;
4404 /* evaluate mapping */
4405 ha->hdr[i].size &= ~SECS32;
4406 gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
4407 ha->hdr[i].heads = hds;
4408 ha->hdr[i].secs = secs;
4409 /* round size */
4410 ha->hdr[i].size = cyls * hds * secs;
4411 }
4412 spin_unlock_irqrestore(&ha->smp_lock, flags);
4413 if (status != S_OK)
4414 continue;
4415
4416 /* extended info, if GDT_64BIT, for drives > 2 TB */
4417 /* but we need ha->info2, not yet stored in scp->SCp */
4418
4419 /* devtype, cluster info, R/W attribs */
4420 cmd->Service = CACHESERVICE;
4421 cmd->OpCode = GDT_DEVTYPE;
4422 if (ha->cache_feat & GDT_64BIT)
4423 cmd->u.cache64.DeviceNo = i;
4424 else
4425 cmd->u.cache.DeviceNo = i;
4426
4427 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4428
4429 spin_lock_irqsave(&ha->smp_lock, flags);
4430 ha->hdr[i].devtype = (status == S_OK ? (u16)info : 0);
4431 spin_unlock_irqrestore(&ha->smp_lock, flags);
4432
4433 cmd->Service = CACHESERVICE;
4434 cmd->OpCode = GDT_CLUST_INFO;
4435 if (ha->cache_feat & GDT_64BIT)
4436 cmd->u.cache64.DeviceNo = i;
4437 else
4438 cmd->u.cache.DeviceNo = i;
4439
4440 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4441
4442 spin_lock_irqsave(&ha->smp_lock, flags);
4443 ha->hdr[i].cluster_type =
4444 ((status == S_OK && !shared_access) ? (u16)info : 0);
4445 spin_unlock_irqrestore(&ha->smp_lock, flags);
4446 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
4447
4448 cmd->Service = CACHESERVICE;
4449 cmd->OpCode = GDT_RW_ATTRIBS;
4450 if (ha->cache_feat & GDT_64BIT)
4451 cmd->u.cache64.DeviceNo = i;
4452 else
4453 cmd->u.cache.DeviceNo = i;
4454
4455 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4456
4457 spin_lock_irqsave(&ha->smp_lock, flags);
4458 ha->hdr[i].rw_attribs = (status == S_OK ? (u16)info : 0);
4459 spin_unlock_irqrestore(&ha->smp_lock, flags);
4460 }
4461
4462 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
4463 rc = -EFAULT;
4464 else
4465 rc = 0;
4466
4467 free_fail:
4468 kfree(rsc);
4469 kfree(cmd);
4470 return rc;
4471 }
4472
4473 static int gdth_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
4474 {
4475 gdth_ha_str *ha;
4476 Scsi_Cmnd *scp;
4477 unsigned long flags;
4478 char cmnd[MAX_COMMAND_SIZE];
4479 void __user *argp = (void __user *)arg;
4480
4481 memset(cmnd, 0xff, 12);
4482
4483 TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
4484
4485 switch (cmd) {
4486 case GDTIOCTL_CTRCNT:
4487 {
4488 int cnt = gdth_ctr_count;
4489 if (put_user(cnt, (int __user *)argp))
4490 return -EFAULT;
4491 break;
4492 }
4493
4494 case GDTIOCTL_DRVERS:
4495 {
4496 int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
4497 if (put_user(ver, (int __user *)argp))
4498 return -EFAULT;
4499 break;
4500 }
4501
4502 case GDTIOCTL_OSVERS:
4503 {
4504 gdth_ioctl_osvers osv;
4505
4506 osv.version = (u8)(LINUX_VERSION_CODE >> 16);
4507 osv.subversion = (u8)(LINUX_VERSION_CODE >> 8);
4508 osv.revision = (u16)(LINUX_VERSION_CODE & 0xff);
4509 if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
4510 return -EFAULT;
4511 break;
4512 }
4513
4514 case GDTIOCTL_CTRTYPE:
4515 {
4516 gdth_ioctl_ctrtype ctrt;
4517
4518 if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
4519 (NULL == (ha = gdth_find_ha(ctrt.ionode))))
4520 return -EFAULT;
4521
4522 if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
4523 ctrt.type = (u8)((ha->stype>>20) - 0x10);
4524 } else {
4525 if (ha->type != GDT_PCIMPR) {
4526 ctrt.type = (u8)((ha->stype<<4) + 6);
4527 } else {
4528 ctrt.type =
4529 (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
4530 if (ha->stype >= 0x300)
4531 ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
4532 else
4533 ctrt.ext_type = 0x6000 | ha->stype;
4534 }
4535 ctrt.device_id = ha->pdev->device;
4536 ctrt.sub_device_id = ha->pdev->subsystem_device;
4537 }
4538 ctrt.info = ha->brd_phys;
4539 ctrt.oem_id = ha->oem_id;
4540 if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
4541 return -EFAULT;
4542 break;
4543 }
4544
4545 case GDTIOCTL_GENERAL:
4546 return ioc_general(argp, cmnd);
4547
4548 case GDTIOCTL_EVENT:
4549 return ioc_event(argp);
4550
4551 case GDTIOCTL_LOCKDRV:
4552 return ioc_lockdrv(argp);
4553
4554 case GDTIOCTL_LOCKCHN:
4555 {
4556 gdth_ioctl_lockchn lchn;
4557 u8 i, j;
4558
4559 if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
4560 (NULL == (ha = gdth_find_ha(lchn.ionode))))
4561 return -EFAULT;
4562
4563 i = lchn.channel;
4564 if (i < ha->bus_cnt) {
4565 if (lchn.lock) {
4566 spin_lock_irqsave(&ha->smp_lock, flags);
4567 ha->raw[i].lock = 1;
4568 spin_unlock_irqrestore(&ha->smp_lock, flags);
4569 for (j = 0; j < ha->tid_cnt; ++j)
4570 gdth_wait_completion(ha, i, j);
4571 } else {
4572 spin_lock_irqsave(&ha->smp_lock, flags);
4573 ha->raw[i].lock = 0;
4574 spin_unlock_irqrestore(&ha->smp_lock, flags);
4575 for (j = 0; j < ha->tid_cnt; ++j)
4576 gdth_next(ha);
4577 }
4578 }
4579 break;
4580 }
4581
4582 case GDTIOCTL_RESCAN:
4583 return ioc_rescan(argp, cmnd);
4584
4585 case GDTIOCTL_HDRLIST:
4586 return ioc_hdrlist(argp, cmnd);
4587
4588 case GDTIOCTL_RESET_BUS:
4589 {
4590 gdth_ioctl_reset res;
4591 int rval;
4592
4593 if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
4594 (NULL == (ha = gdth_find_ha(res.ionode))))
4595 return -EFAULT;
4596
4597 scp = kzalloc(sizeof(*scp), GFP_KERNEL);
4598 if (!scp)
4599 return -ENOMEM;
4600 scp->device = ha->sdev;
4601 scp->cmd_len = 12;
4602 scp->device->channel = res.number;
4603 rval = gdth_eh_bus_reset(scp);
4604 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
4605 kfree(scp);
4606
4607 if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
4608 return -EFAULT;
4609 break;
4610 }
4611
4612 case GDTIOCTL_RESET_DRV:
4613 return ioc_resetdrv(argp, cmnd);
4614
4615 default:
4616 break;
4617 }
4618 return 0;
4619 }
4620
4621 static long gdth_unlocked_ioctl(struct file *file, unsigned int cmd,
4622 unsigned long arg)
4623 {
4624 int ret;
4625
4626 lock_kernel();
4627 ret = gdth_ioctl(file, cmd, arg);
4628 unlock_kernel();
4629
4630 return ret;
4631 }
4632
4633 /* flush routine */
4634 static void gdth_flush(gdth_ha_str *ha)
4635 {
4636 int i;
4637 gdth_cmd_str gdtcmd;
4638 char cmnd[MAX_COMMAND_SIZE];
4639 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
4640
4641 TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
4642
4643 for (i = 0; i < MAX_HDRIVES; ++i) {
4644 if (ha->hdr[i].present) {
4645 gdtcmd.BoardNode = LOCALBOARD;
4646 gdtcmd.Service = CACHESERVICE;
4647 gdtcmd.OpCode = GDT_FLUSH;
4648 if (ha->cache_feat & GDT_64BIT) {
4649 gdtcmd.u.cache64.DeviceNo = i;
4650 gdtcmd.u.cache64.BlockNo = 1;
4651 gdtcmd.u.cache64.sg_canz = 0;
4652 } else {
4653 gdtcmd.u.cache.DeviceNo = i;
4654 gdtcmd.u.cache.BlockNo = 1;
4655 gdtcmd.u.cache.sg_canz = 0;
4656 }
4657 TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
4658
4659 gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
4660 }
4661 }
4662 }
4663
4664 /* configure lun */
4665 static int gdth_slave_configure(struct scsi_device *sdev)
4666 {
4667 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
4668 sdev->skip_ms_page_3f = 1;
4669 sdev->skip_ms_page_8 = 1;
4670 return 0;
4671 }
4672
4673 static struct scsi_host_template gdth_template = {
4674 .name = "GDT SCSI Disk Array Controller",
4675 .info = gdth_info,
4676 .queuecommand = gdth_queuecommand,
4677 .eh_bus_reset_handler = gdth_eh_bus_reset,
4678 .slave_configure = gdth_slave_configure,
4679 .bios_param = gdth_bios_param,
4680 .proc_info = gdth_proc_info,
4681 .eh_timed_out = gdth_timed_out,
4682 .proc_name = "gdth",
4683 .can_queue = GDTH_MAXCMDS,
4684 .this_id = -1,
4685 .sg_tablesize = GDTH_MAXSG,
4686 .cmd_per_lun = GDTH_MAXC_P_L,
4687 .unchecked_isa_dma = 1,
4688 .use_clustering = ENABLE_CLUSTERING,
4689 };
4690
4691 #ifdef CONFIG_ISA
4692 static int __init gdth_isa_probe_one(u32 isa_bios)
4693 {
4694 struct Scsi_Host *shp;
4695 gdth_ha_str *ha;
4696 dma_addr_t scratch_dma_handle = 0;
4697 int error, i;
4698
4699 if (!gdth_search_isa(isa_bios))
4700 return -ENXIO;
4701
4702 shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
4703 if (!shp)
4704 return -ENOMEM;
4705 ha = shost_priv(shp);
4706
4707 error = -ENODEV;
4708 if (!gdth_init_isa(isa_bios,ha))
4709 goto out_host_put;
4710
4711 /* controller found and initialized */
4712 printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
4713 isa_bios, ha->irq, ha->drq);
4714
4715 error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
4716 if (error) {
4717 printk("GDT-ISA: Unable to allocate IRQ\n");
4718 goto out_host_put;
4719 }
4720
4721 error = request_dma(ha->drq, "gdth");
4722 if (error) {
4723 printk("GDT-ISA: Unable to allocate DMA channel\n");
4724 goto out_free_irq;
4725 }
4726
4727 set_dma_mode(ha->drq,DMA_MODE_CASCADE);
4728 enable_dma(ha->drq);
4729 shp->unchecked_isa_dma = 1;
4730 shp->irq = ha->irq;
4731 shp->dma_channel = ha->drq;
4732
4733 ha->hanum = gdth_ctr_count++;
4734 ha->shost = shp;
4735
4736 ha->pccb = &ha->cmdext;
4737 ha->ccb_phys = 0L;
4738 ha->pdev = NULL;
4739
4740 error = -ENOMEM;
4741
4742 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4743 &scratch_dma_handle);
4744 if (!ha->pscratch)
4745 goto out_dec_counters;
4746 ha->scratch_phys = scratch_dma_handle;
4747
4748 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4749 &scratch_dma_handle);
4750 if (!ha->pmsg)
4751 goto out_free_pscratch;
4752 ha->msg_phys = scratch_dma_handle;
4753
4754 #ifdef INT_COAL
4755 ha->coal_stat = pci_alloc_consistent(ha->pdev,
4756 sizeof(gdth_coal_status) * MAXOFFSETS,
4757 &scratch_dma_handle);
4758 if (!ha->coal_stat)
4759 goto out_free_pmsg;
4760 ha->coal_stat_phys = scratch_dma_handle;
4761 #endif
4762
4763 ha->scratch_busy = FALSE;
4764 ha->req_first = NULL;
4765 ha->tid_cnt = MAX_HDRIVES;
4766 if (max_ids > 0 && max_ids < ha->tid_cnt)
4767 ha->tid_cnt = max_ids;
4768 for (i = 0; i < GDTH_MAXCMDS; ++i)
4769 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4770 ha->scan_mode = rescan ? 0x10 : 0;
4771
4772 error = -ENODEV;
4773 if (!gdth_search_drives(ha)) {
4774 printk("GDT-ISA: Error during device scan\n");
4775 goto out_free_coal_stat;
4776 }
4777
4778 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4779 hdr_channel = ha->bus_cnt;
4780 ha->virt_bus = hdr_channel;
4781
4782 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4783 shp->max_cmd_len = 16;
4784
4785 shp->max_id = ha->tid_cnt;
4786 shp->max_lun = MAXLUN;
4787 shp->max_channel = ha->bus_cnt;
4788
4789 spin_lock_init(&ha->smp_lock);
4790 gdth_enable_int(ha);
4791
4792 error = scsi_add_host(shp, NULL);
4793 if (error)
4794 goto out_free_coal_stat;
4795 list_add_tail(&ha->list, &gdth_instances);
4796 gdth_timer_init();
4797
4798 scsi_scan_host(shp);
4799
4800 return 0;
4801
4802 out_free_coal_stat:
4803 #ifdef INT_COAL
4804 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
4805 ha->coal_stat, ha->coal_stat_phys);
4806 out_free_pmsg:
4807 #endif
4808 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4809 ha->pmsg, ha->msg_phys);
4810 out_free_pscratch:
4811 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4812 ha->pscratch, ha->scratch_phys);
4813 out_dec_counters:
4814 gdth_ctr_count--;
4815 out_free_irq:
4816 free_irq(ha->irq, ha);
4817 out_host_put:
4818 scsi_host_put(shp);
4819 return error;
4820 }
4821 #endif /* CONFIG_ISA */
4822
4823 #ifdef CONFIG_EISA
4824 static int __init gdth_eisa_probe_one(u16 eisa_slot)
4825 {
4826 struct Scsi_Host *shp;
4827 gdth_ha_str *ha;
4828 dma_addr_t scratch_dma_handle = 0;
4829 int error, i;
4830
4831 if (!gdth_search_eisa(eisa_slot))
4832 return -ENXIO;
4833
4834 shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
4835 if (!shp)
4836 return -ENOMEM;
4837 ha = shost_priv(shp);
4838
4839 error = -ENODEV;
4840 if (!gdth_init_eisa(eisa_slot,ha))
4841 goto out_host_put;
4842
4843 /* controller found and initialized */
4844 printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
4845 eisa_slot >> 12, ha->irq);
4846
4847 error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
4848 if (error) {
4849 printk("GDT-EISA: Unable to allocate IRQ\n");
4850 goto out_host_put;
4851 }
4852
4853 shp->unchecked_isa_dma = 0;
4854 shp->irq = ha->irq;
4855 shp->dma_channel = 0xff;
4856
4857 ha->hanum = gdth_ctr_count++;
4858 ha->shost = shp;
4859
4860 TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
4861
4862 ha->pccb = &ha->cmdext;
4863 ha->ccb_phys = 0L;
4864
4865 error = -ENOMEM;
4866
4867 ha->pdev = NULL;
4868 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4869 &scratch_dma_handle);
4870 if (!ha->pscratch)
4871 goto out_free_irq;
4872 ha->scratch_phys = scratch_dma_handle;
4873
4874 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4875 &scratch_dma_handle);
4876 if (!ha->pmsg)
4877 goto out_free_pscratch;
4878 ha->msg_phys = scratch_dma_handle;
4879
4880 #ifdef INT_COAL
4881 ha->coal_stat = pci_alloc_consistent(ha->pdev,
4882 sizeof(gdth_coal_status) * MAXOFFSETS,
4883 &scratch_dma_handle);
4884 if (!ha->coal_stat)
4885 goto out_free_pmsg;
4886 ha->coal_stat_phys = scratch_dma_handle;
4887 #endif
4888
4889 ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
4890 sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
4891 if (!ha->ccb_phys)
4892 goto out_free_coal_stat;
4893
4894 ha->scratch_busy = FALSE;
4895 ha->req_first = NULL;
4896 ha->tid_cnt = MAX_HDRIVES;
4897 if (max_ids > 0 && max_ids < ha->tid_cnt)
4898 ha->tid_cnt = max_ids;
4899 for (i = 0; i < GDTH_MAXCMDS; ++i)
4900 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4901 ha->scan_mode = rescan ? 0x10 : 0;
4902
4903 if (!gdth_search_drives(ha)) {
4904 printk("GDT-EISA: Error during device scan\n");
4905 error = -ENODEV;
4906 goto out_free_ccb_phys;
4907 }
4908
4909 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4910 hdr_channel = ha->bus_cnt;
4911 ha->virt_bus = hdr_channel;
4912
4913 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4914 shp->max_cmd_len = 16;
4915
4916 shp->max_id = ha->tid_cnt;
4917 shp->max_lun = MAXLUN;
4918 shp->max_channel = ha->bus_cnt;
4919
4920 spin_lock_init(&ha->smp_lock);
4921 gdth_enable_int(ha);
4922
4923 error = scsi_add_host(shp, NULL);
4924 if (error)
4925 goto out_free_ccb_phys;
4926 list_add_tail(&ha->list, &gdth_instances);
4927 gdth_timer_init();
4928
4929 scsi_scan_host(shp);
4930
4931 return 0;
4932
4933 out_free_ccb_phys:
4934 pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
4935 PCI_DMA_BIDIRECTIONAL);
4936 out_free_coal_stat:
4937 #ifdef INT_COAL
4938 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
4939 ha->coal_stat, ha->coal_stat_phys);
4940 out_free_pmsg:
4941 #endif
4942 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4943 ha->pmsg, ha->msg_phys);
4944 out_free_pscratch:
4945 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4946 ha->pscratch, ha->scratch_phys);
4947 out_free_irq:
4948 free_irq(ha->irq, ha);
4949 gdth_ctr_count--;
4950 out_host_put:
4951 scsi_host_put(shp);
4952 return error;
4953 }
4954 #endif /* CONFIG_EISA */
4955
4956 #ifdef CONFIG_PCI
4957 static int __devinit gdth_pci_probe_one(gdth_pci_str *pcistr,
4958 gdth_ha_str **ha_out)
4959 {
4960 struct Scsi_Host *shp;
4961 gdth_ha_str *ha;
4962 dma_addr_t scratch_dma_handle = 0;
4963 int error, i;
4964 struct pci_dev *pdev = pcistr->pdev;
4965
4966 *ha_out = NULL;
4967
4968 shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
4969 if (!shp)
4970 return -ENOMEM;
4971 ha = shost_priv(shp);
4972
4973 error = -ENODEV;
4974 if (!gdth_init_pci(pdev, pcistr, ha))
4975 goto out_host_put;
4976
4977 /* controller found and initialized */
4978 printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
4979 pdev->bus->number,
4980 PCI_SLOT(pdev->devfn),
4981 ha->irq);
4982
4983 error = request_irq(ha->irq, gdth_interrupt,
4984 IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
4985 if (error) {
4986 printk("GDT-PCI: Unable to allocate IRQ\n");
4987 goto out_host_put;
4988 }
4989
4990 shp->unchecked_isa_dma = 0;
4991 shp->irq = ha->irq;
4992 shp->dma_channel = 0xff;
4993
4994 ha->hanum = gdth_ctr_count++;
4995 ha->shost = shp;
4996
4997 ha->pccb = &ha->cmdext;
4998 ha->ccb_phys = 0L;
4999
5000 error = -ENOMEM;
5001
5002 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
5003 &scratch_dma_handle);
5004 if (!ha->pscratch)
5005 goto out_free_irq;
5006 ha->scratch_phys = scratch_dma_handle;
5007
5008 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
5009 &scratch_dma_handle);
5010 if (!ha->pmsg)
5011 goto out_free_pscratch;
5012 ha->msg_phys = scratch_dma_handle;
5013
5014 #ifdef INT_COAL
5015 ha->coal_stat = pci_alloc_consistent(ha->pdev,
5016 sizeof(gdth_coal_status) * MAXOFFSETS,
5017 &scratch_dma_handle);
5018 if (!ha->coal_stat)
5019 goto out_free_pmsg;
5020 ha->coal_stat_phys = scratch_dma_handle;
5021 #endif
5022
5023 ha->scratch_busy = FALSE;
5024 ha->req_first = NULL;
5025 ha->tid_cnt = pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
5026 if (max_ids > 0 && max_ids < ha->tid_cnt)
5027 ha->tid_cnt = max_ids;
5028 for (i = 0; i < GDTH_MAXCMDS; ++i)
5029 ha->cmd_tab[i].cmnd = UNUSED_CMND;
5030 ha->scan_mode = rescan ? 0x10 : 0;
5031
5032 error = -ENODEV;
5033 if (!gdth_search_drives(ha)) {
5034 printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
5035 goto out_free_coal_stat;
5036 }
5037
5038 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
5039 hdr_channel = ha->bus_cnt;
5040 ha->virt_bus = hdr_channel;
5041
5042 /* 64-bit DMA only supported from FW >= x.43 */
5043 if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
5044 !ha->dma64_support) {
5045 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
5046 printk(KERN_WARNING "GDT-PCI %d: "
5047 "Unable to set 32-bit DMA\n", ha->hanum);
5048 goto out_free_coal_stat;
5049 }
5050 } else {
5051 shp->max_cmd_len = 16;
5052 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
5053 printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
5054 } else if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
5055 printk(KERN_WARNING "GDT-PCI %d: "
5056 "Unable to set 64/32-bit DMA\n", ha->hanum);
5057 goto out_free_coal_stat;
5058 }
5059 }
5060
5061 shp->max_id = ha->tid_cnt;
5062 shp->max_lun = MAXLUN;
5063 shp->max_channel = ha->bus_cnt;
5064
5065 spin_lock_init(&ha->smp_lock);
5066 gdth_enable_int(ha);
5067
5068 error = scsi_add_host(shp, &pdev->dev);
5069 if (error)
5070 goto out_free_coal_stat;
5071 list_add_tail(&ha->list, &gdth_instances);
5072
5073 pci_set_drvdata(ha->pdev, ha);
5074 gdth_timer_init();
5075
5076 scsi_scan_host(shp);
5077
5078 *ha_out = ha;
5079
5080 return 0;
5081
5082 out_free_coal_stat:
5083 #ifdef INT_COAL
5084 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
5085 ha->coal_stat, ha->coal_stat_phys);
5086 out_free_pmsg:
5087 #endif
5088 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5089 ha->pmsg, ha->msg_phys);
5090 out_free_pscratch:
5091 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5092 ha->pscratch, ha->scratch_phys);
5093 out_free_irq:
5094 free_irq(ha->irq, ha);
5095 gdth_ctr_count--;
5096 out_host_put:
5097 scsi_host_put(shp);
5098 return error;
5099 }
5100 #endif /* CONFIG_PCI */
5101
5102 static void gdth_remove_one(gdth_ha_str *ha)
5103 {
5104 struct Scsi_Host *shp = ha->shost;
5105
5106 TRACE2(("gdth_remove_one()\n"));
5107
5108 scsi_remove_host(shp);
5109
5110 gdth_flush(ha);
5111
5112 if (ha->sdev) {
5113 scsi_free_host_dev(ha->sdev);
5114 ha->sdev = NULL;
5115 }
5116
5117 if (shp->irq)
5118 free_irq(shp->irq,ha);
5119
5120 #ifdef CONFIG_ISA
5121 if (shp->dma_channel != 0xff)
5122 free_dma(shp->dma_channel);
5123 #endif
5124 #ifdef INT_COAL
5125 if (ha->coal_stat)
5126 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
5127 MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
5128 #endif
5129 if (ha->pscratch)
5130 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5131 ha->pscratch, ha->scratch_phys);
5132 if (ha->pmsg)
5133 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5134 ha->pmsg, ha->msg_phys);
5135 if (ha->ccb_phys)
5136 pci_unmap_single(ha->pdev,ha->ccb_phys,
5137 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
5138
5139 scsi_host_put(shp);
5140 }
5141
5142 static int gdth_halt(struct notifier_block *nb, unsigned long event, void *buf)
5143 {
5144 gdth_ha_str *ha;
5145
5146 TRACE2(("gdth_halt() event %d\n", (int)event));
5147 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
5148 return NOTIFY_DONE;
5149
5150 list_for_each_entry(ha, &gdth_instances, list)
5151 gdth_flush(ha);
5152
5153 return NOTIFY_OK;
5154 }
5155
5156 static struct notifier_block gdth_notifier = {
5157 gdth_halt, NULL, 0
5158 };
5159
5160 static int __init gdth_init(void)
5161 {
5162 if (disable) {
5163 printk("GDT-HA: Controller driver disabled from"
5164 " command line !\n");
5165 return 0;
5166 }
5167
5168 printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",
5169 GDTH_VERSION_STR);
5170
5171 /* initializations */
5172 gdth_polling = TRUE;
5173 gdth_clear_events();
5174 init_timer(&gdth_timer);
5175
5176 /* As default we do not probe for EISA or ISA controllers */
5177 if (probe_eisa_isa) {
5178 /* scanning for controllers, at first: ISA controller */
5179 #ifdef CONFIG_ISA
5180 u32 isa_bios;
5181 for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
5182 isa_bios += 0x8000UL)
5183 gdth_isa_probe_one(isa_bios);
5184 #endif
5185 #ifdef CONFIG_EISA
5186 {
5187 u16 eisa_slot;
5188 for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
5189 eisa_slot += 0x1000)
5190 gdth_eisa_probe_one(eisa_slot);
5191 }
5192 #endif
5193 }
5194
5195 #ifdef CONFIG_PCI
5196 /* scanning for PCI controllers */
5197 if (pci_register_driver(&gdth_pci_driver)) {
5198 gdth_ha_str *ha;
5199
5200 list_for_each_entry(ha, &gdth_instances, list)
5201 gdth_remove_one(ha);
5202 return -ENODEV;
5203 }
5204 #endif /* CONFIG_PCI */
5205
5206 TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
5207
5208 major = register_chrdev(0,"gdth", &gdth_fops);
5209 register_reboot_notifier(&gdth_notifier);
5210 gdth_polling = FALSE;
5211 return 0;
5212 }
5213
5214 static void __exit gdth_exit(void)
5215 {
5216 gdth_ha_str *ha;
5217
5218 unregister_chrdev(major, "gdth");
5219 unregister_reboot_notifier(&gdth_notifier);
5220
5221 #ifdef GDTH_STATISTICS
5222 del_timer_sync(&gdth_timer);
5223 #endif
5224
5225 #ifdef CONFIG_PCI
5226 pci_unregister_driver(&gdth_pci_driver);
5227 #endif
5228
5229 list_for_each_entry(ha, &gdth_instances, list)
5230 gdth_remove_one(ha);
5231 }
5232
5233 module_init(gdth_init);
5234 module_exit(gdth_exit);
5235
5236 #ifndef MODULE
5237 __setup("gdth=", option_setup);
5238 #endif
Tomato firmware and modifications.