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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / scsi / dc395x.h
blobd1a8eb3b5f2fe6b831132584e823071acb48fe68
1 /************************************************************************/
2 /* */
3 /* dc395x.h */
4 /* */
5 /* Device Driver for Tekram DC395(U/UW/F), DC315(U) */
6 /* PCI SCSI Bus Master Host Adapter */
7 /* (SCSI chip set used Tekram ASIC TRM-S1040) */
8 /* */
9 /************************************************************************/
10 #ifndef DC395x_H
11 #define DC395x_H
12
13 /************************************************************************/
14 /* */
15 /* Initial values */
16 /* */
17 /************************************************************************/
18 #define DC395x_MAX_CMD_QUEUE 32
19 /* #define DC395x_MAX_QTAGS 32 */
20 #define DC395x_MAX_QTAGS 16
21 #define DC395x_MAX_SCSI_ID 16
22 #define DC395x_MAX_CMD_PER_LUN DC395x_MAX_QTAGS
23 #define DC395x_MAX_SG_TABLESIZE 64 /* HW limitation */
24 #define DC395x_MAX_SG_LISTENTRY 64 /* Must be equal or lower to previous */
25 /* item */
26 #define DC395x_MAX_SRB_CNT 63
27 /* #define DC395x_MAX_CAN_QUEUE 7 * DC395x_MAX_QTAGS */
28 #define DC395x_MAX_CAN_QUEUE DC395x_MAX_SRB_CNT
29 #define DC395x_END_SCAN 2
30 #define DC395x_SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */
31 #define DC395x_MAX_RETRIES 3
32
33
34 #define NORM_REC_LVL 0
35
36 /************************************************************************/
37 /* */
38 /* Various definitions */
39 /* */
40 /************************************************************************/
41 #define BIT31 0x80000000
42 #define BIT30 0x40000000
43 #define BIT29 0x20000000
44 #define BIT28 0x10000000
45 #define BIT27 0x08000000
46 #define BIT26 0x04000000
47 #define BIT25 0x02000000
48 #define BIT24 0x01000000
49 #define BIT23 0x00800000
50 #define BIT22 0x00400000
51 #define BIT21 0x00200000
52 #define BIT20 0x00100000
53 #define BIT19 0x00080000
54 #define BIT18 0x00040000
55 #define BIT17 0x00020000
56 #define BIT16 0x00010000
57 #define BIT15 0x00008000
58 #define BIT14 0x00004000
59 #define BIT13 0x00002000
60 #define BIT12 0x00001000
61 #define BIT11 0x00000800
62 #define BIT10 0x00000400
63 #define BIT9 0x00000200
64 #define BIT8 0x00000100
65 #define BIT7 0x00000080
66 #define BIT6 0x00000040
67 #define BIT5 0x00000020
68 #define BIT4 0x00000010
69 #define BIT3 0x00000008
70 #define BIT2 0x00000004
71 #define BIT1 0x00000002
72 #define BIT0 0x00000001
73
74 /* UnitCtrlFlag */
75 #define UNIT_ALLOCATED BIT0
76 #define UNIT_INFO_CHANGED BIT1
77 #define FORMATING_MEDIA BIT2
78 #define UNIT_RETRY BIT3
79
80 /* UnitFlags */
81 #define DASD_SUPPORT BIT0
82 #define SCSI_SUPPORT BIT1
83 #define ASPI_SUPPORT BIT2
84
85 /* SRBState machine definition */
86 #define SRB_FREE 0x0000
87 #define SRB_WAIT 0x0001
88 #define SRB_READY 0x0002
89 #define SRB_MSGOUT 0x0004 /* arbitration+msg_out 1st byte */
90 #define SRB_MSGIN 0x0008
91 #define SRB_EXTEND_MSGIN 0x0010
92 #define SRB_COMMAND 0x0020
93 #define SRB_START_ 0x0040 /* arbitration+msg_out+command_out */
94 #define SRB_DISCONNECT 0x0080
95 #define SRB_DATA_XFER 0x0100
96 #define SRB_XFERPAD 0x0200
97 #define SRB_STATUS 0x0400
98 #define SRB_COMPLETED 0x0800
99 #define SRB_ABORT_SENT 0x1000
100 #define SRB_DO_SYNC_NEGO 0x2000
101 #define SRB_DO_WIDE_NEGO 0x4000
102 #define SRB_UNEXPECT_RESEL 0x8000
103
104 /************************************************************************/
105 /* */
106 /* ACB Config */
107 /* */
108 /************************************************************************/
109 #define HCC_WIDE_CARD 0x20
110 #define HCC_SCSI_RESET 0x10
111 #define HCC_PARITY 0x08
112 #define HCC_AUTOTERM 0x04
113 #define HCC_LOW8TERM 0x02
114 #define HCC_UP8TERM 0x01
115
116 /* ACBFlag */
117 #define RESET_DEV BIT0
118 #define RESET_DETECT BIT1
119 #define RESET_DONE BIT2
120
121 /* DCBFlag */
122 #define ABORT_DEV_ BIT0
123
124 /* SRBstatus */
125 #define SRB_OK BIT0
126 #define ABORTION BIT1
127 #define OVER_RUN BIT2
128 #define UNDER_RUN BIT3
129 #define PARITY_ERROR BIT4
130 #define SRB_ERROR BIT5
131
132 /* SRBFlag */
133 #define DATAOUT BIT7
134 #define DATAIN BIT6
135 #define RESIDUAL_VALID BIT5
136 #define ENABLE_TIMER BIT4
137 #define RESET_DEV0 BIT2
138 #define ABORT_DEV BIT1
139 #define AUTO_REQSENSE BIT0
140
141 /* Adapter status */
142 #define H_STATUS_GOOD 0
143 #define H_SEL_TIMEOUT 0x11
144 #define H_OVER_UNDER_RUN 0x12
145 #define H_UNEXP_BUS_FREE 0x13
146 #define H_TARGET_PHASE_F 0x14
147 #define H_INVALID_CCB_OP 0x16
148 #define H_LINK_CCB_BAD 0x17
149 #define H_BAD_TARGET_DIR 0x18
150 #define H_DUPLICATE_CCB 0x19
151 #define H_BAD_CCB_OR_SG 0x1A
152 #define H_ABORT 0x0FF
153
154 /* SCSI BUS Status byte codes */
155 #define SCSI_STAT_GOOD 0x0 /* Good status */
156 #define SCSI_STAT_CHECKCOND 0x02 /* SCSI Check Condition */
157 #define SCSI_STAT_CONDMET 0x04 /* Condition Met */
158 #define SCSI_STAT_BUSY 0x08 /* Target busy status */
159 #define SCSI_STAT_INTER 0x10 /* Intermediate status */
160 #define SCSI_STAT_INTERCONDMET 0x14 /* Intermediate condition met */
161 #define SCSI_STAT_RESCONFLICT 0x18 /* Reservation conflict */
162 #define SCSI_STAT_CMDTERM 0x22 /* Command Terminated */
163 #define SCSI_STAT_QUEUEFULL 0x28 /* Queue Full */
164 #define SCSI_STAT_UNEXP_BUS_F 0xFD /* Unexpect Bus Free */
165 #define SCSI_STAT_BUS_RST_DETECT 0xFE /* Scsi Bus Reset detected */
166 #define SCSI_STAT_SEL_TIMEOUT 0xFF /* Selection Time out */
167
168 /* Sync_Mode */
169 #define SYNC_WIDE_TAG_ATNT_DISABLE 0
170 #define SYNC_NEGO_ENABLE BIT0
171 #define SYNC_NEGO_DONE BIT1
172 #define WIDE_NEGO_ENABLE BIT2
173 #define WIDE_NEGO_DONE BIT3
174 #define WIDE_NEGO_STATE BIT4
175 #define EN_TAG_QUEUEING BIT5
176 #define EN_ATN_STOP BIT6
177
178 #define SYNC_NEGO_OFFSET 15
179
180 /* SCSI MSG BYTE */
181 #define MSG_COMPLETE 0x00
182 #define MSG_EXTENDED 0x01
183 #define MSG_SAVE_PTR 0x02
184 #define MSG_RESTORE_PTR 0x03
185 #define MSG_DISCONNECT 0x04
186 #define MSG_INITIATOR_ERROR 0x05
187 #define MSG_ABORT 0x06
188 #define MSG_REJECT_ 0x07
189 #define MSG_NOP 0x08
190 #define MSG_PARITY_ERROR 0x09
191 #define MSG_LINK_CMD_COMPL 0x0A
192 #define MSG_LINK_CMD_COMPL_FLG 0x0B
193 #define MSG_BUS_RESET 0x0C
194 #define MSG_ABORT_TAG 0x0D
195 #define MSG_SIMPLE_QTAG 0x20
196 #define MSG_HEAD_QTAG 0x21
197 #define MSG_ORDER_QTAG 0x22
198 #define MSG_IGNOREWIDE 0x23
199 #define MSG_IDENTIFY 0x80
200 #define MSG_HOST_ID 0xC0
201
202 /* SCSI STATUS BYTE */
203 #define STATUS_GOOD 0x00
204 #define CHECK_CONDITION_ 0x02
205 #define STATUS_BUSY 0x08
206 #define STATUS_INTERMEDIATE 0x10
207 #define RESERVE_CONFLICT 0x18
208
209 /* cmd->result */
210 #define STATUS_MASK_ 0xFF
211 #define MSG_MASK 0xFF00
212 #define RETURN_MASK 0xFF0000
213
214 /************************************************************************/
215 /* */
216 /* Inquiry Data format */
217 /* */
218 /************************************************************************/
219 struct ScsiInqData
220 { /* INQ */
221 u8 DevType; /* Periph Qualifier & Periph Dev Type */
222 u8 RMB_TypeMod; /* rem media bit & Dev Type Modifier */
223 u8 Vers; /* ISO, ECMA, & ANSI versions */
224 u8 RDF; /* AEN, TRMIOP, & response data format */
225 u8 AddLen; /* length of additional data */
226 u8 Res1; /* reserved */
227 u8 Res2; /* reserved */
228 u8 Flags; /* RelADr, Wbus32, Wbus16, Sync, etc. */
229 u8 VendorID[8]; /* Vendor Identification */
230 u8 ProductID[16]; /* Product Identification */
231 u8 ProductRev[4]; /* Product Revision */
232 };
233
234 /* Inquiry byte 0 masks */
235 #define SCSI_DEVTYPE 0x1F /* Peripheral Device Type */
236 #define SCSI_PERIPHQUAL 0xE0 /* Peripheral Qualifier */
237 /* Inquiry byte 1 mask */
238 #define SCSI_REMOVABLE_MEDIA 0x80 /* Removable Media bit (1=removable) */
239 /* Peripheral Device Type definitions */
240 /* See include/scsi/scsi.h */
241 #define TYPE_NODEV SCSI_DEVTYPE /* Unknown or no device type */
242 #ifndef TYPE_PRINTER /* */
243 # define TYPE_PRINTER 0x02 /* Printer device */
244 #endif /* */
245 #ifndef TYPE_COMM /* */
246 # define TYPE_COMM 0x09 /* Communications device */
247 #endif
248
249 /************************************************************************/
250 /* */
251 /* Inquiry flag definitions (Inq data byte 7) */
252 /* */
253 /************************************************************************/
254 #define SCSI_INQ_RELADR 0x80 /* device supports relative addressing */
255 #define SCSI_INQ_WBUS32 0x40 /* device supports 32 bit data xfers */
256 #define SCSI_INQ_WBUS16 0x20 /* device supports 16 bit data xfers */
257 #define SCSI_INQ_SYNC 0x10 /* device supports synchronous xfer */
258 #define SCSI_INQ_LINKED 0x08 /* device supports linked commands */
259 #define SCSI_INQ_CMDQUEUE 0x02 /* device supports command queueing */
260 #define SCSI_INQ_SFTRE 0x01 /* device supports soft resets */
261
262 #define ENABLE_CE 1
263 #define DISABLE_CE 0
264 #define EEPROM_READ 0x80
265
266 /************************************************************************/
267 /* */
268 /* The PCI configuration register offset for TRM_S1040 */
269 /* */
270 /************************************************************************/
271 #define TRM_S1040_ID 0x00 /* Vendor and Device ID */
272 #define TRM_S1040_COMMAND 0x04 /* PCI command register */
273 #define TRM_S1040_IOBASE 0x10 /* I/O Space base address */
274 #define TRM_S1040_ROMBASE 0x30 /* Expansion ROM Base Address */
275 #define TRM_S1040_INTLINE 0x3C /* Interrupt line */
276
277 /************************************************************************/
278 /* */
279 /* The SCSI register offset for TRM_S1040 */
280 /* */
281 /************************************************************************/
282 #define TRM_S1040_SCSI_STATUS 0x80 /* SCSI Status (R) */
283 #define COMMANDPHASEDONE 0x2000 /* SCSI command phase done */
284 #define SCSIXFERDONE 0x0800 /* SCSI SCSI transfer done */
285 #define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI SCSI transfer count to zero */
286 #define SCSIINTERRUPT 0x0080 /* SCSI interrupt pending */
287 #define COMMANDABORT 0x0040 /* SCSI command abort */
288 #define SEQUENCERACTIVE 0x0020 /* SCSI sequencer active */
289 #define PHASEMISMATCH 0x0010 /* SCSI phase mismatch */
290 #define PARITYERROR 0x0008 /* SCSI parity error */
291
292 #define PHASEMASK 0x0007 /* Phase MSG/CD/IO */
293 #define PH_DATA_OUT 0x00 /* Data out phase */
294 #define PH_DATA_IN 0x01 /* Data in phase */
295 #define PH_COMMAND 0x02 /* Command phase */
296 #define PH_STATUS 0x03 /* Status phase */
297 #define PH_BUS_FREE 0x05 /* Invalid phase used as bus free */
298 #define PH_MSG_OUT 0x06 /* Message out phase */
299 #define PH_MSG_IN 0x07 /* Message in phase */
300
301 #define TRM_S1040_SCSI_CONTROL 0x80 /* SCSI Control (W) */
302 #define DO_CLRATN 0x0400 /* Clear ATN */
303 #define DO_SETATN 0x0200 /* Set ATN */
304 #define DO_CMDABORT 0x0100 /* Abort SCSI command */
305 #define DO_RSTMODULE 0x0010 /* Reset SCSI chip */
306 #define DO_RSTSCSI 0x0008 /* Reset SCSI bus */
307 #define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */
308 #define DO_DATALATCH 0x0002 /* Enable SCSI bus data input (latched) */
309 /* #define DO_DATALATCH 0x0000 */ /* KG: DISable SCSI bus data latch */
310 #define DO_HWRESELECT 0x0001 /* Enable hardware reselection */
311
312 #define TRM_S1040_SCSI_FIFOCNT 0x82 /* SCSI FIFO Counter 5bits(R) */
313 #define TRM_S1040_SCSI_SIGNAL 0x83 /* SCSI low level signal (R/W) */
314
315 #define TRM_S1040_SCSI_INTSTATUS 0x84 /* SCSI Interrupt Status (R) */
316 #define INT_SCAM 0x80 /* SCAM selection interrupt */
317 #define INT_SELECT 0x40 /* Selection interrupt */
318 #define INT_SELTIMEOUT 0x20 /* Selection timeout interrupt */
319 #define INT_DISCONNECT 0x10 /* Bus disconnected interrupt */
320 #define INT_RESELECTED 0x08 /* Reselected interrupt */
321 #define INT_SCSIRESET 0x04 /* SCSI reset detected interrupt */
322 #define INT_BUSSERVICE 0x02 /* Bus service interrupt */
323 #define INT_CMDDONE 0x01 /* SCSI command done interrupt */
324
325 #define TRM_S1040_SCSI_OFFSET 0x84 /* SCSI Offset Count (W) */
326
327 /************************************************************************/
328 /* */
329 /* Bit Name Definition */
330 /* --------- ------------- ---------------------------- */
331 /* 07-05 0 RSVD Reversed. Always 0. */
332 /* 04 0 OFFSET4 Reversed for LVDS. Always 0. */
333 /* 03-00 0 OFFSET[03:00] Offset number from 0 to 15 */
334 /* */
335 /************************************************************************/
336
337 #define TRM_S1040_SCSI_SYNC 0x85 /* SCSI Synchronous Control (R/W) */
338 #define LVDS_SYNC 0x20 /* Enable LVDS synchronous */
339 #define WIDE_SYNC 0x10 /* Enable WIDE synchronous */
340 #define ALT_SYNC 0x08 /* Enable Fast-20 alternate synchronous */
341
342 /************************************************************************/
343 /* */
344 /* SYNCM 7 6 5 4 3 2 1 0 */
345 /* Name RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0 */
346 /* Default 0 0 0 0 0 0 0 0 */
347 /* */
348 /* Bit Name Definition */
349 /* --------- ------------- --------------------------- */
350 /* 07-06 0 RSVD Reversed. Always read 0 */
351 /* 05 0 LVDS Reversed. Always read 0 */
352 /* 04 0 WIDE/WSCSI Enable wide (16-bits) SCSI */
353 /* transfer. */
354 /* 03 0 ALTPERD/ALTPD Alternate (Sync./Period) mode. */
355 /* */
356 /* @@ When this bit is set, */
357 /* the synchronous period bits 2:0 */
358 /* in the Synchronous Mode register */
359 /* are used to transfer data */
360 /* at the Fast-20 rate. */
361 /* @@ When this bit is unset, */
362 /* the synchronous period bits 2:0 */
363 /* in the Synchronous Mode Register */
364 /* are used to transfer data */
365 /* at the Fast-10 rate (or Fast-40 w/ LVDS). */
366 /* */
367 /* 02-00 0 PERIOD[2:0]/ Synchronous SCSI Transfer Rate. */
368 /* SXPD[02:00] These 3 bits specify */
369 /* the Synchronous SCSI Transfer */
370 /* Rate for Fast-20 and Fast-10. */
371 /* These bits are also reset */
372 /* by a SCSI Bus reset. */
373 /* */
374 /* For Fast-10 bit ALTPD = 0 and LVDS = 0 */
375 /* and bit2,bit1,bit0 is defined as follows : */
376 /* */
377 /* 000 100ns, 10.0 MHz */
378 /* 001 150ns, 6.6 MHz */
379 /* 010 200ns, 5.0 MHz */
380 /* 011 250ns, 4.0 MHz */
381 /* 100 300ns, 3.3 MHz */
382 /* 101 350ns, 2.8 MHz */
383 /* 110 400ns, 2.5 MHz */
384 /* 111 450ns, 2.2 MHz */
385 /* */
386 /* For Fast-20 bit ALTPD = 1 and LVDS = 0 */
387 /* and bit2,bit1,bit0 is defined as follows : */
388 /* */
389 /* 000 50ns, 20.0 MHz */
390 /* 001 75ns, 13.3 MHz */
391 /* 010 100ns, 10.0 MHz */
392 /* 011 125ns, 8.0 MHz */
393 /* 100 150ns, 6.6 MHz */
394 /* 101 175ns, 5.7 MHz */
395 /* 110 200ns, 5.0 MHz */
396 /* 111 250ns, 4.0 MHz KG: Maybe 225ns, 4.4 MHz */
397 /* */
398 /* For Fast-40 bit ALTPD = 0 and LVDS = 1 */
399 /* and bit2,bit1,bit0 is defined as follows : */
400 /* */
401 /* 000 25ns, 40.0 MHz */
402 /* 001 50ns, 20.0 MHz */
403 /* 010 75ns, 13.3 MHz */
404 /* 011 100ns, 10.0 MHz */
405 /* 100 125ns, 8.0 MHz */
406 /* 101 150ns, 6.6 MHz */
407 /* 110 175ns, 5.7 MHz */
408 /* 111 200ns, 5.0 MHz */
409 /* */
410 /************************************************************************/
411
412 #define TRM_S1040_SCSI_TARGETID 0x86 /* SCSI Target ID (R/W) */
413 #define TRM_S1040_SCSI_IDMSG 0x87 /* SCSI Identify Message (R) */
414 #define TRM_S1040_SCSI_HOSTID 0x87 /* SCSI Host ID (W) */
415 #define TRM_S1040_SCSI_COUNTER 0x88 /* SCSI Transfer Counter 24bits(R/W) */
416
417 #define TRM_S1040_SCSI_INTEN 0x8C /* SCSI Interrupt Enable (R/W) */
418 #define EN_SCAM 0x80 /* Enable SCAM selection interrupt */
419 #define EN_SELECT 0x40 /* Enable selection interrupt */
420 #define EN_SELTIMEOUT 0x20 /* Enable selection timeout interrupt */
421 #define EN_DISCONNECT 0x10 /* Enable bus disconnected interrupt */
422 #define EN_RESELECTED 0x08 /* Enable reselected interrupt */
423 #define EN_SCSIRESET 0x04 /* Enable SCSI reset detected interrupt */
424 #define EN_BUSSERVICE 0x02 /* Enable bus service interrupt */
425 #define EN_CMDDONE 0x01 /* Enable SCSI command done interrupt */
426
427 #define TRM_S1040_SCSI_CONFIG0 0x8D /* SCSI Configuration 0 (R/W) */
428 #define PHASELATCH 0x40 /* Enable phase latch */
429 #define INITIATOR 0x20 /* Enable initiator mode */
430 #define PARITYCHECK 0x10 /* Enable parity check */
431 #define BLOCKRST 0x01 /* Disable SCSI reset1 */
432
433 #define TRM_S1040_SCSI_CONFIG1 0x8E /* SCSI Configuration 1 (R/W) */
434 #define ACTIVE_NEGPLUS 0x10 /* Enhance active negation */
435 #define FILTER_DISABLE 0x08 /* Disable SCSI data filter */
436 #define FAST_FILTER 0x04 /* ? */
437 #define ACTIVE_NEG 0x02 /* Enable active negation */
438
439 #define TRM_S1040_SCSI_CONFIG2 0x8F /* SCSI Configuration 2 (R/W) */
440 #define CFG2_WIDEFIFO 0x02 /* */
441
442 #define TRM_S1040_SCSI_COMMAND 0x90 /* SCSI Command (R/W) */
443 #define SCMD_COMP 0x12 /* Command complete */
444 #define SCMD_SEL_ATN 0x60 /* Selection with ATN */
445 #define SCMD_SEL_ATN3 0x64 /* Selection with ATN3 */
446 #define SCMD_SEL_ATNSTOP 0xB8 /* Selection with ATN and Stop */
447 #define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */
448 #define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */
449 #define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */
450 #define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */
451 #define SCMD_MSGACCEPT 0xD8 /* Message accept */
452
453 /************************************************************************/
454 /* */
455 /* Code Command Description */
456 /* ---- ---------------------------------------- */
457 /* 02 Enable reselection with FIFO */
458 /* 40 Select without ATN with FIFO */
459 /* 60 Select with ATN with FIFO */
460 /* 64 Select with ATN3 with FIFO */
461 /* A0 Select with ATN and stop with FIFO */
462 /* C0 Transfer information out with FIFO */
463 /* C1 Transfer information out with DMA */
464 /* C2 Transfer information in with FIFO */
465 /* C3 Transfer information in with DMA */
466 /* 12 Initiator command complete with FIFO */
467 /* 50 Initiator transfer information out sequence without ATN */
468 /* with FIFO */
469 /* 70 Initiator transfer information out sequence with ATN */
470 /* with FIFO */
471 /* 74 Initiator transfer information out sequence with ATN3 */
472 /* with FIFO */
473 /* 52 Initiator transfer information in sequence without ATN */
474 /* with FIFO */
475 /* 72 Initiator transfer information in sequence with ATN */
476 /* with FIFO */
477 /* 76 Initiator transfer information in sequence with ATN3 */
478 /* with FIFO */
479 /* 90 Initiator transfer information out command complete */
480 /* with FIFO */
481 /* 92 Initiator transfer information in command complete */
482 /* with FIFO */
483 /* D2 Enable selection */
484 /* 08 Reselection */
485 /* 48 Disconnect command with FIFO */
486 /* 88 Terminate command with FIFO */
487 /* C8 Target command complete with FIFO */
488 /* 18 SCAM Arbitration/ Selection */
489 /* 5A Enable reselection */
490 /* 98 Select without ATN with FIFO */
491 /* B8 Select with ATN with FIFO */
492 /* D8 Message Accepted */
493 /* 58 NOP */
494 /* */
495 /************************************************************************/
496
497 #define TRM_S1040_SCSI_TIMEOUT 0x91 /* SCSI Time Out Value (R/W) */
498 #define TRM_S1040_SCSI_FIFO 0x98 /* SCSI FIFO (R/W) */
499
500 #define TRM_S1040_SCSI_TCR0 0x9C /* SCSI Target Control 0 (R/W) */
501 #define TCR0_WIDE_NEGO_DONE 0x8000 /* Wide nego done */
502 #define TCR0_SYNC_NEGO_DONE 0x4000 /* Synchronous nego done */
503 #define TCR0_ENABLE_LVDS 0x2000 /* Enable LVDS synchronous */
504 #define TCR0_ENABLE_WIDE 0x1000 /* Enable WIDE synchronous */
505 #define TCR0_ENABLE_ALT 0x0800 /* Enable alternate synchronous */
506 #define TCR0_PERIOD_MASK 0x0700 /* Transfer rate */
507
508 #define TCR0_DO_WIDE_NEGO 0x0080 /* Do wide NEGO */
509 #define TCR0_DO_SYNC_NEGO 0x0040 /* Do sync NEGO */
510 #define TCR0_DISCONNECT_EN 0x0020 /* Disconnection enable */
511 #define TCR0_OFFSET_MASK 0x001F /* Offset number */
512
513 #define TRM_S1040_SCSI_TCR1 0x9E /* SCSI Target Control 1 (R/W) */
514 #define MAXTAG_MASK 0x7F00 /* Maximum tags (127) */
515 #define NON_TAG_BUSY 0x0080 /* Non tag command active */
516 #define ACTTAG_MASK 0x007F /* Active tags */
517
518 /************************************************************************/
519 /* */
520 /* The DMA register offset for TRM_S1040 */
521 /* */
522 /************************************************************************/
523 #define TRM_S1040_DMA_COMMAND 0xA0 /* DMA Command (R/W) */
524 #define DMACMD_SG 0x02 /* Enable HW S/G support */
525 #define DMACMD_DIR 0x01 /* 1 = read from SCSI write to Host */
526 #define XFERDATAIN_SG 0x0103 /* Transfer data in w/ SG */
527 #define XFERDATAOUT_SG 0x0102 /* Transfer data out w/ SG */
528 #define XFERDATAIN 0x0101 /* Transfer data in w/o SG */
529 #define XFERDATAOUT 0x0100 /* Transfer data out w/o SG */
530
531 #define TRM_S1040_DMA_FIFOCNT 0xA1 /* DMA FIFO Counter (R) */
532
533 #define TRM_S1040_DMA_CONTROL 0xA1 /* DMA Control (W) */
534 #define DMARESETMODULE 0x10 /* Reset PCI/DMA module */
535 #define STOPDMAXFER 0x08 /* Stop DMA transfer */
536 #define ABORTXFER 0x04 /* Abort DMA transfer */
537 #define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */
538 #define STARTDMAXFER 0x01 /* Start DMA transfer */
539
540 #define TRM_S1040_DMA_FIFOSTAT 0xA2 /* DMA FIFO Status (R) */
541
542 #define TRM_S1040_DMA_STATUS 0xA3 /* DMA Interrupt Status (R/W) */
543 #define XFERPENDING 0x80 /* Transfer pending */
544 #define SCSIBUSY 0x40 /* SCSI busy */
545 #define GLOBALINT 0x20 /* DMA_INTEN bit 0-4 set */
546 #define FORCEDMACOMP 0x10 /* Force DMA transfer complete */
547 #define DMAXFERERROR 0x08 /* DMA transfer error */
548 #define DMAXFERABORT 0x04 /* DMA transfer abort */
549 #define DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */
550 #define SCSICOMP 0x01 /* SCSI complete interrupt */
551
552 #define TRM_S1040_DMA_INTEN 0xA4 /* DMA Interrupt Enable (R/W) */
553 #define EN_FORCEDMACOMP 0x10 /* Force DMA transfer complete */
554 #define EN_DMAXFERERROR 0x08 /* DMA transfer error */
555 #define EN_DMAXFERABORT 0x04 /* DMA transfer abort */
556 #define EN_DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */
557 #define EN_SCSIINTR 0x01 /* Enable SCSI complete interrupt */
558
559 #define TRM_S1040_DMA_CONFIG 0xA6 /* DMA Configuration (R/W) */
560 #define DMA_ENHANCE 0x8000 /* Enable DMA enhance feature (SG?) */
561 #define DMA_PCI_DUAL_ADDR 0x4000 /* */
562 #define DMA_CFG_RES 0x2000 /* Always 1 */
563 #define DMA_AUTO_CLR_FIFO 0x1000 /* DISable DMA auto clear FIFO */
564 #define DMA_MEM_MULTI_READ 0x0800 /* */
565 #define DMA_MEM_WRITE_INVAL 0x0400 /* Memory write and invalidate */
566 #define DMA_FIFO_CTRL 0x0300 /* Control FIFO operation with DMA */
567 #define DMA_FIFO_HALF_HALF 0x0200 /* Keep half filled on both read/write */
568
569 #define TRM_S1040_DMA_XCNT 0xA8 /* DMA Transfer Counter (R/W), 24bits */
570 #define TRM_S1040_DMA_CXCNT 0xAC /* DMA Current Transfer Counter (R) */
571 #define TRM_S1040_DMA_XLOWADDR 0xB0 /* DMA Transfer Physical Low Address */
572 #define TRM_S1040_DMA_XHIGHADDR 0xB4 /* DMA Transfer Physical High Address */
573
574 /************************************************************************/
575 /* */
576 /* The general register offset for TRM_S1040 */
577 /* */
578 /************************************************************************/
579 #define TRM_S1040_GEN_CONTROL 0xD4 /* Global Control */
580 #define CTRL_LED 0x80 /* Control onboard LED */
581 #define EN_EEPROM 0x10 /* Enable EEPROM programming */
582 #define DIS_TERM 0x08 /* Disable onboard termination */
583 #define AUTOTERM 0x04 /* Enable Auto SCSI terminator */
584 #define LOW8TERM 0x02 /* Enable Lower 8 bit SCSI terminator */
585 #define UP8TERM 0x01 /* Enable Upper 8 bit SCSI terminator */
586
587 #define TRM_S1040_GEN_STATUS 0xD5 /* Global Status */
588 #define GTIMEOUT 0x80 /* Global timer reach 0 */
589 #define EXT68HIGH 0x40 /* Higher 8 bit connected externally */
590 #define INT68HIGH 0x20 /* Higher 8 bit connected internally */
591 #define CON5068 0x10 /* External 50/68 pin connected (low) */
592 #define CON68 0x08 /* Internal 68 pin connected (low) */
593 #define CON50 0x04 /* Internal 50 pin connected (low!) */
594 #define WIDESCSI 0x02 /* Wide SCSI card */
595 #define STATUS_LOAD_DEFAULT 0x01 /* */
596
597 #define TRM_S1040_GEN_NVRAM 0xD6 /* Serial NON-VOLATILE RAM port */
598 #define NVR_BITOUT 0x08 /* Serial data out */
599 #define NVR_BITIN 0x04 /* Serial data in */
600 #define NVR_CLOCK 0x02 /* Serial clock */
601 #define NVR_SELECT 0x01 /* Serial select */
602
603 #define TRM_S1040_GEN_EDATA 0xD7 /* Parallel EEPROM data port */
604 #define TRM_S1040_GEN_EADDRESS 0xD8 /* Parallel EEPROM address */
605 #define TRM_S1040_GEN_TIMER 0xDB /* Global timer */
606
607 /************************************************************************/
608 /* */
609 /* NvmTarCfg0: Target configuration byte 0 :..pDCB->DevMode */
610 /* */
611 /************************************************************************/
612 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */
613 #define NTC_DO_TAG_QUEUEING 0x10 /* Enable SCSI tag queuing */
614 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */
615 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */
616 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */
617 #define NTC_DO_PARITY_CHK 0x01 /* (it sould define at NAC) */
618 /* Parity check enable */
619
620 /************************************************************************/
621 /* */
622 /* Nvram Initiater bits definition */
623 /* */
624 /************************************************************************/
625
626 /************************************************************************/
627 /* */
628 /* Nvram Adapter Cfg bits definition */
629 /* */
630 /************************************************************************/
631 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */
632 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */
633 #define NAC_GREATER_1G 0x02 /* > 1G support enable */
634 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */
635 /* #define NAC_DO_PARITY_CHK 0x08 */ /* Parity check enable */
636
637 #endif
Tomato firmware and modifications.