[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / scsi / bfa / include / bfi / bfi_ctreg.h
| blob | 4e8f96811680bad0ecf45ef48c2bbb42c89b6271 |
1 /*
2 * Copyright (c) 2005-2009 Brocade Communications Systems, Inc.
3 * All rights reserved
4 * www.brocade.com
5 *
6 * Linux driver for Brocade Fibre Channel Host Bus Adapter.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License (GPL) Version 2 as
10 * published by the Free Software Foundation
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 */
18 /*
19 * bfi_ctreg.h catapult host block register definitions
20 *
21 * !!! Do not edit. Auto generated. !!!
22 */
24 #ifndef __BFI_CTREG_H__
25 #define __BFI_CTREG_H__
28 #define HOSTFN0_LPU_MBOX0_0 0x00019200
29 #define HOSTFN1_LPU_MBOX0_8 0x00019260
30 #define LPU_HOSTFN0_MBOX0_0 0x00019280
31 #define LPU_HOSTFN1_MBOX0_8 0x000192e0
32 #define HOSTFN2_LPU_MBOX0_0 0x00019400
33 #define HOSTFN3_LPU_MBOX0_8 0x00019460
34 #define LPU_HOSTFN2_MBOX0_0 0x00019480
35 #define LPU_HOSTFN3_MBOX0_8 0x000194e0
36 #define HOSTFN0_INT_STATUS 0x00014000
37 #define __HOSTFN0_HALT_OCCURRED 0x01000000
38 #define __HOSTFN0_INT_STATUS_LVL_MK 0x00f00000
39 #define __HOSTFN0_INT_STATUS_LVL_SH 20
40 #define __HOSTFN0_INT_STATUS_LVL(_v) ((_v) << __HOSTFN0_INT_STATUS_LVL_SH)
41 #define __HOSTFN0_INT_STATUS_P_MK 0x000f0000
42 #define __HOSTFN0_INT_STATUS_P_SH 16
43 #define __HOSTFN0_INT_STATUS_P(_v) ((_v) << __HOSTFN0_INT_STATUS_P_SH)
44 #define __HOSTFN0_INT_STATUS_F 0x0000ffff
45 #define HOSTFN0_INT_MSK 0x00014004
46 #define HOST_PAGE_NUM_FN0 0x00014008
47 #define __HOST_PAGE_NUM_FN 0x000001ff
48 #define HOST_MSIX_ERR_INDEX_FN0 0x0001400c
49 #define __MSIX_ERR_INDEX_FN 0x000001ff
50 #define HOSTFN1_INT_STATUS 0x00014100
51 #define __HOSTFN1_HALT_OCCURRED 0x01000000
52 #define __HOSTFN1_INT_STATUS_LVL_MK 0x00f00000
53 #define __HOSTFN1_INT_STATUS_LVL_SH 20
54 #define __HOSTFN1_INT_STATUS_LVL(_v) ((_v) << __HOSTFN1_INT_STATUS_LVL_SH)
55 #define __HOSTFN1_INT_STATUS_P_MK 0x000f0000
56 #define __HOSTFN1_INT_STATUS_P_SH 16
57 #define __HOSTFN1_INT_STATUS_P(_v) ((_v) << __HOSTFN1_INT_STATUS_P_SH)
58 #define __HOSTFN1_INT_STATUS_F 0x0000ffff
59 #define HOSTFN1_INT_MSK 0x00014104
60 #define HOST_PAGE_NUM_FN1 0x00014108
61 #define HOST_MSIX_ERR_INDEX_FN1 0x0001410c
62 #define APP_PLL_425_CTL_REG 0x00014204
63 #define __P_425_PLL_LOCK 0x80000000
64 #define __APP_PLL_425_SRAM_USE_100MHZ 0x00100000
65 #define __APP_PLL_425_RESET_TIMER_MK 0x000e0000
66 #define __APP_PLL_425_RESET_TIMER_SH 17
67 #define __APP_PLL_425_RESET_TIMER(_v) ((_v) << __APP_PLL_425_RESET_TIMER_SH)
68 #define __APP_PLL_425_LOGIC_SOFT_RESET 0x00010000
69 #define __APP_PLL_425_CNTLMT0_1_MK 0x0000c000
70 #define __APP_PLL_425_CNTLMT0_1_SH 14
71 #define __APP_PLL_425_CNTLMT0_1(_v) ((_v) << __APP_PLL_425_CNTLMT0_1_SH)
72 #define __APP_PLL_425_JITLMT0_1_MK 0x00003000
73 #define __APP_PLL_425_JITLMT0_1_SH 12
74 #define __APP_PLL_425_JITLMT0_1(_v) ((_v) << __APP_PLL_425_JITLMT0_1_SH)
75 #define __APP_PLL_425_HREF 0x00000800
76 #define __APP_PLL_425_HDIV 0x00000400
77 #define __APP_PLL_425_P0_1_MK 0x00000300
78 #define __APP_PLL_425_P0_1_SH 8
79 #define __APP_PLL_425_P0_1(_v) ((_v) << __APP_PLL_425_P0_1_SH)
80 #define __APP_PLL_425_Z0_2_MK 0x000000e0
81 #define __APP_PLL_425_Z0_2_SH 5
82 #define __APP_PLL_425_Z0_2(_v) ((_v) << __APP_PLL_425_Z0_2_SH)
83 #define __APP_PLL_425_RSEL200500 0x00000010
84 #define __APP_PLL_425_ENARST 0x00000008
85 #define __APP_PLL_425_BYPASS 0x00000004
86 #define __APP_PLL_425_LRESETN 0x00000002
87 #define __APP_PLL_425_ENABLE 0x00000001
88 #define APP_PLL_312_CTL_REG 0x00014208
89 #define __P_312_PLL_LOCK 0x80000000
90 #define __ENABLE_MAC_AHB_1 0x00800000
91 #define __ENABLE_MAC_AHB_0 0x00400000
92 #define __ENABLE_MAC_1 0x00200000
93 #define __ENABLE_MAC_0 0x00100000
94 #define __APP_PLL_312_RESET_TIMER_MK 0x000e0000
95 #define __APP_PLL_312_RESET_TIMER_SH 17
96 #define __APP_PLL_312_RESET_TIMER(_v) ((_v) << __APP_PLL_312_RESET_TIMER_SH)
97 #define __APP_PLL_312_LOGIC_SOFT_RESET 0x00010000
98 #define __APP_PLL_312_CNTLMT0_1_MK 0x0000c000
99 #define __APP_PLL_312_CNTLMT0_1_SH 14
100 #define __APP_PLL_312_CNTLMT0_1(_v) ((_v) << __APP_PLL_312_CNTLMT0_1_SH)
101 #define __APP_PLL_312_JITLMT0_1_MK 0x00003000
102 #define __APP_PLL_312_JITLMT0_1_SH 12
103 #define __APP_PLL_312_JITLMT0_1(_v) ((_v) << __APP_PLL_312_JITLMT0_1_SH)
104 #define __APP_PLL_312_HREF 0x00000800
105 #define __APP_PLL_312_HDIV 0x00000400
106 #define __APP_PLL_312_P0_1_MK 0x00000300
107 #define __APP_PLL_312_P0_1_SH 8
108 #define __APP_PLL_312_P0_1(_v) ((_v) << __APP_PLL_312_P0_1_SH)
109 #define __APP_PLL_312_Z0_2_MK 0x000000e0
110 #define __APP_PLL_312_Z0_2_SH 5
111 #define __APP_PLL_312_Z0_2(_v) ((_v) << __APP_PLL_312_Z0_2_SH)
112 #define __APP_PLL_312_RSEL200500 0x00000010
113 #define __APP_PLL_312_ENARST 0x00000008
114 #define __APP_PLL_312_BYPASS 0x00000004
115 #define __APP_PLL_312_LRESETN 0x00000002
116 #define __APP_PLL_312_ENABLE 0x00000001
117 #define MBIST_CTL_REG 0x00014220
118 #define __EDRAM_BISTR_START 0x00000004
119 #define __MBIST_RESET 0x00000002
120 #define __MBIST_START 0x00000001
121 #define MBIST_STAT_REG 0x00014224
122 #define __EDRAM_BISTR_STATUS 0x00000008
123 #define __EDRAM_BISTR_DONE 0x00000004
124 #define __MEM_BIT_STATUS 0x00000002
125 #define __MBIST_DONE 0x00000001
126 #define HOST_SEM0_REG 0x00014230
127 #define __HOST_SEMAPHORE 0x00000001
128 #define HOST_SEM1_REG 0x00014234
129 #define HOST_SEM2_REG 0x00014238
130 #define HOST_SEM3_REG 0x0001423c
131 #define HOST_SEM0_INFO_REG 0x00014240
132 #define HOST_SEM1_INFO_REG 0x00014244
133 #define HOST_SEM2_INFO_REG 0x00014248
134 #define HOST_SEM3_INFO_REG 0x0001424c
135 #define ETH_MAC_SER_REG 0x00014288
136 #define __APP_EMS_CKBUFAMPIN 0x00000020
137 #define __APP_EMS_REFCLKSEL 0x00000010
138 #define __APP_EMS_CMLCKSEL 0x00000008
139 #define __APP_EMS_REFCKBUFEN2 0x00000004
140 #define __APP_EMS_REFCKBUFEN1 0x00000002
141 #define __APP_EMS_CHANNEL_SEL 0x00000001
142 #define HOSTFN2_INT_STATUS 0x00014300
143 #define __HOSTFN2_HALT_OCCURRED 0x01000000
144 #define __HOSTFN2_INT_STATUS_LVL_MK 0x00f00000
145 #define __HOSTFN2_INT_STATUS_LVL_SH 20
146 #define __HOSTFN2_INT_STATUS_LVL(_v) ((_v) << __HOSTFN2_INT_STATUS_LVL_SH)
147 #define __HOSTFN2_INT_STATUS_P_MK 0x000f0000
148 #define __HOSTFN2_INT_STATUS_P_SH 16
149 #define __HOSTFN2_INT_STATUS_P(_v) ((_v) << __HOSTFN2_INT_STATUS_P_SH)
150 #define __HOSTFN2_INT_STATUS_F 0x0000ffff
151 #define HOSTFN2_INT_MSK 0x00014304
152 #define HOST_PAGE_NUM_FN2 0x00014308
153 #define HOST_MSIX_ERR_INDEX_FN2 0x0001430c
154 #define HOSTFN3_INT_STATUS 0x00014400
155 #define __HALT_OCCURRED 0x01000000
156 #define __HOSTFN3_INT_STATUS_LVL_MK 0x00f00000
157 #define __HOSTFN3_INT_STATUS_LVL_SH 20
158 #define __HOSTFN3_INT_STATUS_LVL(_v) ((_v) << __HOSTFN3_INT_STATUS_LVL_SH)
159 #define __HOSTFN3_INT_STATUS_P_MK 0x000f0000
160 #define __HOSTFN3_INT_STATUS_P_SH 16
161 #define __HOSTFN3_INT_STATUS_P(_v) ((_v) << __HOSTFN3_INT_STATUS_P_SH)
162 #define __HOSTFN3_INT_STATUS_F 0x0000ffff
163 #define HOSTFN3_INT_MSK 0x00014404
164 #define HOST_PAGE_NUM_FN3 0x00014408
165 #define HOST_MSIX_ERR_INDEX_FN3 0x0001440c
166 #define FNC_ID_REG 0x00014600
167 #define __FUNCTION_NUMBER 0x00000007
168 #define FNC_PERS_REG 0x00014604
169 #define __F3_FUNCTION_ACTIVE 0x80000000
170 #define __F3_FUNCTION_MODE 0x40000000
171 #define __F3_PORT_MAP_MK 0x30000000
172 #define __F3_PORT_MAP_SH 28
173 #define __F3_PORT_MAP(_v) ((_v) << __F3_PORT_MAP_SH)
174 #define __F3_VM_MODE 0x08000000
175 #define __F3_INTX_STATUS_MK 0x07000000
176 #define __F3_INTX_STATUS_SH 24
177 #define __F3_INTX_STATUS(_v) ((_v) << __F3_INTX_STATUS_SH)
178 #define __F2_FUNCTION_ACTIVE 0x00800000
179 #define __F2_FUNCTION_MODE 0x00400000
180 #define __F2_PORT_MAP_MK 0x00300000
181 #define __F2_PORT_MAP_SH 20
182 #define __F2_PORT_MAP(_v) ((_v) << __F2_PORT_MAP_SH)
183 #define __F2_VM_MODE 0x00080000
184 #define __F2_INTX_STATUS_MK 0x00070000
185 #define __F2_INTX_STATUS_SH 16
186 #define __F2_INTX_STATUS(_v) ((_v) << __F2_INTX_STATUS_SH)
187 #define __F1_FUNCTION_ACTIVE 0x00008000
188 #define __F1_FUNCTION_MODE 0x00004000
189 #define __F1_PORT_MAP_MK 0x00003000
190 #define __F1_PORT_MAP_SH 12
191 #define __F1_PORT_MAP(_v) ((_v) << __F1_PORT_MAP_SH)
192 #define __F1_VM_MODE 0x00000800
193 #define __F1_INTX_STATUS_MK 0x00000700
194 #define __F1_INTX_STATUS_SH 8
195 #define __F1_INTX_STATUS(_v) ((_v) << __F1_INTX_STATUS_SH)
196 #define __F0_FUNCTION_ACTIVE 0x00000080
197 #define __F0_FUNCTION_MODE 0x00000040
198 #define __F0_PORT_MAP_MK 0x00000030
199 #define __F0_PORT_MAP_SH 4
200 #define __F0_PORT_MAP(_v) ((_v) << __F0_PORT_MAP_SH)
201 #define __F0_VM_MODE 0x00000008
202 #define __F0_INTX_STATUS 0x00000007
209 };
210 #define OP_MODE 0x0001460c
211 #define __APP_ETH_CLK_LOWSPEED 0x00000004
212 #define __GLOBAL_CORECLK_HALFSPEED 0x00000002
213 #define __GLOBAL_FCOE_MODE 0x00000001
214 #define HOST_SEM4_REG 0x00014610
215 #define HOST_SEM5_REG 0x00014614
216 #define HOST_SEM6_REG 0x00014618
217 #define HOST_SEM7_REG 0x0001461c
218 #define HOST_SEM4_INFO_REG 0x00014620
219 #define HOST_SEM5_INFO_REG 0x00014624
220 #define HOST_SEM6_INFO_REG 0x00014628
221 #define HOST_SEM7_INFO_REG 0x0001462c
222 #define HOSTFN0_LPU0_MBOX0_CMD_STAT 0x00019000
223 #define __HOSTFN0_LPU0_MBOX0_INFO_MK 0xfffffffe
224 #define __HOSTFN0_LPU0_MBOX0_INFO_SH 1
225 #define __HOSTFN0_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN0_LPU0_MBOX0_INFO_SH)
226 #define __HOSTFN0_LPU0_MBOX0_CMD_STATUS 0x00000001
227 #define HOSTFN0_LPU1_MBOX0_CMD_STAT 0x00019004
228 #define __HOSTFN0_LPU1_MBOX0_INFO_MK 0xfffffffe
229 #define __HOSTFN0_LPU1_MBOX0_INFO_SH 1
230 #define __HOSTFN0_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN0_LPU1_MBOX0_INFO_SH)
231 #define __HOSTFN0_LPU1_MBOX0_CMD_STATUS 0x00000001
232 #define LPU0_HOSTFN0_MBOX0_CMD_STAT 0x00019008
233 #define __LPU0_HOSTFN0_MBOX0_INFO_MK 0xfffffffe
234 #define __LPU0_HOSTFN0_MBOX0_INFO_SH 1
235 #define __LPU0_HOSTFN0_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN0_MBOX0_INFO_SH)
236 #define __LPU0_HOSTFN0_MBOX0_CMD_STATUS 0x00000001
237 #define LPU1_HOSTFN0_MBOX0_CMD_STAT 0x0001900c
238 #define __LPU1_HOSTFN0_MBOX0_INFO_MK 0xfffffffe
239 #define __LPU1_HOSTFN0_MBOX0_INFO_SH 1
240 #define __LPU1_HOSTFN0_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN0_MBOX0_INFO_SH)
241 #define __LPU1_HOSTFN0_MBOX0_CMD_STATUS 0x00000001
242 #define HOSTFN1_LPU0_MBOX0_CMD_STAT 0x00019010
243 #define __HOSTFN1_LPU0_MBOX0_INFO_MK 0xfffffffe
244 #define __HOSTFN1_LPU0_MBOX0_INFO_SH 1
245 #define __HOSTFN1_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN1_LPU0_MBOX0_INFO_SH)
246 #define __HOSTFN1_LPU0_MBOX0_CMD_STATUS 0x00000001
247 #define HOSTFN1_LPU1_MBOX0_CMD_STAT 0x00019014
248 #define __HOSTFN1_LPU1_MBOX0_INFO_MK 0xfffffffe
249 #define __HOSTFN1_LPU1_MBOX0_INFO_SH 1
250 #define __HOSTFN1_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN1_LPU1_MBOX0_INFO_SH)
251 #define __HOSTFN1_LPU1_MBOX0_CMD_STATUS 0x00000001
252 #define LPU0_HOSTFN1_MBOX0_CMD_STAT 0x00019018
253 #define __LPU0_HOSTFN1_MBOX0_INFO_MK 0xfffffffe
254 #define __LPU0_HOSTFN1_MBOX0_INFO_SH 1
255 #define __LPU0_HOSTFN1_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN1_MBOX0_INFO_SH)
256 #define __LPU0_HOSTFN1_MBOX0_CMD_STATUS 0x00000001
257 #define LPU1_HOSTFN1_MBOX0_CMD_STAT 0x0001901c
258 #define __LPU1_HOSTFN1_MBOX0_INFO_MK 0xfffffffe
259 #define __LPU1_HOSTFN1_MBOX0_INFO_SH 1
260 #define __LPU1_HOSTFN1_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN1_MBOX0_INFO_SH)
261 #define __LPU1_HOSTFN1_MBOX0_CMD_STATUS 0x00000001
262 #define HOSTFN2_LPU0_MBOX0_CMD_STAT 0x00019150
263 #define __HOSTFN2_LPU0_MBOX0_INFO_MK 0xfffffffe
264 #define __HOSTFN2_LPU0_MBOX0_INFO_SH 1
265 #define __HOSTFN2_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN2_LPU0_MBOX0_INFO_SH)
266 #define __HOSTFN2_LPU0_MBOX0_CMD_STATUS 0x00000001
267 #define HOSTFN2_LPU1_MBOX0_CMD_STAT 0x00019154
268 #define __HOSTFN2_LPU1_MBOX0_INFO_MK 0xfffffffe
269 #define __HOSTFN2_LPU1_MBOX0_INFO_SH 1
270 #define __HOSTFN2_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN2_LPU1_MBOX0_INFO_SH)
271 #define __HOSTFN2_LPU1_MBOX0BOX0_CMD_STATUS 0x00000001
272 #define LPU0_HOSTFN2_MBOX0_CMD_STAT 0x00019158
273 #define __LPU0_HOSTFN2_MBOX0_INFO_MK 0xfffffffe
274 #define __LPU0_HOSTFN2_MBOX0_INFO_SH 1
275 #define __LPU0_HOSTFN2_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN2_MBOX0_INFO_SH)
276 #define __LPU0_HOSTFN2_MBOX0_CMD_STATUS 0x00000001
277 #define LPU1_HOSTFN2_MBOX0_CMD_STAT 0x0001915c
278 #define __LPU1_HOSTFN2_MBOX0_INFO_MK 0xfffffffe
279 #define __LPU1_HOSTFN2_MBOX0_INFO_SH 1
280 #define __LPU1_HOSTFN2_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN2_MBOX0_INFO_SH)
281 #define __LPU1_HOSTFN2_MBOX0_CMD_STATUS 0x00000001
282 #define HOSTFN3_LPU0_MBOX0_CMD_STAT 0x00019160
283 #define __HOSTFN3_LPU0_MBOX0_INFO_MK 0xfffffffe
284 #define __HOSTFN3_LPU0_MBOX0_INFO_SH 1
285 #define __HOSTFN3_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN3_LPU0_MBOX0_INFO_SH)
286 #define __HOSTFN3_LPU0_MBOX0_CMD_STATUS 0x00000001
287 #define HOSTFN3_LPU1_MBOX0_CMD_STAT 0x00019164
288 #define __HOSTFN3_LPU1_MBOX0_INFO_MK 0xfffffffe
289 #define __HOSTFN3_LPU1_MBOX0_INFO_SH 1
290 #define __HOSTFN3_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN3_LPU1_MBOX0_INFO_SH)
291 #define __HOSTFN3_LPU1_MBOX0_CMD_STATUS 0x00000001
292 #define LPU0_HOSTFN3_MBOX0_CMD_STAT 0x00019168
293 #define __LPU0_HOSTFN3_MBOX0_INFO_MK 0xfffffffe
294 #define __LPU0_HOSTFN3_MBOX0_INFO_SH 1
295 #define __LPU0_HOSTFN3_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN3_MBOX0_INFO_SH)
296 #define __LPU0_HOSTFN3_MBOX0_CMD_STATUS 0x00000001
297 #define LPU1_HOSTFN3_MBOX0_CMD_STAT 0x0001916c
298 #define __LPU1_HOSTFN3_MBOX0_INFO_MK 0xfffffffe
299 #define __LPU1_HOSTFN3_MBOX0_INFO_SH 1
300 #define __LPU1_HOSTFN3_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN3_MBOX0_INFO_SH)
301 #define __LPU1_HOSTFN3_MBOX0_CMD_STATUS 0x00000001
302 #define FW_INIT_HALT_P0 0x000191ac
303 #define __FW_INIT_HALT_P 0x00000001
304 #define FW_INIT_HALT_P1 0x000191bc
305 #define CPE_PI_PTR_Q0 0x00038000
306 #define __CPE_PI_UNUSED_MK 0xffff0000
307 #define __CPE_PI_UNUSED_SH 16
308 #define __CPE_PI_UNUSED(_v) ((_v) << __CPE_PI_UNUSED_SH)
309 #define __CPE_PI_PTR 0x0000ffff
310 #define CPE_PI_PTR_Q1 0x00038040
311 #define CPE_CI_PTR_Q0 0x00038004
312 #define __CPE_CI_UNUSED_MK 0xffff0000
313 #define __CPE_CI_UNUSED_SH 16
314 #define __CPE_CI_UNUSED(_v) ((_v) << __CPE_CI_UNUSED_SH)
315 #define __CPE_CI_PTR 0x0000ffff
316 #define CPE_CI_PTR_Q1 0x00038044
317 #define CPE_DEPTH_Q0 0x00038008
318 #define __CPE_DEPTH_UNUSED_MK 0xf8000000
319 #define __CPE_DEPTH_UNUSED_SH 27
320 #define __CPE_DEPTH_UNUSED(_v) ((_v) << __CPE_DEPTH_UNUSED_SH)
321 #define __CPE_MSIX_VEC_INDEX_MK 0x07ff0000
322 #define __CPE_MSIX_VEC_INDEX_SH 16
323 #define __CPE_MSIX_VEC_INDEX(_v) ((_v) << __CPE_MSIX_VEC_INDEX_SH)
324 #define __CPE_DEPTH 0x0000ffff
325 #define CPE_DEPTH_Q1 0x00038048
326 #define CPE_QCTRL_Q0 0x0003800c
327 #define __CPE_CTRL_UNUSED30_MK 0xfc000000
328 #define __CPE_CTRL_UNUSED30_SH 26
329 #define __CPE_CTRL_UNUSED30(_v) ((_v) << __CPE_CTRL_UNUSED30_SH)
330 #define __CPE_FUNC_INT_CTRL_MK 0x03000000
331 #define __CPE_FUNC_INT_CTRL_SH 24
332 #define __CPE_FUNC_INT_CTRL(_v) ((_v) << __CPE_FUNC_INT_CTRL_SH)
338 };
339 #define __CPE_CTRL_UNUSED20_MK 0x00f00000
340 #define __CPE_CTRL_UNUSED20_SH 20
341 #define __CPE_CTRL_UNUSED20(_v) ((_v) << __CPE_CTRL_UNUSED20_SH)
342 #define __CPE_SCI_TH_MK 0x000f0000
343 #define __CPE_SCI_TH_SH 16
344 #define __CPE_SCI_TH(_v) ((_v) << __CPE_SCI_TH_SH)
345 #define __CPE_CTRL_UNUSED10_MK 0x0000c000
346 #define __CPE_CTRL_UNUSED10_SH 14
347 #define __CPE_CTRL_UNUSED10(_v) ((_v) << __CPE_CTRL_UNUSED10_SH)
348 #define __CPE_ACK_PENDING 0x00002000
349 #define __CPE_CTRL_UNUSED40_MK 0x00001c00
350 #define __CPE_CTRL_UNUSED40_SH 10
351 #define __CPE_CTRL_UNUSED40(_v) ((_v) << __CPE_CTRL_UNUSED40_SH)
352 #define __CPE_PCIEID_MK 0x00000300
353 #define __CPE_PCIEID_SH 8
354 #define __CPE_PCIEID(_v) ((_v) << __CPE_PCIEID_SH)
355 #define __CPE_CTRL_UNUSED00_MK 0x000000fe
356 #define __CPE_CTRL_UNUSED00_SH 1
357 #define __CPE_CTRL_UNUSED00(_v) ((_v) << __CPE_CTRL_UNUSED00_SH)
358 #define __CPE_ESIZE 0x00000001
359 #define CPE_QCTRL_Q1 0x0003804c
360 #define __CPE_CTRL_UNUSED31_MK 0xfc000000
361 #define __CPE_CTRL_UNUSED31_SH 26
362 #define __CPE_CTRL_UNUSED31(_v) ((_v) << __CPE_CTRL_UNUSED31_SH)
363 #define __CPE_CTRL_UNUSED21_MK 0x00f00000
364 #define __CPE_CTRL_UNUSED21_SH 20
365 #define __CPE_CTRL_UNUSED21(_v) ((_v) << __CPE_CTRL_UNUSED21_SH)
366 #define __CPE_CTRL_UNUSED11_MK 0x0000c000
367 #define __CPE_CTRL_UNUSED11_SH 14
368 #define __CPE_CTRL_UNUSED11(_v) ((_v) << __CPE_CTRL_UNUSED11_SH)
369 #define __CPE_CTRL_UNUSED41_MK 0x00001c00
370 #define __CPE_CTRL_UNUSED41_SH 10
371 #define __CPE_CTRL_UNUSED41(_v) ((_v) << __CPE_CTRL_UNUSED41_SH)
372 #define __CPE_CTRL_UNUSED01_MK 0x000000fe
373 #define __CPE_CTRL_UNUSED01_SH 1
374 #define __CPE_CTRL_UNUSED01(_v) ((_v) << __CPE_CTRL_UNUSED01_SH)
375 #define RME_PI_PTR_Q0 0x00038020
376 #define __LATENCY_TIME_STAMP_MK 0xffff0000
377 #define __LATENCY_TIME_STAMP_SH 16
378 #define __LATENCY_TIME_STAMP(_v) ((_v) << __LATENCY_TIME_STAMP_SH)
379 #define __RME_PI_PTR 0x0000ffff
380 #define RME_PI_PTR_Q1 0x00038060
381 #define RME_CI_PTR_Q0 0x00038024
382 #define __DELAY_TIME_STAMP_MK 0xffff0000
383 #define __DELAY_TIME_STAMP_SH 16
384 #define __DELAY_TIME_STAMP(_v) ((_v) << __DELAY_TIME_STAMP_SH)
385 #define __RME_CI_PTR 0x0000ffff
386 #define RME_CI_PTR_Q1 0x00038064
387 #define RME_DEPTH_Q0 0x00038028
388 #define __RME_DEPTH_UNUSED_MK 0xf8000000
389 #define __RME_DEPTH_UNUSED_SH 27
390 #define __RME_DEPTH_UNUSED(_v) ((_v) << __RME_DEPTH_UNUSED_SH)
391 #define __RME_MSIX_VEC_INDEX_MK 0x07ff0000
392 #define __RME_MSIX_VEC_INDEX_SH 16
393 #define __RME_MSIX_VEC_INDEX(_v) ((_v) << __RME_MSIX_VEC_INDEX_SH)
394 #define __RME_DEPTH 0x0000ffff
395 #define RME_DEPTH_Q1 0x00038068
396 #define RME_QCTRL_Q0 0x0003802c
397 #define __RME_INT_LATENCY_TIMER_MK 0xff000000
398 #define __RME_INT_LATENCY_TIMER_SH 24
399 #define __RME_INT_LATENCY_TIMER(_v) ((_v) << __RME_INT_LATENCY_TIMER_SH)
400 #define __RME_INT_DELAY_TIMER_MK 0x00ff0000
401 #define __RME_INT_DELAY_TIMER_SH 16
402 #define __RME_INT_DELAY_TIMER(_v) ((_v) << __RME_INT_DELAY_TIMER_SH)
403 #define __RME_INT_DELAY_DISABLE 0x00008000
404 #define __RME_DLY_DELAY_DISABLE 0x00004000
405 #define __RME_ACK_PENDING 0x00002000
406 #define __RME_FULL_INTERRUPT_DISABLE 0x00001000
407 #define __RME_CTRL_UNUSED10_MK 0x00000c00
408 #define __RME_CTRL_UNUSED10_SH 10
409 #define __RME_CTRL_UNUSED10(_v) ((_v) << __RME_CTRL_UNUSED10_SH)
410 #define __RME_PCIEID_MK 0x00000300
411 #define __RME_PCIEID_SH 8
412 #define __RME_PCIEID(_v) ((_v) << __RME_PCIEID_SH)
413 #define __RME_CTRL_UNUSED00_MK 0x000000fe
414 #define __RME_CTRL_UNUSED00_SH 1
415 #define __RME_CTRL_UNUSED00(_v) ((_v) << __RME_CTRL_UNUSED00_SH)
416 #define __RME_ESIZE 0x00000001
417 #define RME_QCTRL_Q1 0x0003806c
418 #define __RME_CTRL_UNUSED11_MK 0x00000c00
419 #define __RME_CTRL_UNUSED11_SH 10
420 #define __RME_CTRL_UNUSED11(_v) ((_v) << __RME_CTRL_UNUSED11_SH)
421 #define __RME_CTRL_UNUSED01_MK 0x000000fe
422 #define __RME_CTRL_UNUSED01_SH 1
423 #define __RME_CTRL_UNUSED01(_v) ((_v) << __RME_CTRL_UNUSED01_SH)
424 #define PSS_CTL_REG 0x00018800
425 #define __PSS_I2C_CLK_DIV_MK 0x007f0000
426 #define __PSS_I2C_CLK_DIV_SH 16
427 #define __PSS_I2C_CLK_DIV(_v) ((_v) << __PSS_I2C_CLK_DIV_SH)
428 #define __PSS_LMEM_INIT_DONE 0x00001000
429 #define __PSS_LMEM_RESET 0x00000200
430 #define __PSS_LMEM_INIT_EN 0x00000100
431 #define __PSS_LPU1_RESET 0x00000002
432 #define __PSS_LPU0_RESET 0x00000001
433 #define PSS_ERR_STATUS_REG 0x00018810
434 #define __PSS_LPU1_TCM_READ_ERR 0x00200000
435 #define __PSS_LPU0_TCM_READ_ERR 0x00100000
436 #define __PSS_LMEM5_CORR_ERR 0x00080000
437 #define __PSS_LMEM4_CORR_ERR 0x00040000
438 #define __PSS_LMEM3_CORR_ERR 0x00020000
439 #define __PSS_LMEM2_CORR_ERR 0x00010000
440 #define __PSS_LMEM1_CORR_ERR 0x00008000
441 #define __PSS_LMEM0_CORR_ERR 0x00004000
442 #define __PSS_LMEM5_UNCORR_ERR 0x00002000
443 #define __PSS_LMEM4_UNCORR_ERR 0x00001000
444 #define __PSS_LMEM3_UNCORR_ERR 0x00000800
445 #define __PSS_LMEM2_UNCORR_ERR 0x00000400
446 #define __PSS_LMEM1_UNCORR_ERR 0x00000200
447 #define __PSS_LMEM0_UNCORR_ERR 0x00000100
448 #define __PSS_BAL_PERR 0x00000080
449 #define __PSS_DIP_IF_ERR 0x00000040
450 #define __PSS_IOH_IF_ERR 0x00000020
451 #define __PSS_TDS_IF_ERR 0x00000010
452 #define __PSS_RDS_IF_ERR 0x00000008
453 #define __PSS_SGM_IF_ERR 0x00000004
454 #define __PSS_LPU1_RAM_ERR 0x00000002
455 #define __PSS_LPU0_RAM_ERR 0x00000001
456 #define ERR_SET_REG 0x00018818
457 #define __PSS_ERR_STATUS_SET 0x003fffff
458 #define PMM_1T_RESET_REG_P0 0x0002381c
459 #define __PMM_1T_RESET_P 0x00000001
460 #define PMM_1T_RESET_REG_P1 0x00023c1c
461 #define HQM_QSET0_RXQ_DRBL_P0 0x00038000
462 #define __RXQ0_ADD_VECTORS_P 0x80000000
463 #define __RXQ0_STOP_P 0x40000000
464 #define __RXQ0_PRD_PTR_P 0x0000ffff
465 #define HQM_QSET1_RXQ_DRBL_P0 0x00038080
466 #define __RXQ1_ADD_VECTORS_P 0x80000000
467 #define __RXQ1_STOP_P 0x40000000
468 #define __RXQ1_PRD_PTR_P 0x0000ffff
469 #define HQM_QSET0_RXQ_DRBL_P1 0x0003c000
470 #define HQM_QSET1_RXQ_DRBL_P1 0x0003c080
471 #define HQM_QSET0_TXQ_DRBL_P0 0x00038020
472 #define __TXQ0_ADD_VECTORS_P 0x80000000
473 #define __TXQ0_STOP_P 0x40000000
474 #define __TXQ0_PRD_PTR_P 0x0000ffff
475 #define HQM_QSET1_TXQ_DRBL_P0 0x000380a0
476 #define __TXQ1_ADD_VECTORS_P 0x80000000
477 #define __TXQ1_STOP_P 0x40000000
478 #define __TXQ1_PRD_PTR_P 0x0000ffff
479 #define HQM_QSET0_TXQ_DRBL_P1 0x0003c020
480 #define HQM_QSET1_TXQ_DRBL_P1 0x0003c0a0
481 #define HQM_QSET0_IB_DRBL_1_P0 0x00038040
482 #define __IB1_0_ACK_P 0x80000000
483 #define __IB1_0_DISABLE_P 0x40000000
484 #define __IB1_0_NUM_OF_ACKED_EVENTS_P 0x0000ffff
485 #define HQM_QSET1_IB_DRBL_1_P0 0x000380c0
486 #define __IB1_1_ACK_P 0x80000000
487 #define __IB1_1_DISABLE_P 0x40000000
488 #define __IB1_1_NUM_OF_ACKED_EVENTS_P 0x0000ffff
489 #define HQM_QSET0_IB_DRBL_1_P1 0x0003c040
490 #define HQM_QSET1_IB_DRBL_1_P1 0x0003c0c0
491 #define HQM_QSET0_IB_DRBL_2_P0 0x00038060
492 #define __IB2_0_ACK_P 0x80000000
493 #define __IB2_0_DISABLE_P 0x40000000
494 #define __IB2_0_NUM_OF_ACKED_EVENTS_P 0x0000ffff
495 #define HQM_QSET1_IB_DRBL_2_P0 0x000380e0
496 #define __IB2_1_ACK_P 0x80000000
497 #define __IB2_1_DISABLE_P 0x40000000
498 #define __IB2_1_NUM_OF_ACKED_EVENTS_P 0x0000ffff
499 #define HQM_QSET0_IB_DRBL_2_P1 0x0003c060
500 #define HQM_QSET1_IB_DRBL_2_P1 0x0003c0e0
503 /*
504 * These definitions are either in error/missing in spec. Its auto-generated
505 * from hard coded values in regparse.pl.
506 */
507 #define __EMPHPOST_AT_4G_MK_FIX 0x0000001c
508 #define __EMPHPOST_AT_4G_SH_FIX 0x00000002
509 #define __EMPHPRE_AT_4G_FIX 0x00000003
510 #define __SFP_TXRATE_EN_FIX 0x00000100
511 #define __SFP_RXRATE_EN_FIX 0x00000080
514 /*
515 * These register definitions are auto-generated from hard coded values
516 * in regparse.pl.
517 */
520 /*
521 * These register mapping definitions are auto-generated from mapping tables
522 * in regparse.pl.
523 */
524 #define BFA_IOC0_HBEAT_REG HOST_SEM0_INFO_REG
525 #define BFA_IOC0_STATE_REG HOST_SEM1_INFO_REG
526 #define BFA_IOC1_HBEAT_REG HOST_SEM2_INFO_REG
527 #define BFA_IOC1_STATE_REG HOST_SEM3_INFO_REG
528 #define BFA_FW_USE_COUNT HOST_SEM4_INFO_REG
530 #define CPE_DEPTH_Q(__n) \
531 (CPE_DEPTH_Q0 + (__n) * (CPE_DEPTH_Q1 - CPE_DEPTH_Q0))
532 #define CPE_QCTRL_Q(__n) \
533 (CPE_QCTRL_Q0 + (__n) * (CPE_QCTRL_Q1 - CPE_QCTRL_Q0))
534 #define CPE_PI_PTR_Q(__n) \
535 (CPE_PI_PTR_Q0 + (__n) * (CPE_PI_PTR_Q1 - CPE_PI_PTR_Q0))
536 #define CPE_CI_PTR_Q(__n) \
537 (CPE_CI_PTR_Q0 + (__n) * (CPE_CI_PTR_Q1 - CPE_CI_PTR_Q0))
538 #define RME_DEPTH_Q(__n) \
539 (RME_DEPTH_Q0 + (__n) * (RME_DEPTH_Q1 - RME_DEPTH_Q0))
540 #define RME_QCTRL_Q(__n) \
541 (RME_QCTRL_Q0 + (__n) * (RME_QCTRL_Q1 - RME_QCTRL_Q0))
542 #define RME_PI_PTR_Q(__n) \
543 (RME_PI_PTR_Q0 + (__n) * (RME_PI_PTR_Q1 - RME_PI_PTR_Q0))
544 #define RME_CI_PTR_Q(__n) \
545 (RME_CI_PTR_Q0 + (__n) * (RME_CI_PTR_Q1 - RME_CI_PTR_Q0))
546 #define HQM_QSET_RXQ_DRBL_P0(__n) \
547 (HQM_QSET0_RXQ_DRBL_P0 + (__n) * (HQM_QSET1_RXQ_DRBL_P0 - \
548 HQM_QSET0_RXQ_DRBL_P0))
549 #define HQM_QSET_TXQ_DRBL_P0(__n) \
550 (HQM_QSET0_TXQ_DRBL_P0 + (__n) * (HQM_QSET1_TXQ_DRBL_P0 - \
551 HQM_QSET0_TXQ_DRBL_P0))
552 #define HQM_QSET_IB_DRBL_1_P0(__n) \
553 (HQM_QSET0_IB_DRBL_1_P0 + (__n) * (HQM_QSET1_IB_DRBL_1_P0 - \
554 HQM_QSET0_IB_DRBL_1_P0))
555 #define HQM_QSET_IB_DRBL_2_P0(__n) \
556 (HQM_QSET0_IB_DRBL_2_P0 + (__n) * (HQM_QSET1_IB_DRBL_2_P0 - \
557 HQM_QSET0_IB_DRBL_2_P0))
558 #define HQM_QSET_RXQ_DRBL_P1(__n) \
559 (HQM_QSET0_RXQ_DRBL_P1 + (__n) * (HQM_QSET1_RXQ_DRBL_P1 - \
560 HQM_QSET0_RXQ_DRBL_P1))
561 #define HQM_QSET_TXQ_DRBL_P1(__n) \
562 (HQM_QSET0_TXQ_DRBL_P1 + (__n) * (HQM_QSET1_TXQ_DRBL_P1 - \
563 HQM_QSET0_TXQ_DRBL_P1))
564 #define HQM_QSET_IB_DRBL_1_P1(__n) \
565 (HQM_QSET0_IB_DRBL_1_P1 + (__n) * (HQM_QSET1_IB_DRBL_1_P1 - \
566 HQM_QSET0_IB_DRBL_1_P1))
567 #define HQM_QSET_IB_DRBL_2_P1(__n) \
568 (HQM_QSET0_IB_DRBL_2_P1 + (__n) * (HQM_QSET1_IB_DRBL_2_P1 - \
569 HQM_QSET0_IB_DRBL_2_P1))
571 #define CPE_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
572 #define RME_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
573 #define CPE_Q_MASK(__q) ((__q) & 0x3)
574 #define RME_Q_MASK(__q) ((__q) & 0x3)
577 /*
578 * PCI MSI-X vector defines
579 */
591 };
593 /*
594 * And corresponding host interrupt status bit field defines
595 */
596 #define __HFN_INT_CPE_Q0 0x00000001U
597 #define __HFN_INT_CPE_Q1 0x00000002U
598 #define __HFN_INT_CPE_Q2 0x00000004U
599 #define __HFN_INT_CPE_Q3 0x00000008U
600 #define __HFN_INT_CPE_Q4 0x00000010U
601 #define __HFN_INT_CPE_Q5 0x00000020U
602 #define __HFN_INT_CPE_Q6 0x00000040U
603 #define __HFN_INT_CPE_Q7 0x00000080U
604 #define __HFN_INT_RME_Q0 0x00000100U
605 #define __HFN_INT_RME_Q1 0x00000200U
606 #define __HFN_INT_RME_Q2 0x00000400U
607 #define __HFN_INT_RME_Q3 0x00000800U
608 #define __HFN_INT_RME_Q4 0x00001000U
609 #define __HFN_INT_RME_Q5 0x00002000U
610 #define __HFN_INT_RME_Q6 0x00004000U
611 #define __HFN_INT_RME_Q7 0x00008000U
612 #define __HFN_INT_ERR_EMC 0x00010000U
613 #define __HFN_INT_ERR_LPU0 0x00020000U
614 #define __HFN_INT_ERR_LPU1 0x00040000U
615 #define __HFN_INT_ERR_PSS 0x00080000U
616 #define __HFN_INT_MBOX_LPU0 0x00100000U
617 #define __HFN_INT_MBOX_LPU1 0x00200000U
618 #define __HFN_INT_MBOX1_LPU0 0x00400000U
619 #define __HFN_INT_MBOX1_LPU1 0x00800000U
620 #define __HFN_INT_LL_HALT 0x01000000U
621 #define __HFN_INT_CPE_MASK 0x000000ffU
622 #define __HFN_INT_RME_MASK 0x0000ff00U
625 /*
626 * catapult memory map.
627 */
628 #define LL_PGN_HQM0 0x0096
629 #define LL_PGN_HQM1 0x0097
630 #define PSS_SMEM_PAGE_START 0x8000
631 #define PSS_SMEM_PGNUM(_pg0, _ma) ((_pg0) + ((_ma) >> 15))
632 #define PSS_SMEM_PGOFF(_ma) ((_ma) & 0x7fff)
634 /*
635 * End of catapult memory map
636 */