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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / scsi / be2iscsi / be_main.h
blob90eb74f6bcabae536e298542910c2edf73179829
1 /**
2 * Copyright (C) 2005 - 2010 ServerEngines
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Written by: Jayamohan Kallickal (jayamohank@serverengines.com)
11 *
12 * Contact Information:
13 * linux-drivers@serverengines.com
14 *
15 * ServerEngines
16 * 209 N. Fair Oaks Ave
17 * Sunnyvale, CA 94085
18 *
19 */
20
21 #ifndef _BEISCSI_MAIN_
22 #define _BEISCSI_MAIN_
23
24 #include <linux/kernel.h>
25 #include <linux/pci.h>
26 #include <linux/if_ether.h>
27 #include <linux/in.h>
28 #include <scsi/scsi.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <scsi/scsi_device.h>
31 #include <scsi/scsi_host.h>
32 #include <scsi/iscsi_proto.h>
33 #include <scsi/libiscsi.h>
34 #include <scsi/scsi_transport_iscsi.h>
35
36 #include "be.h"
37 #define DRV_NAME "be2iscsi"
38 #define BUILD_STR "2.0.549.0"
39 #define BE_NAME "ServerEngines BladeEngine2" \
40 "Linux iSCSI Driver version" BUILD_STR
41 #define DRV_DESC BE_NAME " " "Driver"
42
43 #define BE_VENDOR_ID 0x19A2
44 /* DEVICE ID's for BE2 */
45 #define BE_DEVICE_ID1 0x212
46 #define OC_DEVICE_ID1 0x702
47 #define OC_DEVICE_ID2 0x703
48
49 /* DEVICE ID's for BE3 */
50 #define BE_DEVICE_ID2 0x222
51 #define OC_DEVICE_ID3 0x712
52
53 #define BE2_IO_DEPTH 1024
54 #define BE2_MAX_SESSIONS 256
55 #define BE2_CMDS_PER_CXN 128
56 #define BE2_TMFS 16
57 #define BE2_NOPOUT_REQ 16
58 #define BE2_SGE 32
59 #define BE2_DEFPDU_HDR_SZ 64
60 #define BE2_DEFPDU_DATA_SZ 8192
61
62 #define MAX_CPUS 31
63 #define BEISCSI_SGLIST_ELEMENTS 30
64
65 #define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
66 #define BEISCSI_MAX_SECTORS 2048 /* scsi_host->max_sectors */
67
68 #define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
69 #define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
70 #define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
71 #define BEISCSI_MAX_FRAGS_INIT 192
72 #define BE_NUM_MSIX_ENTRIES 1
73
74 #define MPU_EP_CONTROL 0
75 #define MPU_EP_SEMAPHORE 0xac
76 #define BE2_SOFT_RESET 0x5c
77 #define BE2_PCI_ONLINE0 0xb0
78 #define BE2_PCI_ONLINE1 0xb4
79 #define BE2_SET_RESET 0x80
80 #define BE2_MPU_IRAM_ONLINE 0x00000080
81
82 #define BE_SENSE_INFO_SIZE 258
83 #define BE_ISCSI_PDU_HEADER_SIZE 64
84 #define BE_MIN_MEM_SIZE 16384
85 #define MAX_CMD_SZ 65536
86 #define IIOC_SCSI_DATA 0x05 /* Write Operation */
87
88 #define DBG_LVL 0x00000001
89 #define DBG_LVL_1 0x00000001
90 #define DBG_LVL_2 0x00000002
91 #define DBG_LVL_3 0x00000004
92 #define DBG_LVL_4 0x00000008
93 #define DBG_LVL_5 0x00000010
94 #define DBG_LVL_6 0x00000020
95 #define DBG_LVL_7 0x00000040
96 #define DBG_LVL_8 0x00000080
97
98 #define SE_DEBUG(debug_mask, fmt, args...) \
99 do { \
100 if (debug_mask & DBG_LVL) { \
101 printk(KERN_ERR "(%s():%d):", __func__, __LINE__);\
102 printk(fmt, ##args); \
103 } \
104 } while (0);
105
106 #define BE_ADAPTER_UP 0x00000000
107 #define BE_ADAPTER_LINK_DOWN 0x00000001
108 /**
109 * hardware needs the async PDU buffers to be posted in multiples of 8
110 * So have atleast 8 of them by default
111 */
112
113 #define HWI_GET_ASYNC_PDU_CTX(phwi) (phwi->phwi_ctxt->pasync_ctx)
114
115 /********* Memory BAR register ************/
116 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
117 /**
118 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
119 * Disable" may still globally block interrupts in addition to individual
120 * interrupt masks; a mechanism for the device driver to block all interrupts
121 * atomically without having to arbitrate for the PCI Interrupt Disable bit
122 * with the OS.
123 */
124 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
125
126 /********* ISR0 Register offset **********/
127 #define CEV_ISR0_OFFSET 0xC18
128 #define CEV_ISR_SIZE 4
129
130 /**
131 * Macros for reading/writing a protection domain or CSR registers
132 * in BladeEngine.
133 */
134
135 #define DB_TXULP0_OFFSET 0x40
136 #define DB_RXULP0_OFFSET 0xA0
137 /********* Event Q door bell *************/
138 #define DB_EQ_OFFSET DB_CQ_OFFSET
139 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
140 /* Clear the interrupt for this eq */
141 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
142 /* Must be 1 */
143 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
144 /* Number of event entries processed */
145 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
146 /* Rearm bit */
147 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
148
149 /********* Compl Q door bell *************/
150 #define DB_CQ_OFFSET 0x120
151 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
152 /* Number of event entries processed */
153 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
154 /* Rearm bit */
155 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
156
157 #define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
158 #define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\
159 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id)
160 #define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\
161 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id)
162
163 #define PAGES_REQUIRED(x) \
164 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
165
166 enum be_mem_enum {
167 HWI_MEM_ADDN_CONTEXT,
168 HWI_MEM_WRB,
169 HWI_MEM_WRBH,
170 HWI_MEM_SGLH,
171 HWI_MEM_SGE,
172 HWI_MEM_ASYNC_HEADER_BUF, /* 5 */
173 HWI_MEM_ASYNC_DATA_BUF,
174 HWI_MEM_ASYNC_HEADER_RING,
175 HWI_MEM_ASYNC_DATA_RING,
176 HWI_MEM_ASYNC_HEADER_HANDLE,
177 HWI_MEM_ASYNC_DATA_HANDLE, /* 10 */
178 HWI_MEM_ASYNC_PDU_CONTEXT,
179 ISCSI_MEM_GLOBAL_HEADER,
180 SE_MEM_MAX
181 };
182
183 struct be_bus_address32 {
184 unsigned int address_lo;
185 unsigned int address_hi;
186 };
187
188 struct be_bus_address64 {
189 unsigned long long address;
190 };
191
192 struct be_bus_address {
193 union {
194 struct be_bus_address32 a32;
195 struct be_bus_address64 a64;
196 } u;
197 };
198
199 struct mem_array {
200 struct be_bus_address bus_address; /* Bus address of location */
201 void *virtual_address; /* virtual address to the location */
202 unsigned int size; /* Size required by memory block */
203 };
204
205 struct be_mem_descriptor {
206 unsigned int index; /* Index of this memory parameter */
207 unsigned int category; /* type indicates cached/non-cached */
208 unsigned int num_elements; /* number of elements in this
209 * descriptor
210 */
211 unsigned int alignment_mask; /* Alignment mask for this block */
212 unsigned int size_in_bytes; /* Size required by memory block */
213 struct mem_array *mem_array;
214 };
215
216 struct sgl_handle {
217 unsigned int sgl_index;
218 unsigned int type;
219 unsigned int cid;
220 struct iscsi_task *task;
221 struct iscsi_sge *pfrag;
222 };
223
224 struct hba_parameters {
225 unsigned int ios_per_ctrl;
226 unsigned int cxns_per_ctrl;
227 unsigned int asyncpdus_per_ctrl;
228 unsigned int icds_per_ctrl;
229 unsigned int num_sge_per_io;
230 unsigned int defpdu_hdr_sz;
231 unsigned int defpdu_data_sz;
232 unsigned int num_cq_entries;
233 unsigned int num_eq_entries;
234 unsigned int wrbs_per_cxn;
235 unsigned int crashmode;
236 unsigned int hba_num;
237
238 unsigned int mgmt_ws_sz;
239 unsigned int hwi_ws_sz;
240
241 unsigned int eto;
242 unsigned int ldto;
243
244 unsigned int dbg_flags;
245 unsigned int num_cxn;
246
247 unsigned int eq_timer;
248 /**
249 * These are calculated from other params. They're here
250 * for debug purposes
251 */
252 unsigned int num_mcc_pages;
253 unsigned int num_mcc_cq_pages;
254 unsigned int num_cq_pages;
255 unsigned int num_eq_pages;
256
257 unsigned int num_async_pdu_buf_pages;
258 unsigned int num_async_pdu_buf_sgl_pages;
259 unsigned int num_async_pdu_buf_cq_pages;
260
261 unsigned int num_async_pdu_hdr_pages;
262 unsigned int num_async_pdu_hdr_sgl_pages;
263 unsigned int num_async_pdu_hdr_cq_pages;
264
265 unsigned int num_sge;
266 };
267
268 struct invalidate_command_table {
269 unsigned short icd;
270 unsigned short cid;
271 } __packed;
272
273 struct beiscsi_hba {
274 struct hba_parameters params;
275 struct hwi_controller *phwi_ctrlr;
276 unsigned int mem_req[SE_MEM_MAX];
277 /* PCI BAR mapped addresses */
278 u8 __iomem *csr_va; /* CSR */
279 u8 __iomem *db_va; /* Door Bell */
280 u8 __iomem *pci_va; /* PCI Config */
281 struct be_bus_address csr_pa; /* CSR */
282 struct be_bus_address db_pa; /* CSR */
283 struct be_bus_address pci_pa; /* CSR */
284 /* PCI representation of our HBA */
285 struct pci_dev *pcidev;
286 unsigned int state;
287 unsigned short asic_revision;
288 unsigned int num_cpus;
289 unsigned int nxt_cqid;
290 struct msix_entry msix_entries[MAX_CPUS + 1];
291 bool msix_enabled;
292 struct be_mem_descriptor *init_mem;
293
294 unsigned short io_sgl_alloc_index;
295 unsigned short io_sgl_free_index;
296 unsigned short io_sgl_hndl_avbl;
297 struct sgl_handle **io_sgl_hndl_base;
298 struct sgl_handle **sgl_hndl_array;
299
300 unsigned short eh_sgl_alloc_index;
301 unsigned short eh_sgl_free_index;
302 unsigned short eh_sgl_hndl_avbl;
303 struct sgl_handle **eh_sgl_hndl_base;
304 spinlock_t io_sgl_lock;
305 spinlock_t mgmt_sgl_lock;
306 spinlock_t isr_lock;
307 unsigned int age;
308 unsigned short avlbl_cids;
309 unsigned short cid_alloc;
310 unsigned short cid_free;
311 struct beiscsi_conn *conn_table[BE2_MAX_SESSIONS * 2];
312 struct list_head hba_queue;
313 unsigned short *cid_array;
314 struct iscsi_endpoint **ep_array;
315 struct iscsi_boot_kset *boot_kset;
316 struct Scsi_Host *shost;
317 struct {
318 /**
319 * group together since they are used most frequently
320 * for cid to cri conversion
321 */
322 unsigned int iscsi_cid_start;
323 unsigned int phys_port;
324
325 unsigned int isr_offset;
326 unsigned int iscsi_icd_start;
327 unsigned int iscsi_cid_count;
328 unsigned int iscsi_icd_count;
329 unsigned int pci_function;
330
331 unsigned short cid_alloc;
332 unsigned short cid_free;
333 unsigned short avlbl_cids;
334 unsigned short iscsi_features;
335 spinlock_t cid_lock;
336 } fw_config;
337
338 u8 mac_address[ETH_ALEN];
339 unsigned short todo_cq;
340 unsigned short todo_mcc_cq;
341 char wq_name[20];
342 struct workqueue_struct *wq; /* The actuak work queue */
343 struct work_struct work_cqs; /* The work being queued */
344 struct be_ctrl_info ctrl;
345 unsigned int generation;
346 unsigned int read_mac_address;
347 struct mgmt_session_info boot_sess;
348 struct invalidate_command_table inv_tbl[128];
349
350 };
351
352 struct beiscsi_session {
353 struct pci_pool *bhs_pool;
354 };
355
356 /**
357 * struct beiscsi_conn - iscsi connection structure
358 */
359 struct beiscsi_conn {
360 struct iscsi_conn *conn;
361 struct beiscsi_hba *phba;
362 u32 exp_statsn;
363 u32 beiscsi_conn_cid;
364 struct beiscsi_endpoint *ep;
365 unsigned short login_in_progress;
366 struct wrb_handle *plogin_wrb_handle;
367 struct sgl_handle *plogin_sgl_handle;
368 struct beiscsi_session *beiscsi_sess;
369 struct iscsi_task *task;
370 };
371
372 /* This structure is used by the chip */
373 struct pdu_data_out {
374 u32 dw[12];
375 };
376 /**
377 * Pseudo amap definition in which each bit of the actual structure is defined
378 * as a byte: used to calculate offset/shift/mask of each field
379 */
380 struct amap_pdu_data_out {
381 u8 opcode[6]; /* opcode */
382 u8 rsvd0[2]; /* should be 0 */
383 u8 rsvd1[7];
384 u8 final_bit; /* F bit */
385 u8 rsvd2[16];
386 u8 ahs_length[8]; /* no AHS */
387 u8 data_len_hi[8];
388 u8 data_len_lo[16]; /* DataSegmentLength */
389 u8 lun[64];
390 u8 itt[32]; /* ITT; initiator task tag */
391 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
392 u8 rsvd3[32];
393 u8 exp_stat_sn[32];
394 u8 rsvd4[32];
395 u8 data_sn[32];
396 u8 buffer_offset[32];
397 u8 rsvd5[32];
398 };
399
400 struct be_cmd_bhs {
401 struct iscsi_cmd iscsi_hdr;
402 unsigned char pad1[16];
403 struct pdu_data_out iscsi_data_pdu;
404 unsigned char pad2[BE_SENSE_INFO_SIZE -
405 sizeof(struct pdu_data_out)];
406 };
407
408 struct beiscsi_io_task {
409 struct wrb_handle *pwrb_handle;
410 struct sgl_handle *psgl_handle;
411 struct beiscsi_conn *conn;
412 struct scsi_cmnd *scsi_cmnd;
413 unsigned int cmd_sn;
414 unsigned int flags;
415 unsigned short cid;
416 unsigned short header_len;
417 itt_t libiscsi_itt;
418 struct be_cmd_bhs *cmd_bhs;
419 struct be_bus_address bhs_pa;
420 unsigned short bhs_len;
421 };
422
423 struct be_nonio_bhs {
424 struct iscsi_hdr iscsi_hdr;
425 unsigned char pad1[16];
426 struct pdu_data_out iscsi_data_pdu;
427 unsigned char pad2[BE_SENSE_INFO_SIZE -
428 sizeof(struct pdu_data_out)];
429 };
430
431 struct be_status_bhs {
432 struct iscsi_cmd iscsi_hdr;
433 unsigned char pad1[16];
434 /**
435 * The plus 2 below is to hold the sense info length that gets
436 * DMA'ed by RxULP
437 */
438 unsigned char sense_info[BE_SENSE_INFO_SIZE];
439 };
440
441 struct iscsi_sge {
442 u32 dw[4];
443 };
444
445 /**
446 * Pseudo amap definition in which each bit of the actual structure is defined
447 * as a byte: used to calculate offset/shift/mask of each field
448 */
449 struct amap_iscsi_sge {
450 u8 addr_hi[32];
451 u8 addr_lo[32];
452 u8 sge_offset[22]; /* DWORD 2 */
453 u8 rsvd0[9]; /* DWORD 2 */
454 u8 last_sge; /* DWORD 2 */
455 u8 len[17]; /* DWORD 3 */
456 u8 rsvd1[15]; /* DWORD 3 */
457 };
458
459 struct beiscsi_offload_params {
460 u32 dw[5];
461 };
462
463 #define OFFLD_PARAMS_ERL 0x00000003
464 #define OFFLD_PARAMS_DDE 0x00000004
465 #define OFFLD_PARAMS_HDE 0x00000008
466 #define OFFLD_PARAMS_IR2T 0x00000010
467 #define OFFLD_PARAMS_IMD 0x00000020
468
469 /**
470 * Pseudo amap definition in which each bit of the actual structure is defined
471 * as a byte: used to calculate offset/shift/mask of each field
472 */
473 struct amap_beiscsi_offload_params {
474 u8 max_burst_length[32];
475 u8 max_send_data_segment_length[32];
476 u8 first_burst_length[32];
477 u8 erl[2];
478 u8 dde[1];
479 u8 hde[1];
480 u8 ir2t[1];
481 u8 imd[1];
482 u8 pad[26];
483 u8 exp_statsn[32];
484 };
485
486 /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
487 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
488
489 struct async_pdu_handle {
490 struct list_head link;
491 struct be_bus_address pa;
492 void *pbuffer;
493 unsigned int consumed;
494 unsigned char index;
495 unsigned char is_header;
496 unsigned short cri;
497 unsigned long buffer_len;
498 };
499
500 struct hwi_async_entry {
501 struct {
502 unsigned char hdr_received;
503 unsigned char hdr_len;
504 unsigned short bytes_received;
505 unsigned int bytes_needed;
506 struct list_head list;
507 } wait_queue;
508
509 struct list_head header_busy_list;
510 struct list_head data_busy_list;
511 };
512
513 struct hwi_async_pdu_context {
514 struct {
515 struct be_bus_address pa_base;
516 void *va_base;
517 void *ring_base;
518 struct async_pdu_handle *handle_base;
519
520 unsigned int host_write_ptr;
521 unsigned int ep_read_ptr;
522 unsigned int writables;
523
524 unsigned int free_entries;
525 unsigned int busy_entries;
526 unsigned int buffer_size;
527 unsigned int num_entries;
528
529 struct list_head free_list;
530 } async_header;
531
532 struct {
533 struct be_bus_address pa_base;
534 void *va_base;
535 void *ring_base;
536 struct async_pdu_handle *handle_base;
537
538 unsigned int host_write_ptr;
539 unsigned int ep_read_ptr;
540 unsigned int writables;
541
542 unsigned int free_entries;
543 unsigned int busy_entries;
544 unsigned int buffer_size;
545 struct list_head free_list;
546 unsigned int num_entries;
547 } async_data;
548
549 /**
550 * This is a varying size list! Do not add anything
551 * after this entry!!
552 */
553 struct hwi_async_entry async_entry[BE2_MAX_SESSIONS * 2];
554 };
555
556 #define PDUCQE_CODE_MASK 0x0000003F
557 #define PDUCQE_DPL_MASK 0xFFFF0000
558 #define PDUCQE_INDEX_MASK 0x0000FFFF
559
560 struct i_t_dpdu_cqe {
561 u32 dw[4];
562 } __packed;
563
564 /**
565 * Pseudo amap definition in which each bit of the actual structure is defined
566 * as a byte: used to calculate offset/shift/mask of each field
567 */
568 struct amap_i_t_dpdu_cqe {
569 u8 db_addr_hi[32];
570 u8 db_addr_lo[32];
571 u8 code[6];
572 u8 cid[10];
573 u8 dpl[16];
574 u8 index[16];
575 u8 num_cons[10];
576 u8 rsvd0[4];
577 u8 final;
578 u8 valid;
579 } __packed;
580
581 #define CQE_VALID_MASK 0x80000000
582 #define CQE_CODE_MASK 0x0000003F
583 #define CQE_CID_MASK 0x0000FFC0
584
585 #define EQE_VALID_MASK 0x00000001
586 #define EQE_MAJORCODE_MASK 0x0000000E
587 #define EQE_RESID_MASK 0xFFFF0000
588
589 struct be_eq_entry {
590 u32 dw[1];
591 } __packed;
592
593 /**
594 * Pseudo amap definition in which each bit of the actual structure is defined
595 * as a byte: used to calculate offset/shift/mask of each field
596 */
597 struct amap_eq_entry {
598 u8 valid; /* DWORD 0 */
599 u8 major_code[3]; /* DWORD 0 */
600 u8 minor_code[12]; /* DWORD 0 */
601 u8 resource_id[16]; /* DWORD 0 */
602
603 } __packed;
604
605 struct cq_db {
606 u32 dw[1];
607 } __packed;
608
609 /**
610 * Pseudo amap definition in which each bit of the actual structure is defined
611 * as a byte: used to calculate offset/shift/mask of each field
612 */
613 struct amap_cq_db {
614 u8 qid[10];
615 u8 event[1];
616 u8 rsvd0[5];
617 u8 num_popped[13];
618 u8 rearm[1];
619 u8 rsvd1[2];
620 } __packed;
621
622 void beiscsi_process_eq(struct beiscsi_hba *phba);
623
624 struct iscsi_wrb {
625 u32 dw[16];
626 } __packed;
627
628 #define WRB_TYPE_MASK 0xF0000000
629
630 /**
631 * Pseudo amap definition in which each bit of the actual structure is defined
632 * as a byte: used to calculate offset/shift/mask of each field
633 */
634 struct amap_iscsi_wrb {
635 u8 lun[14]; /* DWORD 0 */
636 u8 lt; /* DWORD 0 */
637 u8 invld; /* DWORD 0 */
638 u8 wrb_idx[8]; /* DWORD 0 */
639 u8 dsp; /* DWORD 0 */
640 u8 dmsg; /* DWORD 0 */
641 u8 undr_run; /* DWORD 0 */
642 u8 over_run; /* DWORD 0 */
643 u8 type[4]; /* DWORD 0 */
644 u8 ptr2nextwrb[8]; /* DWORD 1 */
645 u8 r2t_exp_dtl[24]; /* DWORD 1 */
646 u8 sgl_icd_idx[12]; /* DWORD 2 */
647 u8 rsvd0[20]; /* DWORD 2 */
648 u8 exp_data_sn[32]; /* DWORD 3 */
649 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
650 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
651 u8 cmdsn_itt[32]; /* DWORD 6 */
652 u8 dif_ref_tag[32]; /* DWORD 7 */
653 u8 sge0_addr_hi[32]; /* DWORD 8 */
654 u8 sge0_addr_lo[32]; /* DWORD 9 */
655 u8 sge0_offset[22]; /* DWORD 10 */
656 u8 pbs; /* DWORD 10 */
657 u8 dif_mode[2]; /* DWORD 10 */
658 u8 rsvd1[6]; /* DWORD 10 */
659 u8 sge0_last; /* DWORD 10 */
660 u8 sge0_len[17]; /* DWORD 11 */
661 u8 dif_meta_tag[14]; /* DWORD 11 */
662 u8 sge0_in_ddr; /* DWORD 11 */
663 u8 sge1_addr_hi[32]; /* DWORD 12 */
664 u8 sge1_addr_lo[32]; /* DWORD 13 */
665 u8 sge1_r2t_offset[22]; /* DWORD 14 */
666 u8 rsvd2[9]; /* DWORD 14 */
667 u8 sge1_last; /* DWORD 14 */
668 u8 sge1_len[17]; /* DWORD 15 */
669 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
670 u8 rsvd3[2]; /* DWORD 15 */
671 u8 sge1_in_ddr; /* DWORD 15 */
672
673 } __packed;
674
675 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
676 void
677 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
678
679 void beiscsi_process_all_cqs(struct work_struct *work);
680
681 struct pdu_nop_out {
682 u32 dw[12];
683 };
684
685 /**
686 * Pseudo amap definition in which each bit of the actual structure is defined
687 * as a byte: used to calculate offset/shift/mask of each field
688 */
689 struct amap_pdu_nop_out {
690 u8 opcode[6]; /* opcode 0x00 */
691 u8 i_bit; /* I Bit */
692 u8 x_bit; /* reserved; should be 0 */
693 u8 fp_bit_filler1[7];
694 u8 f_bit; /* always 1 */
695 u8 reserved1[16];
696 u8 ahs_length[8]; /* no AHS */
697 u8 data_len_hi[8];
698 u8 data_len_lo[16]; /* DataSegmentLength */
699 u8 lun[64];
700 u8 itt[32]; /* initiator id for ping or 0xffffffff */
701 u8 ttt[32]; /* target id for ping or 0xffffffff */
702 u8 cmd_sn[32];
703 u8 exp_stat_sn[32];
704 u8 reserved5[128];
705 };
706
707 #define PDUBASE_OPCODE_MASK 0x0000003F
708 #define PDUBASE_DATALENHI_MASK 0x0000FF00
709 #define PDUBASE_DATALENLO_MASK 0xFFFF0000
710
711 struct pdu_base {
712 u32 dw[16];
713 } __packed;
714
715 /**
716 * Pseudo amap definition in which each bit of the actual structure is defined
717 * as a byte: used to calculate offset/shift/mask of each field
718 */
719 struct amap_pdu_base {
720 u8 opcode[6];
721 u8 i_bit; /* immediate bit */
722 u8 x_bit; /* reserved, always 0 */
723 u8 reserved1[24]; /* opcode-specific fields */
724 u8 ahs_length[8]; /* length units is 4 byte words */
725 u8 data_len_hi[8];
726 u8 data_len_lo[16]; /* DatasegmentLength */
727 u8 lun[64]; /* lun or opcode-specific fields */
728 u8 itt[32]; /* initiator task tag */
729 u8 reserved4[224];
730 };
731
732 struct iscsi_target_context_update_wrb {
733 u32 dw[16];
734 } __packed;
735
736 /**
737 * Pseudo amap definition in which each bit of the actual structure is defined
738 * as a byte: used to calculate offset/shift/mask of each field
739 */
740 struct amap_iscsi_target_context_update_wrb {
741 u8 lun[14]; /* DWORD 0 */
742 u8 lt; /* DWORD 0 */
743 u8 invld; /* DWORD 0 */
744 u8 wrb_idx[8]; /* DWORD 0 */
745 u8 dsp; /* DWORD 0 */
746 u8 dmsg; /* DWORD 0 */
747 u8 undr_run; /* DWORD 0 */
748 u8 over_run; /* DWORD 0 */
749 u8 type[4]; /* DWORD 0 */
750 u8 ptr2nextwrb[8]; /* DWORD 1 */
751 u8 max_burst_length[19]; /* DWORD 1 */
752 u8 rsvd0[5]; /* DWORD 1 */
753 u8 rsvd1[15]; /* DWORD 2 */
754 u8 max_send_data_segment_length[17]; /* DWORD 2 */
755 u8 first_burst_length[14]; /* DWORD 3 */
756 u8 rsvd2[2]; /* DWORD 3 */
757 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
758 u8 rsvd3[5]; /* DWORD 3 */
759 u8 session_state[3]; /* DWORD 3 */
760 u8 rsvd4[16]; /* DWORD 4 */
761 u8 tx_jumbo; /* DWORD 4 */
762 u8 hde; /* DWORD 4 */
763 u8 dde; /* DWORD 4 */
764 u8 erl[2]; /* DWORD 4 */
765 u8 domain_id[5]; /* DWORD 4 */
766 u8 mode; /* DWORD 4 */
767 u8 imd; /* DWORD 4 */
768 u8 ir2t; /* DWORD 4 */
769 u8 notpredblq[2]; /* DWORD 4 */
770 u8 compltonack; /* DWORD 4 */
771 u8 stat_sn[32]; /* DWORD 5 */
772 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
773 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
774 u8 pad_addr_hi[32]; /* DWORD 8 */
775 u8 pad_addr_lo[32]; /* DWORD 9 */
776 u8 rsvd5[32]; /* DWORD 10 */
777 u8 rsvd6[32]; /* DWORD 11 */
778 u8 rsvd7[32]; /* DWORD 12 */
779 u8 rsvd8[32]; /* DWORD 13 */
780 u8 rsvd9[32]; /* DWORD 14 */
781 u8 rsvd10[32]; /* DWORD 15 */
782
783 } __packed;
784
785 struct be_ring {
786 u32 pages; /* queue size in pages */
787 u32 id; /* queue id assigned by beklib */
788 u32 num; /* number of elements in queue */
789 u32 cidx; /* consumer index */
790 u32 pidx; /* producer index -- not used by most rings */
791 u32 item_size; /* size in bytes of one object */
792
793 void *va; /* The virtual address of the ring. This
794 * should be last to allow 32 & 64 bit debugger
795 * extensions to work.
796 */
797 };
798
799 struct hwi_wrb_context {
800 struct list_head wrb_handle_list;
801 struct list_head wrb_handle_drvr_list;
802 struct wrb_handle **pwrb_handle_base;
803 struct wrb_handle **pwrb_handle_basestd;
804 struct iscsi_wrb *plast_wrb;
805 unsigned short alloc_index;
806 unsigned short free_index;
807 unsigned short wrb_handles_available;
808 unsigned short cid;
809 };
810
811 struct hwi_controller {
812 struct list_head io_sgl_list;
813 struct list_head eh_sgl_list;
814 struct sgl_handle *psgl_handle_base;
815 unsigned int wrb_mem_index;
816
817 struct hwi_wrb_context wrb_context[BE2_MAX_SESSIONS * 2];
818 struct mcc_wrb *pmcc_wrb_base;
819 struct be_ring default_pdu_hdr;
820 struct be_ring default_pdu_data;
821 struct hwi_context_memory *phwi_ctxt;
822 };
823
824 enum hwh_type_enum {
825 HWH_TYPE_IO = 1,
826 HWH_TYPE_LOGOUT = 2,
827 HWH_TYPE_TMF = 3,
828 HWH_TYPE_NOP = 4,
829 HWH_TYPE_IO_RD = 5,
830 HWH_TYPE_LOGIN = 11,
831 HWH_TYPE_INVALID = 0xFFFFFFFF
832 };
833
834 struct wrb_handle {
835 enum hwh_type_enum type;
836 unsigned short wrb_index;
837 unsigned short nxt_wrb_index;
838
839 struct iscsi_task *pio_handle;
840 struct iscsi_wrb *pwrb;
841 };
842
843 struct hwi_context_memory {
844 /* Adaptive interrupt coalescing (AIC) info */
845 u16 min_eqd; /* in usecs */
846 u16 max_eqd; /* in usecs */
847 u16 cur_eqd; /* in usecs */
848 struct be_eq_obj be_eq[MAX_CPUS];
849 struct be_queue_info be_cq[MAX_CPUS];
850
851 struct be_queue_info be_def_hdrq;
852 struct be_queue_info be_def_dataq;
853
854 struct be_queue_info be_wrbq[BE2_MAX_SESSIONS];
855 struct be_mcc_wrb_context *pbe_mcc_context;
856
857 struct hwi_async_pdu_context *pasync_ctx;
858 };
859
860 #endif
Tomato firmware and modifications.