release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/scsi/3w-xxxx.h

   1
   2
   3 #ifndef _3W_XXXX_H
   4 #define _3W_XXXX_H
   5
   6 #include <linux/types.h>
   7
   8 /* AEN strings */
   9 static char *tw_aen_string[] = {
  10         [0x000] = "INFO: AEN queue empty",
  11         [0x001] = "INFO: Soft reset occurred",
  12         [0x002] = "ERROR: Unit degraded: Unit #",
  13         [0x003] = "ERROR: Controller error",
  14         [0x004] = "ERROR: Rebuild failed: Unit #",
  15         [0x005] = "INFO: Rebuild complete: Unit #",
  16         [0x006] = "ERROR: Incomplete unit detected: Unit #",
  17         [0x007] = "INFO: Initialization complete: Unit #",
  18         [0x008] = "WARNING: Unclean shutdown detected: Unit #",
  19         [0x009] = "WARNING: ATA port timeout: Port #",
  20         [0x00A] = "ERROR: Drive error: Port #",
  21         [0x00B] = "INFO: Rebuild started: Unit #",
  22         [0x00C] = "INFO: Initialization started: Unit #",
  23         [0x00D] = "ERROR: Logical unit deleted: Unit #",
  24         [0x00F] = "WARNING: SMART threshold exceeded: Port #",
  25         [0x021] = "WARNING: ATA UDMA downgrade: Port #",
  26         [0x022] = "WARNING: ATA UDMA upgrade: Port #",
  27         [0x023] = "WARNING: Sector repair occurred: Port #",
  28         [0x024] = "ERROR: SBUF integrity check failure",
  29         [0x025] = "ERROR: Lost cached write: Port #",
  30         [0x026] = "ERROR: Drive ECC error detected: Port #",
  31         [0x027] = "ERROR: DCB checksum error: Port #",
  32         [0x028] = "ERROR: DCB unsupported version: Port #",
  33         [0x029] = "INFO: Verify started: Unit #",
  34         [0x02A] = "ERROR: Verify failed: Port #",
  35         [0x02B] = "INFO: Verify complete: Unit #",
  36         [0x02C] = "WARNING: Overwrote bad sector during rebuild: Port #",
  37         [0x02D] = "ERROR: Encountered bad sector during rebuild: Port #",
  38         [0x02E] = "ERROR: Replacement drive is too small: Port #",
  39         [0x02F] = "WARNING: Verify error: Unit not previously initialized: Unit #",
  40         [0x030] = "ERROR: Drive not supported: Port #"
  41 };
  42
  43 /*
  44    Sense key lookup table
  45    Format: ESDC/flags,SenseKey,AdditionalSenseCode,AdditionalSenseCodeQualifier
  46 */
  47 static unsigned char tw_sense_table[][4] =
  48 {
  49   /* Codes for newer firmware */
  50                             // ATA Error                    SCSI Error
  51   {0x01, 0x03, 0x13, 0x00}, // Address mark not found       Address mark not found for data field
  52   {0x04, 0x0b, 0x00, 0x00}, // Aborted command              Aborted command
  53   {0x10, 0x0b, 0x14, 0x00}, // ID not found                 Recorded entity not found
  54   {0x40, 0x03, 0x11, 0x00}, // Uncorrectable ECC error      Unrecovered read error
  55   {0x61, 0x04, 0x00, 0x00}, // Device fault                 Hardware error
  56   {0x84, 0x0b, 0x47, 0x00}, // Data CRC error               SCSI parity error
  57   {0xd0, 0x0b, 0x00, 0x00}, // Device busy                  Aborted command
  58   {0xd1, 0x0b, 0x00, 0x00}, // Device busy                  Aborted command
  59   {0x37, 0x02, 0x04, 0x00}, // Unit offline                 Not ready
  60   {0x09, 0x02, 0x04, 0x00}, // Unrecovered disk error       Not ready
  61
  62   /* Codes for older firmware */
  63                             // 3ware Error                  SCSI Error
  64   {0x51, 0x0b, 0x00, 0x00}  // Unspecified                  Aborted command
  65 };
  66
  67 /* Control register bit definitions */
  68 #define TW_CONTROL_CLEAR_HOST_INTERRUPT        0x00080000
  69 #define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT   0x00040000
  70 #define TW_CONTROL_MASK_COMMAND_INTERRUPT      0x00020000
  71 #define TW_CONTROL_MASK_RESPONSE_INTERRUPT     0x00010000
  72 #define TW_CONTROL_UNMASK_COMMAND_INTERRUPT    0x00008000
  73 #define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT   0x00004000
  74 #define TW_CONTROL_CLEAR_ERROR_STATUS          0x00000200
  75 #define TW_CONTROL_ISSUE_SOFT_RESET            0x00000100
  76 #define TW_CONTROL_ENABLE_INTERRUPTS           0x00000080
  77 #define TW_CONTROL_DISABLE_INTERRUPTS          0x00000040
  78 #define TW_CONTROL_ISSUE_HOST_INTERRUPT        0x00000020
  79 #define TW_CONTROL_CLEAR_PARITY_ERROR          0x00800000
  80 #define TW_CONTROL_CLEAR_QUEUE_ERROR           0x00400000
  81 #define TW_CONTROL_CLEAR_PCI_ABORT             0x00100000
  82 #define TW_CONTROL_CLEAR_SBUF_WRITE_ERROR      0x00000008
  83
  84 /* Status register bit definitions */
  85 #define TW_STATUS_MAJOR_VERSION_MASK           0xF0000000
  86 #define TW_STATUS_MINOR_VERSION_MASK           0x0F000000
  87 #define TW_STATUS_PCI_PARITY_ERROR             0x00800000
  88 #define TW_STATUS_QUEUE_ERROR                  0x00400000
  89 #define TW_STATUS_MICROCONTROLLER_ERROR        0x00200000
  90 #define TW_STATUS_PCI_ABORT                    0x00100000
  91 #define TW_STATUS_HOST_INTERRUPT               0x00080000
  92 #define TW_STATUS_ATTENTION_INTERRUPT          0x00040000
  93 #define TW_STATUS_COMMAND_INTERRUPT            0x00020000
  94 #define TW_STATUS_RESPONSE_INTERRUPT           0x00010000
  95 #define TW_STATUS_COMMAND_QUEUE_FULL           0x00008000
  96 #define TW_STATUS_RESPONSE_QUEUE_EMPTY         0x00004000
  97 #define TW_STATUS_MICROCONTROLLER_READY        0x00002000
  98 #define TW_STATUS_COMMAND_QUEUE_EMPTY          0x00001000
  99 #define TW_STATUS_ALL_INTERRUPTS               0x000F0000
 100 #define TW_STATUS_CLEARABLE_BITS               0x00D00000
 101 #define TW_STATUS_EXPECTED_BITS                0x00002000
 102 #define TW_STATUS_UNEXPECTED_BITS              0x00F00008
 103 #define TW_STATUS_SBUF_WRITE_ERROR             0x00000008
 104 #define TW_STATUS_VALID_INTERRUPT              0x00DF0008
 105
 106 /* RESPONSE QUEUE BIT DEFINITIONS */
 107 #define TW_RESPONSE_ID_MASK                    0x00000FF0
 108
 109 /* PCI related defines */
 110 #define TW_IO_ADDRESS_RANGE                    0x10
 111 #define TW_DEVICE_NAME                         "3ware Storage Controller"
 112 #define TW_VENDOR_ID (0x13C1)   /* 3ware */
 113 #define TW_DEVICE_ID (0x1000)   /* Storage Controller */
 114 #define TW_DEVICE_ID2 (0x1001)  /* 7000 series controller */
 115 #define TW_NUMDEVICES 2
 116 #define TW_PCI_CLEAR_PARITY_ERRORS 0xc100
 117 #define TW_PCI_CLEAR_PCI_ABORT     0x2000
 118
 119 /* Command packet opcodes */
 120 #define TW_OP_NOP             0x0
 121 #define TW_OP_INIT_CONNECTION 0x1
 122 #define TW_OP_READ            0x2
 123 #define TW_OP_WRITE           0x3
 124 #define TW_OP_VERIFY          0x4
 125 #define TW_OP_GET_PARAM       0x12
 126 #define TW_OP_SET_PARAM       0x13
 127 #define TW_OP_SECTOR_INFO     0x1a
 128 #define TW_OP_AEN_LISTEN      0x1c
 129 #define TW_OP_FLUSH_CACHE     0x0e
 130 #define TW_CMD_PACKET         0x1d
 131 #define TW_CMD_PACKET_WITH_DATA 0x1f
 132
 133 /* Asynchronous Event Notification (AEN) Codes */
 134 #define TW_AEN_QUEUE_EMPTY       0x0000
 135 #define TW_AEN_SOFT_RESET        0x0001
 136 #define TW_AEN_DEGRADED_MIRROR   0x0002
 137 #define TW_AEN_CONTROLLER_ERROR  0x0003
 138 #define TW_AEN_REBUILD_FAIL      0x0004
 139 #define TW_AEN_REBUILD_DONE      0x0005
 140 #define TW_AEN_QUEUE_FULL        0x00ff
 141 #define TW_AEN_TABLE_UNDEFINED   0x15
 142 #define TW_AEN_APORT_TIMEOUT     0x0009
 143 #define TW_AEN_DRIVE_ERROR       0x000A
 144 #define TW_AEN_SMART_FAIL        0x000F
 145 #define TW_AEN_SBUF_FAIL         0x0024
 146
 147 /* Phase defines */
 148 #define TW_PHASE_INITIAL 0
 149 #define TW_PHASE_SINGLE 1
 150 #define TW_PHASE_SGLIST 2
 151
 152 /* Misc defines */
 153 #define TW_ALIGNMENT_6000                     64 /* 64 bytes */
 154 #define TW_ALIGNMENT_7000                     4  /* 4 bytes */
 155 #define TW_MAX_UNITS                          16
 156 #define TW_COMMAND_ALIGNMENT_MASK             0x1ff
 157 #define TW_INIT_MESSAGE_CREDITS               0x100
 158 #define TW_INIT_COMMAND_PACKET_SIZE           0x3
 159 #define TW_POLL_MAX_RETRIES                   20000
 160 #define TW_MAX_SGL_LENGTH                     62
 161 #define TW_ATA_PASS_SGL_MAX                   60
 162 #define TW_Q_LENGTH                           256
 163 #define TW_Q_START                            0
 164 #define TW_MAX_SLOT                           32
 165 #define TW_MAX_PCI_BUSES                      255
 166 #define TW_MAX_RESET_TRIES                    3
 167 #define TW_UNIT_INFORMATION_TABLE_BASE        0x300
 168 #define TW_MAX_CMDS_PER_LUN                   254 /* 254 for io, 1 for
 169                                                      chrdev ioctl, one for
 170                                                      internal aen post */
 171 #define TW_BLOCK_SIZE                         0x200 /* 512-byte blocks */
 172 #define TW_IOCTL                              0x80
 173 #define TW_UNIT_ONLINE                        1
 174 #define TW_IN_INTR                            1
 175 #define TW_IN_RESET                           2
 176 #define TW_IN_CHRDEV_IOCTL                    3
 177 #define TW_MAX_SECTORS                        256
 178 #define TW_MAX_IOCTL_SECTORS                  512
 179 #define TW_AEN_WAIT_TIME                      1000
 180 #define TW_IOCTL_WAIT_TIME                    (1 * HZ) /* 1 second */
 181 #define TW_ISR_DONT_COMPLETE                  2
 182 #define TW_ISR_DONT_RESULT                    3
 183 #define TW_IOCTL_TIMEOUT                      25 /* 25 seconds */
 184 #define TW_IOCTL_CHRDEV_TIMEOUT               60 /* 60 seconds */
 185 #define TW_IOCTL_CHRDEV_FREE                  -1
 186 #define TW_DMA_MASK                           DMA_BIT_MASK(32)
 187 #define TW_MAX_CDB_LEN                        16
 188
 189 /* Bitmask macros to eliminate bitfields */
 190
 191 /* opcode: 5, sgloffset: 3 */
 192 #define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f))
 193 #define TW_SGL_OUT(x) ((x >> 5) & 0x7)
 194
 195 /* reserved_1: 4, response_id: 8, reserved_2: 20 */
 196 #define TW_RESID_OUT(x) ((x >> 4) & 0xff)
 197
 198 /* unit: 4, host_id: 4 */
 199 #define TW_UNITHOST_IN(x,y) ((x << 4) | ( y & 0xf))
 200 #define TW_UNIT_OUT(x) (x & 0xf)
 201
 202 /* Macros */
 203 #define TW_CONTROL_REG_ADDR(x) (x->base_addr)
 204 #define TW_STATUS_REG_ADDR(x) (x->base_addr + 0x4)
 205 #define TW_COMMAND_QUEUE_REG_ADDR(x) (x->base_addr + 0x8)
 206 #define TW_RESPONSE_QUEUE_REG_ADDR(x) (x->base_addr + 0xC)
 207 #define TW_CLEAR_ALL_INTERRUPTS(x) (outl(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
 208 #define TW_CLEAR_ATTENTION_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
 209 #define TW_CLEAR_HOST_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
 210 #define TW_DISABLE_INTERRUPTS(x) (outl(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
 211 #define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
 212 #define TW_MASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
 213 #define TW_UNMASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
 214 #define TW_SOFT_RESET(x) (outl(TW_CONTROL_ISSUE_SOFT_RESET | \
 215                         TW_CONTROL_CLEAR_HOST_INTERRUPT | \
 216                         TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \
 217                         TW_CONTROL_MASK_COMMAND_INTERRUPT | \
 218                         TW_CONTROL_MASK_RESPONSE_INTERRUPT | \
 219                         TW_CONTROL_CLEAR_ERROR_STATUS | \
 220                         TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
 221 #define TW_STATUS_ERRORS(x) \
 222         (((x & TW_STATUS_PCI_ABORT) || \
 223         (x & TW_STATUS_PCI_PARITY_ERROR) || \
 224         (x & TW_STATUS_QUEUE_ERROR) || \
 225         (x & TW_STATUS_MICROCONTROLLER_ERROR)) && \
 226         (x & TW_STATUS_MICROCONTROLLER_READY))
 227
 228 #ifdef TW_DEBUG
 229 #define dprintk(msg...) printk(msg)
 230 #else
 231 #define dprintk(msg...) do { } while(0)
 232 #endif
 233
 234 #pragma pack(1)
 235
 236 /* Scatter Gather List Entry */
 237 typedef struct TAG_TW_SG_Entry {
 238         u32 address;
 239         u32 length;
 240 } TW_SG_Entry;
 241
 242 typedef unsigned char TW_Sector[512];
 243
 244 /* Command Packet */
 245 typedef struct TW_Command {
 246         unsigned char opcode__sgloffset;
 247         unsigned char size;
 248         unsigned char request_id;
 249         unsigned char unit__hostid;
 250         /* Second DWORD */
 251         unsigned char status;
 252         unsigned char flags;
 253         union {
 254                 unsigned short block_count;
 255                 unsigned short parameter_count;
 256                 unsigned short message_credits;
 257         } byte6;
 258         union {
 259                 struct {
 260                         u32 lba;
 261                         TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
 262                         u32 padding;    /* pad to 512 bytes */
 263                 } io;
 264                 struct {
 265                         TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
 266                         u32 padding[2];
 267                 } param;
 268                 struct {
 269                         u32 response_queue_pointer;
 270                         u32 padding[125];
 271                 } init_connection;
 272                 struct {
 273                         char version[504];
 274                 } ioctl_miniport_version;
 275         } byte8;
 276 } TW_Command;
 277
 278 #pragma pack()
 279
 280 typedef struct TAG_TW_Ioctl {
 281         unsigned char opcode;
 282         unsigned short table_id;
 283         unsigned char parameter_id;
 284         unsigned char parameter_size_bytes;
 285         unsigned char unit_index;
 286         unsigned char data[1];
 287 } TW_Ioctl;
 288
 289 #pragma pack(1)
 290
 291 /* Structure for new chardev ioctls */
 292 typedef struct TAG_TW_New_Ioctl {
 293         unsigned int data_buffer_length;
 294         unsigned char padding [508];
 295         TW_Command firmware_command;
 296         char data_buffer[1];
 297 } TW_New_Ioctl;
 298
 299 /* GetParam descriptor */
 300 typedef struct {
 301         unsigned short  table_id;
 302         unsigned char   parameter_id;
 303         unsigned char   parameter_size_bytes;
 304         unsigned char   data[1];
 305 } TW_Param, *PTW_Param;
 306
 307 /* Response queue */
 308 typedef union TAG_TW_Response_Queue {
 309         u32 response_id;
 310         u32 value;
 311 } TW_Response_Queue;
 312
 313 typedef int TW_Cmd_State;
 314
 315 #define TW_S_INITIAL   0x1  /* Initial state */
 316 #define TW_S_STARTED   0x2  /* Id in use */
 317 #define TW_S_POSTED    0x4  /* Posted to the controller */
 318 #define TW_S_PENDING   0x8  /* Waiting to be posted in isr */
 319 #define TW_S_COMPLETED 0x10 /* Completed by isr */
 320 #define TW_S_FINISHED  0x20 /* I/O completely done */
 321 #define TW_START_MASK (TW_S_STARTED | TW_S_POSTED | TW_S_PENDING | TW_S_COMPLETED)
 322
 323 /* Command header for ATA pass-thru */
 324 typedef struct TAG_TW_Passthru
 325 {
 326         unsigned char opcode__sgloffset;
 327         unsigned char size;
 328         unsigned char request_id;
 329         unsigned char aport__hostid;
 330         unsigned char status;
 331         unsigned char flags;
 332         unsigned short param;
 333         unsigned short features;
 334         unsigned short sector_count;
 335         unsigned short sector_num;
 336         unsigned short cylinder_lo;
 337         unsigned short cylinder_hi;
 338         unsigned char drive_head;
 339         unsigned char command;
 340         TW_SG_Entry sg_list[TW_ATA_PASS_SGL_MAX];
 341         unsigned char padding[12];
 342 } TW_Passthru;
 343
 344 typedef struct TAG_TW_Device_Extension {
 345         u32                     base_addr;
 346         unsigned long           *alignment_virtual_address[TW_Q_LENGTH];
 347         unsigned long           alignment_physical_address[TW_Q_LENGTH];
 348         int                     is_unit_present[TW_MAX_UNITS];
 349         unsigned long           *command_packet_virtual_address[TW_Q_LENGTH];
 350         unsigned long           command_packet_physical_address[TW_Q_LENGTH];
 351         struct pci_dev          *tw_pci_dev;
 352         struct scsi_cmnd        *srb[TW_Q_LENGTH];
 353         unsigned char           free_queue[TW_Q_LENGTH];
 354         unsigned char           free_head;
 355         unsigned char           free_tail;
 356         unsigned char           pending_queue[TW_Q_LENGTH];
 357         unsigned char           pending_head;
 358         unsigned char           pending_tail;
 359         TW_Cmd_State            state[TW_Q_LENGTH];
 360         u32                     posted_request_count;
 361         u32                     max_posted_request_count;
 362         u32                     request_count_marked_pending;
 363         u32                     pending_request_count;
 364         u32                     max_pending_request_count;
 365         u32                     max_sgl_entries;
 366         u32                     sgl_entries;
 367         u32                     num_resets;
 368         u32                     sector_count;
 369         u32                     max_sector_count;
 370         u32                     aen_count;
 371         struct Scsi_Host        *host;
 372         struct mutex            ioctl_lock;
 373         unsigned short          aen_queue[TW_Q_LENGTH];
 374         unsigned char           aen_head;
 375         unsigned char           aen_tail;
 376         volatile long           flags; /* long req'd for set_bit --RR */
 377         int                     reset_print;
 378         volatile int            chrdev_request_id;
 379         wait_queue_head_t       ioctl_wqueue;
 380 } TW_Device_Extension;
 381
 382 #pragma pack()
 383
 384 #endif /* _3W_XXXX_H */