2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm/setup.h>
28 const char *pci_power_names
[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
31 EXPORT_SYMBOL_GPL(pci_power_names
);
33 int isa_dma_bridge_buggy
;
34 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
37 EXPORT_SYMBOL(pci_pci_problems
);
39 unsigned int pci_pm_d3_delay
;
41 static void pci_dev_d3_sleep(struct pci_dev
*dev
)
43 unsigned int delay
= dev
->d3_delay
;
45 if (delay
< pci_pm_d3_delay
)
46 delay
= pci_pm_d3_delay
;
51 #ifdef CONFIG_PCI_DOMAINS
52 int pci_domains_supported
= 1;
55 #define DEFAULT_CARDBUS_IO_SIZE (256)
56 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
57 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
58 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
59 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
61 #define DEFAULT_HOTPLUG_IO_SIZE (256)
62 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
63 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
64 unsigned long pci_hotplug_io_size
= DEFAULT_HOTPLUG_IO_SIZE
;
65 unsigned long pci_hotplug_mem_size
= DEFAULT_HOTPLUG_MEM_SIZE
;
68 * The default CLS is used if arch didn't set CLS explicitly and not
69 * all pci devices agree on the same value. Arch can override either
70 * the dfl or actual value as it sees fit. Don't forget this is
71 * measured in 32-bit words, not bytes.
73 u8 pci_dfl_cache_line_size __devinitdata
= L1_CACHE_BYTES
>> 2;
74 u8 pci_cache_line_size
;
77 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
78 * @bus: pointer to PCI bus structure to search
80 * Given a PCI bus, returns the highest PCI bus number present in the set
81 * including the given PCI bus and its list of child PCI buses.
83 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
85 struct list_head
*tmp
;
88 max
= bus
->subordinate
;
89 list_for_each(tmp
, &bus
->children
) {
90 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
96 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
98 #ifdef CONFIG_HAS_IOMEM
99 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
102 * Make sure the BAR is actually a memory resource, not an IO resource
104 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
108 return ioremap_nocache(pci_resource_start(pdev
, bar
),
109 pci_resource_len(pdev
, bar
));
111 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
115 #define PCI_FIND_CAP_TTL 48
117 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
118 u8 pos
, int cap
, int *ttl
)
123 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
127 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
133 pos
+= PCI_CAP_LIST_NEXT
;
138 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
141 int ttl
= PCI_FIND_CAP_TTL
;
143 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
146 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
148 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
149 pos
+ PCI_CAP_LIST_NEXT
, cap
);
151 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
153 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
154 unsigned int devfn
, u8 hdr_type
)
158 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
159 if (!(status
& PCI_STATUS_CAP_LIST
))
163 case PCI_HEADER_TYPE_NORMAL
:
164 case PCI_HEADER_TYPE_BRIDGE
:
165 return PCI_CAPABILITY_LIST
;
166 case PCI_HEADER_TYPE_CARDBUS
:
167 return PCI_CB_CAPABILITY_LIST
;
176 * pci_find_capability - query for devices' capabilities
177 * @dev: PCI device to query
178 * @cap: capability code
180 * Tell if a device supports a given PCI capability.
181 * Returns the address of the requested capability structure within the
182 * device's PCI configuration space or 0 in case the device does not
183 * support it. Possible values for @cap:
185 * %PCI_CAP_ID_PM Power Management
186 * %PCI_CAP_ID_AGP Accelerated Graphics Port
187 * %PCI_CAP_ID_VPD Vital Product Data
188 * %PCI_CAP_ID_SLOTID Slot Identification
189 * %PCI_CAP_ID_MSI Message Signalled Interrupts
190 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
191 * %PCI_CAP_ID_PCIX PCI-X
192 * %PCI_CAP_ID_EXP PCI Express
194 int pci_find_capability(struct pci_dev
*dev
, int cap
)
198 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
200 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
206 * pci_bus_find_capability - query for devices' capabilities
207 * @bus: the PCI bus to query
208 * @devfn: PCI device to query
209 * @cap: capability code
211 * Like pci_find_capability() but works for pci devices that do not have a
212 * pci_dev structure set up yet.
214 * Returns the address of the requested capability structure within the
215 * device's PCI configuration space or 0 in case the device does not
218 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
223 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
225 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
227 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
233 * pci_find_ext_capability - Find an extended capability
234 * @dev: PCI device to query
235 * @cap: capability code
237 * Returns the address of the requested extended capability structure
238 * within the device's PCI configuration space or 0 if the device does
239 * not support it. Possible values for @cap:
241 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
242 * %PCI_EXT_CAP_ID_VC Virtual Channel
243 * %PCI_EXT_CAP_ID_DSN Device Serial Number
244 * %PCI_EXT_CAP_ID_PWR Power Budgeting
246 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
250 int pos
= PCI_CFG_SPACE_SIZE
;
252 /* minimum 8 bytes per capability */
253 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
255 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
258 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
262 * If we have no capabilities, this is indicated by cap ID,
263 * cap version and next pointer all being 0.
269 if (PCI_EXT_CAP_ID(header
) == cap
)
272 pos
= PCI_EXT_CAP_NEXT(header
);
273 if (pos
< PCI_CFG_SPACE_SIZE
)
276 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
282 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
285 * pci_bus_find_ext_capability - find an extended capability
286 * @bus: the PCI bus to query
287 * @devfn: PCI device to query
288 * @cap: capability code
290 * Like pci_find_ext_capability() but works for pci devices that do not have a
291 * pci_dev structure set up yet.
293 * Returns the address of the requested capability structure within the
294 * device's PCI configuration space or 0 in case the device does not
297 int pci_bus_find_ext_capability(struct pci_bus
*bus
, unsigned int devfn
,
302 int pos
= PCI_CFG_SPACE_SIZE
;
304 /* minimum 8 bytes per capability */
305 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
307 if (!pci_bus_read_config_dword(bus
, devfn
, pos
, &header
))
309 if (header
== 0xffffffff || header
== 0)
313 if (PCI_EXT_CAP_ID(header
) == cap
)
316 pos
= PCI_EXT_CAP_NEXT(header
);
317 if (pos
< PCI_CFG_SPACE_SIZE
)
320 if (!pci_bus_read_config_dword(bus
, devfn
, pos
, &header
))
327 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
329 int rc
, ttl
= PCI_FIND_CAP_TTL
;
332 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
333 mask
= HT_3BIT_CAP_MASK
;
335 mask
= HT_5BIT_CAP_MASK
;
337 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
338 PCI_CAP_ID_HT
, &ttl
);
340 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
341 if (rc
!= PCIBIOS_SUCCESSFUL
)
344 if ((cap
& mask
) == ht_cap
)
347 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
348 pos
+ PCI_CAP_LIST_NEXT
,
349 PCI_CAP_ID_HT
, &ttl
);
355 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
356 * @dev: PCI device to query
357 * @pos: Position from which to continue searching
358 * @ht_cap: Hypertransport capability code
360 * To be used in conjunction with pci_find_ht_capability() to search for
361 * all capabilities matching @ht_cap. @pos should always be a value returned
362 * from pci_find_ht_capability().
364 * NB. To be 100% safe against broken PCI devices, the caller should take
365 * steps to avoid an infinite loop.
367 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
369 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
371 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
374 * pci_find_ht_capability - query a device's Hypertransport capabilities
375 * @dev: PCI device to query
376 * @ht_cap: Hypertransport capability code
378 * Tell if a device supports a given Hypertransport capability.
379 * Returns an address within the device's PCI configuration space
380 * or 0 in case the device does not support the request capability.
381 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
382 * which has a Hypertransport capability matching @ht_cap.
384 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
388 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
390 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
394 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
397 * pci_find_parent_resource - return resource region of parent bus of given region
398 * @dev: PCI device structure contains resources to be searched
399 * @res: child resource record for which parent is sought
401 * For given resource region of given device, return the resource
402 * region of parent bus the given region is contained in or where
403 * it should be allocated from.
406 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
408 const struct pci_bus
*bus
= dev
->bus
;
410 struct resource
*best
= NULL
, *r
;
412 pci_bus_for_each_resource(bus
, r
, i
) {
415 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
416 continue; /* Not contained */
417 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
418 continue; /* Wrong type */
419 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
420 return r
; /* Exact match */
421 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
422 if (r
->flags
& IORESOURCE_PREFETCH
)
424 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
432 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
433 * @dev: PCI device to have its BARs restored
435 * Restore the BAR values for a given device, so as to make it
436 * accessible by its driver.
439 pci_restore_bars(struct pci_dev
*dev
)
443 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
444 pci_update_resource(dev
, i
);
447 static struct pci_platform_pm_ops
*pci_platform_pm
;
449 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
451 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
452 || !ops
->sleep_wake
|| !ops
->can_wakeup
)
454 pci_platform_pm
= ops
;
458 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
460 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
463 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
466 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
469 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
471 return pci_platform_pm
?
472 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
475 static inline bool platform_pci_can_wakeup(struct pci_dev
*dev
)
477 return pci_platform_pm
? pci_platform_pm
->can_wakeup(dev
) : false;
480 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
482 return pci_platform_pm
?
483 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
486 static inline int platform_pci_run_wake(struct pci_dev
*dev
, bool enable
)
488 return pci_platform_pm
?
489 pci_platform_pm
->run_wake(dev
, enable
) : -ENODEV
;
493 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
495 * @dev: PCI device to handle.
496 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
499 * -EINVAL if the requested state is invalid.
500 * -EIO if device does not support PCI PM or its PM capabilities register has a
501 * wrong version, or device doesn't support the requested state.
502 * 0 if device already is in the requested state.
503 * 0 if device's power state has been successfully changed.
505 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
508 bool need_restore
= false;
510 /* Check if we're already there */
511 if (dev
->current_state
== state
)
517 if (state
< PCI_D0
|| state
> PCI_D3hot
)
520 /* Validate current state:
521 * Can enter D0 from any state, but if we can only go deeper
522 * to sleep if we're already in a low power state
524 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
525 && dev
->current_state
> state
) {
526 dev_err(&dev
->dev
, "invalid power transition "
527 "(from state %d to %d)\n", dev
->current_state
, state
);
531 /* check if this device supports the desired state */
532 if ((state
== PCI_D1
&& !dev
->d1_support
)
533 || (state
== PCI_D2
&& !dev
->d2_support
))
536 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
538 /* If we're (effectively) in D3, force entire word to 0.
539 * This doesn't affect PME_Status, disables PME_En, and
540 * sets PowerState to 0.
542 switch (dev
->current_state
) {
546 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
551 case PCI_UNKNOWN
: /* Boot-up */
552 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
553 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
555 /* Fall-through: force to D0 */
561 /* enter specified state */
562 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
564 /* Mandatory power management transition delays */
565 /* see PCI PM 1.1 5.6.1 table 18 */
566 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
567 pci_dev_d3_sleep(dev
);
568 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
569 udelay(PCI_PM_D2_DELAY
);
571 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
572 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
573 if (dev
->current_state
!= state
&& printk_ratelimit())
574 dev_info(&dev
->dev
, "Refused to change power state, "
575 "currently in D%d\n", dev
->current_state
);
577 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
578 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
579 * from D3hot to D0 _may_ perform an internal reset, thereby
580 * going to "D0 Uninitialized" rather than "D0 Initialized".
581 * For example, at least some versions of the 3c905B and the
582 * 3c556B exhibit this behaviour.
584 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
585 * devices in a D3hot state at boot. Consequently, we need to
586 * restore at least the BARs so that the device will be
587 * accessible to its driver.
590 pci_restore_bars(dev
);
593 pcie_aspm_pm_state_change(dev
->bus
->self
);
599 * pci_update_current_state - Read PCI power state of given device from its
600 * PCI PM registers and cache it
601 * @dev: PCI device to handle.
602 * @state: State to cache in case the device doesn't have the PM capability
604 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
609 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
610 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
612 dev
->current_state
= state
;
617 * pci_platform_power_transition - Use platform to change device power state
618 * @dev: PCI device to handle.
619 * @state: State to put the device into.
621 static int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
625 if (platform_pci_power_manageable(dev
)) {
626 error
= platform_pci_set_power_state(dev
, state
);
628 pci_update_current_state(dev
, state
);
631 /* Fall back to PCI_D0 if native PM is not supported */
633 dev
->current_state
= PCI_D0
;
640 * __pci_start_power_transition - Start power transition of a PCI device
641 * @dev: PCI device to handle.
642 * @state: State to put the device into.
644 static void __pci_start_power_transition(struct pci_dev
*dev
, pci_power_t state
)
647 pci_platform_power_transition(dev
, PCI_D0
);
651 * __pci_complete_power_transition - Complete power transition of a PCI device
652 * @dev: PCI device to handle.
653 * @state: State to put the device into.
655 * This function should not be called directly by device drivers.
657 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
)
659 return state
>= PCI_D0
?
660 pci_platform_power_transition(dev
, state
) : -EINVAL
;
662 EXPORT_SYMBOL_GPL(__pci_complete_power_transition
);
665 * pci_set_power_state - Set the power state of a PCI device
666 * @dev: PCI device to handle.
667 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
669 * Transition a device to a new power state, using the platform firmware and/or
670 * the device's PCI PM registers.
673 * -EINVAL if the requested state is invalid.
674 * -EIO if device does not support PCI PM or its PM capabilities register has a
675 * wrong version, or device doesn't support the requested state.
676 * 0 if device already is in the requested state.
677 * 0 if device's power state has been successfully changed.
679 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
683 /* bound the state we're entering */
684 if (state
> PCI_D3hot
)
686 else if (state
< PCI_D0
)
688 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
690 * If the device or the parent bridge do not support PCI PM,
691 * ignore the request if we're doing anything other than putting
692 * it into D0 (which would only happen on boot).
696 __pci_start_power_transition(dev
, state
);
698 /* This device is quirked not to be put into D3, so
699 don't put it in D3 */
700 if (state
== PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
703 error
= pci_raw_set_power_state(dev
, state
);
705 if (!__pci_complete_power_transition(dev
, state
))
712 * pci_choose_state - Choose the power state of a PCI device
713 * @dev: PCI device to be suspended
714 * @state: target sleep state for the whole system. This is the value
715 * that is passed to suspend() function.
717 * Returns PCI power state suitable for given device and given system
721 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
725 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
728 ret
= platform_pci_choose_state(dev
);
729 if (ret
!= PCI_POWER_ERROR
)
732 switch (state
.event
) {
735 case PM_EVENT_FREEZE
:
736 case PM_EVENT_PRETHAW
:
737 /* REVISIT both freeze and pre-thaw "should" use D0 */
738 case PM_EVENT_SUSPEND
:
739 case PM_EVENT_HIBERNATE
:
742 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
749 EXPORT_SYMBOL(pci_choose_state
);
751 #define PCI_EXP_SAVE_REGS 7
753 #define pcie_cap_has_devctl(type, flags) 1
754 #define pcie_cap_has_lnkctl(type, flags) \
755 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
756 (type == PCI_EXP_TYPE_ROOT_PORT || \
757 type == PCI_EXP_TYPE_ENDPOINT || \
758 type == PCI_EXP_TYPE_LEG_END))
759 #define pcie_cap_has_sltctl(type, flags) \
760 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
761 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
762 (type == PCI_EXP_TYPE_DOWNSTREAM && \
763 (flags & PCI_EXP_FLAGS_SLOT))))
764 #define pcie_cap_has_rtctl(type, flags) \
765 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
766 (type == PCI_EXP_TYPE_ROOT_PORT || \
767 type == PCI_EXP_TYPE_RC_EC))
768 #define pcie_cap_has_devctl2(type, flags) \
769 ((flags & PCI_EXP_FLAGS_VERS) > 1)
770 #define pcie_cap_has_lnkctl2(type, flags) \
771 ((flags & PCI_EXP_FLAGS_VERS) > 1)
772 #define pcie_cap_has_sltctl2(type, flags) \
773 ((flags & PCI_EXP_FLAGS_VERS) > 1)
775 static int pci_save_pcie_state(struct pci_dev
*dev
)
778 struct pci_cap_saved_state
*save_state
;
782 pos
= pci_pcie_cap(dev
);
786 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
788 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
791 cap
= (u16
*)&save_state
->data
[0];
793 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
795 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
796 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
797 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
798 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
799 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
800 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
801 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
802 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
803 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
804 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &cap
[i
++]);
805 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
806 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, &cap
[i
++]);
807 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
808 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, &cap
[i
++]);
813 static void pci_restore_pcie_state(struct pci_dev
*dev
)
816 struct pci_cap_saved_state
*save_state
;
820 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
821 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
822 if (!save_state
|| pos
<= 0)
824 cap
= (u16
*)&save_state
->data
[0];
826 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
828 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
829 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
830 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
831 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
832 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
833 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
834 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
835 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
836 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
837 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, cap
[i
++]);
838 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
839 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, cap
[i
++]);
840 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
841 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, cap
[i
++]);
845 static int pci_save_pcix_state(struct pci_dev
*dev
)
848 struct pci_cap_saved_state
*save_state
;
850 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
854 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
856 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
860 pci_read_config_word(dev
, pos
+ PCI_X_CMD
, (u16
*)save_state
->data
);
865 static void pci_restore_pcix_state(struct pci_dev
*dev
)
868 struct pci_cap_saved_state
*save_state
;
871 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
872 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
873 if (!save_state
|| pos
<= 0)
875 cap
= (u16
*)&save_state
->data
[0];
877 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
882 * pci_save_state - save the PCI configuration space of a device before suspending
883 * @dev: - PCI device that we're dealing with
886 pci_save_state(struct pci_dev
*dev
)
889 for (i
= 0; i
< 16; i
++)
890 pci_read_config_dword(dev
, i
* 4, &dev
->saved_config_space
[i
]);
891 dev
->state_saved
= true;
892 if ((i
= pci_save_pcie_state(dev
)) != 0)
894 if ((i
= pci_save_pcix_state(dev
)) != 0)
900 * pci_restore_state - Restore the saved state of a PCI device
901 * @dev: - PCI device that we're dealing with
904 pci_restore_state(struct pci_dev
*dev
)
909 if (!dev
->state_saved
)
912 /* PCI Express register must be restored first */
913 pci_restore_pcie_state(dev
);
916 * The Base Address register should be programmed before the command
919 for (i
= 15; i
>= 0; i
--) {
920 pci_read_config_dword(dev
, i
* 4, &val
);
921 if (val
!= dev
->saved_config_space
[i
]) {
922 dev_printk(KERN_DEBUG
, &dev
->dev
, "restoring config "
923 "space at offset %#x (was %#x, writing %#x)\n",
924 i
, val
, (int)dev
->saved_config_space
[i
]);
925 pci_write_config_dword(dev
,i
* 4,
926 dev
->saved_config_space
[i
]);
929 pci_restore_pcix_state(dev
);
930 pci_restore_msi_state(dev
);
931 pci_restore_iov_state(dev
);
933 dev
->state_saved
= false;
938 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
942 err
= pci_set_power_state(dev
, PCI_D0
);
943 if (err
< 0 && err
!= -EIO
)
945 err
= pcibios_enable_device(dev
, bars
);
948 pci_fixup_device(pci_fixup_enable
, dev
);
954 * pci_reenable_device - Resume abandoned device
955 * @dev: PCI device to be resumed
957 * Note this function is a backend of pci_default_resume and is not supposed
958 * to be called by normal code, write proper resume handler and use it instead.
960 int pci_reenable_device(struct pci_dev
*dev
)
962 if (pci_is_enabled(dev
))
963 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
967 static int __pci_enable_device_flags(struct pci_dev
*dev
,
968 resource_size_t flags
)
973 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
974 return 0; /* already enabled */
976 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
977 if (dev
->resource
[i
].flags
& flags
)
980 err
= do_pci_enable_device(dev
, bars
);
982 atomic_dec(&dev
->enable_cnt
);
987 * pci_enable_device_io - Initialize a device for use with IO space
988 * @dev: PCI device to be initialized
990 * Initialize device before it's used by a driver. Ask low-level code
991 * to enable I/O resources. Wake up the device if it was suspended.
992 * Beware, this function can fail.
994 int pci_enable_device_io(struct pci_dev
*dev
)
996 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
1000 * pci_enable_device_mem - Initialize a device for use with Memory space
1001 * @dev: PCI device to be initialized
1003 * Initialize device before it's used by a driver. Ask low-level code
1004 * to enable Memory resources. Wake up the device if it was suspended.
1005 * Beware, this function can fail.
1007 int pci_enable_device_mem(struct pci_dev
*dev
)
1009 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
1013 * pci_enable_device - Initialize device before it's used by a driver.
1014 * @dev: PCI device to be initialized
1016 * Initialize device before it's used by a driver. Ask low-level code
1017 * to enable I/O and memory. Wake up the device if it was suspended.
1018 * Beware, this function can fail.
1020 * Note we don't actually enable the device many times if we call
1021 * this function repeatedly (we just increment the count).
1023 int pci_enable_device(struct pci_dev
*dev
)
1025 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
1029 * Managed PCI resources. This manages device on/off, intx/msi/msix
1030 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1031 * there's no need to track it separately. pci_devres is initialized
1032 * when a device is enabled using managed PCI device enable interface.
1035 unsigned int enabled
:1;
1036 unsigned int pinned
:1;
1037 unsigned int orig_intx
:1;
1038 unsigned int restore_intx
:1;
1042 static void pcim_release(struct device
*gendev
, void *res
)
1044 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
1045 struct pci_devres
*this = res
;
1048 if (dev
->msi_enabled
)
1049 pci_disable_msi(dev
);
1050 if (dev
->msix_enabled
)
1051 pci_disable_msix(dev
);
1053 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
1054 if (this->region_mask
& (1 << i
))
1055 pci_release_region(dev
, i
);
1057 if (this->restore_intx
)
1058 pci_intx(dev
, this->orig_intx
);
1060 if (this->enabled
&& !this->pinned
)
1061 pci_disable_device(dev
);
1064 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
1066 struct pci_devres
*dr
, *new_dr
;
1068 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1072 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
1075 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
1078 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
1080 if (pci_is_managed(pdev
))
1081 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1086 * pcim_enable_device - Managed pci_enable_device()
1087 * @pdev: PCI device to be initialized
1089 * Managed pci_enable_device().
1091 int pcim_enable_device(struct pci_dev
*pdev
)
1093 struct pci_devres
*dr
;
1096 dr
= get_pci_dr(pdev
);
1102 rc
= pci_enable_device(pdev
);
1104 pdev
->is_managed
= 1;
1111 * pcim_pin_device - Pin managed PCI device
1112 * @pdev: PCI device to pin
1114 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1115 * driver detach. @pdev must have been enabled with
1116 * pcim_enable_device().
1118 void pcim_pin_device(struct pci_dev
*pdev
)
1120 struct pci_devres
*dr
;
1122 dr
= find_pci_dr(pdev
);
1123 WARN_ON(!dr
|| !dr
->enabled
);
1129 * pcibios_disable_device - disable arch specific PCI resources for device dev
1130 * @dev: the PCI device to disable
1132 * Disables architecture specific PCI resources for the device. This
1133 * is the default implementation. Architecture implementations can
1136 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
1138 static void do_pci_disable_device(struct pci_dev
*dev
)
1142 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1143 if (pci_command
& PCI_COMMAND_MASTER
) {
1144 pci_command
&= ~PCI_COMMAND_MASTER
;
1145 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1148 pcibios_disable_device(dev
);
1152 * pci_disable_enabled_device - Disable device without updating enable_cnt
1153 * @dev: PCI device to disable
1155 * NOTE: This function is a backend of PCI power management routines and is
1156 * not supposed to be called drivers.
1158 void pci_disable_enabled_device(struct pci_dev
*dev
)
1160 if (pci_is_enabled(dev
))
1161 do_pci_disable_device(dev
);
1165 * pci_disable_device - Disable PCI device after use
1166 * @dev: PCI device to be disabled
1168 * Signal to the system that the PCI device is not in use by the system
1169 * anymore. This only involves disabling PCI bus-mastering, if active.
1171 * Note we don't actually disable the device until all callers of
1172 * pci_enable_device() have called pci_disable_device().
1175 pci_disable_device(struct pci_dev
*dev
)
1177 struct pci_devres
*dr
;
1179 dr
= find_pci_dr(dev
);
1183 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
1186 do_pci_disable_device(dev
);
1188 dev
->is_busmaster
= 0;
1192 * pcibios_set_pcie_reset_state - set reset state for device dev
1193 * @dev: the PCIe device reset
1194 * @state: Reset state to enter into
1197 * Sets the PCIe reset state for the device. This is the default
1198 * implementation. Architecture implementations can override this.
1200 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1201 enum pcie_reset_state state
)
1207 * pci_set_pcie_reset_state - set reset state for device dev
1208 * @dev: the PCIe device reset
1209 * @state: Reset state to enter into
1212 * Sets the PCI reset state for the device.
1214 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1216 return pcibios_set_pcie_reset_state(dev
, state
);
1220 * pci_check_pme_status - Check if given device has generated PME.
1221 * @dev: Device to check.
1223 * Check the PME status of the device and if set, clear it and clear PME enable
1224 * (if set). Return 'true' if PME status and PME enable were both set or
1225 * 'false' otherwise.
1227 bool pci_check_pme_status(struct pci_dev
*dev
)
1236 pmcsr_pos
= dev
->pm_cap
+ PCI_PM_CTRL
;
1237 pci_read_config_word(dev
, pmcsr_pos
, &pmcsr
);
1238 if (!(pmcsr
& PCI_PM_CTRL_PME_STATUS
))
1241 /* Clear PME status. */
1242 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
1243 if (pmcsr
& PCI_PM_CTRL_PME_ENABLE
) {
1244 /* Disable PME to avoid interrupt flood. */
1245 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1249 pci_write_config_word(dev
, pmcsr_pos
, pmcsr
);
1255 * Time to wait before the system can be put into a sleep state after reporting
1256 * a wakeup event signaled by a PCI device.
1258 #define PCI_WAKEUP_COOLDOWN 100
1261 * pci_wakeup_event - Report a wakeup event related to a given PCI device.
1262 * @dev: Device to report the wakeup event for.
1264 void pci_wakeup_event(struct pci_dev
*dev
)
1266 if (device_may_wakeup(&dev
->dev
))
1267 pm_wakeup_event(&dev
->dev
, PCI_WAKEUP_COOLDOWN
);
1271 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1272 * @dev: Device to handle.
1275 * Check if @dev has generated PME and queue a resume request for it in that
1278 static int pci_pme_wakeup(struct pci_dev
*dev
, void *ign
)
1280 if (pci_check_pme_status(dev
)) {
1281 pm_request_resume(&dev
->dev
);
1282 pci_wakeup_event(dev
);
1288 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1289 * @bus: Top bus of the subtree to walk.
1291 void pci_pme_wakeup_bus(struct pci_bus
*bus
)
1294 pci_walk_bus(bus
, pci_pme_wakeup
, NULL
);
1298 * pci_pme_capable - check the capability of PCI device to generate PME#
1299 * @dev: PCI device to handle.
1300 * @state: PCI state from which device will issue PME#.
1302 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1307 return !!(dev
->pme_support
& (1 << state
));
1311 * pci_pme_active - enable or disable PCI device's PME# function
1312 * @dev: PCI device to handle.
1313 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1315 * The caller must verify that the device is capable of generating PME# before
1316 * calling this function with @enable equal to 'true'.
1318 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1325 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1326 /* Clear PME_Status by writing 1 to it and enable PME# */
1327 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1329 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1331 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1333 dev_printk(KERN_DEBUG
, &dev
->dev
, "PME# %s\n",
1334 enable
? "enabled" : "disabled");
1338 * __pci_enable_wake - enable PCI device as wakeup event source
1339 * @dev: PCI device affected
1340 * @state: PCI state from which device will issue wakeup events
1341 * @runtime: True if the events are to be generated at run time
1342 * @enable: True to enable event generation; false to disable
1344 * This enables the device as a wakeup event source, or disables it.
1345 * When such events involves platform-specific hooks, those hooks are
1346 * called automatically by this routine.
1348 * Devices with legacy power management (no standard PCI PM capabilities)
1349 * always require such platform hooks.
1352 * 0 is returned on success
1353 * -EINVAL is returned if device is not supposed to wake up the system
1354 * Error code depending on the platform is returned if both the platform and
1355 * the native mechanism fail to enable the generation of wake-up events
1357 int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1358 bool runtime
, bool enable
)
1362 if (enable
&& !runtime
&& !device_may_wakeup(&dev
->dev
))
1365 /* Don't do the same thing twice in a row for one device. */
1366 if (!!enable
== !!dev
->wakeup_prepared
)
1370 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1371 * Anderson we should be doing PME# wake enable followed by ACPI wake
1372 * enable. To disable wake-up we call the platform first, for symmetry.
1378 if (pci_pme_capable(dev
, state
))
1379 pci_pme_active(dev
, true);
1382 error
= runtime
? platform_pci_run_wake(dev
, true) :
1383 platform_pci_sleep_wake(dev
, true);
1387 dev
->wakeup_prepared
= true;
1390 platform_pci_run_wake(dev
, false);
1392 platform_pci_sleep_wake(dev
, false);
1393 pci_pme_active(dev
, false);
1394 dev
->wakeup_prepared
= false;
1399 EXPORT_SYMBOL(__pci_enable_wake
);
1402 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1403 * @dev: PCI device to prepare
1404 * @enable: True to enable wake-up event generation; false to disable
1406 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1407 * and this function allows them to set that up cleanly - pci_enable_wake()
1408 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1409 * ordering constraints.
1411 * This function only returns error code if the device is not capable of
1412 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1413 * enable wake-up power for it.
1415 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1417 return pci_pme_capable(dev
, PCI_D3cold
) ?
1418 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1419 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1423 * pci_target_state - find an appropriate low power state for a given PCI dev
1426 * Use underlying platform code to find a supported low power state for @dev.
1427 * If the platform can't manage @dev, return the deepest state from which it
1428 * can generate wake events, based on any available PME info.
1430 pci_power_t
pci_target_state(struct pci_dev
*dev
)
1432 pci_power_t target_state
= PCI_D3hot
;
1434 if (platform_pci_power_manageable(dev
)) {
1436 * Call the platform to choose the target state of the device
1437 * and enable wake-up from this state if supported.
1439 pci_power_t state
= platform_pci_choose_state(dev
);
1442 case PCI_POWER_ERROR
:
1447 if (pci_no_d1d2(dev
))
1450 target_state
= state
;
1452 } else if (!dev
->pm_cap
) {
1453 target_state
= PCI_D0
;
1454 } else if (device_may_wakeup(&dev
->dev
)) {
1456 * Find the deepest state from which the device can generate
1457 * wake-up events, make it the target state and enable device
1460 if (dev
->pme_support
) {
1462 && !(dev
->pme_support
& (1 << target_state
)))
1467 return target_state
;
1471 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1472 * @dev: Device to handle.
1474 * Choose the power state appropriate for the device depending on whether
1475 * it can wake up the system and/or is power manageable by the platform
1476 * (PCI_D3hot is the default) and put the device into that state.
1478 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1480 pci_power_t target_state
= pci_target_state(dev
);
1483 if (target_state
== PCI_POWER_ERROR
)
1486 pci_enable_wake(dev
, target_state
, device_may_wakeup(&dev
->dev
));
1488 error
= pci_set_power_state(dev
, target_state
);
1491 pci_enable_wake(dev
, target_state
, false);
1497 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1498 * @dev: Device to handle.
1500 * Disable device's system wake-up capability and put it into D0.
1502 int pci_back_from_sleep(struct pci_dev
*dev
)
1504 pci_enable_wake(dev
, PCI_D0
, false);
1505 return pci_set_power_state(dev
, PCI_D0
);
1509 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1510 * @dev: PCI device being suspended.
1512 * Prepare @dev to generate wake-up events at run time and put it into a low
1515 int pci_finish_runtime_suspend(struct pci_dev
*dev
)
1517 pci_power_t target_state
= pci_target_state(dev
);
1520 if (target_state
== PCI_POWER_ERROR
)
1523 __pci_enable_wake(dev
, target_state
, true, pci_dev_run_wake(dev
));
1525 error
= pci_set_power_state(dev
, target_state
);
1528 __pci_enable_wake(dev
, target_state
, true, false);
1534 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1535 * @dev: Device to check.
1537 * Return true if the device itself is cabable of generating wake-up events
1538 * (through the platform or using the native PCIe PME) or if the device supports
1539 * PME and one of its upstream bridges can generate wake-up events.
1541 bool pci_dev_run_wake(struct pci_dev
*dev
)
1543 struct pci_bus
*bus
= dev
->bus
;
1545 if (device_run_wake(&dev
->dev
))
1548 if (!dev
->pme_support
)
1551 while (bus
->parent
) {
1552 struct pci_dev
*bridge
= bus
->self
;
1554 if (device_run_wake(&bridge
->dev
))
1560 /* We have reached the root bus. */
1562 return device_run_wake(bus
->bridge
);
1566 EXPORT_SYMBOL_GPL(pci_dev_run_wake
);
1569 * pci_pm_init - Initialize PM functions of given PCI device
1570 * @dev: PCI device to handle.
1572 void pci_pm_init(struct pci_dev
*dev
)
1577 pm_runtime_forbid(&dev
->dev
);
1578 device_enable_async_suspend(&dev
->dev
);
1579 dev
->wakeup_prepared
= false;
1583 /* find PCI PM capability in list */
1584 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1587 /* Check device's ability to generate PME# */
1588 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
1590 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
1591 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
1592 pmc
& PCI_PM_CAP_VER_MASK
);
1597 dev
->d3_delay
= PCI_PM_D3_WAIT
;
1599 dev
->d1_support
= false;
1600 dev
->d2_support
= false;
1601 if (!pci_no_d1d2(dev
)) {
1602 if (pmc
& PCI_PM_CAP_D1
)
1603 dev
->d1_support
= true;
1604 if (pmc
& PCI_PM_CAP_D2
)
1605 dev
->d2_support
= true;
1607 if (dev
->d1_support
|| dev
->d2_support
)
1608 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
1609 dev
->d1_support
? " D1" : "",
1610 dev
->d2_support
? " D2" : "");
1613 pmc
&= PCI_PM_CAP_PME_MASK
;
1615 dev_printk(KERN_DEBUG
, &dev
->dev
,
1616 "PME# supported from%s%s%s%s%s\n",
1617 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
1618 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
1619 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
1620 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
1621 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
1622 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
1624 * Make device's PM flags reflect the wake-up capability, but
1625 * let the user space enable it to wake up the system as needed.
1627 device_set_wakeup_capable(&dev
->dev
, true);
1628 /* Disable the PME# generation functionality */
1629 pci_pme_active(dev
, false);
1631 dev
->pme_support
= 0;
1636 * platform_pci_wakeup_init - init platform wakeup if present
1639 * Some devices don't have PCI PM caps but can still generate wakeup
1640 * events through platform methods (like ACPI events). If @dev supports
1641 * platform wakeup events, set the device flag to indicate as much. This
1642 * may be redundant if the device also supports PCI PM caps, but double
1643 * initialization should be safe in that case.
1645 void platform_pci_wakeup_init(struct pci_dev
*dev
)
1647 if (!platform_pci_can_wakeup(dev
))
1650 device_set_wakeup_capable(&dev
->dev
, true);
1651 platform_pci_sleep_wake(dev
, false);
1655 * pci_add_save_buffer - allocate buffer for saving given capability registers
1656 * @dev: the PCI device
1657 * @cap: the capability to allocate the buffer for
1658 * @size: requested size of the buffer
1660 static int pci_add_cap_save_buffer(
1661 struct pci_dev
*dev
, char cap
, unsigned int size
)
1664 struct pci_cap_saved_state
*save_state
;
1666 pos
= pci_find_capability(dev
, cap
);
1670 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
1674 save_state
->cap_nr
= cap
;
1675 pci_add_saved_cap(dev
, save_state
);
1681 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1682 * @dev: the PCI device
1684 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
1688 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
1689 PCI_EXP_SAVE_REGS
* sizeof(u16
));
1692 "unable to preallocate PCI Express save buffer\n");
1694 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
1697 "unable to preallocate PCI-X save buffer\n");
1701 * pci_enable_ari - enable ARI forwarding if hardware support it
1702 * @dev: the PCI device
1704 void pci_enable_ari(struct pci_dev
*dev
)
1709 struct pci_dev
*bridge
;
1711 if (!pci_is_pcie(dev
) || dev
->devfn
)
1714 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1718 bridge
= dev
->bus
->self
;
1719 if (!bridge
|| !pci_is_pcie(bridge
))
1722 pos
= pci_pcie_cap(bridge
);
1726 pci_read_config_dword(bridge
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
1727 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
1730 pci_read_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
1731 ctrl
|= PCI_EXP_DEVCTL2_ARI
;
1732 pci_write_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
1734 bridge
->ari_enabled
= 1;
1737 static int pci_acs_enable
;
1740 * pci_request_acs - ask for ACS to be enabled if supported
1742 void pci_request_acs(void)
1748 * pci_enable_acs - enable ACS if hardware support it
1749 * @dev: the PCI device
1751 void pci_enable_acs(struct pci_dev
*dev
)
1757 if (!pci_acs_enable
)
1760 if (!pci_is_pcie(dev
))
1763 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
1767 pci_read_config_word(dev
, pos
+ PCI_ACS_CAP
, &cap
);
1768 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
1770 /* Source Validation */
1771 ctrl
|= (cap
& PCI_ACS_SV
);
1773 /* P2P Request Redirect */
1774 ctrl
|= (cap
& PCI_ACS_RR
);
1776 /* P2P Completion Redirect */
1777 ctrl
|= (cap
& PCI_ACS_CR
);
1779 /* Upstream Forwarding */
1780 ctrl
|= (cap
& PCI_ACS_UF
);
1782 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
1786 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1787 * @dev: the PCI device
1788 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1790 * Perform INTx swizzling for a device behind one level of bridge. This is
1791 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1792 * behind bridges on add-in cards. For devices with ARI enabled, the slot
1793 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
1794 * the PCI Express Base Specification, Revision 2.1)
1796 u8
pci_swizzle_interrupt_pin(struct pci_dev
*dev
, u8 pin
)
1800 if (pci_ari_enabled(dev
->bus
))
1803 slot
= PCI_SLOT(dev
->devfn
);
1805 return (((pin
- 1) + slot
) % 4) + 1;
1809 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
1817 while (!pci_is_root_bus(dev
->bus
)) {
1818 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1819 dev
= dev
->bus
->self
;
1826 * pci_common_swizzle - swizzle INTx all the way to root bridge
1827 * @dev: the PCI device
1828 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1830 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1831 * bridges all the way up to a PCI root bus.
1833 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
1837 while (!pci_is_root_bus(dev
->bus
)) {
1838 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1839 dev
= dev
->bus
->self
;
1842 return PCI_SLOT(dev
->devfn
);
1846 * pci_release_region - Release a PCI bar
1847 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1848 * @bar: BAR to release
1850 * Releases the PCI I/O and memory resources previously reserved by a
1851 * successful call to pci_request_region. Call this function only
1852 * after all use of the PCI regions has ceased.
1854 void pci_release_region(struct pci_dev
*pdev
, int bar
)
1856 struct pci_devres
*dr
;
1858 if (pci_resource_len(pdev
, bar
) == 0)
1860 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
1861 release_region(pci_resource_start(pdev
, bar
),
1862 pci_resource_len(pdev
, bar
));
1863 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
1864 release_mem_region(pci_resource_start(pdev
, bar
),
1865 pci_resource_len(pdev
, bar
));
1867 dr
= find_pci_dr(pdev
);
1869 dr
->region_mask
&= ~(1 << bar
);
1873 * __pci_request_region - Reserved PCI I/O and memory resource
1874 * @pdev: PCI device whose resources are to be reserved
1875 * @bar: BAR to be reserved
1876 * @res_name: Name to be associated with resource.
1877 * @exclusive: whether the region access is exclusive or not
1879 * Mark the PCI region associated with PCI device @pdev BR @bar as
1880 * being reserved by owner @res_name. Do not access any
1881 * address inside the PCI regions unless this call returns
1884 * If @exclusive is set, then the region is marked so that userspace
1885 * is explicitly not allowed to map the resource via /dev/mem or
1886 * sysfs MMIO access.
1888 * Returns 0 on success, or %EBUSY on error. A warning
1889 * message is also printed on failure.
1891 static int __pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
,
1894 struct pci_devres
*dr
;
1896 if (pci_resource_len(pdev
, bar
) == 0)
1899 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
1900 if (!request_region(pci_resource_start(pdev
, bar
),
1901 pci_resource_len(pdev
, bar
), res_name
))
1904 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
1905 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
1906 pci_resource_len(pdev
, bar
), res_name
,
1911 dr
= find_pci_dr(pdev
);
1913 dr
->region_mask
|= 1 << bar
;
1918 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %pR\n", bar
,
1919 &pdev
->resource
[bar
]);
1924 * pci_request_region - Reserve PCI I/O and memory resource
1925 * @pdev: PCI device whose resources are to be reserved
1926 * @bar: BAR to be reserved
1927 * @res_name: Name to be associated with resource
1929 * Mark the PCI region associated with PCI device @pdev BAR @bar as
1930 * being reserved by owner @res_name. Do not access any
1931 * address inside the PCI regions unless this call returns
1934 * Returns 0 on success, or %EBUSY on error. A warning
1935 * message is also printed on failure.
1937 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1939 return __pci_request_region(pdev
, bar
, res_name
, 0);
1943 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1944 * @pdev: PCI device whose resources are to be reserved
1945 * @bar: BAR to be reserved
1946 * @res_name: Name to be associated with resource.
1948 * Mark the PCI region associated with PCI device @pdev BR @bar as
1949 * being reserved by owner @res_name. Do not access any
1950 * address inside the PCI regions unless this call returns
1953 * Returns 0 on success, or %EBUSY on error. A warning
1954 * message is also printed on failure.
1956 * The key difference that _exclusive makes it that userspace is
1957 * explicitly not allowed to map the resource via /dev/mem or
1960 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1962 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
1965 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1966 * @pdev: PCI device whose resources were previously reserved
1967 * @bars: Bitmask of BARs to be released
1969 * Release selected PCI I/O and memory resources previously reserved.
1970 * Call this function only after all use of the PCI regions has ceased.
1972 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
1976 for (i
= 0; i
< 6; i
++)
1977 if (bars
& (1 << i
))
1978 pci_release_region(pdev
, i
);
1981 int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1982 const char *res_name
, int excl
)
1986 for (i
= 0; i
< 6; i
++)
1987 if (bars
& (1 << i
))
1988 if (__pci_request_region(pdev
, i
, res_name
, excl
))
1994 if (bars
& (1 << i
))
1995 pci_release_region(pdev
, i
);
2002 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2003 * @pdev: PCI device whose resources are to be reserved
2004 * @bars: Bitmask of BARs to be requested
2005 * @res_name: Name to be associated with resource
2007 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
2008 const char *res_name
)
2010 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
2013 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
,
2014 int bars
, const char *res_name
)
2016 return __pci_request_selected_regions(pdev
, bars
, res_name
,
2017 IORESOURCE_EXCLUSIVE
);
2021 * pci_release_regions - Release reserved PCI I/O and memory resources
2022 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2024 * Releases all PCI I/O and memory resources previously reserved by a
2025 * successful call to pci_request_regions. Call this function only
2026 * after all use of the PCI regions has ceased.
2029 void pci_release_regions(struct pci_dev
*pdev
)
2031 pci_release_selected_regions(pdev
, (1 << 6) - 1);
2035 * pci_request_regions - Reserved PCI I/O and memory resources
2036 * @pdev: PCI device whose resources are to be reserved
2037 * @res_name: Name to be associated with resource.
2039 * Mark all PCI regions associated with PCI device @pdev as
2040 * being reserved by owner @res_name. Do not access any
2041 * address inside the PCI regions unless this call returns
2044 * Returns 0 on success, or %EBUSY on error. A warning
2045 * message is also printed on failure.
2047 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
2049 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
2053 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2054 * @pdev: PCI device whose resources are to be reserved
2055 * @res_name: Name to be associated with resource.
2057 * Mark all PCI regions associated with PCI device @pdev as
2058 * being reserved by owner @res_name. Do not access any
2059 * address inside the PCI regions unless this call returns
2062 * pci_request_regions_exclusive() will mark the region so that
2063 * /dev/mem and the sysfs MMIO access will not be allowed.
2065 * Returns 0 on success, or %EBUSY on error. A warning
2066 * message is also printed on failure.
2068 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
2070 return pci_request_selected_regions_exclusive(pdev
,
2071 ((1 << 6) - 1), res_name
);
2074 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
2078 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
2080 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
2082 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
2083 if (cmd
!= old_cmd
) {
2084 dev_dbg(&dev
->dev
, "%s bus mastering\n",
2085 enable
? "enabling" : "disabling");
2086 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2088 dev
->is_busmaster
= enable
;
2092 * pci_set_master - enables bus-mastering for device dev
2093 * @dev: the PCI device to enable
2095 * Enables bus-mastering on the device and calls pcibios_set_master()
2096 * to do the needed arch specific settings.
2098 void pci_set_master(struct pci_dev
*dev
)
2100 __pci_set_master(dev
, true);
2101 pcibios_set_master(dev
);
2105 * pci_clear_master - disables bus-mastering for device dev
2106 * @dev: the PCI device to disable
2108 void pci_clear_master(struct pci_dev
*dev
)
2110 __pci_set_master(dev
, false);
2114 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2115 * @dev: the PCI device for which MWI is to be enabled
2117 * Helper function for pci_set_mwi.
2118 * Originally copied from drivers/net/acenic.c.
2119 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2121 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2123 int pci_set_cacheline_size(struct pci_dev
*dev
)
2127 if (!pci_cache_line_size
)
2130 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2131 equal to or multiple of the right value. */
2132 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
2133 if (cacheline_size
>= pci_cache_line_size
&&
2134 (cacheline_size
% pci_cache_line_size
) == 0)
2137 /* Write the correct value. */
2138 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
2140 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
2141 if (cacheline_size
== pci_cache_line_size
)
2144 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
2145 "supported\n", pci_cache_line_size
<< 2);
2149 EXPORT_SYMBOL_GPL(pci_set_cacheline_size
);
2151 #ifdef PCI_DISABLE_MWI
2152 int pci_set_mwi(struct pci_dev
*dev
)
2157 int pci_try_set_mwi(struct pci_dev
*dev
)
2162 void pci_clear_mwi(struct pci_dev
*dev
)
2169 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2170 * @dev: the PCI device for which MWI is enabled
2172 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2174 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2177 pci_set_mwi(struct pci_dev
*dev
)
2182 rc
= pci_set_cacheline_size(dev
);
2186 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2187 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
2188 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
2189 cmd
|= PCI_COMMAND_INVALIDATE
;
2190 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2197 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2198 * @dev: the PCI device for which MWI is enabled
2200 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2201 * Callers are not required to check the return value.
2203 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2205 int pci_try_set_mwi(struct pci_dev
*dev
)
2207 int rc
= pci_set_mwi(dev
);
2212 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2213 * @dev: the PCI device to disable
2215 * Disables PCI Memory-Write-Invalidate transaction on the device
2218 pci_clear_mwi(struct pci_dev
*dev
)
2222 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2223 if (cmd
& PCI_COMMAND_INVALIDATE
) {
2224 cmd
&= ~PCI_COMMAND_INVALIDATE
;
2225 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2228 #endif /* ! PCI_DISABLE_MWI */
2231 * pci_intx - enables/disables PCI INTx for device dev
2232 * @pdev: the PCI device to operate on
2233 * @enable: boolean: whether to enable or disable PCI INTx
2235 * Enables/disables PCI INTx for device dev
2238 pci_intx(struct pci_dev
*pdev
, int enable
)
2240 u16 pci_command
, new;
2242 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
2245 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
2247 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
2250 if (new != pci_command
) {
2251 struct pci_devres
*dr
;
2253 pci_write_config_word(pdev
, PCI_COMMAND
, new);
2255 dr
= find_pci_dr(pdev
);
2256 if (dr
&& !dr
->restore_intx
) {
2257 dr
->restore_intx
= 1;
2258 dr
->orig_intx
= !enable
;
2264 * pci_msi_off - disables any msi or msix capabilities
2265 * @dev: the PCI device to operate on
2267 * If you want to use msi see pci_enable_msi and friends.
2268 * This is a lower level primitive that allows us to disable
2269 * msi operation at the device level.
2271 void pci_msi_off(struct pci_dev
*dev
)
2276 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
2278 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
2279 control
&= ~PCI_MSI_FLAGS_ENABLE
;
2280 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
2282 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
2284 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
2285 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
2286 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
2289 EXPORT_SYMBOL_GPL(pci_msi_off
);
2291 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
2293 return dma_set_max_seg_size(&dev
->dev
, size
);
2295 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
2297 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
2299 return dma_set_seg_boundary(&dev
->dev
, mask
);
2301 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
2303 static int pcie_flr(struct pci_dev
*dev
, int probe
)
2308 u16 status
, control
;
2310 pos
= pci_pcie_cap(dev
);
2314 pci_read_config_dword(dev
, pos
+ PCI_EXP_DEVCAP
, &cap
);
2315 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
2321 /* Wait for Transaction Pending bit clean */
2322 for (i
= 0; i
< 4; i
++) {
2324 msleep((1 << (i
- 1)) * 100);
2326 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVSTA
, &status
);
2327 if (!(status
& PCI_EXP_DEVSTA_TRPND
))
2331 dev_err(&dev
->dev
, "transaction is not cleared; "
2332 "proceeding with reset anyway\n");
2335 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &control
);
2336 control
|= PCI_EXP_DEVCTL_BCR_FLR
;
2337 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, control
);
2344 static int pci_af_flr(struct pci_dev
*dev
, int probe
)
2351 pos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
2355 pci_read_config_byte(dev
, pos
+ PCI_AF_CAP
, &cap
);
2356 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
2362 /* Wait for Transaction Pending bit clean */
2363 for (i
= 0; i
< 4; i
++) {
2365 msleep((1 << (i
- 1)) * 100);
2367 pci_read_config_byte(dev
, pos
+ PCI_AF_STATUS
, &status
);
2368 if (!(status
& PCI_AF_STATUS_TP
))
2372 dev_err(&dev
->dev
, "transaction is not cleared; "
2373 "proceeding with reset anyway\n");
2376 pci_write_config_byte(dev
, pos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
2382 static int pci_pm_reset(struct pci_dev
*dev
, int probe
)
2389 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &csr
);
2390 if (csr
& PCI_PM_CTRL_NO_SOFT_RESET
)
2396 if (dev
->current_state
!= PCI_D0
)
2399 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
2401 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
2402 pci_dev_d3_sleep(dev
);
2404 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
2406 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
2407 pci_dev_d3_sleep(dev
);
2412 static int pci_parent_bus_reset(struct pci_dev
*dev
, int probe
)
2415 struct pci_dev
*pdev
;
2417 if (pci_is_root_bus(dev
->bus
) || dev
->subordinate
|| !dev
->bus
->self
)
2420 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
2427 pci_read_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, &ctrl
);
2428 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
2429 pci_write_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, ctrl
);
2432 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
2433 pci_write_config_word(dev
->bus
->self
, PCI_BRIDGE_CONTROL
, ctrl
);
2439 static int pci_dev_reset(struct pci_dev
*dev
, int probe
)
2446 pci_block_user_cfg_access(dev
);
2447 /* block PM suspend, driver probe, etc. */
2448 device_lock(&dev
->dev
);
2451 rc
= pci_dev_specific_reset(dev
, probe
);
2455 rc
= pcie_flr(dev
, probe
);
2459 rc
= pci_af_flr(dev
, probe
);
2463 rc
= pci_pm_reset(dev
, probe
);
2467 rc
= pci_parent_bus_reset(dev
, probe
);
2470 device_unlock(&dev
->dev
);
2471 pci_unblock_user_cfg_access(dev
);
2478 * __pci_reset_function - reset a PCI device function
2479 * @dev: PCI device to reset
2481 * Some devices allow an individual function to be reset without affecting
2482 * other functions in the same device. The PCI device must be responsive
2483 * to PCI config space in order to use this function.
2485 * The device function is presumed to be unused when this function is called.
2486 * Resetting the device will make the contents of PCI configuration space
2487 * random, so any caller of this must be prepared to reinitialise the
2488 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2491 * Returns 0 if the device function was successfully reset or negative if the
2492 * device doesn't support resetting a single function.
2494 int __pci_reset_function(struct pci_dev
*dev
)
2496 return pci_dev_reset(dev
, 0);
2498 EXPORT_SYMBOL_GPL(__pci_reset_function
);
2501 * pci_probe_reset_function - check whether the device can be safely reset
2502 * @dev: PCI device to reset
2504 * Some devices allow an individual function to be reset without affecting
2505 * other functions in the same device. The PCI device must be responsive
2506 * to PCI config space in order to use this function.
2508 * Returns 0 if the device function can be reset or negative if the
2509 * device doesn't support resetting a single function.
2511 int pci_probe_reset_function(struct pci_dev
*dev
)
2513 return pci_dev_reset(dev
, 1);
2517 * pci_reset_function - quiesce and reset a PCI device function
2518 * @dev: PCI device to reset
2520 * Some devices allow an individual function to be reset without affecting
2521 * other functions in the same device. The PCI device must be responsive
2522 * to PCI config space in order to use this function.
2524 * This function does not just reset the PCI portion of a device, but
2525 * clears all the state associated with the device. This function differs
2526 * from __pci_reset_function in that it saves and restores device state
2529 * Returns 0 if the device function was successfully reset or negative if the
2530 * device doesn't support resetting a single function.
2532 int pci_reset_function(struct pci_dev
*dev
)
2536 rc
= pci_dev_reset(dev
, 1);
2540 pci_save_state(dev
);
2543 * both INTx and MSI are disabled after the Interrupt Disable bit
2544 * is set and the Bus Master bit is cleared.
2546 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
2548 rc
= pci_dev_reset(dev
, 0);
2550 pci_restore_state(dev
);
2554 EXPORT_SYMBOL_GPL(pci_reset_function
);
2557 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2558 * @dev: PCI device to query
2560 * Returns mmrbc: maximum designed memory read count in bytes
2561 * or appropriate error value.
2563 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
2568 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2572 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
2575 return 512 << ((stat
& PCI_X_STATUS_MAX_READ
) >> 21);
2577 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
2580 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2581 * @dev: PCI device to query
2583 * Returns mmrbc: maximum memory read count in bytes
2584 * or appropriate error value.
2586 int pcix_get_mmrbc(struct pci_dev
*dev
)
2591 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2595 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
2598 return 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
2600 EXPORT_SYMBOL(pcix_get_mmrbc
);
2603 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2604 * @dev: PCI device to query
2605 * @mmrbc: maximum memory read count in bytes
2606 * valid values are 512, 1024, 2048, 4096
2608 * If possible sets maximum memory read byte count, some bridges have erratas
2609 * that prevent this.
2611 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
2617 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
2620 v
= ffs(mmrbc
) - 10;
2622 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2626 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
2629 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
2632 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
2635 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
2637 if (v
> o
&& dev
->bus
&&
2638 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
2641 cmd
&= ~PCI_X_CMD_MAX_READ
;
2643 if (pci_write_config_word(dev
, cap
+ PCI_X_CMD
, cmd
))
2648 EXPORT_SYMBOL(pcix_set_mmrbc
);
2651 * pcie_get_readrq - get PCI Express read request size
2652 * @dev: PCI device to query
2654 * Returns maximum memory read request in bytes
2655 * or appropriate error value.
2657 int pcie_get_readrq(struct pci_dev
*dev
)
2662 cap
= pci_pcie_cap(dev
);
2666 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2668 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
2672 EXPORT_SYMBOL(pcie_get_readrq
);
2675 * pcie_set_readrq - set PCI Express maximum memory read request
2676 * @dev: PCI device to query
2677 * @rq: maximum memory read count in bytes
2678 * valid values are 128, 256, 512, 1024, 2048, 4096
2680 * If possible sets maximum read byte count
2682 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
2684 int cap
, err
= -EINVAL
;
2687 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
2690 v
= (ffs(rq
) - 8) << 12;
2692 cap
= pci_pcie_cap(dev
);
2696 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2700 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
2701 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
2703 err
= pci_write_config_dword(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2709 EXPORT_SYMBOL(pcie_set_readrq
);
2712 * pci_select_bars - Make BAR mask from the type of resource
2713 * @dev: the PCI device for which BAR mask is made
2714 * @flags: resource type mask to be selected
2716 * This helper routine makes bar mask from the type of resource.
2718 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
2721 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
2722 if (pci_resource_flags(dev
, i
) & flags
)
2728 * pci_resource_bar - get position of the BAR associated with a resource
2729 * @dev: the PCI device
2730 * @resno: the resource number
2731 * @type: the BAR type to be filled in
2733 * Returns BAR position in config space, or 0 if the BAR is invalid.
2735 int pci_resource_bar(struct pci_dev
*dev
, int resno
, enum pci_bar_type
*type
)
2739 if (resno
< PCI_ROM_RESOURCE
) {
2740 *type
= pci_bar_unknown
;
2741 return PCI_BASE_ADDRESS_0
+ 4 * resno
;
2742 } else if (resno
== PCI_ROM_RESOURCE
) {
2743 *type
= pci_bar_mem32
;
2744 return dev
->rom_base_reg
;
2745 } else if (resno
< PCI_BRIDGE_RESOURCES
) {
2746 /* device specific resource */
2747 reg
= pci_iov_resource_bar(dev
, resno
, type
);
2752 dev_err(&dev
->dev
, "BAR %d: invalid resource\n", resno
);
2756 /* Some architectures require additional programming to enable VGA */
2757 static arch_set_vga_state_t arch_set_vga_state
;
2759 void __init
pci_register_set_vga_state(arch_set_vga_state_t func
)
2761 arch_set_vga_state
= func
; /* NULL disables */
2764 static int pci_set_vga_state_arch(struct pci_dev
*dev
, bool decode
,
2765 unsigned int command_bits
, bool change_bridge
)
2767 if (arch_set_vga_state
)
2768 return arch_set_vga_state(dev
, decode
, command_bits
,
2774 * pci_set_vga_state - set VGA decode state on device and parents if requested
2775 * @dev: the PCI device
2776 * @decode: true = enable decoding, false = disable decoding
2777 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
2778 * @change_bridge: traverse ancestors and change bridges
2780 int pci_set_vga_state(struct pci_dev
*dev
, bool decode
,
2781 unsigned int command_bits
, bool change_bridge
)
2783 struct pci_bus
*bus
;
2784 struct pci_dev
*bridge
;
2788 WARN_ON(command_bits
& ~(PCI_COMMAND_IO
|PCI_COMMAND_MEMORY
));
2790 /* ARCH specific VGA enables */
2791 rc
= pci_set_vga_state_arch(dev
, decode
, command_bits
, change_bridge
);
2795 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2797 cmd
|= command_bits
;
2799 cmd
&= ~command_bits
;
2800 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2802 if (change_bridge
== false)
2809 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
,
2812 cmd
|= PCI_BRIDGE_CTL_VGA
;
2814 cmd
&= ~PCI_BRIDGE_CTL_VGA
;
2815 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
,
2823 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2824 static char resource_alignment_param
[RESOURCE_ALIGNMENT_PARAM_SIZE
] = {0};
2825 static DEFINE_SPINLOCK(resource_alignment_lock
);
2828 * pci_specified_resource_alignment - get resource alignment specified by user.
2829 * @dev: the PCI device to get
2831 * RETURNS: Resource alignment if it is specified.
2832 * Zero if it is not specified.
2834 resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
)
2836 int seg
, bus
, slot
, func
, align_order
, count
;
2837 resource_size_t align
= 0;
2840 spin_lock(&resource_alignment_lock
);
2841 p
= resource_alignment_param
;
2844 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
2850 if (sscanf(p
, "%x:%x:%x.%x%n",
2851 &seg
, &bus
, &slot
, &func
, &count
) != 4) {
2853 if (sscanf(p
, "%x:%x.%x%n",
2854 &bus
, &slot
, &func
, &count
) != 3) {
2855 /* Invalid format */
2856 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: %s\n",
2862 if (seg
== pci_domain_nr(dev
->bus
) &&
2863 bus
== dev
->bus
->number
&&
2864 slot
== PCI_SLOT(dev
->devfn
) &&
2865 func
== PCI_FUNC(dev
->devfn
)) {
2866 if (align_order
== -1) {
2869 align
= 1 << align_order
;
2874 if (*p
!= ';' && *p
!= ',') {
2875 /* End of param or invalid format */
2880 spin_unlock(&resource_alignment_lock
);
2885 * pci_is_reassigndev - check if specified PCI is target device to reassign
2886 * @dev: the PCI device to check
2888 * RETURNS: non-zero for PCI device is a target device to reassign,
2891 int pci_is_reassigndev(struct pci_dev
*dev
)
2893 return (pci_specified_resource_alignment(dev
) != 0);
2896 ssize_t
pci_set_resource_alignment_param(const char *buf
, size_t count
)
2898 if (count
> RESOURCE_ALIGNMENT_PARAM_SIZE
- 1)
2899 count
= RESOURCE_ALIGNMENT_PARAM_SIZE
- 1;
2900 spin_lock(&resource_alignment_lock
);
2901 strncpy(resource_alignment_param
, buf
, count
);
2902 resource_alignment_param
[count
] = '\0';
2903 spin_unlock(&resource_alignment_lock
);
2907 ssize_t
pci_get_resource_alignment_param(char *buf
, size_t size
)
2910 spin_lock(&resource_alignment_lock
);
2911 count
= snprintf(buf
, size
, "%s", resource_alignment_param
);
2912 spin_unlock(&resource_alignment_lock
);
2916 static ssize_t
pci_resource_alignment_show(struct bus_type
*bus
, char *buf
)
2918 return pci_get_resource_alignment_param(buf
, PAGE_SIZE
);
2921 static ssize_t
pci_resource_alignment_store(struct bus_type
*bus
,
2922 const char *buf
, size_t count
)
2924 return pci_set_resource_alignment_param(buf
, count
);
2927 BUS_ATTR(resource_alignment
, 0644, pci_resource_alignment_show
,
2928 pci_resource_alignment_store
);
2930 static int __init
pci_resource_alignment_sysfs_init(void)
2932 return bus_create_file(&pci_bus_type
,
2933 &bus_attr_resource_alignment
);
2936 late_initcall(pci_resource_alignment_sysfs_init
);
2938 static void __devinit
pci_no_domains(void)
2940 #ifdef CONFIG_PCI_DOMAINS
2941 pci_domains_supported
= 0;
2946 * pci_ext_cfg_enabled - can we access extended PCI config space?
2947 * @dev: The PCI device of the root bridge.
2949 * Returns 1 if we can access PCI extended config space (offsets
2950 * greater than 0xff). This is the default implementation. Architecture
2951 * implementations can override this.
2953 int __attribute__ ((weak
)) pci_ext_cfg_avail(struct pci_dev
*dev
)
2958 void __weak
pci_fixup_cardbus(struct pci_bus
*bus
)
2961 EXPORT_SYMBOL(pci_fixup_cardbus
);
2963 static int __init
pci_setup(char *str
)
2966 char *k
= strchr(str
, ',');
2969 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
2970 if (!strcmp(str
, "nomsi")) {
2972 } else if (!strcmp(str
, "noaer")) {
2974 } else if (!strcmp(str
, "nodomains")) {
2976 } else if (!strncmp(str
, "cbiosize=", 9)) {
2977 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
2978 } else if (!strncmp(str
, "cbmemsize=", 10)) {
2979 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
2980 } else if (!strncmp(str
, "resource_alignment=", 19)) {
2981 pci_set_resource_alignment_param(str
+ 19,
2983 } else if (!strncmp(str
, "ecrc=", 5)) {
2984 pcie_ecrc_get_policy(str
+ 5);
2985 } else if (!strncmp(str
, "hpiosize=", 9)) {
2986 pci_hotplug_io_size
= memparse(str
+ 9, &str
);
2987 } else if (!strncmp(str
, "hpmemsize=", 10)) {
2988 pci_hotplug_mem_size
= memparse(str
+ 10, &str
);
2990 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
2998 early_param("pci", pci_setup
);
3000 EXPORT_SYMBOL(pci_reenable_device
);
3001 EXPORT_SYMBOL(pci_enable_device_io
);
3002 EXPORT_SYMBOL(pci_enable_device_mem
);
3003 EXPORT_SYMBOL(pci_enable_device
);
3004 EXPORT_SYMBOL(pcim_enable_device
);
3005 EXPORT_SYMBOL(pcim_pin_device
);
3006 EXPORT_SYMBOL(pci_disable_device
);
3007 EXPORT_SYMBOL(pci_find_capability
);
3008 EXPORT_SYMBOL(pci_bus_find_capability
);
3009 EXPORT_SYMBOL(pci_release_regions
);
3010 EXPORT_SYMBOL(pci_request_regions
);
3011 EXPORT_SYMBOL(pci_request_regions_exclusive
);
3012 EXPORT_SYMBOL(pci_release_region
);
3013 EXPORT_SYMBOL(pci_request_region
);
3014 EXPORT_SYMBOL(pci_request_region_exclusive
);
3015 EXPORT_SYMBOL(pci_release_selected_regions
);
3016 EXPORT_SYMBOL(pci_request_selected_regions
);
3017 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
3018 EXPORT_SYMBOL(pci_set_master
);
3019 EXPORT_SYMBOL(pci_clear_master
);
3020 EXPORT_SYMBOL(pci_set_mwi
);
3021 EXPORT_SYMBOL(pci_try_set_mwi
);
3022 EXPORT_SYMBOL(pci_clear_mwi
);
3023 EXPORT_SYMBOL_GPL(pci_intx
);
3024 EXPORT_SYMBOL(pci_assign_resource
);
3025 EXPORT_SYMBOL(pci_find_parent_resource
);
3026 EXPORT_SYMBOL(pci_select_bars
);
3028 EXPORT_SYMBOL(pci_set_power_state
);
3029 EXPORT_SYMBOL(pci_save_state
);
3030 EXPORT_SYMBOL(pci_restore_state
);
3031 EXPORT_SYMBOL(pci_pme_capable
);
3032 EXPORT_SYMBOL(pci_pme_active
);
3033 EXPORT_SYMBOL(pci_wake_from_d3
);
3034 EXPORT_SYMBOL(pci_target_state
);
3035 EXPORT_SYMBOL(pci_prepare_to_sleep
);
3036 EXPORT_SYMBOL(pci_back_from_sleep
);
3037 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);