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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / wireless / zd1211rw / zd_chip.c
blob63e85ccb3adf24af6e72f77bbfcccdf920e0a402
1 /* ZD1211 USB-WLAN driver for Linux
2 *
3 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
4 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 /* This file implements all the hardware specific functions for the ZD1211
22 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
23 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/errno.h>
28 #include <linux/slab.h>
29
30 #include "zd_def.h"
31 #include "zd_chip.h"
32 #include "zd_mac.h"
33 #include "zd_rf.h"
34
35 void zd_chip_init(struct zd_chip *chip,
36 struct ieee80211_hw *hw,
37 struct usb_interface *intf)
38 {
39 memset(chip, 0, sizeof(*chip));
40 mutex_init(&chip->mutex);
41 zd_usb_init(&chip->usb, hw, intf);
42 zd_rf_init(&chip->rf);
43 }
44
45 void zd_chip_clear(struct zd_chip *chip)
46 {
47 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
48 zd_usb_clear(&chip->usb);
49 zd_rf_clear(&chip->rf);
50 mutex_destroy(&chip->mutex);
51 ZD_MEMCLEAR(chip, sizeof(*chip));
52 }
53
54 static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size)
55 {
56 u8 *addr = zd_mac_get_perm_addr(zd_chip_to_mac(chip));
57 return scnprintf(buffer, size, "%02x-%02x-%02x",
58 addr[0], addr[1], addr[2]);
59 }
60
61 /* Prints an identifier line, which will support debugging. */
62 static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
63 {
64 int i = 0;
65
66 i = scnprintf(buffer, size, "zd1211%s chip ",
67 zd_chip_is_zd1211b(chip) ? "b" : "");
68 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
69 i += scnprintf(buffer+i, size-i, " ");
70 i += scnprint_mac_oui(chip, buffer+i, size-i);
71 i += scnprintf(buffer+i, size-i, " ");
72 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
73 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type,
74 chip->patch_cck_gain ? 'g' : '-',
75 chip->patch_cr157 ? '7' : '-',
76 chip->patch_6m_band_edge ? '6' : '-',
77 chip->new_phy_layout ? 'N' : '-',
78 chip->al2230s_bit ? 'S' : '-');
79 return i;
80 }
81
82 static void print_id(struct zd_chip *chip)
83 {
84 char buffer[80];
85
86 scnprint_id(chip, buffer, sizeof(buffer));
87 buffer[sizeof(buffer)-1] = 0;
88 dev_info(zd_chip_dev(chip), "%s\n", buffer);
89 }
90
91 static zd_addr_t inc_addr(zd_addr_t addr)
92 {
93 u16 a = (u16)addr;
94 /* Control registers use byte addressing, but everything else uses word
95 * addressing. */
96 if ((a & 0xf000) == CR_START)
97 a += 2;
98 else
99 a += 1;
100 return (zd_addr_t)a;
101 }
102
103 /* Read a variable number of 32-bit values. Parameter count is not allowed to
104 * exceed USB_MAX_IOREAD32_COUNT.
105 */
106 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
107 unsigned int count)
108 {
109 int r;
110 int i;
111 zd_addr_t *a16;
112 u16 *v16;
113 unsigned int count16;
114
115 if (count > USB_MAX_IOREAD32_COUNT)
116 return -EINVAL;
117
118 /* Allocate a single memory block for values and addresses. */
119 count16 = 2*count;
120 a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
121 GFP_KERNEL);
122 if (!a16) {
123 dev_dbg_f(zd_chip_dev(chip),
124 "error ENOMEM in allocation of a16\n");
125 r = -ENOMEM;
126 goto out;
127 }
128 v16 = (u16 *)(a16 + count16);
129
130 for (i = 0; i < count; i++) {
131 int j = 2*i;
132 /* We read the high word always first. */
133 a16[j] = inc_addr(addr[i]);
134 a16[j+1] = addr[i];
135 }
136
137 r = zd_ioread16v_locked(chip, v16, a16, count16);
138 if (r) {
139 dev_dbg_f(zd_chip_dev(chip),
140 "error: zd_ioread16v_locked. Error number %d\n", r);
141 goto out;
142 }
143
144 for (i = 0; i < count; i++) {
145 int j = 2*i;
146 values[i] = (v16[j] << 16) | v16[j+1];
147 }
148
149 out:
150 kfree((void *)a16);
151 return r;
152 }
153
154 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
155 unsigned int count)
156 {
157 int i, j, r;
158 struct zd_ioreq16 *ioreqs16;
159 unsigned int count16;
160
161 ZD_ASSERT(mutex_is_locked(&chip->mutex));
162
163 if (count == 0)
164 return 0;
165 if (count > USB_MAX_IOWRITE32_COUNT)
166 return -EINVAL;
167
168 /* Allocate a single memory block for values and addresses. */
169 count16 = 2*count;
170 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_KERNEL);
171 if (!ioreqs16) {
172 r = -ENOMEM;
173 dev_dbg_f(zd_chip_dev(chip),
174 "error %d in ioreqs16 allocation\n", r);
175 goto out;
176 }
177
178 for (i = 0; i < count; i++) {
179 j = 2*i;
180 /* We write the high word always first. */
181 ioreqs16[j].value = ioreqs[i].value >> 16;
182 ioreqs16[j].addr = inc_addr(ioreqs[i].addr);
183 ioreqs16[j+1].value = ioreqs[i].value;
184 ioreqs16[j+1].addr = ioreqs[i].addr;
185 }
186
187 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
188 #ifdef DEBUG
189 if (r) {
190 dev_dbg_f(zd_chip_dev(chip),
191 "error %d in zd_usb_write16v\n", r);
192 }
193 #endif /* DEBUG */
194 out:
195 kfree(ioreqs16);
196 return r;
197 }
198
199 int zd_iowrite16a_locked(struct zd_chip *chip,
200 const struct zd_ioreq16 *ioreqs, unsigned int count)
201 {
202 int r;
203 unsigned int i, j, t, max;
204
205 ZD_ASSERT(mutex_is_locked(&chip->mutex));
206 for (i = 0; i < count; i += j + t) {
207 t = 0;
208 max = count-i;
209 if (max > USB_MAX_IOWRITE16_COUNT)
210 max = USB_MAX_IOWRITE16_COUNT;
211 for (j = 0; j < max; j++) {
212 if (!ioreqs[i+j].addr) {
213 t = 1;
214 break;
215 }
216 }
217
218 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
219 if (r) {
220 dev_dbg_f(zd_chip_dev(chip),
221 "error zd_usb_iowrite16v. Error number %d\n",
222 r);
223 return r;
224 }
225 }
226
227 return 0;
228 }
229
230 /* Writes a variable number of 32 bit registers. The functions will split
231 * that in several USB requests. A split can be forced by inserting an IO
232 * request with an zero address field.
233 */
234 int zd_iowrite32a_locked(struct zd_chip *chip,
235 const struct zd_ioreq32 *ioreqs, unsigned int count)
236 {
237 int r;
238 unsigned int i, j, t, max;
239
240 for (i = 0; i < count; i += j + t) {
241 t = 0;
242 max = count-i;
243 if (max > USB_MAX_IOWRITE32_COUNT)
244 max = USB_MAX_IOWRITE32_COUNT;
245 for (j = 0; j < max; j++) {
246 if (!ioreqs[i+j].addr) {
247 t = 1;
248 break;
249 }
250 }
251
252 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
253 if (r) {
254 dev_dbg_f(zd_chip_dev(chip),
255 "error _zd_iowrite32v_locked."
256 " Error number %d\n", r);
257 return r;
258 }
259 }
260
261 return 0;
262 }
263
264 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
265 {
266 int r;
267
268 mutex_lock(&chip->mutex);
269 r = zd_ioread16_locked(chip, value, addr);
270 mutex_unlock(&chip->mutex);
271 return r;
272 }
273
274 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
275 {
276 int r;
277
278 mutex_lock(&chip->mutex);
279 r = zd_ioread32_locked(chip, value, addr);
280 mutex_unlock(&chip->mutex);
281 return r;
282 }
283
284 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
285 {
286 int r;
287
288 mutex_lock(&chip->mutex);
289 r = zd_iowrite16_locked(chip, value, addr);
290 mutex_unlock(&chip->mutex);
291 return r;
292 }
293
294 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
295 {
296 int r;
297
298 mutex_lock(&chip->mutex);
299 r = zd_iowrite32_locked(chip, value, addr);
300 mutex_unlock(&chip->mutex);
301 return r;
302 }
303
304 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
305 u32 *values, unsigned int count)
306 {
307 int r;
308
309 mutex_lock(&chip->mutex);
310 r = zd_ioread32v_locked(chip, values, addresses, count);
311 mutex_unlock(&chip->mutex);
312 return r;
313 }
314
315 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
316 unsigned int count)
317 {
318 int r;
319
320 mutex_lock(&chip->mutex);
321 r = zd_iowrite32a_locked(chip, ioreqs, count);
322 mutex_unlock(&chip->mutex);
323 return r;
324 }
325
326 static int read_pod(struct zd_chip *chip, u8 *rf_type)
327 {
328 int r;
329 u32 value;
330
331 ZD_ASSERT(mutex_is_locked(&chip->mutex));
332 r = zd_ioread32_locked(chip, &value, E2P_POD);
333 if (r)
334 goto error;
335 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
336
337 *rf_type = value & 0x0f;
338 chip->pa_type = (value >> 16) & 0x0f;
339 chip->patch_cck_gain = (value >> 8) & 0x1;
340 chip->patch_cr157 = (value >> 13) & 0x1;
341 chip->patch_6m_band_edge = (value >> 21) & 0x1;
342 chip->new_phy_layout = (value >> 31) & 0x1;
343 chip->al2230s_bit = (value >> 7) & 0x1;
344 chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
345 chip->supports_tx_led = 1;
346 if (value & (1 << 24)) { /* LED scenario */
347 if (value & (1 << 29))
348 chip->supports_tx_led = 0;
349 }
350
351 dev_dbg_f(zd_chip_dev(chip),
352 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
353 "patch 6M %d new PHY %d link LED%d tx led %d\n",
354 zd_rf_name(*rf_type), *rf_type,
355 chip->pa_type, chip->patch_cck_gain,
356 chip->patch_cr157, chip->patch_6m_band_edge,
357 chip->new_phy_layout,
358 chip->link_led == LED1 ? 1 : 2,
359 chip->supports_tx_led);
360 return 0;
361 error:
362 *rf_type = 0;
363 chip->pa_type = 0;
364 chip->patch_cck_gain = 0;
365 chip->patch_cr157 = 0;
366 chip->patch_6m_band_edge = 0;
367 chip->new_phy_layout = 0;
368 return r;
369 }
370
371 /* MAC address: if custom mac addresses are to be used CR_MAC_ADDR_P1 and
372 * CR_MAC_ADDR_P2 must be overwritten
373 */
374 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
375 {
376 int r;
377 struct zd_ioreq32 reqs[2] = {
378 [0] = { .addr = CR_MAC_ADDR_P1 },
379 [1] = { .addr = CR_MAC_ADDR_P2 },
380 };
381
382 if (mac_addr) {
383 reqs[0].value = (mac_addr[3] << 24)
384 | (mac_addr[2] << 16)
385 | (mac_addr[1] << 8)
386 | mac_addr[0];
387 reqs[1].value = (mac_addr[5] << 8)
388 | mac_addr[4];
389 dev_dbg_f(zd_chip_dev(chip), "mac addr %pM\n", mac_addr);
390 } else {
391 dev_dbg_f(zd_chip_dev(chip), "set NULL mac\n");
392 }
393
394 mutex_lock(&chip->mutex);
395 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
396 mutex_unlock(&chip->mutex);
397 return r;
398 }
399
400 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
401 {
402 int r;
403 u32 value;
404
405 mutex_lock(&chip->mutex);
406 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
407 mutex_unlock(&chip->mutex);
408 if (r)
409 return r;
410
411 *regdomain = value >> 16;
412 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
413
414 return 0;
415 }
416
417 static int read_values(struct zd_chip *chip, u8 *values, size_t count,
418 zd_addr_t e2p_addr, u32 guard)
419 {
420 int r;
421 int i;
422 u32 v;
423
424 ZD_ASSERT(mutex_is_locked(&chip->mutex));
425 for (i = 0;;) {
426 r = zd_ioread32_locked(chip, &v,
427 (zd_addr_t)((u16)e2p_addr+i/2));
428 if (r)
429 return r;
430 v -= guard;
431 if (i+4 < count) {
432 values[i++] = v;
433 values[i++] = v >> 8;
434 values[i++] = v >> 16;
435 values[i++] = v >> 24;
436 continue;
437 }
438 for (;i < count; i++)
439 values[i] = v >> (8*(i%3));
440 return 0;
441 }
442 }
443
444 static int read_pwr_cal_values(struct zd_chip *chip)
445 {
446 return read_values(chip, chip->pwr_cal_values,
447 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
448 0);
449 }
450
451 static int read_pwr_int_values(struct zd_chip *chip)
452 {
453 return read_values(chip, chip->pwr_int_values,
454 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
455 E2P_PWR_INT_GUARD);
456 }
457
458 static int read_ofdm_cal_values(struct zd_chip *chip)
459 {
460 int r;
461 int i;
462 static const zd_addr_t addresses[] = {
463 E2P_36M_CAL_VALUE1,
464 E2P_48M_CAL_VALUE1,
465 E2P_54M_CAL_VALUE1,
466 };
467
468 for (i = 0; i < 3; i++) {
469 r = read_values(chip, chip->ofdm_cal_values[i],
470 E2P_CHANNEL_COUNT, addresses[i], 0);
471 if (r)
472 return r;
473 }
474 return 0;
475 }
476
477 static int read_cal_int_tables(struct zd_chip *chip)
478 {
479 int r;
480
481 r = read_pwr_cal_values(chip);
482 if (r)
483 return r;
484 r = read_pwr_int_values(chip);
485 if (r)
486 return r;
487 r = read_ofdm_cal_values(chip);
488 if (r)
489 return r;
490 return 0;
491 }
492
493 /* phy means physical registers */
494 int zd_chip_lock_phy_regs(struct zd_chip *chip)
495 {
496 int r;
497 u32 tmp;
498
499 ZD_ASSERT(mutex_is_locked(&chip->mutex));
500 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
501 if (r) {
502 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
503 return r;
504 }
505
506 tmp &= ~UNLOCK_PHY_REGS;
507
508 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
509 if (r)
510 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
511 return r;
512 }
513
514 int zd_chip_unlock_phy_regs(struct zd_chip *chip)
515 {
516 int r;
517 u32 tmp;
518
519 ZD_ASSERT(mutex_is_locked(&chip->mutex));
520 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
521 if (r) {
522 dev_err(zd_chip_dev(chip),
523 "error ioread32(CR_REG1): %d\n", r);
524 return r;
525 }
526
527 tmp |= UNLOCK_PHY_REGS;
528
529 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
530 if (r)
531 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
532 return r;
533 }
534
535 /* CR157 can be optionally patched by the EEPROM for original ZD1211 */
536 static int patch_cr157(struct zd_chip *chip)
537 {
538 int r;
539 u16 value;
540
541 if (!chip->patch_cr157)
542 return 0;
543
544 r = zd_ioread16_locked(chip, &value, E2P_PHY_REG);
545 if (r)
546 return r;
547
548 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
549 return zd_iowrite32_locked(chip, value >> 8, CR157);
550 }
551
552 /*
553 * 6M band edge can be optionally overwritten for certain RF's
554 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
555 * bit (for AL2230, AL2230S)
556 */
557 static int patch_6m_band_edge(struct zd_chip *chip, u8 channel)
558 {
559 ZD_ASSERT(mutex_is_locked(&chip->mutex));
560 if (!chip->patch_6m_band_edge)
561 return 0;
562
563 return zd_rf_patch_6m_band_edge(&chip->rf, channel);
564 }
565
566 /* Generic implementation of 6M band edge patching, used by most RFs via
567 * zd_rf_generic_patch_6m() */
568 int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel)
569 {
570 struct zd_ioreq16 ioreqs[] = {
571 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
572 { CR47, 0x1e },
573 };
574
575 if (channel == 1 || channel == 11)
576 ioreqs[0].value = 0x12;
577
578 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
579 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
580 }
581
582 static int zd1211_hw_reset_phy(struct zd_chip *chip)
583 {
584 static const struct zd_ioreq16 ioreqs[] = {
585 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
586 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
587 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
588 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
589 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
590 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
591 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
592 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
593 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
594 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
595 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
596 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
597 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
598 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
599 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
600 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
601 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
602 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
603 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
604 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
605 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
606 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
607 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
608 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
609 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
610 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
611 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
612 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
613 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
614 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
615 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
616 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
617 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
618 { },
619 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
620 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
621 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
622 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
623 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
624 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
625 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
626 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
627 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
628 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
629 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
630 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
631 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
632 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
633 { CR125, 0xaa }, { CR127, 0x03 }, { CR128, 0x14 },
634 { CR129, 0x12 }, { CR130, 0x10 }, { CR131, 0x0C },
635 { CR136, 0xdf }, { CR137, 0x40 }, { CR138, 0xa0 },
636 { CR139, 0xb0 }, { CR140, 0x99 }, { CR141, 0x82 },
637 { CR142, 0x54 }, { CR143, 0x1c }, { CR144, 0x6c },
638 { CR147, 0x07 }, { CR148, 0x4c }, { CR149, 0x50 },
639 { CR150, 0x0e }, { CR151, 0x18 }, { CR160, 0xfe },
640 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
641 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
642 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
643 { CR170, 0xba }, { CR171, 0xba },
644 /* Note: CR204 must lead the CR203 */
645 { CR204, 0x7d },
646 { },
647 { CR203, 0x30 },
648 };
649
650 int r, t;
651
652 dev_dbg_f(zd_chip_dev(chip), "\n");
653
654 r = zd_chip_lock_phy_regs(chip);
655 if (r)
656 goto out;
657
658 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
659 if (r)
660 goto unlock;
661
662 r = patch_cr157(chip);
663 unlock:
664 t = zd_chip_unlock_phy_regs(chip);
665 if (t && !r)
666 r = t;
667 out:
668 return r;
669 }
670
671 static int zd1211b_hw_reset_phy(struct zd_chip *chip)
672 {
673 static const struct zd_ioreq16 ioreqs[] = {
674 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
675 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
676 { CR10, 0x81 },
677 /* power control { { CR11, 1 << 6 }, */
678 { CR11, 0x00 },
679 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
680 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
681 { CR18, 0x0a }, { CR19, 0x48 },
682 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
683 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
684 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
685 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
686 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
687 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
688 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
689 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
690 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
691 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
692 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
693 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
694 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
695 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
696 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
697 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
698 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
699 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
700 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
701 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
702 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
703 { CR94, 0x01 },
704 { CR95, 0x20 }, /* ZD1211B */
705 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
706 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
707 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
708 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
709 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
710 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
711 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
712 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
713 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
714 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
715 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
716 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
717 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
718 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
719 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
720 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
721 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
722 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
723 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
724 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
725 { CR170, 0xba }, { CR171, 0xba },
726 /* Note: CR204 must lead the CR203 */
727 { CR204, 0x7d },
728 {},
729 { CR203, 0x30 },
730 };
731
732 int r, t;
733
734 dev_dbg_f(zd_chip_dev(chip), "\n");
735
736 r = zd_chip_lock_phy_regs(chip);
737 if (r)
738 goto out;
739
740 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
741 t = zd_chip_unlock_phy_regs(chip);
742 if (t && !r)
743 r = t;
744 out:
745 return r;
746 }
747
748 static int hw_reset_phy(struct zd_chip *chip)
749 {
750 return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) :
751 zd1211_hw_reset_phy(chip);
752 }
753
754 static int zd1211_hw_init_hmac(struct zd_chip *chip)
755 {
756 static const struct zd_ioreq32 ioreqs[] = {
757 { CR_ZD1211_RETRY_MAX, ZD1211_RETRY_COUNT },
758 { CR_RX_THRESHOLD, 0x000c0640 },
759 };
760
761 dev_dbg_f(zd_chip_dev(chip), "\n");
762 ZD_ASSERT(mutex_is_locked(&chip->mutex));
763 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
764 }
765
766 static int zd1211b_hw_init_hmac(struct zd_chip *chip)
767 {
768 static const struct zd_ioreq32 ioreqs[] = {
769 { CR_ZD1211B_RETRY_MAX, ZD1211B_RETRY_COUNT },
770 { CR_ZD1211B_CWIN_MAX_MIN_AC0, 0x007f003f },
771 { CR_ZD1211B_CWIN_MAX_MIN_AC1, 0x007f003f },
772 { CR_ZD1211B_CWIN_MAX_MIN_AC2, 0x003f001f },
773 { CR_ZD1211B_CWIN_MAX_MIN_AC3, 0x001f000f },
774 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
775 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
776 { CR_ZD1211B_TXOP, 0x01800824 },
777 { CR_RX_THRESHOLD, 0x000c0eff, },
778 };
779
780 dev_dbg_f(zd_chip_dev(chip), "\n");
781 ZD_ASSERT(mutex_is_locked(&chip->mutex));
782 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
783 }
784
785 static int hw_init_hmac(struct zd_chip *chip)
786 {
787 int r;
788 static const struct zd_ioreq32 ioreqs[] = {
789 { CR_ACK_TIMEOUT_EXT, 0x20 },
790 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
791 { CR_SNIFFER_ON, 0 },
792 { CR_RX_FILTER, STA_RX_FILTER },
793 { CR_GROUP_HASH_P1, 0x00 },
794 { CR_GROUP_HASH_P2, 0x80000000 },
795 { CR_REG1, 0xa4 },
796 { CR_ADDA_PWR_DWN, 0x7f },
797 { CR_BCN_PLCP_CFG, 0x00f00401 },
798 { CR_PHY_DELAY, 0x00 },
799 { CR_ACK_TIMEOUT_EXT, 0x80 },
800 { CR_ADDA_PWR_DWN, 0x00 },
801 { CR_ACK_TIME_80211, 0x100 },
802 { CR_RX_PE_DELAY, 0x70 },
803 { CR_PS_CTRL, 0x10000000 },
804 { CR_RTS_CTS_RATE, 0x02030203 },
805 { CR_AFTER_PNP, 0x1 },
806 { CR_WEP_PROTECT, 0x114 },
807 { CR_IFS_VALUE, IFS_VALUE_DEFAULT },
808 { CR_CAM_MODE, MODE_AP_WDS},
809 };
810
811 ZD_ASSERT(mutex_is_locked(&chip->mutex));
812 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
813 if (r)
814 return r;
815
816 return zd_chip_is_zd1211b(chip) ?
817 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
818 }
819
820 struct aw_pt_bi {
821 u32 atim_wnd_period;
822 u32 pre_tbtt;
823 u32 beacon_interval;
824 };
825
826 static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
827 {
828 int r;
829 static const zd_addr_t aw_pt_bi_addr[] =
830 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
831 u32 values[3];
832
833 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
834 ARRAY_SIZE(aw_pt_bi_addr));
835 if (r) {
836 memset(s, 0, sizeof(*s));
837 return r;
838 }
839
840 s->atim_wnd_period = values[0];
841 s->pre_tbtt = values[1];
842 s->beacon_interval = values[2];
843 return 0;
844 }
845
846 static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
847 {
848 struct zd_ioreq32 reqs[3];
849
850 if (s->beacon_interval <= 5)
851 s->beacon_interval = 5;
852 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
853 s->pre_tbtt = s->beacon_interval - 1;
854 if (s->atim_wnd_period >= s->pre_tbtt)
855 s->atim_wnd_period = s->pre_tbtt - 1;
856
857 reqs[0].addr = CR_ATIM_WND_PERIOD;
858 reqs[0].value = s->atim_wnd_period;
859 reqs[1].addr = CR_PRE_TBTT;
860 reqs[1].value = s->pre_tbtt;
861 reqs[2].addr = CR_BCN_INTERVAL;
862 reqs[2].value = s->beacon_interval;
863
864 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
865 }
866
867
868 static int set_beacon_interval(struct zd_chip *chip, u32 interval)
869 {
870 int r;
871 struct aw_pt_bi s;
872
873 ZD_ASSERT(mutex_is_locked(&chip->mutex));
874 r = get_aw_pt_bi(chip, &s);
875 if (r)
876 return r;
877 s.beacon_interval = interval;
878 return set_aw_pt_bi(chip, &s);
879 }
880
881 int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
882 {
883 int r;
884
885 mutex_lock(&chip->mutex);
886 r = set_beacon_interval(chip, interval);
887 mutex_unlock(&chip->mutex);
888 return r;
889 }
890
891 static int hw_init(struct zd_chip *chip)
892 {
893 int r;
894
895 dev_dbg_f(zd_chip_dev(chip), "\n");
896 ZD_ASSERT(mutex_is_locked(&chip->mutex));
897 r = hw_reset_phy(chip);
898 if (r)
899 return r;
900
901 r = hw_init_hmac(chip);
902 if (r)
903 return r;
904
905 return set_beacon_interval(chip, 100);
906 }
907
908 static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset)
909 {
910 return (zd_addr_t)((u16)chip->fw_regs_base + offset);
911 }
912
913 #ifdef DEBUG
914 static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
915 const char *addr_string)
916 {
917 int r;
918 u32 value;
919
920 r = zd_ioread32_locked(chip, &value, addr);
921 if (r) {
922 dev_dbg_f(zd_chip_dev(chip),
923 "error reading %s. Error number %d\n", addr_string, r);
924 return r;
925 }
926
927 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
928 addr_string, (unsigned int)value);
929 return 0;
930 }
931
932 static int test_init(struct zd_chip *chip)
933 {
934 int r;
935
936 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
937 if (r)
938 return r;
939 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
940 if (r)
941 return r;
942 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
943 }
944
945 static void dump_fw_registers(struct zd_chip *chip)
946 {
947 const zd_addr_t addr[4] = {
948 fw_reg_addr(chip, FW_REG_FIRMWARE_VER),
949 fw_reg_addr(chip, FW_REG_USB_SPEED),
950 fw_reg_addr(chip, FW_REG_FIX_TX_RATE),
951 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
952 };
953
954 int r;
955 u16 values[4];
956
957 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
958 ARRAY_SIZE(addr));
959 if (r) {
960 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
961 r);
962 return;
963 }
964
965 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
966 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
967 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
968 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
969 }
970 #endif /* DEBUG */
971
972 static int print_fw_version(struct zd_chip *chip)
973 {
974 int r;
975 u16 version;
976
977 r = zd_ioread16_locked(chip, &version,
978 fw_reg_addr(chip, FW_REG_FIRMWARE_VER));
979 if (r)
980 return r;
981
982 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
983 return 0;
984 }
985
986 static int set_mandatory_rates(struct zd_chip *chip, int gmode)
987 {
988 u32 rates;
989 ZD_ASSERT(mutex_is_locked(&chip->mutex));
990 /* This sets the mandatory rates, which only depend from the standard
991 * that the device is supporting. Until further notice we should try
992 * to support 802.11g also for full speed USB.
993 */
994 if (!gmode)
995 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
996 else
997 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
998 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
999
1000 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1001 }
1002
1003 int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
1004 int preamble)
1005 {
1006 u32 value = 0;
1007
1008 dev_dbg_f(zd_chip_dev(chip), "preamble=%x\n", preamble);
1009 value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1010 value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1011
1012 /* We always send 11M RTS/self-CTS messages, like the vendor driver. */
1013 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_RTS_RATE;
1014 value |= ZD_RX_CCK << RTSCTS_SH_RTS_MOD_TYPE;
1015 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_CTS_RATE;
1016 value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1017
1018 return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1019 }
1020
1021 int zd_chip_enable_hwint(struct zd_chip *chip)
1022 {
1023 int r;
1024
1025 mutex_lock(&chip->mutex);
1026 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1027 mutex_unlock(&chip->mutex);
1028 return r;
1029 }
1030
1031 static int disable_hwint(struct zd_chip *chip)
1032 {
1033 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1034 }
1035
1036 int zd_chip_disable_hwint(struct zd_chip *chip)
1037 {
1038 int r;
1039
1040 mutex_lock(&chip->mutex);
1041 r = disable_hwint(chip);
1042 mutex_unlock(&chip->mutex);
1043 return r;
1044 }
1045
1046 static int read_fw_regs_offset(struct zd_chip *chip)
1047 {
1048 int r;
1049
1050 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1051 r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base,
1052 FWRAW_REGS_ADDR);
1053 if (r)
1054 return r;
1055 dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n",
1056 (u16)chip->fw_regs_base);
1057
1058 return 0;
1059 }
1060
1061 /* Read mac address using pre-firmware interface */
1062 int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr)
1063 {
1064 dev_dbg_f(zd_chip_dev(chip), "\n");
1065 return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr,
1066 ETH_ALEN);
1067 }
1068
1069 int zd_chip_init_hw(struct zd_chip *chip)
1070 {
1071 int r;
1072 u8 rf_type;
1073
1074 dev_dbg_f(zd_chip_dev(chip), "\n");
1075
1076 mutex_lock(&chip->mutex);
1077
1078 #ifdef DEBUG
1079 r = test_init(chip);
1080 if (r)
1081 goto out;
1082 #endif
1083 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1084 if (r)
1085 goto out;
1086
1087 r = read_fw_regs_offset(chip);
1088 if (r)
1089 goto out;
1090
1091 /* GPI is always disabled, also in the other driver.
1092 */
1093 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1094 if (r)
1095 goto out;
1096 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1097 if (r)
1098 goto out;
1099 /* Currently we support IEEE 802.11g for full and high speed USB.
1100 * It might be discussed, whether we should suppport pure b mode for
1101 * full speed USB.
1102 */
1103 r = set_mandatory_rates(chip, 1);
1104 if (r)
1105 goto out;
1106 /* Disabling interrupts is certainly a smart thing here.
1107 */
1108 r = disable_hwint(chip);
1109 if (r)
1110 goto out;
1111 r = read_pod(chip, &rf_type);
1112 if (r)
1113 goto out;
1114 r = hw_init(chip);
1115 if (r)
1116 goto out;
1117 r = zd_rf_init_hw(&chip->rf, rf_type);
1118 if (r)
1119 goto out;
1120
1121 r = print_fw_version(chip);
1122 if (r)
1123 goto out;
1124
1125 #ifdef DEBUG
1126 dump_fw_registers(chip);
1127 r = test_init(chip);
1128 if (r)
1129 goto out;
1130 #endif /* DEBUG */
1131
1132 r = read_cal_int_tables(chip);
1133 if (r)
1134 goto out;
1135
1136 print_id(chip);
1137 out:
1138 mutex_unlock(&chip->mutex);
1139 return r;
1140 }
1141
1142 static int update_pwr_int(struct zd_chip *chip, u8 channel)
1143 {
1144 u8 value = chip->pwr_int_values[channel - 1];
1145 return zd_iowrite16_locked(chip, value, CR31);
1146 }
1147
1148 static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1149 {
1150 u8 value = chip->pwr_cal_values[channel-1];
1151 return zd_iowrite16_locked(chip, value, CR68);
1152 }
1153
1154 static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1155 {
1156 struct zd_ioreq16 ioreqs[3];
1157
1158 ioreqs[0].addr = CR67;
1159 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1160 ioreqs[1].addr = CR66;
1161 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1162 ioreqs[2].addr = CR65;
1163 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1164
1165 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1166 }
1167
1168 static int update_channel_integration_and_calibration(struct zd_chip *chip,
1169 u8 channel)
1170 {
1171 int r;
1172
1173 if (!zd_rf_should_update_pwr_int(&chip->rf))
1174 return 0;
1175
1176 r = update_pwr_int(chip, channel);
1177 if (r)
1178 return r;
1179 if (zd_chip_is_zd1211b(chip)) {
1180 static const struct zd_ioreq16 ioreqs[] = {
1181 { CR69, 0x28 },
1182 {},
1183 { CR69, 0x2a },
1184 };
1185
1186 r = update_ofdm_cal(chip, channel);
1187 if (r)
1188 return r;
1189 r = update_pwr_cal(chip, channel);
1190 if (r)
1191 return r;
1192 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1193 if (r)
1194 return r;
1195 }
1196
1197 return 0;
1198 }
1199
1200 /* The CCK baseband gain can be optionally patched by the EEPROM */
1201 static int patch_cck_gain(struct zd_chip *chip)
1202 {
1203 int r;
1204 u32 value;
1205
1206 if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf))
1207 return 0;
1208
1209 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1210 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1211 if (r)
1212 return r;
1213 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1214 return zd_iowrite16_locked(chip, value & 0xff, CR47);
1215 }
1216
1217 int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1218 {
1219 int r, t;
1220
1221 mutex_lock(&chip->mutex);
1222 r = zd_chip_lock_phy_regs(chip);
1223 if (r)
1224 goto out;
1225 r = zd_rf_set_channel(&chip->rf, channel);
1226 if (r)
1227 goto unlock;
1228 r = update_channel_integration_and_calibration(chip, channel);
1229 if (r)
1230 goto unlock;
1231 r = patch_cck_gain(chip);
1232 if (r)
1233 goto unlock;
1234 r = patch_6m_band_edge(chip, channel);
1235 if (r)
1236 goto unlock;
1237 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1238 unlock:
1239 t = zd_chip_unlock_phy_regs(chip);
1240 if (t && !r)
1241 r = t;
1242 out:
1243 mutex_unlock(&chip->mutex);
1244 return r;
1245 }
1246
1247 u8 zd_chip_get_channel(struct zd_chip *chip)
1248 {
1249 u8 channel;
1250
1251 mutex_lock(&chip->mutex);
1252 channel = chip->rf.channel;
1253 mutex_unlock(&chip->mutex);
1254 return channel;
1255 }
1256
1257 int zd_chip_control_leds(struct zd_chip *chip, enum led_status status)
1258 {
1259 const zd_addr_t a[] = {
1260 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
1261 CR_LED,
1262 };
1263
1264 int r;
1265 u16 v[ARRAY_SIZE(a)];
1266 struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = {
1267 [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) },
1268 [1] = { CR_LED },
1269 };
1270 u16 other_led;
1271
1272 mutex_lock(&chip->mutex);
1273 r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a));
1274 if (r)
1275 goto out;
1276
1277 other_led = chip->link_led == LED1 ? LED2 : LED1;
1278
1279 switch (status) {
1280 case ZD_LED_OFF:
1281 ioreqs[0].value = FW_LINK_OFF;
1282 ioreqs[1].value = v[1] & ~(LED1|LED2);
1283 break;
1284 case ZD_LED_SCANNING:
1285 ioreqs[0].value = FW_LINK_OFF;
1286 ioreqs[1].value = v[1] & ~other_led;
1287 if (get_seconds() % 3 == 0) {
1288 ioreqs[1].value &= ~chip->link_led;
1289 } else {
1290 ioreqs[1].value |= chip->link_led;
1291 }
1292 break;
1293 case ZD_LED_ASSOCIATED:
1294 ioreqs[0].value = FW_LINK_TX;
1295 ioreqs[1].value = v[1] & ~other_led;
1296 ioreqs[1].value |= chip->link_led;
1297 break;
1298 default:
1299 r = -EINVAL;
1300 goto out;
1301 }
1302
1303 if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
1304 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1305 if (r)
1306 goto out;
1307 }
1308 r = 0;
1309 out:
1310 mutex_unlock(&chip->mutex);
1311 return r;
1312 }
1313
1314 int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates)
1315 {
1316 int r;
1317
1318 if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G))
1319 return -EINVAL;
1320
1321 mutex_lock(&chip->mutex);
1322 r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1323 mutex_unlock(&chip->mutex);
1324 return r;
1325 }
1326
1327 static inline u8 zd_rate_from_ofdm_plcp_header(const void *rx_frame)
1328 {
1329 return ZD_OFDM | zd_ofdm_plcp_header_rate(rx_frame);
1330 }
1331
1332 /**
1333 * zd_rx_rate - report zd-rate
1334 * @rx_frame - received frame
1335 * @rx_status - rx_status as given by the device
1336 *
1337 * This function converts the rate as encoded in the received packet to the
1338 * zd-rate, we are using on other places in the driver.
1339 */
1340 u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1341 {
1342 u8 zd_rate;
1343 if (status->frame_status & ZD_RX_OFDM) {
1344 zd_rate = zd_rate_from_ofdm_plcp_header(rx_frame);
1345 } else {
1346 switch (zd_cck_plcp_header_signal(rx_frame)) {
1347 case ZD_CCK_PLCP_SIGNAL_1M:
1348 zd_rate = ZD_CCK_RATE_1M;
1349 break;
1350 case ZD_CCK_PLCP_SIGNAL_2M:
1351 zd_rate = ZD_CCK_RATE_2M;
1352 break;
1353 case ZD_CCK_PLCP_SIGNAL_5M5:
1354 zd_rate = ZD_CCK_RATE_5_5M;
1355 break;
1356 case ZD_CCK_PLCP_SIGNAL_11M:
1357 zd_rate = ZD_CCK_RATE_11M;
1358 break;
1359 default:
1360 zd_rate = 0;
1361 }
1362 }
1363
1364 return zd_rate;
1365 }
1366
1367 int zd_chip_switch_radio_on(struct zd_chip *chip)
1368 {
1369 int r;
1370
1371 mutex_lock(&chip->mutex);
1372 r = zd_switch_radio_on(&chip->rf);
1373 mutex_unlock(&chip->mutex);
1374 return r;
1375 }
1376
1377 int zd_chip_switch_radio_off(struct zd_chip *chip)
1378 {
1379 int r;
1380
1381 mutex_lock(&chip->mutex);
1382 r = zd_switch_radio_off(&chip->rf);
1383 mutex_unlock(&chip->mutex);
1384 return r;
1385 }
1386
1387 int zd_chip_enable_int(struct zd_chip *chip)
1388 {
1389 int r;
1390
1391 mutex_lock(&chip->mutex);
1392 r = zd_usb_enable_int(&chip->usb);
1393 mutex_unlock(&chip->mutex);
1394 return r;
1395 }
1396
1397 void zd_chip_disable_int(struct zd_chip *chip)
1398 {
1399 mutex_lock(&chip->mutex);
1400 zd_usb_disable_int(&chip->usb);
1401 mutex_unlock(&chip->mutex);
1402 }
1403
1404 int zd_chip_enable_rxtx(struct zd_chip *chip)
1405 {
1406 int r;
1407
1408 mutex_lock(&chip->mutex);
1409 zd_usb_enable_tx(&chip->usb);
1410 r = zd_usb_enable_rx(&chip->usb);
1411 mutex_unlock(&chip->mutex);
1412 return r;
1413 }
1414
1415 void zd_chip_disable_rxtx(struct zd_chip *chip)
1416 {
1417 mutex_lock(&chip->mutex);
1418 zd_usb_disable_rx(&chip->usb);
1419 zd_usb_disable_tx(&chip->usb);
1420 mutex_unlock(&chip->mutex);
1421 }
1422
1423 int zd_rfwritev_locked(struct zd_chip *chip,
1424 const u32* values, unsigned int count, u8 bits)
1425 {
1426 int r;
1427 unsigned int i;
1428
1429 for (i = 0; i < count; i++) {
1430 r = zd_rfwrite_locked(chip, values[i], bits);
1431 if (r)
1432 return r;
1433 }
1434
1435 return 0;
1436 }
1437
1438 /*
1439 * We can optionally program the RF directly through CR regs, if supported by
1440 * the hardware. This is much faster than the older method.
1441 */
1442 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
1443 {
1444 struct zd_ioreq16 ioreqs[] = {
1445 { CR244, (value >> 16) & 0xff },
1446 { CR243, (value >> 8) & 0xff },
1447 { CR242, value & 0xff },
1448 };
1449 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1450 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1451 }
1452
1453 int zd_rfwritev_cr_locked(struct zd_chip *chip,
1454 const u32 *values, unsigned int count)
1455 {
1456 int r;
1457 unsigned int i;
1458
1459 for (i = 0; i < count; i++) {
1460 r = zd_rfwrite_cr_locked(chip, values[i]);
1461 if (r)
1462 return r;
1463 }
1464
1465 return 0;
1466 }
1467
1468 int zd_chip_set_multicast_hash(struct zd_chip *chip,
1469 struct zd_mc_hash *hash)
1470 {
1471 struct zd_ioreq32 ioreqs[] = {
1472 { CR_GROUP_HASH_P1, hash->low },
1473 { CR_GROUP_HASH_P2, hash->high },
1474 };
1475
1476 return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));
1477 }
1478
1479 u64 zd_chip_get_tsf(struct zd_chip *chip)
1480 {
1481 int r;
1482 static const zd_addr_t aw_pt_bi_addr[] =
1483 { CR_TSF_LOW_PART, CR_TSF_HIGH_PART };
1484 u32 values[2];
1485 u64 tsf;
1486
1487 mutex_lock(&chip->mutex);
1488 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
1489 ARRAY_SIZE(aw_pt_bi_addr));
1490 mutex_unlock(&chip->mutex);
1491 if (r)
1492 return 0;
1493
1494 tsf = values[1];
1495 tsf = (tsf << 32) | values[0];
1496
1497 return tsf;
1498 }
Tomato firmware and modifications.