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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / wireless / rt2x00 / rt2800lib.c
blob60039d3fe0a05dbbf0afaa3db7ac8efe8378c84d
1 /*
2 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
4 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
5
6 Based on the original rt2800pci.c and rt2800usb.c.
7 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
8 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
9 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
10 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
11 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
12 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
13 <http://rt2x00.serialmonkey.com>
14
15 This program is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
19
20 This program is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
24
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, write to the
27 Free Software Foundation, Inc.,
28 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31 /*
32 Module: rt2800lib
33 Abstract: rt2800 generic device routines.
34 */
35
36 #include <linux/crc-ccitt.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/slab.h>
40
41 #include "rt2x00.h"
42 #include "rt2800lib.h"
43 #include "rt2800.h"
44
45 /*
46 * Register access.
47 * All access to the CSR registers will go through the methods
48 * rt2800_register_read and rt2800_register_write.
49 * BBP and RF register require indirect register access,
50 * and use the CSR registers BBPCSR and RFCSR to achieve this.
51 * These indirect registers work with busy bits,
52 * and we will try maximal REGISTER_BUSY_COUNT times to access
53 * the register while taking a REGISTER_BUSY_DELAY us delay
54 * between each attampt. When the busy bit is still set at that time,
55 * the access attempt is considered to have failed,
56 * and we will print an error.
57 * The _lock versions must be used if you already hold the csr_mutex
58 */
59 #define WAIT_FOR_BBP(__dev, __reg) \
60 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
61 #define WAIT_FOR_RFCSR(__dev, __reg) \
62 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
63 #define WAIT_FOR_RF(__dev, __reg) \
64 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
65 #define WAIT_FOR_MCU(__dev, __reg) \
66 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
67 H2M_MAILBOX_CSR_OWNER, (__reg))
68
69 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
70 {
71 /* check for rt2872 on SoC */
72 if (!rt2x00_is_soc(rt2x00dev) ||
73 !rt2x00_rt(rt2x00dev, RT2872))
74 return false;
75
76 /* we know for sure that these rf chipsets are used on rt305x boards */
77 if (rt2x00_rf(rt2x00dev, RF3020) ||
78 rt2x00_rf(rt2x00dev, RF3021) ||
79 rt2x00_rf(rt2x00dev, RF3022))
80 return true;
81
82 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
83 return false;
84 }
85
86 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
87 const unsigned int word, const u8 value)
88 {
89 u32 reg;
90
91 mutex_lock(&rt2x00dev->csr_mutex);
92
93 /*
94 * Wait until the BBP becomes available, afterwards we
95 * can safely write the new data into the register.
96 */
97 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
98 reg = 0;
99 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
104
105 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
106 }
107
108 mutex_unlock(&rt2x00dev->csr_mutex);
109 }
110
111 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
112 const unsigned int word, u8 *value)
113 {
114 u32 reg;
115
116 mutex_lock(&rt2x00dev->csr_mutex);
117
118 /*
119 * Wait until the BBP becomes available, afterwards we
120 * can safely write the read request into the register.
121 * After the data has been written, we wait until hardware
122 * returns the correct value, if at any time the register
123 * doesn't become available in time, reg will be 0xffffffff
124 * which means we return 0xff to the caller.
125 */
126 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
127 reg = 0;
128 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
132
133 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
134
135 WAIT_FOR_BBP(rt2x00dev, &reg);
136 }
137
138 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
139
140 mutex_unlock(&rt2x00dev->csr_mutex);
141 }
142
143 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
144 const unsigned int word, const u8 value)
145 {
146 u32 reg;
147
148 mutex_lock(&rt2x00dev->csr_mutex);
149
150 /*
151 * Wait until the RFCSR becomes available, afterwards we
152 * can safely write the new data into the register.
153 */
154 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
155 reg = 0;
156 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
157 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
160
161 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
162 }
163
164 mutex_unlock(&rt2x00dev->csr_mutex);
165 }
166
167 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
168 const unsigned int word, u8 *value)
169 {
170 u32 reg;
171
172 mutex_lock(&rt2x00dev->csr_mutex);
173
174 /*
175 * Wait until the RFCSR becomes available, afterwards we
176 * can safely write the read request into the register.
177 * After the data has been written, we wait until hardware
178 * returns the correct value, if at any time the register
179 * doesn't become available in time, reg will be 0xffffffff
180 * which means we return 0xff to the caller.
181 */
182 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
183 reg = 0;
184 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
185 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
187
188 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
189
190 WAIT_FOR_RFCSR(rt2x00dev, &reg);
191 }
192
193 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
194
195 mutex_unlock(&rt2x00dev->csr_mutex);
196 }
197
198 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
199 const unsigned int word, const u32 value)
200 {
201 u32 reg;
202
203 mutex_lock(&rt2x00dev->csr_mutex);
204
205 /*
206 * Wait until the RF becomes available, afterwards we
207 * can safely write the new data into the register.
208 */
209 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
210 reg = 0;
211 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
215
216 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
217 rt2x00_rf_write(rt2x00dev, word, value);
218 }
219
220 mutex_unlock(&rt2x00dev->csr_mutex);
221 }
222
223 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
224 const u8 command, const u8 token,
225 const u8 arg0, const u8 arg1)
226 {
227 u32 reg;
228
229 /*
230 * SOC devices don't support MCU requests.
231 */
232 if (rt2x00_is_soc(rt2x00dev))
233 return;
234
235 mutex_lock(&rt2x00dev->csr_mutex);
236
237 /*
238 * Wait until the MCU becomes available, afterwards we
239 * can safely write the new data into the register.
240 */
241 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
242 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
243 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
244 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
245 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
246 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
247
248 reg = 0;
249 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
250 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
251 }
252
253 mutex_unlock(&rt2x00dev->csr_mutex);
254 }
255 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
256
257 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
258 {
259 unsigned int i;
260 u32 reg;
261
262 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
263 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
264 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
265 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
266 return 0;
267
268 msleep(1);
269 }
270
271 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
272 return -EACCES;
273 }
274 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
275
276 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
277 {
278 u16 fw_crc;
279 u16 crc;
280
281 /*
282 * The last 2 bytes in the firmware array are the crc checksum itself,
283 * this means that we should never pass those 2 bytes to the crc
284 * algorithm.
285 */
286 fw_crc = (data[len - 2] << 8 | data[len - 1]);
287
288 /*
289 * Use the crc ccitt algorithm.
290 * This will return the same value as the legacy driver which
291 * used bit ordering reversion on the both the firmware bytes
292 * before input input as well as on the final output.
293 * Obviously using crc ccitt directly is much more efficient.
294 */
295 crc = crc_ccitt(~0, data, len - 2);
296
297 /*
298 * There is a small difference between the crc-itu-t + bitrev and
299 * the crc-ccitt crc calculation. In the latter method the 2 bytes
300 * will be swapped, use swab16 to convert the crc to the correct
301 * value.
302 */
303 crc = swab16(crc);
304
305 return fw_crc == crc;
306 }
307
308 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
309 const u8 *data, const size_t len)
310 {
311 size_t offset = 0;
312 size_t fw_len;
313 bool multiple;
314
315 /*
316 * PCI(e) & SOC devices require firmware with a length
317 * of 8kb. USB devices require firmware files with a length
318 * of 4kb. Certain USB chipsets however require different firmware,
319 * which Ralink only provides attached to the original firmware
320 * file. Thus for USB devices, firmware files have a length
321 * which is a multiple of 4kb.
322 */
323 if (rt2x00_is_usb(rt2x00dev)) {
324 fw_len = 4096;
325 multiple = true;
326 } else {
327 fw_len = 8192;
328 multiple = true;
329 }
330
331 /*
332 * Validate the firmware length
333 */
334 if (len != fw_len && (!multiple || (len % fw_len) != 0))
335 return FW_BAD_LENGTH;
336
337 /*
338 * Check if the chipset requires one of the upper parts
339 * of the firmware.
340 */
341 if (rt2x00_is_usb(rt2x00dev) &&
342 !rt2x00_rt(rt2x00dev, RT2860) &&
343 !rt2x00_rt(rt2x00dev, RT2872) &&
344 !rt2x00_rt(rt2x00dev, RT3070) &&
345 ((len / fw_len) == 1))
346 return FW_BAD_VERSION;
347
348 /*
349 * 8kb firmware files must be checked as if it were
350 * 2 separate firmware files.
351 */
352 while (offset < len) {
353 if (!rt2800_check_firmware_crc(data + offset, fw_len))
354 return FW_BAD_CRC;
355
356 offset += fw_len;
357 }
358
359 return FW_OK;
360 }
361 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
362
363 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
364 const u8 *data, const size_t len)
365 {
366 unsigned int i;
367 u32 reg;
368
369 /*
370 * Wait for stable hardware.
371 */
372 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
373 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
374 if (reg && reg != ~0)
375 break;
376 msleep(1);
377 }
378
379 if (i == REGISTER_BUSY_COUNT) {
380 ERROR(rt2x00dev, "Unstable hardware.\n");
381 return -EBUSY;
382 }
383
384 if (rt2x00_is_pci(rt2x00dev))
385 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
386
387 /*
388 * Disable DMA, will be reenabled later when enabling
389 * the radio.
390 */
391 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
392 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
393 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
394 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
395 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
396 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
397 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
398
399 /*
400 * Write firmware to the device.
401 */
402 rt2800_drv_write_firmware(rt2x00dev, data, len);
403
404 /*
405 * Wait for device to stabilize.
406 */
407 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
408 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
409 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
410 break;
411 msleep(1);
412 }
413
414 if (i == REGISTER_BUSY_COUNT) {
415 ERROR(rt2x00dev, "PBF system register not ready.\n");
416 return -EBUSY;
417 }
418
419 /*
420 * Initialize firmware.
421 */
422 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
423 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
424 msleep(1);
425
426 return 0;
427 }
428 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
429
430 void rt2800_write_txwi(__le32 *txwi, struct txentry_desc *txdesc)
431 {
432 u32 word;
433
434 /*
435 * Initialize TX Info descriptor
436 */
437 rt2x00_desc_read(txwi, 0, &word);
438 rt2x00_set_field32(&word, TXWI_W0_FRAG,
439 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
440 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
441 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
442 rt2x00_set_field32(&word, TXWI_W0_TS,
443 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
444 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
445 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
446 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
447 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
448 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
449 rt2x00_set_field32(&word, TXWI_W0_BW,
450 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
451 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
452 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
453 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
454 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
455 rt2x00_desc_write(txwi, 0, word);
456
457 rt2x00_desc_read(txwi, 1, &word);
458 rt2x00_set_field32(&word, TXWI_W1_ACK,
459 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
460 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
461 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
462 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
463 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
464 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
465 txdesc->key_idx : 0xff);
466 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
467 txdesc->length);
468 rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->queue + 1);
469 rt2x00_desc_write(txwi, 1, word);
470
471 /*
472 * Always write 0 to IV/EIV fields, hardware will insert the IV
473 * from the IVEIV register when TXD_W3_WIV is set to 0.
474 * When TXD_W3_WIV is set to 1 it will use the IV data
475 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
476 * crypto entry in the registers should be used to encrypt the frame.
477 */
478 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
479 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
480 }
481 EXPORT_SYMBOL_GPL(rt2800_write_txwi);
482
483 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxwi_w2)
484 {
485 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
486 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
487 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
488 u16 eeprom;
489 u8 offset0;
490 u8 offset1;
491 u8 offset2;
492
493 if (rt2x00dev->rx_status.band == IEEE80211_BAND_2GHZ) {
494 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
495 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
496 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
497 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
498 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
499 } else {
500 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
501 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
502 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
503 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
504 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
505 }
506
507 /*
508 * Convert the value from the descriptor into the RSSI value
509 * If the value in the descriptor is 0, it is considered invalid
510 * and the default (extremely low) rssi value is assumed
511 */
512 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
513 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
514 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
515
516 /*
517 * mac80211 only accepts a single RSSI value. Calculating the
518 * average doesn't deliver a fair answer either since -60:-60 would
519 * be considered equally good as -50:-70 while the second is the one
520 * which gives less energy...
521 */
522 rssi0 = max(rssi0, rssi1);
523 return max(rssi0, rssi2);
524 }
525
526 void rt2800_process_rxwi(struct queue_entry *entry,
527 struct rxdone_entry_desc *rxdesc)
528 {
529 __le32 *rxwi = (__le32 *) entry->skb->data;
530 u32 word;
531
532 rt2x00_desc_read(rxwi, 0, &word);
533
534 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
535 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
536
537 rt2x00_desc_read(rxwi, 1, &word);
538
539 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
540 rxdesc->flags |= RX_FLAG_SHORT_GI;
541
542 if (rt2x00_get_field32(word, RXWI_W1_BW))
543 rxdesc->flags |= RX_FLAG_40MHZ;
544
545 /*
546 * Detect RX rate, always use MCS as signal type.
547 */
548 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
549 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
550 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
551
552 /*
553 * Mask of 0x8 bit to remove the short preamble flag.
554 */
555 if (rxdesc->rate_mode == RATE_MODE_CCK)
556 rxdesc->signal &= ~0x8;
557
558 rt2x00_desc_read(rxwi, 2, &word);
559
560 /*
561 * Convert descriptor AGC value to RSSI value.
562 */
563 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
564
565 /*
566 * Remove RXWI descriptor from start of buffer.
567 */
568 skb_pull(entry->skb, RXWI_DESC_SIZE);
569 }
570 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
571
572 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
573 {
574 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
575 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
576 unsigned int beacon_base;
577 u32 reg;
578
579 /*
580 * Disable beaconing while we are reloading the beacon data,
581 * otherwise we might be sending out invalid data.
582 */
583 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
584 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
585 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
586
587 /*
588 * Add space for the TXWI in front of the skb.
589 */
590 skb_push(entry->skb, TXWI_DESC_SIZE);
591 memset(entry->skb, 0, TXWI_DESC_SIZE);
592
593 /*
594 * Register descriptor details in skb frame descriptor.
595 */
596 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
597 skbdesc->desc = entry->skb->data;
598 skbdesc->desc_len = TXWI_DESC_SIZE;
599
600 /*
601 * Add the TXWI for the beacon to the skb.
602 */
603 rt2800_write_txwi((__le32 *)entry->skb->data, txdesc);
604
605 /*
606 * Dump beacon to userspace through debugfs.
607 */
608 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
609
610 /*
611 * Write entire beacon with TXWI to register.
612 */
613 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
614 rt2800_register_multiwrite(rt2x00dev, beacon_base,
615 entry->skb->data, entry->skb->len);
616
617 /*
618 * Enable beaconing again.
619 */
620 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
621 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
622 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
623 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
624
625 /*
626 * Clean up beacon skb.
627 */
628 dev_kfree_skb_any(entry->skb);
629 entry->skb = NULL;
630 }
631 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
632
633 static void inline rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
634 unsigned int beacon_base)
635 {
636 int i;
637
638 /*
639 * For the Beacon base registers we only need to clear
640 * the whole TXWI which (when set to 0) will invalidate
641 * the entire beacon.
642 */
643 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
644 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
645 }
646
647 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
648 const struct rt2x00debug rt2800_rt2x00debug = {
649 .owner = THIS_MODULE,
650 .csr = {
651 .read = rt2800_register_read,
652 .write = rt2800_register_write,
653 .flags = RT2X00DEBUGFS_OFFSET,
654 .word_base = CSR_REG_BASE,
655 .word_size = sizeof(u32),
656 .word_count = CSR_REG_SIZE / sizeof(u32),
657 },
658 .eeprom = {
659 .read = rt2x00_eeprom_read,
660 .write = rt2x00_eeprom_write,
661 .word_base = EEPROM_BASE,
662 .word_size = sizeof(u16),
663 .word_count = EEPROM_SIZE / sizeof(u16),
664 },
665 .bbp = {
666 .read = rt2800_bbp_read,
667 .write = rt2800_bbp_write,
668 .word_base = BBP_BASE,
669 .word_size = sizeof(u8),
670 .word_count = BBP_SIZE / sizeof(u8),
671 },
672 .rf = {
673 .read = rt2x00_rf_read,
674 .write = rt2800_rf_write,
675 .word_base = RF_BASE,
676 .word_size = sizeof(u32),
677 .word_count = RF_SIZE / sizeof(u32),
678 },
679 };
680 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
681 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
682
683 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
684 {
685 u32 reg;
686
687 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
688 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
689 }
690 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
691
692 #ifdef CONFIG_RT2X00_LIB_LEDS
693 static void rt2800_brightness_set(struct led_classdev *led_cdev,
694 enum led_brightness brightness)
695 {
696 struct rt2x00_led *led =
697 container_of(led_cdev, struct rt2x00_led, led_dev);
698 unsigned int enabled = brightness != LED_OFF;
699 unsigned int bg_mode =
700 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
701 unsigned int polarity =
702 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
703 EEPROM_FREQ_LED_POLARITY);
704 unsigned int ledmode =
705 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
706 EEPROM_FREQ_LED_MODE);
707
708 if (led->type == LED_TYPE_RADIO) {
709 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
710 enabled ? 0x20 : 0);
711 } else if (led->type == LED_TYPE_ASSOC) {
712 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
713 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
714 } else if (led->type == LED_TYPE_QUALITY) {
715 /*
716 * The brightness is divided into 6 levels (0 - 5),
717 * The specs tell us the following levels:
718 * 0, 1 ,3, 7, 15, 31
719 * to determine the level in a simple way we can simply
720 * work with bitshifting:
721 * (1 << level) - 1
722 */
723 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
724 (1 << brightness / (LED_FULL / 6)) - 1,
725 polarity);
726 }
727 }
728
729 static int rt2800_blink_set(struct led_classdev *led_cdev,
730 unsigned long *delay_on, unsigned long *delay_off)
731 {
732 struct rt2x00_led *led =
733 container_of(led_cdev, struct rt2x00_led, led_dev);
734 u32 reg;
735
736 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
737 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
738 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
739 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
740
741 return 0;
742 }
743
744 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
745 struct rt2x00_led *led, enum led_type type)
746 {
747 led->rt2x00dev = rt2x00dev;
748 led->type = type;
749 led->led_dev.brightness_set = rt2800_brightness_set;
750 led->led_dev.blink_set = rt2800_blink_set;
751 led->flags = LED_INITIALIZED;
752 }
753 #endif /* CONFIG_RT2X00_LIB_LEDS */
754
755 /*
756 * Configuration handlers.
757 */
758 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
759 struct rt2x00lib_crypto *crypto,
760 struct ieee80211_key_conf *key)
761 {
762 struct mac_wcid_entry wcid_entry;
763 struct mac_iveiv_entry iveiv_entry;
764 u32 offset;
765 u32 reg;
766
767 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
768
769 if (crypto->cmd == SET_KEY) {
770 rt2800_register_read(rt2x00dev, offset, &reg);
771 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
772 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
773 /*
774 * Both the cipher as the BSS Idx numbers are split in a main
775 * value of 3 bits, and a extended field for adding one additional
776 * bit to the value.
777 */
778 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
779 (crypto->cipher & 0x7));
780 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
781 (crypto->cipher & 0x8) >> 3);
782 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
783 (crypto->bssidx & 0x7));
784 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
785 (crypto->bssidx & 0x8) >> 3);
786 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
787 rt2800_register_write(rt2x00dev, offset, reg);
788 } else {
789 rt2800_register_write(rt2x00dev, offset, 0);
790 }
791
792 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
793
794 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
795 if ((crypto->cipher == CIPHER_TKIP) ||
796 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
797 (crypto->cipher == CIPHER_AES))
798 iveiv_entry.iv[3] |= 0x20;
799 iveiv_entry.iv[3] |= key->keyidx << 6;
800 rt2800_register_multiwrite(rt2x00dev, offset,
801 &iveiv_entry, sizeof(iveiv_entry));
802
803 offset = MAC_WCID_ENTRY(key->hw_key_idx);
804
805 memset(&wcid_entry, 0, sizeof(wcid_entry));
806 if (crypto->cmd == SET_KEY)
807 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
808 rt2800_register_multiwrite(rt2x00dev, offset,
809 &wcid_entry, sizeof(wcid_entry));
810 }
811
812 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
813 struct rt2x00lib_crypto *crypto,
814 struct ieee80211_key_conf *key)
815 {
816 struct hw_key_entry key_entry;
817 struct rt2x00_field32 field;
818 u32 offset;
819 u32 reg;
820
821 if (crypto->cmd == SET_KEY) {
822 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
823
824 memcpy(key_entry.key, crypto->key,
825 sizeof(key_entry.key));
826 memcpy(key_entry.tx_mic, crypto->tx_mic,
827 sizeof(key_entry.tx_mic));
828 memcpy(key_entry.rx_mic, crypto->rx_mic,
829 sizeof(key_entry.rx_mic));
830
831 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
832 rt2800_register_multiwrite(rt2x00dev, offset,
833 &key_entry, sizeof(key_entry));
834 }
835
836 /*
837 * The cipher types are stored over multiple registers
838 * starting with SHARED_KEY_MODE_BASE each word will have
839 * 32 bits and contains the cipher types for 2 bssidx each.
840 * Using the correct defines correctly will cause overhead,
841 * so just calculate the correct offset.
842 */
843 field.bit_offset = 4 * (key->hw_key_idx % 8);
844 field.bit_mask = 0x7 << field.bit_offset;
845
846 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
847
848 rt2800_register_read(rt2x00dev, offset, &reg);
849 rt2x00_set_field32(&reg, field,
850 (crypto->cmd == SET_KEY) * crypto->cipher);
851 rt2800_register_write(rt2x00dev, offset, reg);
852
853 /*
854 * Update WCID information
855 */
856 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
857
858 return 0;
859 }
860 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
861
862 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
863 struct rt2x00lib_crypto *crypto,
864 struct ieee80211_key_conf *key)
865 {
866 struct hw_key_entry key_entry;
867 u32 offset;
868
869 if (crypto->cmd == SET_KEY) {
870 /*
871 * 1 pairwise key is possible per AID, this means that the AID
872 * equals our hw_key_idx. Make sure the WCID starts _after_ the
873 * last possible shared key entry.
874 */
875 if (crypto->aid > (256 - 32))
876 return -ENOSPC;
877
878 key->hw_key_idx = 32 + crypto->aid;
879
880 memcpy(key_entry.key, crypto->key,
881 sizeof(key_entry.key));
882 memcpy(key_entry.tx_mic, crypto->tx_mic,
883 sizeof(key_entry.tx_mic));
884 memcpy(key_entry.rx_mic, crypto->rx_mic,
885 sizeof(key_entry.rx_mic));
886
887 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
888 rt2800_register_multiwrite(rt2x00dev, offset,
889 &key_entry, sizeof(key_entry));
890 }
891
892 /*
893 * Update WCID information
894 */
895 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
896
897 return 0;
898 }
899 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
900
901 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
902 const unsigned int filter_flags)
903 {
904 u32 reg;
905
906 /*
907 * Start configuration steps.
908 * Note that the version error will always be dropped
909 * and broadcast frames will always be accepted since
910 * there is no filter for it at this time.
911 */
912 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
913 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
914 !(filter_flags & FIF_FCSFAIL));
915 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
916 !(filter_flags & FIF_PLCPFAIL));
917 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
918 !(filter_flags & FIF_PROMISC_IN_BSS));
919 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
920 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
921 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
922 !(filter_flags & FIF_ALLMULTI));
923 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
924 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
925 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
926 !(filter_flags & FIF_CONTROL));
927 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
928 !(filter_flags & FIF_CONTROL));
929 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
930 !(filter_flags & FIF_CONTROL));
931 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
932 !(filter_flags & FIF_CONTROL));
933 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
934 !(filter_flags & FIF_CONTROL));
935 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
936 !(filter_flags & FIF_PSPOLL));
937 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
938 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
939 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
940 !(filter_flags & FIF_CONTROL));
941 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
942 }
943 EXPORT_SYMBOL_GPL(rt2800_config_filter);
944
945 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
946 struct rt2x00intf_conf *conf, const unsigned int flags)
947 {
948 u32 reg;
949
950 if (flags & CONFIG_UPDATE_TYPE) {
951 /*
952 * Clear current synchronisation setup.
953 */
954 rt2800_clear_beacon(rt2x00dev,
955 HW_BEACON_OFFSET(intf->beacon->entry_idx));
956 /*
957 * Enable synchronisation.
958 */
959 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
960 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
961 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
962 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
963 (conf->sync == TSF_SYNC_ADHOC ||
964 conf->sync == TSF_SYNC_AP_NONE));
965 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
966
967 /*
968 * Enable pre tbtt interrupt for beaconing modes
969 */
970 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
971 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER,
972 (conf->sync == TSF_SYNC_AP_NONE));
973 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
974
975 }
976
977 if (flags & CONFIG_UPDATE_MAC) {
978 reg = le32_to_cpu(conf->mac[1]);
979 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
980 conf->mac[1] = cpu_to_le32(reg);
981
982 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
983 conf->mac, sizeof(conf->mac));
984 }
985
986 if (flags & CONFIG_UPDATE_BSSID) {
987 reg = le32_to_cpu(conf->bssid[1]);
988 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
989 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
990 conf->bssid[1] = cpu_to_le32(reg);
991
992 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
993 conf->bssid, sizeof(conf->bssid));
994 }
995 }
996 EXPORT_SYMBOL_GPL(rt2800_config_intf);
997
998 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
999 {
1000 u32 reg;
1001
1002 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1003 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1004 !!erp->short_preamble);
1005 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1006 !!erp->short_preamble);
1007 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1008
1009 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1010 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1011 erp->cts_protection ? 2 : 0);
1012 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1013
1014 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1015 erp->basic_rates);
1016 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1017
1018 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1019 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
1020 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1021
1022 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1023 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1024 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1025
1026 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1027 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1028 erp->beacon_int * 16);
1029 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1030 }
1031 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1032
1033 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1034 {
1035 u8 r1;
1036 u8 r3;
1037
1038 rt2800_bbp_read(rt2x00dev, 1, &r1);
1039 rt2800_bbp_read(rt2x00dev, 3, &r3);
1040
1041 /*
1042 * Configure the TX antenna.
1043 */
1044 switch ((int)ant->tx) {
1045 case 1:
1046 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1047 break;
1048 case 2:
1049 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1050 break;
1051 case 3:
1052 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1053 break;
1054 }
1055
1056 /*
1057 * Configure the RX antenna.
1058 */
1059 switch ((int)ant->rx) {
1060 case 1:
1061 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1062 break;
1063 case 2:
1064 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1065 break;
1066 case 3:
1067 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1068 break;
1069 }
1070
1071 rt2800_bbp_write(rt2x00dev, 3, r3);
1072 rt2800_bbp_write(rt2x00dev, 1, r1);
1073 }
1074 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1075
1076 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1077 struct rt2x00lib_conf *libconf)
1078 {
1079 u16 eeprom;
1080 short lna_gain;
1081
1082 if (libconf->rf.channel <= 14) {
1083 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1084 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1085 } else if (libconf->rf.channel <= 64) {
1086 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1087 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1088 } else if (libconf->rf.channel <= 128) {
1089 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1090 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1091 } else {
1092 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1093 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1094 }
1095
1096 rt2x00dev->lna_gain = lna_gain;
1097 }
1098
1099 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1100 struct ieee80211_conf *conf,
1101 struct rf_channel *rf,
1102 struct channel_info *info)
1103 {
1104 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1105
1106 if (rt2x00dev->default_ant.tx == 1)
1107 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1108
1109 if (rt2x00dev->default_ant.rx == 1) {
1110 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1111 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1112 } else if (rt2x00dev->default_ant.rx == 2)
1113 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1114
1115 if (rf->channel > 14) {
1116 /*
1117 * When TX power is below 0, we should increase it by 7 to
1118 * make it a positive value (Minumum value is -7).
1119 * However this means that values between 0 and 7 have
1120 * double meaning, and we should set a 7DBm boost flag.
1121 */
1122 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1123 (info->default_power1 >= 0));
1124
1125 if (info->default_power1 < 0)
1126 info->default_power1 += 7;
1127
1128 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
1129 TXPOWER_A_TO_DEV(info->default_power1));
1130
1131 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1132 (info->default_power2 >= 0));
1133
1134 if (info->default_power2 < 0)
1135 info->default_power2 += 7;
1136
1137 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
1138 TXPOWER_A_TO_DEV(info->default_power2));
1139 } else {
1140 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
1141 TXPOWER_G_TO_DEV(info->default_power1));
1142 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
1143 TXPOWER_G_TO_DEV(info->default_power2));
1144 }
1145
1146 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1147
1148 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1149 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1150 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1151 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1152
1153 udelay(200);
1154
1155 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1156 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1157 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1158 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1159
1160 udelay(200);
1161
1162 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1163 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1164 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1165 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1166 }
1167
1168 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1169 struct ieee80211_conf *conf,
1170 struct rf_channel *rf,
1171 struct channel_info *info)
1172 {
1173 u8 rfcsr;
1174
1175 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1176 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1177
1178 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1179 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1180 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1181
1182 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1183 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1184 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1185
1186 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1187 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1188 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1189
1190 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1191 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1192 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1193
1194 rt2800_rfcsr_write(rt2x00dev, 24,
1195 rt2x00dev->calibration[conf_is_ht40(conf)]);
1196
1197 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1198 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1199 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1200 }
1201
1202 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1203 struct ieee80211_conf *conf,
1204 struct rf_channel *rf,
1205 struct channel_info *info)
1206 {
1207 u32 reg;
1208 unsigned int tx_pin;
1209 u8 bbp;
1210
1211 if (rt2x00_rf(rt2x00dev, RF2020) ||
1212 rt2x00_rf(rt2x00dev, RF3020) ||
1213 rt2x00_rf(rt2x00dev, RF3021) ||
1214 rt2x00_rf(rt2x00dev, RF3022))
1215 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1216 else
1217 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1218
1219 /*
1220 * Change BBP settings
1221 */
1222 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1223 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1224 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1225 rt2800_bbp_write(rt2x00dev, 86, 0);
1226
1227 if (rf->channel <= 14) {
1228 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1229 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1230 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1231 } else {
1232 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1233 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1234 }
1235 } else {
1236 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1237
1238 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1239 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1240 else
1241 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1242 }
1243
1244 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1245 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1246 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1247 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1248 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1249
1250 tx_pin = 0;
1251
1252 /* Turn on unused PA or LNA when not using 1T or 1R */
1253 if (rt2x00dev->default_ant.tx != 1) {
1254 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1255 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1256 }
1257
1258 /* Turn on unused PA or LNA when not using 1T or 1R */
1259 if (rt2x00dev->default_ant.rx != 1) {
1260 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1261 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1262 }
1263
1264 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1265 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1266 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1267 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1268 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1269 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1270
1271 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1272
1273 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1274 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1275 rt2800_bbp_write(rt2x00dev, 4, bbp);
1276
1277 rt2800_bbp_read(rt2x00dev, 3, &bbp);
1278 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
1279 rt2800_bbp_write(rt2x00dev, 3, bbp);
1280
1281 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1282 if (conf_is_ht40(conf)) {
1283 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1284 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1285 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1286 } else {
1287 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1288 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1289 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1290 }
1291 }
1292
1293 msleep(1);
1294 }
1295
1296 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1297 const int max_txpower)
1298 {
1299 u8 txpower;
1300 u8 max_value = (u8)max_txpower;
1301 u16 eeprom;
1302 int i;
1303 u32 reg;
1304 u8 r1;
1305 u32 offset;
1306
1307 /*
1308 * set to normal tx power mode: +/- 0dBm
1309 */
1310 rt2800_bbp_read(rt2x00dev, 1, &r1);
1311 rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
1312 rt2800_bbp_write(rt2x00dev, 1, r1);
1313
1314 /*
1315 * The eeprom contains the tx power values for each rate. These
1316 * values map to 100% tx power. Each 16bit word contains four tx
1317 * power values and the order is the same as used in the TX_PWR_CFG
1318 * registers.
1319 */
1320 offset = TX_PWR_CFG_0;
1321
1322 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1323 /* just to be safe */
1324 if (offset > TX_PWR_CFG_4)
1325 break;
1326
1327 rt2800_register_read(rt2x00dev, offset, &reg);
1328
1329 /* read the next four txpower values */
1330 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1331 &eeprom);
1332
1333 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1334 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1335 * TX_PWR_CFG_4: unknown */
1336 txpower = rt2x00_get_field16(eeprom,
1337 EEPROM_TXPOWER_BYRATE_RATE0);
1338 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
1339 min(txpower, max_value));
1340
1341 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1342 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1343 * TX_PWR_CFG_4: unknown */
1344 txpower = rt2x00_get_field16(eeprom,
1345 EEPROM_TXPOWER_BYRATE_RATE1);
1346 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
1347 min(txpower, max_value));
1348
1349 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1350 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
1351 * TX_PWR_CFG_4: unknown */
1352 txpower = rt2x00_get_field16(eeprom,
1353 EEPROM_TXPOWER_BYRATE_RATE2);
1354 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
1355 min(txpower, max_value));
1356
1357 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1358 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
1359 * TX_PWR_CFG_4: unknown */
1360 txpower = rt2x00_get_field16(eeprom,
1361 EEPROM_TXPOWER_BYRATE_RATE3);
1362 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
1363 min(txpower, max_value));
1364
1365 /* read the next four txpower values */
1366 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1367 &eeprom);
1368
1369 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1370 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1371 * TX_PWR_CFG_4: unknown */
1372 txpower = rt2x00_get_field16(eeprom,
1373 EEPROM_TXPOWER_BYRATE_RATE0);
1374 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
1375 min(txpower, max_value));
1376
1377 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1378 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1379 * TX_PWR_CFG_4: unknown */
1380 txpower = rt2x00_get_field16(eeprom,
1381 EEPROM_TXPOWER_BYRATE_RATE1);
1382 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
1383 min(txpower, max_value));
1384
1385 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1386 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1387 * TX_PWR_CFG_4: unknown */
1388 txpower = rt2x00_get_field16(eeprom,
1389 EEPROM_TXPOWER_BYRATE_RATE2);
1390 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
1391 min(txpower, max_value));
1392
1393 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1394 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1395 * TX_PWR_CFG_4: unknown */
1396 txpower = rt2x00_get_field16(eeprom,
1397 EEPROM_TXPOWER_BYRATE_RATE3);
1398 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
1399 min(txpower, max_value));
1400
1401 rt2800_register_write(rt2x00dev, offset, reg);
1402
1403 /* next TX_PWR_CFG register */
1404 offset += 4;
1405 }
1406 }
1407
1408 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1409 struct rt2x00lib_conf *libconf)
1410 {
1411 u32 reg;
1412
1413 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1414 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1415 libconf->conf->short_frame_max_tx_count);
1416 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1417 libconf->conf->long_frame_max_tx_count);
1418 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1419 }
1420
1421 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1422 struct rt2x00lib_conf *libconf)
1423 {
1424 enum dev_state state =
1425 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1426 STATE_SLEEP : STATE_AWAKE;
1427 u32 reg;
1428
1429 if (state == STATE_SLEEP) {
1430 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1431
1432 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1433 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1434 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1435 libconf->conf->listen_interval - 1);
1436 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1437 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1438
1439 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1440 } else {
1441 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1442 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1443 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1444 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1445 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1446
1447 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1448 }
1449 }
1450
1451 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1452 struct rt2x00lib_conf *libconf,
1453 const unsigned int flags)
1454 {
1455 /* Always recalculate LNA gain before changing configuration */
1456 rt2800_config_lna_gain(rt2x00dev, libconf);
1457
1458 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1459 rt2800_config_channel(rt2x00dev, libconf->conf,
1460 &libconf->rf, &libconf->channel);
1461 if (flags & IEEE80211_CONF_CHANGE_POWER)
1462 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1463 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1464 rt2800_config_retry_limit(rt2x00dev, libconf);
1465 if (flags & IEEE80211_CONF_CHANGE_PS)
1466 rt2800_config_ps(rt2x00dev, libconf);
1467 }
1468 EXPORT_SYMBOL_GPL(rt2800_config);
1469
1470 /*
1471 * Link tuning
1472 */
1473 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1474 {
1475 u32 reg;
1476
1477 /*
1478 * Update FCS error count from register.
1479 */
1480 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1481 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1482 }
1483 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1484
1485 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1486 {
1487 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1488 if (rt2x00_rt(rt2x00dev, RT3070) ||
1489 rt2x00_rt(rt2x00dev, RT3071) ||
1490 rt2x00_rt(rt2x00dev, RT3090) ||
1491 rt2x00_rt(rt2x00dev, RT3390))
1492 return 0x1c + (2 * rt2x00dev->lna_gain);
1493 else
1494 return 0x2e + rt2x00dev->lna_gain;
1495 }
1496
1497 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1498 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1499 else
1500 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1501 }
1502
1503 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1504 struct link_qual *qual, u8 vgc_level)
1505 {
1506 if (qual->vgc_level != vgc_level) {
1507 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1508 qual->vgc_level = vgc_level;
1509 qual->vgc_level_reg = vgc_level;
1510 }
1511 }
1512
1513 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1514 {
1515 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1516 }
1517 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1518
1519 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1520 const u32 count)
1521 {
1522 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
1523 return;
1524
1525 /*
1526 * When RSSI is better then -80 increase VGC level with 0x10
1527 */
1528 rt2800_set_vgc(rt2x00dev, qual,
1529 rt2800_get_default_vgc(rt2x00dev) +
1530 ((qual->rssi > -80) * 0x10));
1531 }
1532 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1533
1534 /*
1535 * Initialization functions.
1536 */
1537 int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1538 {
1539 u32 reg;
1540 u16 eeprom;
1541 unsigned int i;
1542 int ret;
1543
1544 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1545 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1546 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1547 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1548 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1549 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1550 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1551
1552 ret = rt2800_drv_init_registers(rt2x00dev);
1553 if (ret)
1554 return ret;
1555
1556 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1557 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1558 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1559 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1560 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1561 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1562
1563 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1564 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1565 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1566 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1567 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1568 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1569
1570 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1571 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1572
1573 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1574
1575 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1576 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
1577 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1578 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1579 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1580 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1581 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1582 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1583
1584 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1585
1586 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1587 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1588 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1589 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1590
1591 if (rt2x00_rt(rt2x00dev, RT3071) ||
1592 rt2x00_rt(rt2x00dev, RT3090) ||
1593 rt2x00_rt(rt2x00dev, RT3390)) {
1594 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1595 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1596 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1597 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1598 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1599 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1600 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1601 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1602 0x0000002c);
1603 else
1604 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1605 0x0000000f);
1606 } else {
1607 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1608 }
1609 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
1610 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1611
1612 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1613 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1614 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1615 } else {
1616 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1617 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1618 }
1619 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1620 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1621 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1622 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
1623 } else {
1624 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1625 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1626 }
1627
1628 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1629 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1630 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1631 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1632 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1633 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1634 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1635 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1636 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1637 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1638
1639 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1640 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1641 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
1642 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1643 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1644
1645 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1646 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1647 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
1648 rt2x00_rt(rt2x00dev, RT2883) ||
1649 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
1650 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1651 else
1652 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1653 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1654 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1655 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1656
1657 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1658 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1659 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1660 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1661 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1662 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1663 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1664 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1665 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1666
1667 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1668
1669 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1670 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1671 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1672 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1673 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1674 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1675 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1676 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1677
1678 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1679 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1680 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
1681 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1682 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1683 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
1684 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1685 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1686 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1687
1688 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1689 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1690 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1691 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1692 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1693 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1694 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1695 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1696 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1697 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1698 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
1699 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1700
1701 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1702 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1703 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1704 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1705 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1706 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1707 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1708 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1709 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1710 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1711 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
1712 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1713
1714 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1715 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1716 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1717 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1718 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1719 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1720 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1721 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1722 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1723 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1724 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
1725 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1726
1727 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1728 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1729 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1730 !rt2x00_is_usb(rt2x00dev));
1731 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1732 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1733 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1734 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1735 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1736 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1737 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1738 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
1739 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1740
1741 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1742 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1743 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1744 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1745 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1746 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1747 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1748 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1749 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1750 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1751 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
1752 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1753
1754 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1755 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1756 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1757 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1758 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1759 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1760 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1761 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1762 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1763 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1764 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
1765 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1766
1767 if (rt2x00_is_usb(rt2x00dev)) {
1768 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1769
1770 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1771 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1772 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1773 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1774 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1775 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1776 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1777 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1778 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1779 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1780 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1781 }
1782
1783 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1784 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1785
1786 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1787 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1788 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1789 IEEE80211_MAX_RTS_THRESHOLD);
1790 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1791 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1792
1793 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1794
1795 /*
1796 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
1797 * time should be set to 16. However, the original Ralink driver uses
1798 * 16 for both and indeed using a value of 10 for CCK SIFS results in
1799 * connection problems with 11g + CTS protection. Hence, use the same
1800 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
1801 */
1802 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1803 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
1804 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
1805 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1806 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1807 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1808 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1809
1810 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1811
1812 /*
1813 * ASIC will keep garbage value after boot, clear encryption keys.
1814 */
1815 for (i = 0; i < 4; i++)
1816 rt2800_register_write(rt2x00dev,
1817 SHARED_KEY_MODE_ENTRY(i), 0);
1818
1819 for (i = 0; i < 256; i++) {
1820 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1821 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1822 wcid, sizeof(wcid));
1823
1824 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1825 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1826 }
1827
1828 /*
1829 * Clear all beacons
1830 */
1831 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
1832 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
1833 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
1834 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
1835 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
1836 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
1837 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
1838 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
1839
1840 if (rt2x00_is_usb(rt2x00dev)) {
1841 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
1842 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
1843 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
1844 }
1845
1846 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1847 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1848 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1849 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1850 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1851 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1852 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1853 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1854 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1855 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1856
1857 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1858 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1859 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1860 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1861 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1862 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1863 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1864 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1865 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1866 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1867
1868 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1869 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1870 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1871 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1872 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1873 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1874 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1875 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1876 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1877 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1878
1879 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1880 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1881 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1882 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1883 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1884 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1885
1886 /*
1887 * We must clear the error counters.
1888 * These registers are cleared on read,
1889 * so we may pass a useless variable to store the value.
1890 */
1891 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1892 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1893 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1894 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1895 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1896 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1897
1898 /*
1899 * Setup leadtime for pre tbtt interrupt to 6ms
1900 */
1901 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
1902 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
1903 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
1904
1905 return 0;
1906 }
1907 EXPORT_SYMBOL_GPL(rt2800_init_registers);
1908
1909 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1910 {
1911 unsigned int i;
1912 u32 reg;
1913
1914 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1915 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1916 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1917 return 0;
1918
1919 udelay(REGISTER_BUSY_DELAY);
1920 }
1921
1922 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1923 return -EACCES;
1924 }
1925
1926 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1927 {
1928 unsigned int i;
1929 u8 value;
1930
1931 /*
1932 * BBP was enabled after firmware was loaded,
1933 * but we need to reactivate it now.
1934 */
1935 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1936 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1937 msleep(1);
1938
1939 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1940 rt2800_bbp_read(rt2x00dev, 0, &value);
1941 if ((value != 0xff) && (value != 0x00))
1942 return 0;
1943 udelay(REGISTER_BUSY_DELAY);
1944 }
1945
1946 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1947 return -EACCES;
1948 }
1949
1950 int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1951 {
1952 unsigned int i;
1953 u16 eeprom;
1954 u8 reg_id;
1955 u8 value;
1956
1957 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1958 rt2800_wait_bbp_ready(rt2x00dev)))
1959 return -EACCES;
1960
1961 if (rt2800_is_305x_soc(rt2x00dev))
1962 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1963
1964 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1965 rt2800_bbp_write(rt2x00dev, 66, 0x38);
1966
1967 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1968 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1969 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1970 } else {
1971 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1972 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1973 }
1974
1975 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1976
1977 if (rt2x00_rt(rt2x00dev, RT3070) ||
1978 rt2x00_rt(rt2x00dev, RT3071) ||
1979 rt2x00_rt(rt2x00dev, RT3090) ||
1980 rt2x00_rt(rt2x00dev, RT3390)) {
1981 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1982 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1983 rt2800_bbp_write(rt2x00dev, 81, 0x33);
1984 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1985 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1986 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1987 } else {
1988 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1989 }
1990
1991 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1992 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1993
1994 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
1995 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1996 else
1997 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1998
1999 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2000 rt2800_bbp_write(rt2x00dev, 91, 0x04);
2001 rt2800_bbp_write(rt2x00dev, 92, 0x00);
2002
2003 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2004 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2005 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2006 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2007 rt2800_is_305x_soc(rt2x00dev))
2008 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2009 else
2010 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2011
2012 if (rt2800_is_305x_soc(rt2x00dev))
2013 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2014 else
2015 rt2800_bbp_write(rt2x00dev, 105, 0x05);
2016 rt2800_bbp_write(rt2x00dev, 106, 0x35);
2017
2018 if (rt2x00_rt(rt2x00dev, RT3071) ||
2019 rt2x00_rt(rt2x00dev, RT3090) ||
2020 rt2x00_rt(rt2x00dev, RT3390)) {
2021 rt2800_bbp_read(rt2x00dev, 138, &value);
2022
2023 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2024 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2025 value |= 0x20;
2026 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2027 value &= ~0x02;
2028
2029 rt2800_bbp_write(rt2x00dev, 138, value);
2030 }
2031
2032
2033 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2034 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2035
2036 if (eeprom != 0xffff && eeprom != 0x0000) {
2037 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2038 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2039 rt2800_bbp_write(rt2x00dev, reg_id, value);
2040 }
2041 }
2042
2043 return 0;
2044 }
2045 EXPORT_SYMBOL_GPL(rt2800_init_bbp);
2046
2047 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2048 bool bw40, u8 rfcsr24, u8 filter_target)
2049 {
2050 unsigned int i;
2051 u8 bbp;
2052 u8 rfcsr;
2053 u8 passband;
2054 u8 stopband;
2055 u8 overtuned = 0;
2056
2057 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2058
2059 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2060 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2061 rt2800_bbp_write(rt2x00dev, 4, bbp);
2062
2063 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2064 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2065 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2066
2067 /*
2068 * Set power & frequency of passband test tone
2069 */
2070 rt2800_bbp_write(rt2x00dev, 24, 0);
2071
2072 for (i = 0; i < 100; i++) {
2073 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2074 msleep(1);
2075
2076 rt2800_bbp_read(rt2x00dev, 55, &passband);
2077 if (passband)
2078 break;
2079 }
2080
2081 /*
2082 * Set power & frequency of stopband test tone
2083 */
2084 rt2800_bbp_write(rt2x00dev, 24, 0x06);
2085
2086 for (i = 0; i < 100; i++) {
2087 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2088 msleep(1);
2089
2090 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2091
2092 if ((passband - stopband) <= filter_target) {
2093 rfcsr24++;
2094 overtuned += ((passband - stopband) == filter_target);
2095 } else
2096 break;
2097
2098 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2099 }
2100
2101 rfcsr24 -= !!overtuned;
2102
2103 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2104 return rfcsr24;
2105 }
2106
2107 int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2108 {
2109 u8 rfcsr;
2110 u8 bbp;
2111 u32 reg;
2112 u16 eeprom;
2113
2114 if (!rt2x00_rt(rt2x00dev, RT3070) &&
2115 !rt2x00_rt(rt2x00dev, RT3071) &&
2116 !rt2x00_rt(rt2x00dev, RT3090) &&
2117 !rt2x00_rt(rt2x00dev, RT3390) &&
2118 !rt2800_is_305x_soc(rt2x00dev))
2119 return 0;
2120
2121 /*
2122 * Init RF calibration.
2123 */
2124 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2125 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2126 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2127 msleep(1);
2128 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2129 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2130
2131 if (rt2x00_rt(rt2x00dev, RT3070) ||
2132 rt2x00_rt(rt2x00dev, RT3071) ||
2133 rt2x00_rt(rt2x00dev, RT3090)) {
2134 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2135 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2136 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2137 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
2138 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2139 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
2140 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2141 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2142 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2143 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2144 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2145 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2146 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2147 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2148 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2149 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2150 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2151 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2152 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
2153 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2154 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2155 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2156 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2157 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
2158 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2159 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2160 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2161 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2162 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2163 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2164 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
2165 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2166 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2167 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
2168 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2169 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2170 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2171 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2172 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2173 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2174 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2175 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
2176 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2177 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
2178 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2179 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2180 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2181 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2182 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2183 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2184 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2185 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2186 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2187 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2188 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2189 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2190 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2191 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2192 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2193 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2194 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2195 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2196 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2197 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2198 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2199 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2200 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2201 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2202 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2203 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2204 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2205 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2206 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2207 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2208 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2209 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2210 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2211 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2212 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2213 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2214 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2215 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2216 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
2217 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2218 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2219 return 0;
2220 }
2221
2222 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2223 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2224 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2225 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2226 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2227 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2228 rt2x00_rt(rt2x00dev, RT3090)) {
2229 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2230 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2231 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2232
2233 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2234
2235 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2236 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2237 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2238 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
2239 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2240 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
2241 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2242 else
2243 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2244 }
2245 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2246 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2247 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2248 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2249 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2250 }
2251
2252 /*
2253 * Set RX Filter calibration for 20MHz and 40MHz
2254 */
2255 if (rt2x00_rt(rt2x00dev, RT3070)) {
2256 rt2x00dev->calibration[0] =
2257 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2258 rt2x00dev->calibration[1] =
2259 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
2260 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2261 rt2x00_rt(rt2x00dev, RT3090) ||
2262 rt2x00_rt(rt2x00dev, RT3390)) {
2263 rt2x00dev->calibration[0] =
2264 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2265 rt2x00dev->calibration[1] =
2266 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
2267 }
2268
2269 /*
2270 * Set back to initial state
2271 */
2272 rt2800_bbp_write(rt2x00dev, 24, 0);
2273
2274 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2275 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2276 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2277
2278 /*
2279 * set BBP back to BW20
2280 */
2281 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2282 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2283 rt2800_bbp_write(rt2x00dev, 4, bbp);
2284
2285 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2286 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2287 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2288 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
2289 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2290
2291 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2292 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2293 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2294
2295 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2296 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
2297 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2298 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2299 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2300 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
2301 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2302 }
2303 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2304 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2305 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2306 rt2x00_get_field16(eeprom,
2307 EEPROM_TXMIXER_GAIN_BG_VAL));
2308 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2309
2310 if (rt2x00_rt(rt2x00dev, RT3090)) {
2311 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2312
2313 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2314 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2315 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2316 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2317 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2318
2319 rt2800_bbp_write(rt2x00dev, 138, bbp);
2320 }
2321
2322 if (rt2x00_rt(rt2x00dev, RT3071) ||
2323 rt2x00_rt(rt2x00dev, RT3090) ||
2324 rt2x00_rt(rt2x00dev, RT3390)) {
2325 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2326 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2327 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2328 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2329 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2330 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2331 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2332
2333 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2334 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2335 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2336
2337 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2338 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2339 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2340
2341 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2342 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2343 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2344 }
2345
2346 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
2347 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
2348 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2349 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
2350 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2351 else
2352 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2353 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2354 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2355 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2356 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2357 }
2358
2359 return 0;
2360 }
2361 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
2362
2363 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2364 {
2365 u32 reg;
2366
2367 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2368
2369 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2370 }
2371 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2372
2373 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2374 {
2375 u32 reg;
2376
2377 mutex_lock(&rt2x00dev->csr_mutex);
2378
2379 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
2380 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2381 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2382 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
2383 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
2384
2385 /* Wait until the EEPROM has been loaded */
2386 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2387
2388 /* Apparently the data is read from end to start */
2389 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2390 (u32 *)&rt2x00dev->eeprom[i]);
2391 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2392 (u32 *)&rt2x00dev->eeprom[i + 2]);
2393 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2394 (u32 *)&rt2x00dev->eeprom[i + 4]);
2395 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2396 (u32 *)&rt2x00dev->eeprom[i + 6]);
2397
2398 mutex_unlock(&rt2x00dev->csr_mutex);
2399 }
2400
2401 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2402 {
2403 unsigned int i;
2404
2405 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2406 rt2800_efuse_read(rt2x00dev, i);
2407 }
2408 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2409
2410 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2411 {
2412 u16 word;
2413 u8 *mac;
2414 u8 default_lna_gain;
2415
2416 /*
2417 * Start validation of the data that has been read.
2418 */
2419 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2420 if (!is_valid_ether_addr(mac)) {
2421 random_ether_addr(mac);
2422 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2423 }
2424
2425 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2426 if (word == 0xffff) {
2427 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2428 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2429 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2430 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2431 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2432 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
2433 rt2x00_rt(rt2x00dev, RT2872)) {
2434 /*
2435 * There is a max of 2 RX streams for RT28x0 series
2436 */
2437 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2438 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2439 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2440 }
2441
2442 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2443 if (word == 0xffff) {
2444 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2445 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2446 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2447 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2448 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2449 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2450 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2451 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2452 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2453 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2454 rt2x00_set_field16(&word, EEPROM_NIC_ANT_DIVERSITY, 0);
2455 rt2x00_set_field16(&word, EEPROM_NIC_DAC_TEST, 0);
2456 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2457 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2458 }
2459
2460 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2461 if ((word & 0x00ff) == 0x00ff) {
2462 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2463 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2464 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2465 }
2466 if ((word & 0xff00) == 0xff00) {
2467 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2468 LED_MODE_TXRX_ACTIVITY);
2469 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2470 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2471 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2472 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2473 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2474 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
2475 }
2476
2477 /*
2478 * During the LNA validation we are going to use
2479 * lna0 as correct value. Note that EEPROM_LNA
2480 * is never validated.
2481 */
2482 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2483 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2484
2485 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2486 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2487 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2488 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2489 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2490 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2491
2492 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2493 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2494 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2495 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2496 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2497 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2498 default_lna_gain);
2499 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2500
2501 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2502 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2503 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2504 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2505 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2506 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2507
2508 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2509 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2510 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2511 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2512 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2513 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2514 default_lna_gain);
2515 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2516
2517 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
2518 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
2519 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
2520 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
2521 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
2522 rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
2523
2524 return 0;
2525 }
2526 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2527
2528 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2529 {
2530 u32 reg;
2531 u16 value;
2532 u16 eeprom;
2533
2534 /*
2535 * Read EEPROM word for configuration.
2536 */
2537 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2538
2539 /*
2540 * Identify RF chipset.
2541 */
2542 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2543 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2544
2545 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2546 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2547
2548 if (!rt2x00_rt(rt2x00dev, RT2860) &&
2549 !rt2x00_rt(rt2x00dev, RT2872) &&
2550 !rt2x00_rt(rt2x00dev, RT2883) &&
2551 !rt2x00_rt(rt2x00dev, RT3070) &&
2552 !rt2x00_rt(rt2x00dev, RT3071) &&
2553 !rt2x00_rt(rt2x00dev, RT3090) &&
2554 !rt2x00_rt(rt2x00dev, RT3390) &&
2555 !rt2x00_rt(rt2x00dev, RT3572)) {
2556 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2557 return -ENODEV;
2558 }
2559
2560 if (!rt2x00_rf(rt2x00dev, RF2820) &&
2561 !rt2x00_rf(rt2x00dev, RF2850) &&
2562 !rt2x00_rf(rt2x00dev, RF2720) &&
2563 !rt2x00_rf(rt2x00dev, RF2750) &&
2564 !rt2x00_rf(rt2x00dev, RF3020) &&
2565 !rt2x00_rf(rt2x00dev, RF2020) &&
2566 !rt2x00_rf(rt2x00dev, RF3021) &&
2567 !rt2x00_rf(rt2x00dev, RF3022) &&
2568 !rt2x00_rf(rt2x00dev, RF3052)) {
2569 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2570 return -ENODEV;
2571 }
2572
2573 /*
2574 * Identify default antenna configuration.
2575 */
2576 rt2x00dev->default_ant.tx =
2577 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2578 rt2x00dev->default_ant.rx =
2579 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2580
2581 /*
2582 * Read frequency offset and RF programming sequence.
2583 */
2584 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2585 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2586
2587 /*
2588 * Read external LNA informations.
2589 */
2590 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2591
2592 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2593 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2594 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2595 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2596
2597 /*
2598 * Detect if this device has an hardware controlled radio.
2599 */
2600 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2601 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2602
2603 /*
2604 * Store led settings, for correct led behaviour.
2605 */
2606 #ifdef CONFIG_RT2X00_LIB_LEDS
2607 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2608 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2609 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2610
2611 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2612 #endif /* CONFIG_RT2X00_LIB_LEDS */
2613
2614 return 0;
2615 }
2616 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2617
2618 /*
2619 * RF value list for rt28xx
2620 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2621 */
2622 static const struct rf_channel rf_vals[] = {
2623 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2624 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2625 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2626 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2627 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2628 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2629 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2630 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2631 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2632 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2633 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2634 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2635 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2636 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2637
2638 /* 802.11 UNI / HyperLan 2 */
2639 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2640 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2641 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2642 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2643 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2644 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2645 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2646 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2647 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2648 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2649 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2650 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2651
2652 /* 802.11 HyperLan 2 */
2653 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2654 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2655 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2656 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2657 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2658 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2659 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2660 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2661 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2662 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2663 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2664 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2665 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2666 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2667 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2668 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2669
2670 /* 802.11 UNII */
2671 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2672 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2673 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2674 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2675 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2676 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2677 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2678 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2679 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2680 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2681 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2682
2683 /* 802.11 Japan */
2684 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2685 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2686 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2687 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2688 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2689 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2690 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2691 };
2692
2693 /*
2694 * RF value list for rt3xxx
2695 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
2696 */
2697 static const struct rf_channel rf_vals_3x[] = {
2698 {1, 241, 2, 2 },
2699 {2, 241, 2, 7 },
2700 {3, 242, 2, 2 },
2701 {4, 242, 2, 7 },
2702 {5, 243, 2, 2 },
2703 {6, 243, 2, 7 },
2704 {7, 244, 2, 2 },
2705 {8, 244, 2, 7 },
2706 {9, 245, 2, 2 },
2707 {10, 245, 2, 7 },
2708 {11, 246, 2, 2 },
2709 {12, 246, 2, 7 },
2710 {13, 247, 2, 2 },
2711 {14, 248, 2, 4 },
2712
2713 /* 802.11 UNI / HyperLan 2 */
2714 {36, 0x56, 0, 4},
2715 {38, 0x56, 0, 6},
2716 {40, 0x56, 0, 8},
2717 {44, 0x57, 0, 0},
2718 {46, 0x57, 0, 2},
2719 {48, 0x57, 0, 4},
2720 {52, 0x57, 0, 8},
2721 {54, 0x57, 0, 10},
2722 {56, 0x58, 0, 0},
2723 {60, 0x58, 0, 4},
2724 {62, 0x58, 0, 6},
2725 {64, 0x58, 0, 8},
2726
2727 /* 802.11 HyperLan 2 */
2728 {100, 0x5b, 0, 8},
2729 {102, 0x5b, 0, 10},
2730 {104, 0x5c, 0, 0},
2731 {108, 0x5c, 0, 4},
2732 {110, 0x5c, 0, 6},
2733 {112, 0x5c, 0, 8},
2734 {116, 0x5d, 0, 0},
2735 {118, 0x5d, 0, 2},
2736 {120, 0x5d, 0, 4},
2737 {124, 0x5d, 0, 8},
2738 {126, 0x5d, 0, 10},
2739 {128, 0x5e, 0, 0},
2740 {132, 0x5e, 0, 4},
2741 {134, 0x5e, 0, 6},
2742 {136, 0x5e, 0, 8},
2743 {140, 0x5f, 0, 0},
2744
2745 /* 802.11 UNII */
2746 {149, 0x5f, 0, 9},
2747 {151, 0x5f, 0, 11},
2748 {153, 0x60, 0, 1},
2749 {157, 0x60, 0, 5},
2750 {159, 0x60, 0, 7},
2751 {161, 0x60, 0, 9},
2752 {165, 0x61, 0, 1},
2753 {167, 0x61, 0, 3},
2754 {169, 0x61, 0, 5},
2755 {171, 0x61, 0, 7},
2756 {173, 0x61, 0, 9},
2757 };
2758
2759 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2760 {
2761 struct hw_mode_spec *spec = &rt2x00dev->spec;
2762 struct channel_info *info;
2763 char *default_power1;
2764 char *default_power2;
2765 unsigned int i;
2766 unsigned short max_power;
2767 u16 eeprom;
2768
2769 /*
2770 * Disable powersaving as default on PCI devices.
2771 */
2772 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
2773 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2774
2775 /*
2776 * Initialize all hw fields.
2777 */
2778 rt2x00dev->hw->flags =
2779 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2780 IEEE80211_HW_SIGNAL_DBM |
2781 IEEE80211_HW_SUPPORTS_PS |
2782 IEEE80211_HW_PS_NULLFUNC_STACK |
2783 IEEE80211_HW_AMPDU_AGGREGATION;
2784
2785 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2786 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2787 rt2x00_eeprom_addr(rt2x00dev,
2788 EEPROM_MAC_ADDR_0));
2789
2790 /*
2791 * As rt2800 has a global fallback table we cannot specify
2792 * more then one tx rate per frame but since the hw will
2793 * try several rates (based on the fallback table) we should
2794 * still initialize max_rates to the maximum number of rates
2795 * we are going to try. Otherwise mac80211 will truncate our
2796 * reported tx rates and the rc algortihm will end up with
2797 * incorrect data.
2798 */
2799 rt2x00dev->hw->max_rates = 7;
2800 rt2x00dev->hw->max_rate_tries = 1;
2801
2802 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2803
2804 /*
2805 * Initialize hw_mode information.
2806 */
2807 spec->supported_bands = SUPPORT_BAND_2GHZ;
2808 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2809
2810 if (rt2x00_rf(rt2x00dev, RF2820) ||
2811 rt2x00_rf(rt2x00dev, RF2720)) {
2812 spec->num_channels = 14;
2813 spec->channels = rf_vals;
2814 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
2815 rt2x00_rf(rt2x00dev, RF2750)) {
2816 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2817 spec->num_channels = ARRAY_SIZE(rf_vals);
2818 spec->channels = rf_vals;
2819 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2820 rt2x00_rf(rt2x00dev, RF2020) ||
2821 rt2x00_rf(rt2x00dev, RF3021) ||
2822 rt2x00_rf(rt2x00dev, RF3022)) {
2823 spec->num_channels = 14;
2824 spec->channels = rf_vals_3x;
2825 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
2826 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2827 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
2828 spec->channels = rf_vals_3x;
2829 }
2830
2831 /*
2832 * Initialize HT information.
2833 */
2834 if (!rt2x00_rf(rt2x00dev, RF2020))
2835 spec->ht.ht_supported = true;
2836 else
2837 spec->ht.ht_supported = false;
2838
2839 spec->ht.cap =
2840 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2841 IEEE80211_HT_CAP_GRN_FLD |
2842 IEEE80211_HT_CAP_SGI_20 |
2843 IEEE80211_HT_CAP_SGI_40;
2844
2845 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2)
2846 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
2847
2848 spec->ht.cap |=
2849 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) <<
2850 IEEE80211_HT_CAP_RX_STBC_SHIFT;
2851
2852 spec->ht.ampdu_factor = 3;
2853 spec->ht.ampdu_density = 4;
2854 spec->ht.mcs.tx_params =
2855 IEEE80211_HT_MCS_TX_DEFINED |
2856 IEEE80211_HT_MCS_TX_RX_DIFF |
2857 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2858 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2859
2860 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2861 case 3:
2862 spec->ht.mcs.rx_mask[2] = 0xff;
2863 case 2:
2864 spec->ht.mcs.rx_mask[1] = 0xff;
2865 case 1:
2866 spec->ht.mcs.rx_mask[0] = 0xff;
2867 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2868 break;
2869 }
2870
2871 /*
2872 * Create channel information array
2873 */
2874 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2875 if (!info)
2876 return -ENOMEM;
2877
2878 spec->channels_info = info;
2879
2880 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
2881 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
2882 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2883 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2884
2885 for (i = 0; i < 14; i++) {
2886 info[i].max_power = max_power;
2887 info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]);
2888 info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
2889 }
2890
2891 if (spec->num_channels > 14) {
2892 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
2893 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2894 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2895
2896 for (i = 14; i < spec->num_channels; i++) {
2897 info[i].max_power = max_power;
2898 info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]);
2899 info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
2900 }
2901 }
2902
2903 return 0;
2904 }
2905 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2906
2907 /*
2908 * IEEE80211 stack callback functions.
2909 */
2910 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
2911 u16 *iv16)
2912 {
2913 struct rt2x00_dev *rt2x00dev = hw->priv;
2914 struct mac_iveiv_entry iveiv_entry;
2915 u32 offset;
2916
2917 offset = MAC_IVEIV_ENTRY(hw_key_idx);
2918 rt2800_register_multiread(rt2x00dev, offset,
2919 &iveiv_entry, sizeof(iveiv_entry));
2920
2921 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2922 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2923 }
2924 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
2925
2926 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2927 {
2928 struct rt2x00_dev *rt2x00dev = hw->priv;
2929 u32 reg;
2930 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2931
2932 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2933 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2934 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2935
2936 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2937 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2938 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2939
2940 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2941 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2942 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2943
2944 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2945 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2946 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2947
2948 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2949 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2950 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2951
2952 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2953 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2954 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2955
2956 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2957 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2958 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2959
2960 return 0;
2961 }
2962 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
2963
2964 int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2965 const struct ieee80211_tx_queue_params *params)
2966 {
2967 struct rt2x00_dev *rt2x00dev = hw->priv;
2968 struct data_queue *queue;
2969 struct rt2x00_field32 field;
2970 int retval;
2971 u32 reg;
2972 u32 offset;
2973
2974 /*
2975 * First pass the configuration through rt2x00lib, that will
2976 * update the queue settings and validate the input. After that
2977 * we are free to update the registers based on the value
2978 * in the queue parameter.
2979 */
2980 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2981 if (retval)
2982 return retval;
2983
2984 /*
2985 * We only need to perform additional register initialization
2986 * for WMM queues/
2987 */
2988 if (queue_idx >= 4)
2989 return 0;
2990
2991 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2992
2993 /* Update WMM TXOP register */
2994 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2995 field.bit_offset = (queue_idx & 1) * 16;
2996 field.bit_mask = 0xffff << field.bit_offset;
2997
2998 rt2800_register_read(rt2x00dev, offset, &reg);
2999 rt2x00_set_field32(&reg, field, queue->txop);
3000 rt2800_register_write(rt2x00dev, offset, reg);
3001
3002 /* Update WMM registers */
3003 field.bit_offset = queue_idx * 4;
3004 field.bit_mask = 0xf << field.bit_offset;
3005
3006 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3007 rt2x00_set_field32(&reg, field, queue->aifs);
3008 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3009
3010 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3011 rt2x00_set_field32(&reg, field, queue->cw_min);
3012 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3013
3014 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3015 rt2x00_set_field32(&reg, field, queue->cw_max);
3016 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3017
3018 /* Update EDCA registers */
3019 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3020
3021 rt2800_register_read(rt2x00dev, offset, &reg);
3022 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3023 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3024 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3025 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3026 rt2800_register_write(rt2x00dev, offset, reg);
3027
3028 return 0;
3029 }
3030 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
3031
3032 u64 rt2800_get_tsf(struct ieee80211_hw *hw)
3033 {
3034 struct rt2x00_dev *rt2x00dev = hw->priv;
3035 u64 tsf;
3036 u32 reg;
3037
3038 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3039 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3040 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3041 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3042
3043 return tsf;
3044 }
3045 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
3046
3047 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3048 enum ieee80211_ampdu_mlme_action action,
3049 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3050 {
3051 int ret = 0;
3052
3053 switch (action) {
3054 case IEEE80211_AMPDU_RX_START:
3055 case IEEE80211_AMPDU_RX_STOP:
3056 /* we don't support RX aggregation yet */
3057 ret = -ENOTSUPP;
3058 break;
3059 case IEEE80211_AMPDU_TX_START:
3060 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3061 break;
3062 case IEEE80211_AMPDU_TX_STOP:
3063 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3064 break;
3065 case IEEE80211_AMPDU_TX_OPERATIONAL:
3066 break;
3067 default:
3068 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
3069 }
3070
3071 return ret;
3072 }
3073 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
3074
3075 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3076 MODULE_VERSION(DRV_VERSION);
3077 MODULE_DESCRIPTION("Ralink RT2800 library");
3078 MODULE_LICENSE("GPL");
Tomato firmware and modifications.