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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / wireless / p54 / p54pci.c
blob4ff50294700de8d7f1a56b08217c6d9a339f54ff
1
2 /*
3 * Linux device driver for PCI based Prism54
4 *
5 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
6 * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
7 *
8 * Based on the islsm (softmac prism54) driver, which is:
9 * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16 #include <linux/init.h>
17 #include <linux/pci.h>
18 #include <linux/slab.h>
19 #include <linux/firmware.h>
20 #include <linux/etherdevice.h>
21 #include <linux/delay.h>
22 #include <linux/completion.h>
23 #include <net/mac80211.h>
24
25 #include "p54.h"
26 #include "lmac.h"
27 #include "p54pci.h"
28
29 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
30 MODULE_DESCRIPTION("Prism54 PCI wireless driver");
31 MODULE_LICENSE("GPL");
32 MODULE_ALIAS("prism54pci");
33 MODULE_FIRMWARE("isl3886pci");
34
35 static DEFINE_PCI_DEVICE_TABLE(p54p_table) = {
36 /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
37 { PCI_DEVICE(0x1260, 0x3890) },
38 /* 3COM 3CRWE154G72 Wireless LAN adapter */
39 { PCI_DEVICE(0x10b7, 0x6001) },
40 /* Intersil PRISM Indigo Wireless LAN adapter */
41 { PCI_DEVICE(0x1260, 0x3877) },
42 /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
43 { PCI_DEVICE(0x1260, 0x3886) },
44 /* Intersil PRISM Xbow Wireless LAN adapter (Symbol AP-300) */
45 { PCI_DEVICE(0x1260, 0xffff) },
46 { },
47 };
48
49 MODULE_DEVICE_TABLE(pci, p54p_table);
50
51 static int p54p_upload_firmware(struct ieee80211_hw *dev)
52 {
53 struct p54p_priv *priv = dev->priv;
54 __le32 reg;
55 int err;
56 __le32 *data;
57 u32 remains, left, device_addr;
58
59 P54P_WRITE(int_enable, cpu_to_le32(0));
60 P54P_READ(int_enable);
61 udelay(10);
62
63 reg = P54P_READ(ctrl_stat);
64 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
65 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
66 P54P_WRITE(ctrl_stat, reg);
67 P54P_READ(ctrl_stat);
68 udelay(10);
69
70 reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
71 P54P_WRITE(ctrl_stat, reg);
72 wmb();
73 udelay(10);
74
75 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
76 P54P_WRITE(ctrl_stat, reg);
77 wmb();
78
79 /* wait for the firmware to reset properly */
80 mdelay(10);
81
82 err = p54_parse_firmware(dev, priv->firmware);
83 if (err)
84 return err;
85
86 if (priv->common.fw_interface != FW_LM86) {
87 dev_err(&priv->pdev->dev, "wrong firmware, "
88 "please get a LM86(PCI) firmware a try again.\n");
89 return -EINVAL;
90 }
91
92 data = (__le32 *) priv->firmware->data;
93 remains = priv->firmware->size;
94 device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
95 while (remains) {
96 u32 i = 0;
97 left = min((u32)0x1000, remains);
98 P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
99 P54P_READ(int_enable);
100
101 device_addr += 0x1000;
102 while (i < left) {
103 P54P_WRITE(direct_mem_win[i], *data++);
104 i += sizeof(u32);
105 }
106
107 remains -= left;
108 P54P_READ(int_enable);
109 }
110
111 reg = P54P_READ(ctrl_stat);
112 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
113 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
114 reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
115 P54P_WRITE(ctrl_stat, reg);
116 P54P_READ(ctrl_stat);
117 udelay(10);
118
119 reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
120 P54P_WRITE(ctrl_stat, reg);
121 wmb();
122 udelay(10);
123
124 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
125 P54P_WRITE(ctrl_stat, reg);
126 wmb();
127 udelay(10);
128
129 /* wait for the firmware to boot properly */
130 mdelay(100);
131
132 return 0;
133 }
134
135 static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
136 int ring_index, struct p54p_desc *ring, u32 ring_limit,
137 struct sk_buff **rx_buf, u32 index)
138 {
139 struct p54p_priv *priv = dev->priv;
140 struct p54p_ring_control *ring_control = priv->ring_control;
141 u32 limit, idx, i;
142
143 idx = le32_to_cpu(ring_control->host_idx[ring_index]);
144 limit = idx;
145 limit -= index;
146 limit = ring_limit - limit;
147
148 i = idx % ring_limit;
149 while (limit-- > 1) {
150 struct p54p_desc *desc = &ring[i];
151
152 if (!desc->host_addr) {
153 struct sk_buff *skb;
154 dma_addr_t mapping;
155 skb = dev_alloc_skb(priv->common.rx_mtu + 32);
156 if (!skb)
157 break;
158
159 mapping = pci_map_single(priv->pdev,
160 skb_tail_pointer(skb),
161 priv->common.rx_mtu + 32,
162 PCI_DMA_FROMDEVICE);
163
164 if (pci_dma_mapping_error(priv->pdev, mapping)) {
165 dev_kfree_skb_any(skb);
166 dev_err(&priv->pdev->dev,
167 "RX DMA Mapping error\n");
168 break;
169 }
170
171 desc->host_addr = cpu_to_le32(mapping);
172 desc->device_addr = 0;
173 desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
174 desc->flags = 0;
175 rx_buf[i] = skb;
176 }
177
178 i++;
179 idx++;
180 i %= ring_limit;
181 }
182
183 wmb();
184 ring_control->host_idx[ring_index] = cpu_to_le32(idx);
185 }
186
187 static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
188 int ring_index, struct p54p_desc *ring, u32 ring_limit,
189 struct sk_buff **rx_buf)
190 {
191 struct p54p_priv *priv = dev->priv;
192 struct p54p_ring_control *ring_control = priv->ring_control;
193 struct p54p_desc *desc;
194 u32 idx, i;
195
196 i = (*index) % ring_limit;
197 (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
198 idx %= ring_limit;
199 while (i != idx) {
200 u16 len;
201 struct sk_buff *skb;
202 desc = &ring[i];
203 len = le16_to_cpu(desc->len);
204 skb = rx_buf[i];
205
206 if (!skb) {
207 i++;
208 i %= ring_limit;
209 continue;
210 }
211
212 if (unlikely(len > priv->common.rx_mtu)) {
213 if (net_ratelimit())
214 dev_err(&priv->pdev->dev, "rx'd frame size "
215 "exceeds length threshold.\n");
216
217 len = priv->common.rx_mtu;
218 }
219 skb_put(skb, len);
220
221 if (p54_rx(dev, skb)) {
222 pci_unmap_single(priv->pdev,
223 le32_to_cpu(desc->host_addr),
224 priv->common.rx_mtu + 32,
225 PCI_DMA_FROMDEVICE);
226 rx_buf[i] = NULL;
227 desc->host_addr = 0;
228 } else {
229 skb_trim(skb, 0);
230 desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
231 }
232
233 i++;
234 i %= ring_limit;
235 }
236
237 p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf, *index);
238 }
239
240 static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
241 int ring_index, struct p54p_desc *ring, u32 ring_limit,
242 struct sk_buff **tx_buf)
243 {
244 struct p54p_priv *priv = dev->priv;
245 struct p54p_ring_control *ring_control = priv->ring_control;
246 struct p54p_desc *desc;
247 struct sk_buff *skb;
248 u32 idx, i;
249
250 i = (*index) % ring_limit;
251 (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
252 idx %= ring_limit;
253
254 while (i != idx) {
255 desc = &ring[i];
256
257 skb = tx_buf[i];
258 tx_buf[i] = NULL;
259
260 pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
261 le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
262
263 desc->host_addr = 0;
264 desc->device_addr = 0;
265 desc->len = 0;
266 desc->flags = 0;
267
268 if (skb && FREE_AFTER_TX(skb))
269 p54_free_skb(dev, skb);
270
271 i++;
272 i %= ring_limit;
273 }
274 }
275
276 static void p54p_tasklet(unsigned long dev_id)
277 {
278 struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
279 struct p54p_priv *priv = dev->priv;
280 struct p54p_ring_control *ring_control = priv->ring_control;
281
282 p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
283 ARRAY_SIZE(ring_control->tx_mgmt),
284 priv->tx_buf_mgmt);
285
286 p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
287 ARRAY_SIZE(ring_control->tx_data),
288 priv->tx_buf_data);
289
290 p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
291 ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
292
293 p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
294 ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
295
296 wmb();
297 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
298 }
299
300 static irqreturn_t p54p_interrupt(int irq, void *dev_id)
301 {
302 struct ieee80211_hw *dev = dev_id;
303 struct p54p_priv *priv = dev->priv;
304 __le32 reg;
305
306 reg = P54P_READ(int_ident);
307 if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
308 goto out;
309 }
310 P54P_WRITE(int_ack, reg);
311
312 reg &= P54P_READ(int_enable);
313
314 if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
315 tasklet_schedule(&priv->tasklet);
316 else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
317 complete(&priv->boot_comp);
318
319 out:
320 return reg ? IRQ_HANDLED : IRQ_NONE;
321 }
322
323 static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
324 {
325 unsigned long flags;
326 struct p54p_priv *priv = dev->priv;
327 struct p54p_ring_control *ring_control = priv->ring_control;
328 struct p54p_desc *desc;
329 dma_addr_t mapping;
330 u32 device_idx, idx, i;
331
332 spin_lock_irqsave(&priv->lock, flags);
333 device_idx = le32_to_cpu(ring_control->device_idx[1]);
334 idx = le32_to_cpu(ring_control->host_idx[1]);
335 i = idx % ARRAY_SIZE(ring_control->tx_data);
336
337 mapping = pci_map_single(priv->pdev, skb->data, skb->len,
338 PCI_DMA_TODEVICE);
339 if (pci_dma_mapping_error(priv->pdev, mapping)) {
340 spin_unlock_irqrestore(&priv->lock, flags);
341 p54_free_skb(dev, skb);
342 dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
343 return ;
344 }
345 priv->tx_buf_data[i] = skb;
346
347 desc = &ring_control->tx_data[i];
348 desc->host_addr = cpu_to_le32(mapping);
349 desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
350 desc->len = cpu_to_le16(skb->len);
351 desc->flags = 0;
352
353 wmb();
354 ring_control->host_idx[1] = cpu_to_le32(idx + 1);
355 spin_unlock_irqrestore(&priv->lock, flags);
356
357 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
358 P54P_READ(dev_int);
359 }
360
361 static void p54p_stop(struct ieee80211_hw *dev)
362 {
363 struct p54p_priv *priv = dev->priv;
364 struct p54p_ring_control *ring_control = priv->ring_control;
365 unsigned int i;
366 struct p54p_desc *desc;
367
368 P54P_WRITE(int_enable, cpu_to_le32(0));
369 P54P_READ(int_enable);
370 udelay(10);
371
372 free_irq(priv->pdev->irq, dev);
373
374 tasklet_kill(&priv->tasklet);
375
376 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
377
378 for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
379 desc = &ring_control->rx_data[i];
380 if (desc->host_addr)
381 pci_unmap_single(priv->pdev,
382 le32_to_cpu(desc->host_addr),
383 priv->common.rx_mtu + 32,
384 PCI_DMA_FROMDEVICE);
385 kfree_skb(priv->rx_buf_data[i]);
386 priv->rx_buf_data[i] = NULL;
387 }
388
389 for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
390 desc = &ring_control->rx_mgmt[i];
391 if (desc->host_addr)
392 pci_unmap_single(priv->pdev,
393 le32_to_cpu(desc->host_addr),
394 priv->common.rx_mtu + 32,
395 PCI_DMA_FROMDEVICE);
396 kfree_skb(priv->rx_buf_mgmt[i]);
397 priv->rx_buf_mgmt[i] = NULL;
398 }
399
400 for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
401 desc = &ring_control->tx_data[i];
402 if (desc->host_addr)
403 pci_unmap_single(priv->pdev,
404 le32_to_cpu(desc->host_addr),
405 le16_to_cpu(desc->len),
406 PCI_DMA_TODEVICE);
407
408 p54_free_skb(dev, priv->tx_buf_data[i]);
409 priv->tx_buf_data[i] = NULL;
410 }
411
412 for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
413 desc = &ring_control->tx_mgmt[i];
414 if (desc->host_addr)
415 pci_unmap_single(priv->pdev,
416 le32_to_cpu(desc->host_addr),
417 le16_to_cpu(desc->len),
418 PCI_DMA_TODEVICE);
419
420 p54_free_skb(dev, priv->tx_buf_mgmt[i]);
421 priv->tx_buf_mgmt[i] = NULL;
422 }
423
424 memset(ring_control, 0, sizeof(*ring_control));
425 }
426
427 static int p54p_open(struct ieee80211_hw *dev)
428 {
429 struct p54p_priv *priv = dev->priv;
430 int err;
431
432 init_completion(&priv->boot_comp);
433 err = request_irq(priv->pdev->irq, p54p_interrupt,
434 IRQF_SHARED, "p54pci", dev);
435 if (err) {
436 dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
437 return err;
438 }
439
440 memset(priv->ring_control, 0, sizeof(*priv->ring_control));
441 err = p54p_upload_firmware(dev);
442 if (err) {
443 free_irq(priv->pdev->irq, dev);
444 return err;
445 }
446 priv->rx_idx_data = priv->tx_idx_data = 0;
447 priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
448
449 p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
450 ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data, 0);
451
452 p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
453 ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt, 0);
454
455 P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
456 P54P_READ(ring_control_base);
457 wmb();
458 udelay(10);
459
460 P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
461 P54P_READ(int_enable);
462 wmb();
463 udelay(10);
464
465 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
466 P54P_READ(dev_int);
467
468 if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
469 wiphy_err(dev->wiphy, "Cannot boot firmware!\n");
470 p54p_stop(dev);
471 return -ETIMEDOUT;
472 }
473
474 P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
475 P54P_READ(int_enable);
476 wmb();
477 udelay(10);
478
479 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
480 P54P_READ(dev_int);
481 wmb();
482 udelay(10);
483
484 return 0;
485 }
486
487 static int __devinit p54p_probe(struct pci_dev *pdev,
488 const struct pci_device_id *id)
489 {
490 struct p54p_priv *priv;
491 struct ieee80211_hw *dev;
492 unsigned long mem_addr, mem_len;
493 int err;
494
495 err = pci_enable_device(pdev);
496 if (err) {
497 dev_err(&pdev->dev, "Cannot enable new PCI device\n");
498 return err;
499 }
500
501 mem_addr = pci_resource_start(pdev, 0);
502 mem_len = pci_resource_len(pdev, 0);
503 if (mem_len < sizeof(struct p54p_csr)) {
504 dev_err(&pdev->dev, "Too short PCI resources\n");
505 goto err_disable_dev;
506 }
507
508 err = pci_request_regions(pdev, "p54pci");
509 if (err) {
510 dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
511 goto err_disable_dev;
512 }
513
514 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
515 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
516 dev_err(&pdev->dev, "No suitable DMA available\n");
517 goto err_free_reg;
518 }
519
520 pci_set_master(pdev);
521 pci_try_set_mwi(pdev);
522
523 pci_write_config_byte(pdev, 0x40, 0);
524 pci_write_config_byte(pdev, 0x41, 0);
525
526 dev = p54_init_common(sizeof(*priv));
527 if (!dev) {
528 dev_err(&pdev->dev, "ieee80211 alloc failed\n");
529 err = -ENOMEM;
530 goto err_free_reg;
531 }
532
533 priv = dev->priv;
534 priv->pdev = pdev;
535
536 SET_IEEE80211_DEV(dev, &pdev->dev);
537 pci_set_drvdata(pdev, dev);
538
539 priv->map = ioremap(mem_addr, mem_len);
540 if (!priv->map) {
541 dev_err(&pdev->dev, "Cannot map device memory\n");
542 err = -ENOMEM;
543 goto err_free_dev;
544 }
545
546 priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
547 &priv->ring_control_dma);
548 if (!priv->ring_control) {
549 dev_err(&pdev->dev, "Cannot allocate rings\n");
550 err = -ENOMEM;
551 goto err_iounmap;
552 }
553 priv->common.open = p54p_open;
554 priv->common.stop = p54p_stop;
555 priv->common.tx = p54p_tx;
556
557 spin_lock_init(&priv->lock);
558 tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev);
559
560 err = request_firmware(&priv->firmware, "isl3886pci",
561 &priv->pdev->dev);
562 if (err) {
563 dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
564 err = request_firmware(&priv->firmware, "isl3886",
565 &priv->pdev->dev);
566 if (err)
567 goto err_free_common;
568 }
569
570 err = p54p_open(dev);
571 if (err)
572 goto err_free_common;
573 err = p54_read_eeprom(dev);
574 p54p_stop(dev);
575 if (err)
576 goto err_free_common;
577
578 err = p54_register_common(dev, &pdev->dev);
579 if (err)
580 goto err_free_common;
581
582 return 0;
583
584 err_free_common:
585 release_firmware(priv->firmware);
586 pci_free_consistent(pdev, sizeof(*priv->ring_control),
587 priv->ring_control, priv->ring_control_dma);
588
589 err_iounmap:
590 iounmap(priv->map);
591
592 err_free_dev:
593 pci_set_drvdata(pdev, NULL);
594 p54_free_common(dev);
595
596 err_free_reg:
597 pci_release_regions(pdev);
598 err_disable_dev:
599 pci_disable_device(pdev);
600 return err;
601 }
602
603 static void __devexit p54p_remove(struct pci_dev *pdev)
604 {
605 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
606 struct p54p_priv *priv;
607
608 if (!dev)
609 return;
610
611 p54_unregister_common(dev);
612 priv = dev->priv;
613 release_firmware(priv->firmware);
614 pci_free_consistent(pdev, sizeof(*priv->ring_control),
615 priv->ring_control, priv->ring_control_dma);
616 iounmap(priv->map);
617 pci_release_regions(pdev);
618 pci_disable_device(pdev);
619 p54_free_common(dev);
620 }
621
622 #ifdef CONFIG_PM
623 static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
624 {
625 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
626 struct p54p_priv *priv = dev->priv;
627
628 if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
629 ieee80211_stop_queues(dev);
630 p54p_stop(dev);
631 }
632
633 pci_save_state(pdev);
634 pci_set_power_state(pdev, pci_choose_state(pdev, state));
635 return 0;
636 }
637
638 static int p54p_resume(struct pci_dev *pdev)
639 {
640 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
641 struct p54p_priv *priv = dev->priv;
642
643 pci_set_power_state(pdev, PCI_D0);
644 pci_restore_state(pdev);
645
646 if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
647 p54p_open(dev);
648 ieee80211_wake_queues(dev);
649 }
650
651 return 0;
652 }
653 #endif /* CONFIG_PM */
654
655 static struct pci_driver p54p_driver = {
656 .name = "p54pci",
657 .id_table = p54p_table,
658 .probe = p54p_probe,
659 .remove = __devexit_p(p54p_remove),
660 #ifdef CONFIG_PM
661 .suspend = p54p_suspend,
662 .resume = p54p_resume,
663 #endif /* CONFIG_PM */
664 };
665
666 static int __init p54p_init(void)
667 {
668 return pci_register_driver(&p54p_driver);
669 }
670
671 static void __exit p54p_exit(void)
672 {
673 pci_unregister_driver(&p54p_driver);
674 }
675
676 module_init(p54p_init);
677 module_exit(p54p_exit);
Tomato firmware and modifications.