release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/wireless/iwlwifi/iwl-csr.h

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
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  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
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  17  * General Public License for more details.
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  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22  * USA
  23  *
  24  * The full GNU General Public License is included in this distribution
  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
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  48  *    from this software without specific prior written permission.
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  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #ifndef __iwl_csr_h__
  64 #define __iwl_csr_h__
  65 /*
  66  * CSR (control and status registers)
  67  *
  68  * CSR registers are mapped directly into PCI bus space, and are accessible
  69  * whenever platform supplies power to device, even when device is in
  70  * low power states due to driver-invoked device resets
  71  * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
  72  *
  73  * Use iwl_write32() and iwl_read32() family to access these registers;
  74  * these provide simple PCI bus access, without waking up the MAC.
  75  * Do not use iwl_write_direct32() family for these registers;
  76  * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
  77  * The MAC (uCode processor, etc.) does not need to be powered up for accessing
  78  * the CSR registers.
  79  *
  80  * NOTE:  Device does need to be awake in order to read this memory
  81  *        via CSR_EEPROM and CSR_OTP registers
  82  */
  83 #define CSR_BASE    (0x000)
  84
  85 #define CSR_HW_IF_CONFIG_REG    (CSR_BASE+0x000) /* hardware interface config */
  86 #define CSR_INT_COALESCING      (CSR_BASE+0x004) /* accum ints, 32-usec units */
  87 #define CSR_INT                 (CSR_BASE+0x008) /* host interrupt status/ack */
  88 #define CSR_INT_MASK            (CSR_BASE+0x00c) /* host interrupt enable */
  89 #define CSR_FH_INT_STATUS       (CSR_BASE+0x010) /* busmaster int status/ack*/
  90 #define CSR_GPIO_IN             (CSR_BASE+0x018) /* read external chip pins */
  91 #define CSR_RESET               (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
  92 #define CSR_GP_CNTRL            (CSR_BASE+0x024)
  93
  94 /* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */
  95 #define CSR_INT_PERIODIC_REG    (CSR_BASE+0x005)
  96
  97 #define CSR_HW_REV              (CSR_BASE+0x028)
  98
  99 /*
 100  * EEPROM and OTP (one-time-programmable) memory reads
 101  *
 102  * NOTE:  Device must be awake, initialized via apm_ops.init(),
 103  *        in order to read.
 104  */
 105 #define CSR_EEPROM_REG          (CSR_BASE+0x02c)
 106 #define CSR_EEPROM_GP           (CSR_BASE+0x030)
 107 #define CSR_OTP_GP_REG          (CSR_BASE+0x034)
 108
 109 #define CSR_GIO_REG             (CSR_BASE+0x03C)
 110 #define CSR_GP_UCODE_REG        (CSR_BASE+0x048)
 111 #define CSR_GP_DRIVER_REG       (CSR_BASE+0x050)
 112
 113 /*
 114  * UCODE-DRIVER GP (general purpose) mailbox registers.
 115  * SET/CLR registers set/clear bit(s) if "1" is written.
 116  */
 117 #define CSR_UCODE_DRV_GP1       (CSR_BASE+0x054)
 118 #define CSR_UCODE_DRV_GP1_SET   (CSR_BASE+0x058)
 119 #define CSR_UCODE_DRV_GP1_CLR   (CSR_BASE+0x05c)
 120 #define CSR_UCODE_DRV_GP2       (CSR_BASE+0x060)
 121
 122 #define CSR_LED_REG             (CSR_BASE+0x094)
 123 #define CSR_DRAM_INT_TBL_REG    (CSR_BASE+0x0A0)
 124
 125 /* GIO Chicken Bits (PCI Express bus link power management) */
 126 #define CSR_GIO_CHICKEN_BITS    (CSR_BASE+0x100)
 127
 128 /* Analog phase-lock-loop configuration  */
 129 #define CSR_ANA_PLL_CFG         (CSR_BASE+0x20c)
 130
 131 #define CSR_HW_REV_WA_REG               (CSR_BASE+0x22C)
 132
 133 #define CSR_DBG_HPET_MEM_REG            (CSR_BASE+0x240)
 134 #define CSR_DBG_LINK_PWR_MGMT_REG       (CSR_BASE+0x250)
 135
 136 /* Bits for CSR_HW_IF_CONFIG_REG */
 137 #define CSR49_HW_IF_CONFIG_REG_BIT_4965_R       (0x00000010)
 138 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER      (0x00000C00)
 139 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI         (0x00000100)
 140 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI       (0x00000200)
 141
 142 #define CSR39_HW_IF_CONFIG_REG_BIT_3945_MB         (0x00000100)
 143 #define CSR39_HW_IF_CONFIG_REG_BIT_3945_MM         (0x00000200)
 144 #define CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC            (0x00000400)
 145 #define CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE         (0x00000800)
 146 #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A    (0x00000000)
 147 #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B    (0x00001000)
 148
 149 #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A   (0x00080000)
 150 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
 151 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY      (0x00400000) /* PCI_OWN_SEM */
 152 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
 153 #define CSR_HW_IF_CONFIG_REG_PREPARE              (0x08000000) /* WAKE_ME */
 154
 155 #define CSR_INT_PERIODIC_DIS                    (0x00) /* disable periodic int*/
 156 #define CSR_INT_PERIODIC_ENA                    (0xFF) /* 255*32 usec ~ 8 msec*/
 157
 158 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
 159  * acknowledged (reset) by host writing "1" to flagged bits. */
 160 #define CSR_INT_BIT_FH_RX        (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
 161 #define CSR_INT_BIT_HW_ERR       (1 << 29) /* DMA hardware error FH_INT[31] */
 162 #define CSR_INT_BIT_RX_PERIODIC  (1 << 28) /* Rx periodic */
 163 #define CSR_INT_BIT_FH_TX        (1 << 27) /* Tx DMA FH_INT[1:0] */
 164 #define CSR_INT_BIT_SCD          (1 << 26) /* TXQ pointer advanced */
 165 #define CSR_INT_BIT_SW_ERR       (1 << 25) /* uCode error */
 166 #define CSR_INT_BIT_RF_KILL      (1 << 7)  /* HW RFKILL switch GP_CNTRL[27] toggled */
 167 #define CSR_INT_BIT_CT_KILL      (1 << 6)  /* Critical temp (chip too hot) rfkill */
 168 #define CSR_INT_BIT_SW_RX        (1 << 3)  /* Rx, command responses, 3945 */
 169 #define CSR_INT_BIT_WAKEUP       (1 << 1)  /* NIC controller waking up (pwr mgmt) */
 170 #define CSR_INT_BIT_ALIVE        (1 << 0)  /* uCode interrupts once it initializes */
 171
 172 #define CSR_INI_SET_MASK        (CSR_INT_BIT_FH_RX   | \
 173                                  CSR_INT_BIT_HW_ERR  | \
 174                                  CSR_INT_BIT_FH_TX   | \
 175                                  CSR_INT_BIT_SW_ERR  | \
 176                                  CSR_INT_BIT_RF_KILL | \
 177                                  CSR_INT_BIT_SW_RX   | \
 178                                  CSR_INT_BIT_WAKEUP  | \
 179                                  CSR_INT_BIT_ALIVE)
 180
 181 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
 182 #define CSR_FH_INT_BIT_ERR       (1 << 31) /* Error */
 183 #define CSR_FH_INT_BIT_HI_PRIOR  (1 << 30) /* High priority Rx, bypass coalescing */
 184 #define CSR39_FH_INT_BIT_RX_CHNL2  (1 << 18) /* Rx channel 2 (3945 only) */
 185 #define CSR_FH_INT_BIT_RX_CHNL1  (1 << 17) /* Rx channel 1 */
 186 #define CSR_FH_INT_BIT_RX_CHNL0  (1 << 16) /* Rx channel 0 */
 187 #define CSR39_FH_INT_BIT_TX_CHNL6  (1 << 6)  /* Tx channel 6 (3945 only) */
 188 #define CSR_FH_INT_BIT_TX_CHNL1  (1 << 1)  /* Tx channel 1 */
 189 #define CSR_FH_INT_BIT_TX_CHNL0  (1 << 0)  /* Tx channel 0 */
 190
 191 #define CSR39_FH_INT_RX_MASK    (CSR_FH_INT_BIT_HI_PRIOR | \
 192                                  CSR39_FH_INT_BIT_RX_CHNL2 | \
 193                                  CSR_FH_INT_BIT_RX_CHNL1 | \
 194                                  CSR_FH_INT_BIT_RX_CHNL0)
 195
 196
 197 #define CSR39_FH_INT_TX_MASK    (CSR39_FH_INT_BIT_TX_CHNL6 | \
 198                                  CSR_FH_INT_BIT_TX_CHNL1 | \
 199                                  CSR_FH_INT_BIT_TX_CHNL0)
 200
 201 #define CSR49_FH_INT_RX_MASK    (CSR_FH_INT_BIT_HI_PRIOR | \
 202                                  CSR_FH_INT_BIT_RX_CHNL1 | \
 203                                  CSR_FH_INT_BIT_RX_CHNL0)
 204
 205 #define CSR49_FH_INT_TX_MASK    (CSR_FH_INT_BIT_TX_CHNL1 | \
 206                                  CSR_FH_INT_BIT_TX_CHNL0)
 207
 208 /* GPIO */
 209 #define CSR_GPIO_IN_BIT_AUX_POWER                   (0x00000200)
 210 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC                (0x00000000)
 211 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC               (0x00000200)
 212
 213 /* RESET */
 214 #define CSR_RESET_REG_FLAG_NEVO_RESET                (0x00000001)
 215 #define CSR_RESET_REG_FLAG_FORCE_NMI                 (0x00000002)
 216 #define CSR_RESET_REG_FLAG_SW_RESET                  (0x00000080)
 217 #define CSR_RESET_REG_FLAG_MASTER_DISABLED           (0x00000100)
 218 #define CSR_RESET_REG_FLAG_STOP_MASTER               (0x00000200)
 219 #define CSR_RESET_LINK_PWR_MGMT_DISABLED             (0x80000000)
 220
 221 /*
 222  * GP (general purpose) CONTROL REGISTER
 223  * Bit fields:
 224  *    27:  HW_RF_KILL_SW
 225  *         Indicates state of (platform's) hardware RF-Kill switch
 226  * 26-24:  POWER_SAVE_TYPE
 227  *         Indicates current power-saving mode:
 228  *         000 -- No power saving
 229  *         001 -- MAC power-down
 230  *         010 -- PHY (radio) power-down
 231  *         011 -- Error
 232  *   9-6:  SYS_CONFIG
 233  *         Indicates current system configuration, reflecting pins on chip
 234  *         as forced high/low by device circuit board.
 235  *     4:  GOING_TO_SLEEP
 236  *         Indicates MAC is entering a power-saving sleep power-down.
 237  *         Not a good time to access device-internal resources.
 238  *     3:  MAC_ACCESS_REQ
 239  *         Host sets this to request and maintain MAC wakeup, to allow host
 240  *         access to device-internal resources.  Host must wait for
 241  *         MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
 242  *         device registers.
 243  *     2:  INIT_DONE
 244  *         Host sets this to put device into fully operational D0 power mode.
 245  *         Host resets this after SW_RESET to put device into low power mode.
 246  *     0:  MAC_CLOCK_READY
 247  *         Indicates MAC (ucode processor, etc.) is powered up and can run.
 248  *         Internal resources are accessible.
 249  *         NOTE:  This does not indicate that the processor is actually running.
 250  *         NOTE:  This does not indicate that 4965 or 3945 has completed
 251  *                init or post-power-down restore of internal SRAM memory.
 252  *                Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
 253  *                SRAM is restored and uCode is in normal operation mode.
 254  *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
 255  *                do not need to save/restore it.
 256  *         NOTE:  After device reset, this bit remains "0" until host sets
 257  *                INIT_DONE
 258  */
 259 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY        (0x00000001)
 260 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE              (0x00000004)
 261 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ         (0x00000008)
 262 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP         (0x00000010)
 263
 264 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN           (0x00000001)
 265
 266 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE         (0x07000000)
 267 #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE         (0x04000000)
 268 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW          (0x08000000)
 269
 270
 271 /* HW REV */
 272 #define CSR_HW_REV_TYPE_MSK            (0x00000F0)
 273 #define CSR_HW_REV_TYPE_3945           (0x00000D0)
 274 #define CSR_HW_REV_TYPE_4965           (0x0000000)
 275 #define CSR_HW_REV_TYPE_5300           (0x0000020)
 276 #define CSR_HW_REV_TYPE_5350           (0x0000030)
 277 #define CSR_HW_REV_TYPE_5100           (0x0000050)
 278 #define CSR_HW_REV_TYPE_5150           (0x0000040)
 279 #define CSR_HW_REV_TYPE_1000           (0x0000060)
 280 #define CSR_HW_REV_TYPE_6x00           (0x0000070)
 281 #define CSR_HW_REV_TYPE_6x50           (0x0000080)
 282 #define CSR_HW_REV_TYPE_6x50g2         (0x0000084)
 283 #define CSR_HW_REV_TYPE_6x00g2         (0x00000B0)
 284 #define CSR_HW_REV_TYPE_NONE           (0x00000F0)
 285
 286 /* EEPROM REG */
 287 #define CSR_EEPROM_REG_READ_VALID_MSK   (0x00000001)
 288 #define CSR_EEPROM_REG_BIT_CMD          (0x00000002)
 289 #define CSR_EEPROM_REG_MSK_ADDR         (0x0000FFFC)
 290 #define CSR_EEPROM_REG_MSK_DATA         (0xFFFF0000)
 291
 292 /* EEPROM GP */
 293 #define CSR_EEPROM_GP_VALID_MSK         (0x00000007) /* signature */
 294 #define CSR_EEPROM_GP_IF_OWNER_MSK      (0x00000180)
 295 #define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP    (0x00000000)
 296 #define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP          (0x00000001)
 297 #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K         (0x00000002)
 298 #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K         (0x00000004)
 299
 300 /* One-time-programmable memory general purpose reg */
 301 #define CSR_OTP_GP_REG_DEVICE_SELECT    (0x00010000) /* 0 - EEPROM, 1 - OTP */
 302 #define CSR_OTP_GP_REG_OTP_ACCESS_MODE  (0x00020000) /* 0 - absolute, 1 - relative */
 303 #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK          (0x00100000) /* bit 20 */
 304 #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK        (0x00200000) /* bit 21 */
 305
 306 /* GP REG */
 307 #define CSR_GP_REG_POWER_SAVE_STATUS_MSK            (0x03000000) /* bit 24/25 */
 308 #define CSR_GP_REG_NO_POWER_SAVE            (0x00000000)
 309 #define CSR_GP_REG_MAC_POWER_SAVE           (0x01000000)
 310 #define CSR_GP_REG_PHY_POWER_SAVE           (0x02000000)
 311 #define CSR_GP_REG_POWER_SAVE_ERROR         (0x03000000)
 312
 313
 314 /* CSR GIO */
 315 #define CSR_GIO_REG_VAL_L0S_ENABLED     (0x00000002)
 316
 317 /*
 318  * UCODE-DRIVER GP (general purpose) mailbox register 1
 319  * Host driver and uCode write and/or read this register to communicate with
 320  * each other.
 321  * Bit fields:
 322  *     4:  UCODE_DISABLE
 323  *         Host sets this to request permanent halt of uCode, same as
 324  *         sending CARD_STATE command with "halt" bit set.
 325  *     3:  CT_KILL_EXIT
 326  *         Host sets this to request exit from CT_KILL state, i.e. host thinks
 327  *         device temperature is low enough to continue normal operation.
 328  *     2:  CMD_BLOCKED
 329  *         Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
 330  *         to release uCode to clear all Tx and command queues, enter
 331  *         unassociated mode, and power down.
 332  *         NOTE:  Some devices also use HBUS_TARG_MBX_C register for this bit.
 333  *     1:  SW_BIT_RFKILL
 334  *         Host sets this when issuing CARD_STATE command to request
 335  *         device sleep.
 336  *     0:  MAC_SLEEP
 337  *         uCode sets this when preparing a power-saving power-down.
 338  *         uCode resets this when power-up is complete and SRAM is sane.
 339  *         NOTE:  3945/4965 saves internal SRAM data to host when powering down,
 340  *                and must restore this data after powering back up.
 341  *                MAC_SLEEP is the best indication that restore is complete.
 342  *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
 343  *                do not need to save/restore it.
 344  */
 345 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP             (0x00000001)
 346 #define CSR_UCODE_SW_BIT_RFKILL                     (0x00000002)
 347 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED           (0x00000004)
 348 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT      (0x00000008)
 349
 350 /* GP Driver */
 351 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK         (0x00000003)
 352 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB     (0x00000000)
 353 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB     (0x00000001)
 354 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA     (0x00000002)
 355 #define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6    (0x00000004)
 356
 357 /* GIO Chicken Bits (PCI Express bus link power management) */
 358 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX  (0x00800000)
 359 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER  (0x20000000)
 360
 361 /* LED */
 362 #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
 363 #define CSR_LED_REG_TRUN_ON (0x78)
 364 #define CSR_LED_REG_TRUN_OFF (0x38)
 365
 366 /* ANA_PLL */
 367 #define CSR39_ANA_PLL_CFG_VAL        (0x01000000)
 368 #define CSR50_ANA_PLL_CFG_VAL        (0x00880300)
 369
 370 /* HPET MEM debug */
 371 #define CSR_DBG_HPET_MEM_REG_VAL        (0xFFFF0000)
 372
 373 /* DRAM INT TABLE */
 374 #define CSR_DRAM_INT_TBL_ENABLE         (1 << 31)
 375 #define CSR_DRAM_INIT_TBL_WRAP_CHECK    (1 << 27)
 376
 377 /*
 378  * HBUS (Host-side Bus)
 379  *
 380  * HBUS registers are mapped directly into PCI bus space, but are used
 381  * to indirectly access device's internal memory or registers that
 382  * may be powered-down.
 383  *
 384  * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
 385  * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
 386  * to make sure the MAC (uCode processor, etc.) is powered up for accessing
 387  * internal resources.
 388  *
 389  * Do not use iwl_write32()/iwl_read32() family to access these registers;
 390  * these provide only simple PCI bus access, without waking up the MAC.
 391  */
 392 #define HBUS_BASE       (0x400)
 393
 394 /*
 395  * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
 396  * structures, error log, event log, verifying uCode load).
 397  * First write to address register, then read from or write to data register
 398  * to complete the job.  Once the address register is set up, accesses to
 399  * data registers auto-increment the address by one dword.
 400  * Bit usage for address registers (read or write):
 401  *  0-31:  memory address within device
 402  */
 403 #define HBUS_TARG_MEM_RADDR     (HBUS_BASE+0x00c)
 404 #define HBUS_TARG_MEM_WADDR     (HBUS_BASE+0x010)
 405 #define HBUS_TARG_MEM_WDAT      (HBUS_BASE+0x018)
 406 #define HBUS_TARG_MEM_RDAT      (HBUS_BASE+0x01c)
 407
 408 #define HBUS_TARG_MBX_C         (HBUS_BASE+0x030)
 409 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED         (0x00000004)
 410
 411 /*
 412  * Registers for accessing device's internal peripheral registers
 413  * (e.g. SCD, BSM, etc.).  First write to address register,
 414  * then read from or write to data register to complete the job.
 415  * Bit usage for address registers (read or write):
 416  *  0-15:  register address (offset) within device
 417  * 24-25:  (# bytes - 1) to read or write (e.g. 3 for dword)
 418  */
 419 #define HBUS_TARG_PRPH_WADDR    (HBUS_BASE+0x044)
 420 #define HBUS_TARG_PRPH_RADDR    (HBUS_BASE+0x048)
 421 #define HBUS_TARG_PRPH_WDAT     (HBUS_BASE+0x04c)
 422 #define HBUS_TARG_PRPH_RDAT     (HBUS_BASE+0x050)
 423
 424 /*
 425  * Per-Tx-queue write pointer (index, really!)
 426  * Indicates index to next TFD that driver will fill (1 past latest filled).
 427  * Bit usage:
 428  *  0-7:  queue write index
 429  * 11-8:  queue selector
 430  */
 431 #define HBUS_TARG_WRPTR         (HBUS_BASE+0x060)
 432
 433 #endif /* !__iwl_csr_h__ */