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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / wireless / b43 / main.c
blob8373094f08eb8ea571fae24d4c9dec71ee896aba
1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 SDIO support
12 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
13
14 Some parts of the code in this file are derived from the ipw2200
15 driver Copyright(c) 2003 - 2004 Intel Corporation.
16
17 This program is free software; you can redistribute it and/or modify
18 it under the terms of the GNU General Public License as published by
19 the Free Software Foundation; either version 2 of the License, or
20 (at your option) any later version.
21
22 This program is distributed in the hope that it will be useful,
23 but WITHOUT ANY WARRANTY; without even the implied warranty of
24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 GNU General Public License for more details.
26
27 You should have received a copy of the GNU General Public License
28 along with this program; see the file COPYING. If not, write to
29 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
30 Boston, MA 02110-1301, USA.
31
32 */
33
34 #include <linux/delay.h>
35 #include <linux/init.h>
36 #include <linux/moduleparam.h>
37 #include <linux/if_arp.h>
38 #include <linux/etherdevice.h>
39 #include <linux/firmware.h>
40 #include <linux/wireless.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
43 #include <linux/io.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/slab.h>
46 #include <asm/unaligned.h>
47
48 #include "b43.h"
49 #include "main.h"
50 #include "debugfs.h"
51 #include "phy_common.h"
52 #include "phy_g.h"
53 #include "phy_n.h"
54 #include "dma.h"
55 #include "pio.h"
56 #include "sysfs.h"
57 #include "xmit.h"
58 #include "lo.h"
59 #include "pcmcia.h"
60 #include "sdio.h"
61 #include <linux/mmc/sdio_func.h>
62
63 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64 MODULE_AUTHOR("Martin Langer");
65 MODULE_AUTHOR("Stefano Brivio");
66 MODULE_AUTHOR("Michael Buesch");
67 MODULE_AUTHOR("Gábor Stefanik");
68 MODULE_LICENSE("GPL");
69
70 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
71 MODULE_FIRMWARE("b43/ucode11.fw");
72 MODULE_FIRMWARE("b43/ucode13.fw");
73 MODULE_FIRMWARE("b43/ucode14.fw");
74 MODULE_FIRMWARE("b43/ucode15.fw");
75 MODULE_FIRMWARE("b43/ucode5.fw");
76 MODULE_FIRMWARE("b43/ucode9.fw");
77
78 static int modparam_bad_frames_preempt;
79 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
80 MODULE_PARM_DESC(bad_frames_preempt,
81 "enable(1) / disable(0) Bad Frames Preemption");
82
83 static char modparam_fwpostfix[16];
84 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
85 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
86
87 static int modparam_hwpctl;
88 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
89 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
90
91 static int modparam_nohwcrypt;
92 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
93 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
94
95 static int modparam_hwtkip;
96 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
97 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
98
99 static int modparam_qos = 1;
100 module_param_named(qos, modparam_qos, int, 0444);
101 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
102
103 static int modparam_btcoex = 1;
104 module_param_named(btcoex, modparam_btcoex, int, 0444);
105 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
106
107 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
108 module_param_named(verbose, b43_modparam_verbose, int, 0644);
109 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
110
111 static int b43_modparam_pio = B43_PIO_DEFAULT;
112 module_param_named(pio, b43_modparam_pio, int, 0644);
113 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
114
115 static const struct ssb_device_id b43_ssb_tbl[] = {
116 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
117 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
118 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
119 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
120 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
121 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
122 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
123 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
124 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
125 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
126 SSB_DEVTABLE_END
127 };
128
129 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
130
131 /* Channel and ratetables are shared for all devices.
132 * They can't be const, because ieee80211 puts some precalculated
133 * data in there. This data is the same for all devices, so we don't
134 * get concurrency issues */
135 #define RATETAB_ENT(_rateid, _flags) \
136 { \
137 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
138 .hw_value = (_rateid), \
139 .flags = (_flags), \
140 }
141
142 /*
143 * NOTE: When changing this, sync with xmit.c's
144 * b43_plcp_get_bitrate_idx_* functions!
145 */
146 static struct ieee80211_rate __b43_ratetable[] = {
147 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
148 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
149 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
150 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
151 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
152 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
153 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
154 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
155 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
156 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
157 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
158 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
159 };
160
161 #define b43_a_ratetable (__b43_ratetable + 4)
162 #define b43_a_ratetable_size 8
163 #define b43_b_ratetable (__b43_ratetable + 0)
164 #define b43_b_ratetable_size 4
165 #define b43_g_ratetable (__b43_ratetable + 0)
166 #define b43_g_ratetable_size 12
167
168 #define CHAN4G(_channel, _freq, _flags) { \
169 .band = IEEE80211_BAND_2GHZ, \
170 .center_freq = (_freq), \
171 .hw_value = (_channel), \
172 .flags = (_flags), \
173 .max_antenna_gain = 0, \
174 .max_power = 30, \
175 }
176 static struct ieee80211_channel b43_2ghz_chantable[] = {
177 CHAN4G(1, 2412, 0),
178 CHAN4G(2, 2417, 0),
179 CHAN4G(3, 2422, 0),
180 CHAN4G(4, 2427, 0),
181 CHAN4G(5, 2432, 0),
182 CHAN4G(6, 2437, 0),
183 CHAN4G(7, 2442, 0),
184 CHAN4G(8, 2447, 0),
185 CHAN4G(9, 2452, 0),
186 CHAN4G(10, 2457, 0),
187 CHAN4G(11, 2462, 0),
188 CHAN4G(12, 2467, 0),
189 CHAN4G(13, 2472, 0),
190 CHAN4G(14, 2484, 0),
191 };
192 #undef CHAN4G
193
194 #define CHAN5G(_channel, _flags) { \
195 .band = IEEE80211_BAND_5GHZ, \
196 .center_freq = 5000 + (5 * (_channel)), \
197 .hw_value = (_channel), \
198 .flags = (_flags), \
199 .max_antenna_gain = 0, \
200 .max_power = 30, \
201 }
202 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
203 CHAN5G(32, 0), CHAN5G(34, 0),
204 CHAN5G(36, 0), CHAN5G(38, 0),
205 CHAN5G(40, 0), CHAN5G(42, 0),
206 CHAN5G(44, 0), CHAN5G(46, 0),
207 CHAN5G(48, 0), CHAN5G(50, 0),
208 CHAN5G(52, 0), CHAN5G(54, 0),
209 CHAN5G(56, 0), CHAN5G(58, 0),
210 CHAN5G(60, 0), CHAN5G(62, 0),
211 CHAN5G(64, 0), CHAN5G(66, 0),
212 CHAN5G(68, 0), CHAN5G(70, 0),
213 CHAN5G(72, 0), CHAN5G(74, 0),
214 CHAN5G(76, 0), CHAN5G(78, 0),
215 CHAN5G(80, 0), CHAN5G(82, 0),
216 CHAN5G(84, 0), CHAN5G(86, 0),
217 CHAN5G(88, 0), CHAN5G(90, 0),
218 CHAN5G(92, 0), CHAN5G(94, 0),
219 CHAN5G(96, 0), CHAN5G(98, 0),
220 CHAN5G(100, 0), CHAN5G(102, 0),
221 CHAN5G(104, 0), CHAN5G(106, 0),
222 CHAN5G(108, 0), CHAN5G(110, 0),
223 CHAN5G(112, 0), CHAN5G(114, 0),
224 CHAN5G(116, 0), CHAN5G(118, 0),
225 CHAN5G(120, 0), CHAN5G(122, 0),
226 CHAN5G(124, 0), CHAN5G(126, 0),
227 CHAN5G(128, 0), CHAN5G(130, 0),
228 CHAN5G(132, 0), CHAN5G(134, 0),
229 CHAN5G(136, 0), CHAN5G(138, 0),
230 CHAN5G(140, 0), CHAN5G(142, 0),
231 CHAN5G(144, 0), CHAN5G(145, 0),
232 CHAN5G(146, 0), CHAN5G(147, 0),
233 CHAN5G(148, 0), CHAN5G(149, 0),
234 CHAN5G(150, 0), CHAN5G(151, 0),
235 CHAN5G(152, 0), CHAN5G(153, 0),
236 CHAN5G(154, 0), CHAN5G(155, 0),
237 CHAN5G(156, 0), CHAN5G(157, 0),
238 CHAN5G(158, 0), CHAN5G(159, 0),
239 CHAN5G(160, 0), CHAN5G(161, 0),
240 CHAN5G(162, 0), CHAN5G(163, 0),
241 CHAN5G(164, 0), CHAN5G(165, 0),
242 CHAN5G(166, 0), CHAN5G(168, 0),
243 CHAN5G(170, 0), CHAN5G(172, 0),
244 CHAN5G(174, 0), CHAN5G(176, 0),
245 CHAN5G(178, 0), CHAN5G(180, 0),
246 CHAN5G(182, 0), CHAN5G(184, 0),
247 CHAN5G(186, 0), CHAN5G(188, 0),
248 CHAN5G(190, 0), CHAN5G(192, 0),
249 CHAN5G(194, 0), CHAN5G(196, 0),
250 CHAN5G(198, 0), CHAN5G(200, 0),
251 CHAN5G(202, 0), CHAN5G(204, 0),
252 CHAN5G(206, 0), CHAN5G(208, 0),
253 CHAN5G(210, 0), CHAN5G(212, 0),
254 CHAN5G(214, 0), CHAN5G(216, 0),
255 CHAN5G(218, 0), CHAN5G(220, 0),
256 CHAN5G(222, 0), CHAN5G(224, 0),
257 CHAN5G(226, 0), CHAN5G(228, 0),
258 };
259
260 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
261 CHAN5G(34, 0), CHAN5G(36, 0),
262 CHAN5G(38, 0), CHAN5G(40, 0),
263 CHAN5G(42, 0), CHAN5G(44, 0),
264 CHAN5G(46, 0), CHAN5G(48, 0),
265 CHAN5G(52, 0), CHAN5G(56, 0),
266 CHAN5G(60, 0), CHAN5G(64, 0),
267 CHAN5G(100, 0), CHAN5G(104, 0),
268 CHAN5G(108, 0), CHAN5G(112, 0),
269 CHAN5G(116, 0), CHAN5G(120, 0),
270 CHAN5G(124, 0), CHAN5G(128, 0),
271 CHAN5G(132, 0), CHAN5G(136, 0),
272 CHAN5G(140, 0), CHAN5G(149, 0),
273 CHAN5G(153, 0), CHAN5G(157, 0),
274 CHAN5G(161, 0), CHAN5G(165, 0),
275 CHAN5G(184, 0), CHAN5G(188, 0),
276 CHAN5G(192, 0), CHAN5G(196, 0),
277 CHAN5G(200, 0), CHAN5G(204, 0),
278 CHAN5G(208, 0), CHAN5G(212, 0),
279 CHAN5G(216, 0),
280 };
281 #undef CHAN5G
282
283 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
284 .band = IEEE80211_BAND_5GHZ,
285 .channels = b43_5ghz_nphy_chantable,
286 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
287 .bitrates = b43_a_ratetable,
288 .n_bitrates = b43_a_ratetable_size,
289 };
290
291 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
292 .band = IEEE80211_BAND_5GHZ,
293 .channels = b43_5ghz_aphy_chantable,
294 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
295 .bitrates = b43_a_ratetable,
296 .n_bitrates = b43_a_ratetable_size,
297 };
298
299 static struct ieee80211_supported_band b43_band_2GHz = {
300 .band = IEEE80211_BAND_2GHZ,
301 .channels = b43_2ghz_chantable,
302 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
303 .bitrates = b43_g_ratetable,
304 .n_bitrates = b43_g_ratetable_size,
305 };
306
307 static void b43_wireless_core_exit(struct b43_wldev *dev);
308 static int b43_wireless_core_init(struct b43_wldev *dev);
309 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
310 static int b43_wireless_core_start(struct b43_wldev *dev);
311
312 static int b43_ratelimit(struct b43_wl *wl)
313 {
314 if (!wl || !wl->current_dev)
315 return 1;
316 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
317 return 1;
318 /* We are up and running.
319 * Ratelimit the messages to avoid DoS over the net. */
320 return net_ratelimit();
321 }
322
323 void b43info(struct b43_wl *wl, const char *fmt, ...)
324 {
325 va_list args;
326
327 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
328 return;
329 if (!b43_ratelimit(wl))
330 return;
331 va_start(args, fmt);
332 printk(KERN_INFO "b43-%s: ",
333 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
334 vprintk(fmt, args);
335 va_end(args);
336 }
337
338 void b43err(struct b43_wl *wl, const char *fmt, ...)
339 {
340 va_list args;
341
342 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
343 return;
344 if (!b43_ratelimit(wl))
345 return;
346 va_start(args, fmt);
347 printk(KERN_ERR "b43-%s ERROR: ",
348 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
349 vprintk(fmt, args);
350 va_end(args);
351 }
352
353 void b43warn(struct b43_wl *wl, const char *fmt, ...)
354 {
355 va_list args;
356
357 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
358 return;
359 if (!b43_ratelimit(wl))
360 return;
361 va_start(args, fmt);
362 printk(KERN_WARNING "b43-%s warning: ",
363 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
364 vprintk(fmt, args);
365 va_end(args);
366 }
367
368 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
369 {
370 va_list args;
371
372 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
373 return;
374 va_start(args, fmt);
375 printk(KERN_DEBUG "b43-%s debug: ",
376 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
377 vprintk(fmt, args);
378 va_end(args);
379 }
380
381 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
382 {
383 u32 macctl;
384
385 B43_WARN_ON(offset % 4 != 0);
386
387 macctl = b43_read32(dev, B43_MMIO_MACCTL);
388 if (macctl & B43_MACCTL_BE)
389 val = swab32(val);
390
391 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
392 mmiowb();
393 b43_write32(dev, B43_MMIO_RAM_DATA, val);
394 }
395
396 static inline void b43_shm_control_word(struct b43_wldev *dev,
397 u16 routing, u16 offset)
398 {
399 u32 control;
400
401 /* "offset" is the WORD offset. */
402 control = routing;
403 control <<= 16;
404 control |= offset;
405 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
406 }
407
408 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
409 {
410 u32 ret;
411
412 if (routing == B43_SHM_SHARED) {
413 B43_WARN_ON(offset & 0x0001);
414 if (offset & 0x0003) {
415 /* Unaligned access */
416 b43_shm_control_word(dev, routing, offset >> 2);
417 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
418 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
419 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
420
421 goto out;
422 }
423 offset >>= 2;
424 }
425 b43_shm_control_word(dev, routing, offset);
426 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
427 out:
428 return ret;
429 }
430
431 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
432 {
433 u16 ret;
434
435 if (routing == B43_SHM_SHARED) {
436 B43_WARN_ON(offset & 0x0001);
437 if (offset & 0x0003) {
438 /* Unaligned access */
439 b43_shm_control_word(dev, routing, offset >> 2);
440 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
441
442 goto out;
443 }
444 offset >>= 2;
445 }
446 b43_shm_control_word(dev, routing, offset);
447 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
448 out:
449 return ret;
450 }
451
452 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
453 {
454 if (routing == B43_SHM_SHARED) {
455 B43_WARN_ON(offset & 0x0001);
456 if (offset & 0x0003) {
457 /* Unaligned access */
458 b43_shm_control_word(dev, routing, offset >> 2);
459 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
460 value & 0xFFFF);
461 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
462 b43_write16(dev, B43_MMIO_SHM_DATA,
463 (value >> 16) & 0xFFFF);
464 return;
465 }
466 offset >>= 2;
467 }
468 b43_shm_control_word(dev, routing, offset);
469 b43_write32(dev, B43_MMIO_SHM_DATA, value);
470 }
471
472 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
473 {
474 if (routing == B43_SHM_SHARED) {
475 B43_WARN_ON(offset & 0x0001);
476 if (offset & 0x0003) {
477 /* Unaligned access */
478 b43_shm_control_word(dev, routing, offset >> 2);
479 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
480 return;
481 }
482 offset >>= 2;
483 }
484 b43_shm_control_word(dev, routing, offset);
485 b43_write16(dev, B43_MMIO_SHM_DATA, value);
486 }
487
488 /* Read HostFlags */
489 u64 b43_hf_read(struct b43_wldev *dev)
490 {
491 u64 ret;
492
493 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
494 ret <<= 16;
495 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
496 ret <<= 16;
497 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
498
499 return ret;
500 }
501
502 /* Write HostFlags */
503 void b43_hf_write(struct b43_wldev *dev, u64 value)
504 {
505 u16 lo, mi, hi;
506
507 lo = (value & 0x00000000FFFFULL);
508 mi = (value & 0x0000FFFF0000ULL) >> 16;
509 hi = (value & 0xFFFF00000000ULL) >> 32;
510 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
511 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
512 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
513 }
514
515 /* Read the firmware capabilities bitmask (Opensource firmware only) */
516 static u16 b43_fwcapa_read(struct b43_wldev *dev)
517 {
518 B43_WARN_ON(!dev->fw.opensource);
519 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
520 }
521
522 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
523 {
524 u32 low, high;
525
526 B43_WARN_ON(dev->dev->id.revision < 3);
527
528 /* The hardware guarantees us an atomic read, if we
529 * read the low register first. */
530 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
531 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
532
533 *tsf = high;
534 *tsf <<= 32;
535 *tsf |= low;
536 }
537
538 static void b43_time_lock(struct b43_wldev *dev)
539 {
540 u32 macctl;
541
542 macctl = b43_read32(dev, B43_MMIO_MACCTL);
543 macctl |= B43_MACCTL_TBTTHOLD;
544 b43_write32(dev, B43_MMIO_MACCTL, macctl);
545 /* Commit the write */
546 b43_read32(dev, B43_MMIO_MACCTL);
547 }
548
549 static void b43_time_unlock(struct b43_wldev *dev)
550 {
551 u32 macctl;
552
553 macctl = b43_read32(dev, B43_MMIO_MACCTL);
554 macctl &= ~B43_MACCTL_TBTTHOLD;
555 b43_write32(dev, B43_MMIO_MACCTL, macctl);
556 /* Commit the write */
557 b43_read32(dev, B43_MMIO_MACCTL);
558 }
559
560 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
561 {
562 u32 low, high;
563
564 B43_WARN_ON(dev->dev->id.revision < 3);
565
566 low = tsf;
567 high = (tsf >> 32);
568 /* The hardware guarantees us an atomic write, if we
569 * write the low register first. */
570 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
571 mmiowb();
572 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
573 mmiowb();
574 }
575
576 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
577 {
578 b43_time_lock(dev);
579 b43_tsf_write_locked(dev, tsf);
580 b43_time_unlock(dev);
581 }
582
583 static
584 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
585 {
586 static const u8 zero_addr[ETH_ALEN] = { 0 };
587 u16 data;
588
589 if (!mac)
590 mac = zero_addr;
591
592 offset |= 0x0020;
593 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
594
595 data = mac[0];
596 data |= mac[1] << 8;
597 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
598 data = mac[2];
599 data |= mac[3] << 8;
600 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
601 data = mac[4];
602 data |= mac[5] << 8;
603 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
604 }
605
606 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
607 {
608 const u8 *mac;
609 const u8 *bssid;
610 u8 mac_bssid[ETH_ALEN * 2];
611 int i;
612 u32 tmp;
613
614 bssid = dev->wl->bssid;
615 mac = dev->wl->mac_addr;
616
617 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
618
619 memcpy(mac_bssid, mac, ETH_ALEN);
620 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
621
622 /* Write our MAC address and BSSID to template ram */
623 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
624 tmp = (u32) (mac_bssid[i + 0]);
625 tmp |= (u32) (mac_bssid[i + 1]) << 8;
626 tmp |= (u32) (mac_bssid[i + 2]) << 16;
627 tmp |= (u32) (mac_bssid[i + 3]) << 24;
628 b43_ram_write(dev, 0x20 + i, tmp);
629 }
630 }
631
632 static void b43_upload_card_macaddress(struct b43_wldev *dev)
633 {
634 b43_write_mac_bssid_templates(dev);
635 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
636 }
637
638 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
639 {
640 /* slot_time is in usec. */
641 /* This test used to exit for all but a G PHY. */
642 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
643 return;
644 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
645 /* Shared memory location 0x0010 is the slot time and should be
646 * set to slot_time; however, this register is initially 0 and changing
647 * the value adversely affects the transmit rate for BCM4311
648 * devices. Until this behavior is unterstood, delete this step
649 *
650 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
651 */
652 }
653
654 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
655 {
656 b43_set_slot_time(dev, 9);
657 }
658
659 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
660 {
661 b43_set_slot_time(dev, 20);
662 }
663
664 /* DummyTransmission function, as documented on
665 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
666 */
667 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
668 {
669 struct b43_phy *phy = &dev->phy;
670 unsigned int i, max_loop;
671 u16 value;
672 u32 buffer[5] = {
673 0x00000000,
674 0x00D40000,
675 0x00000000,
676 0x01000000,
677 0x00000000,
678 };
679
680 if (ofdm) {
681 max_loop = 0x1E;
682 buffer[0] = 0x000201CC;
683 } else {
684 max_loop = 0xFA;
685 buffer[0] = 0x000B846E;
686 }
687
688 for (i = 0; i < 5; i++)
689 b43_ram_write(dev, i * 4, buffer[i]);
690
691 b43_write16(dev, 0x0568, 0x0000);
692 if (dev->dev->id.revision < 11)
693 b43_write16(dev, 0x07C0, 0x0000);
694 else
695 b43_write16(dev, 0x07C0, 0x0100);
696 value = (ofdm ? 0x41 : 0x40);
697 b43_write16(dev, 0x050C, value);
698 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
699 b43_write16(dev, 0x0514, 0x1A02);
700 b43_write16(dev, 0x0508, 0x0000);
701 b43_write16(dev, 0x050A, 0x0000);
702 b43_write16(dev, 0x054C, 0x0000);
703 b43_write16(dev, 0x056A, 0x0014);
704 b43_write16(dev, 0x0568, 0x0826);
705 b43_write16(dev, 0x0500, 0x0000);
706 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
707 //SPEC TODO
708 }
709
710 switch (phy->type) {
711 case B43_PHYTYPE_N:
712 b43_write16(dev, 0x0502, 0x00D0);
713 break;
714 case B43_PHYTYPE_LP:
715 b43_write16(dev, 0x0502, 0x0050);
716 break;
717 default:
718 b43_write16(dev, 0x0502, 0x0030);
719 }
720
721 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
722 b43_radio_write16(dev, 0x0051, 0x0017);
723 for (i = 0x00; i < max_loop; i++) {
724 value = b43_read16(dev, 0x050E);
725 if (value & 0x0080)
726 break;
727 udelay(10);
728 }
729 for (i = 0x00; i < 0x0A; i++) {
730 value = b43_read16(dev, 0x050E);
731 if (value & 0x0400)
732 break;
733 udelay(10);
734 }
735 for (i = 0x00; i < 0x19; i++) {
736 value = b43_read16(dev, 0x0690);
737 if (!(value & 0x0100))
738 break;
739 udelay(10);
740 }
741 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
742 b43_radio_write16(dev, 0x0051, 0x0037);
743 }
744
745 static void key_write(struct b43_wldev *dev,
746 u8 index, u8 algorithm, const u8 *key)
747 {
748 unsigned int i;
749 u32 offset;
750 u16 value;
751 u16 kidx;
752
753 /* Key index/algo block */
754 kidx = b43_kidx_to_fw(dev, index);
755 value = ((kidx << 4) | algorithm);
756 b43_shm_write16(dev, B43_SHM_SHARED,
757 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
758
759 /* Write the key to the Key Table Pointer offset */
760 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
761 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
762 value = key[i];
763 value |= (u16) (key[i + 1]) << 8;
764 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
765 }
766 }
767
768 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
769 {
770 u32 addrtmp[2] = { 0, 0, };
771 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
772
773 if (b43_new_kidx_api(dev))
774 pairwise_keys_start = B43_NR_GROUP_KEYS;
775
776 B43_WARN_ON(index < pairwise_keys_start);
777 /* We have four default TX keys and possibly four default RX keys.
778 * Physical mac 0 is mapped to physical key 4 or 8, depending
779 * on the firmware version.
780 * So we must adjust the index here.
781 */
782 index -= pairwise_keys_start;
783 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
784
785 if (addr) {
786 addrtmp[0] = addr[0];
787 addrtmp[0] |= ((u32) (addr[1]) << 8);
788 addrtmp[0] |= ((u32) (addr[2]) << 16);
789 addrtmp[0] |= ((u32) (addr[3]) << 24);
790 addrtmp[1] = addr[4];
791 addrtmp[1] |= ((u32) (addr[5]) << 8);
792 }
793
794 /* Receive match transmitter address (RCMTA) mechanism */
795 b43_shm_write32(dev, B43_SHM_RCMTA,
796 (index * 2) + 0, addrtmp[0]);
797 b43_shm_write16(dev, B43_SHM_RCMTA,
798 (index * 2) + 1, addrtmp[1]);
799 }
800
801 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
802 * When a packet is received, the iv32 is checked.
803 * - if it doesn't the packet is returned without modification (and software
804 * decryption can be done). That's what happen when iv16 wrap.
805 * - if it does, the rc4 key is computed, and decryption is tried.
806 * Either it will success and B43_RX_MAC_DEC is returned,
807 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
808 * and the packet is not usable (it got modified by the ucode).
809 * So in order to never have B43_RX_MAC_DECERR, we should provide
810 * a iv32 and phase1key that match. Because we drop packets in case of
811 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
812 * packets will be lost without higher layer knowing (ie no resync possible
813 * until next wrap).
814 *
815 * NOTE : this should support 50 key like RCMTA because
816 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
817 */
818 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
819 u16 *phase1key)
820 {
821 unsigned int i;
822 u32 offset;
823 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
824
825 if (!modparam_hwtkip)
826 return;
827
828 if (b43_new_kidx_api(dev))
829 pairwise_keys_start = B43_NR_GROUP_KEYS;
830
831 B43_WARN_ON(index < pairwise_keys_start);
832 /* We have four default TX keys and possibly four default RX keys.
833 * Physical mac 0 is mapped to physical key 4 or 8, depending
834 * on the firmware version.
835 * So we must adjust the index here.
836 */
837 index -= pairwise_keys_start;
838 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
839
840 if (b43_debug(dev, B43_DBG_KEYS)) {
841 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
842 index, iv32);
843 }
844 /* Write the key to the RX tkip shared mem */
845 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
846 for (i = 0; i < 10; i += 2) {
847 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
848 phase1key ? phase1key[i / 2] : 0);
849 }
850 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
851 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
852 }
853
854 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
855 struct ieee80211_vif *vif,
856 struct ieee80211_key_conf *keyconf,
857 struct ieee80211_sta *sta,
858 u32 iv32, u16 *phase1key)
859 {
860 struct b43_wl *wl = hw_to_b43_wl(hw);
861 struct b43_wldev *dev;
862 int index = keyconf->hw_key_idx;
863
864 if (B43_WARN_ON(!modparam_hwtkip))
865 return;
866
867 /* This is only called from the RX path through mac80211, where
868 * our mutex is already locked. */
869 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
870 dev = wl->current_dev;
871 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
872
873 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
874
875 rx_tkip_phase1_write(dev, index, iv32, phase1key);
876 /* only pairwise TKIP keys are supported right now */
877 if (WARN_ON(!sta))
878 return;
879 keymac_write(dev, index, sta->addr);
880 }
881
882 static void do_key_write(struct b43_wldev *dev,
883 u8 index, u8 algorithm,
884 const u8 *key, size_t key_len, const u8 *mac_addr)
885 {
886 u8 buf[B43_SEC_KEYSIZE] = { 0, };
887 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
888
889 if (b43_new_kidx_api(dev))
890 pairwise_keys_start = B43_NR_GROUP_KEYS;
891
892 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
893 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
894
895 if (index >= pairwise_keys_start)
896 keymac_write(dev, index, NULL); /* First zero out mac. */
897 if (algorithm == B43_SEC_ALGO_TKIP) {
898 /*
899 * We should provide an initial iv32, phase1key pair.
900 * We could start with iv32=0 and compute the corresponding
901 * phase1key, but this means calling ieee80211_get_tkip_key
902 * with a fake skb (or export other tkip function).
903 * Because we are lazy we hope iv32 won't start with
904 * 0xffffffff and let's b43_op_update_tkip_key provide a
905 * correct pair.
906 */
907 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
908 } else if (index >= pairwise_keys_start) /* clear it */
909 rx_tkip_phase1_write(dev, index, 0, NULL);
910 if (key)
911 memcpy(buf, key, key_len);
912 key_write(dev, index, algorithm, buf);
913 if (index >= pairwise_keys_start)
914 keymac_write(dev, index, mac_addr);
915
916 dev->key[index].algorithm = algorithm;
917 }
918
919 static int b43_key_write(struct b43_wldev *dev,
920 int index, u8 algorithm,
921 const u8 *key, size_t key_len,
922 const u8 *mac_addr,
923 struct ieee80211_key_conf *keyconf)
924 {
925 int i;
926 int pairwise_keys_start;
927
928 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
929 * - Temporal Encryption Key (128 bits)
930 * - Temporal Authenticator Tx MIC Key (64 bits)
931 * - Temporal Authenticator Rx MIC Key (64 bits)
932 *
933 * Hardware only store TEK
934 */
935 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
936 key_len = 16;
937 if (key_len > B43_SEC_KEYSIZE)
938 return -EINVAL;
939 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
940 /* Check that we don't already have this key. */
941 B43_WARN_ON(dev->key[i].keyconf == keyconf);
942 }
943 if (index < 0) {
944 /* Pairwise key. Get an empty slot for the key. */
945 if (b43_new_kidx_api(dev))
946 pairwise_keys_start = B43_NR_GROUP_KEYS;
947 else
948 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
949 for (i = pairwise_keys_start;
950 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
951 i++) {
952 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
953 if (!dev->key[i].keyconf) {
954 /* found empty */
955 index = i;
956 break;
957 }
958 }
959 if (index < 0) {
960 b43warn(dev->wl, "Out of hardware key memory\n");
961 return -ENOSPC;
962 }
963 } else
964 B43_WARN_ON(index > 3);
965
966 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
967 if ((index <= 3) && !b43_new_kidx_api(dev)) {
968 /* Default RX key */
969 B43_WARN_ON(mac_addr);
970 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
971 }
972 keyconf->hw_key_idx = index;
973 dev->key[index].keyconf = keyconf;
974
975 return 0;
976 }
977
978 static int b43_key_clear(struct b43_wldev *dev, int index)
979 {
980 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
981 return -EINVAL;
982 do_key_write(dev, index, B43_SEC_ALGO_NONE,
983 NULL, B43_SEC_KEYSIZE, NULL);
984 if ((index <= 3) && !b43_new_kidx_api(dev)) {
985 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
986 NULL, B43_SEC_KEYSIZE, NULL);
987 }
988 dev->key[index].keyconf = NULL;
989
990 return 0;
991 }
992
993 static void b43_clear_keys(struct b43_wldev *dev)
994 {
995 int i, count;
996
997 if (b43_new_kidx_api(dev))
998 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
999 else
1000 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1001 for (i = 0; i < count; i++)
1002 b43_key_clear(dev, i);
1003 }
1004
1005 static void b43_dump_keymemory(struct b43_wldev *dev)
1006 {
1007 unsigned int i, index, count, offset, pairwise_keys_start;
1008 u8 mac[ETH_ALEN];
1009 u16 algo;
1010 u32 rcmta0;
1011 u16 rcmta1;
1012 u64 hf;
1013 struct b43_key *key;
1014
1015 if (!b43_debug(dev, B43_DBG_KEYS))
1016 return;
1017
1018 hf = b43_hf_read(dev);
1019 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1020 !!(hf & B43_HF_USEDEFKEYS));
1021 if (b43_new_kidx_api(dev)) {
1022 pairwise_keys_start = B43_NR_GROUP_KEYS;
1023 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1024 } else {
1025 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1026 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1027 }
1028 for (index = 0; index < count; index++) {
1029 key = &(dev->key[index]);
1030 printk(KERN_DEBUG "Key slot %02u: %s",
1031 index, (key->keyconf == NULL) ? " " : "*");
1032 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1033 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1034 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1035 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1036 }
1037
1038 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1039 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1040 printk(" Algo: %04X/%02X", algo, key->algorithm);
1041
1042 if (index >= pairwise_keys_start) {
1043 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1044 printk(" TKIP: ");
1045 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1046 for (i = 0; i < 14; i += 2) {
1047 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1048 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1049 }
1050 }
1051 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1052 ((index - pairwise_keys_start) * 2) + 0);
1053 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1054 ((index - pairwise_keys_start) * 2) + 1);
1055 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1056 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1057 printk(" MAC: %pM", mac);
1058 } else
1059 printk(" DEFAULT KEY");
1060 printk("\n");
1061 }
1062 }
1063
1064 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1065 {
1066 u32 macctl;
1067 u16 ucstat;
1068 bool hwps;
1069 bool awake;
1070 int i;
1071
1072 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1073 (ps_flags & B43_PS_DISABLED));
1074 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1075
1076 if (ps_flags & B43_PS_ENABLED) {
1077 hwps = 1;
1078 } else if (ps_flags & B43_PS_DISABLED) {
1079 hwps = 0;
1080 } else {
1081 // and thus is not an AP and we are associated, set bit 25
1082 }
1083 if (ps_flags & B43_PS_AWAKE) {
1084 awake = 1;
1085 } else if (ps_flags & B43_PS_ASLEEP) {
1086 awake = 0;
1087 } else {
1088 // successful, set bit26
1089 }
1090
1091 hwps = 0;
1092 awake = 1;
1093
1094 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1095 if (hwps)
1096 macctl |= B43_MACCTL_HWPS;
1097 else
1098 macctl &= ~B43_MACCTL_HWPS;
1099 if (awake)
1100 macctl |= B43_MACCTL_AWAKE;
1101 else
1102 macctl &= ~B43_MACCTL_AWAKE;
1103 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1104 /* Commit write */
1105 b43_read32(dev, B43_MMIO_MACCTL);
1106 if (awake && dev->dev->id.revision >= 5) {
1107 /* Wait for the microcode to wake up. */
1108 for (i = 0; i < 100; i++) {
1109 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1110 B43_SHM_SH_UCODESTAT);
1111 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1112 break;
1113 udelay(10);
1114 }
1115 }
1116 }
1117
1118 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1119 {
1120 u32 tmslow;
1121 u32 macctl;
1122
1123 flags |= B43_TMSLOW_PHYCLKEN;
1124 flags |= B43_TMSLOW_PHYRESET;
1125 ssb_device_enable(dev->dev, flags);
1126 msleep(2); /* Wait for the PLL to turn on. */
1127
1128 /* Now take the PHY out of Reset again */
1129 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1130 tmslow |= SSB_TMSLOW_FGC;
1131 tmslow &= ~B43_TMSLOW_PHYRESET;
1132 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1133 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1134 msleep(1);
1135 tmslow &= ~SSB_TMSLOW_FGC;
1136 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1137 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1138 msleep(1);
1139
1140 /* Turn Analog ON, but only if we already know the PHY-type.
1141 * This protects against very early setup where we don't know the
1142 * PHY-type, yet. wireless_core_reset will be called once again later,
1143 * when we know the PHY-type. */
1144 if (dev->phy.ops)
1145 dev->phy.ops->switch_analog(dev, 1);
1146
1147 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1148 macctl &= ~B43_MACCTL_GMODE;
1149 if (flags & B43_TMSLOW_GMODE)
1150 macctl |= B43_MACCTL_GMODE;
1151 macctl |= B43_MACCTL_IHR_ENABLED;
1152 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1153 }
1154
1155 static void handle_irq_transmit_status(struct b43_wldev *dev)
1156 {
1157 u32 v0, v1;
1158 u16 tmp;
1159 struct b43_txstatus stat;
1160
1161 while (1) {
1162 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1163 if (!(v0 & 0x00000001))
1164 break;
1165 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1166
1167 stat.cookie = (v0 >> 16);
1168 stat.seq = (v1 & 0x0000FFFF);
1169 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1170 tmp = (v0 & 0x0000FFFF);
1171 stat.frame_count = ((tmp & 0xF000) >> 12);
1172 stat.rts_count = ((tmp & 0x0F00) >> 8);
1173 stat.supp_reason = ((tmp & 0x001C) >> 2);
1174 stat.pm_indicated = !!(tmp & 0x0080);
1175 stat.intermediate = !!(tmp & 0x0040);
1176 stat.for_ampdu = !!(tmp & 0x0020);
1177 stat.acked = !!(tmp & 0x0002);
1178
1179 b43_handle_txstatus(dev, &stat);
1180 }
1181 }
1182
1183 static void drain_txstatus_queue(struct b43_wldev *dev)
1184 {
1185 u32 dummy;
1186
1187 if (dev->dev->id.revision < 5)
1188 return;
1189 /* Read all entries from the microcode TXstatus FIFO
1190 * and throw them away.
1191 */
1192 while (1) {
1193 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1194 if (!(dummy & 0x00000001))
1195 break;
1196 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1197 }
1198 }
1199
1200 static u32 b43_jssi_read(struct b43_wldev *dev)
1201 {
1202 u32 val = 0;
1203
1204 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1205 val <<= 16;
1206 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1207
1208 return val;
1209 }
1210
1211 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1212 {
1213 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1214 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1215 }
1216
1217 static void b43_generate_noise_sample(struct b43_wldev *dev)
1218 {
1219 b43_jssi_write(dev, 0x7F7F7F7F);
1220 b43_write32(dev, B43_MMIO_MACCMD,
1221 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1222 }
1223
1224 static void b43_calculate_link_quality(struct b43_wldev *dev)
1225 {
1226 /* Top half of Link Quality calculation. */
1227
1228 if (dev->phy.type != B43_PHYTYPE_G)
1229 return;
1230 if (dev->noisecalc.calculation_running)
1231 return;
1232 dev->noisecalc.calculation_running = 1;
1233 dev->noisecalc.nr_samples = 0;
1234
1235 b43_generate_noise_sample(dev);
1236 }
1237
1238 static void handle_irq_noise(struct b43_wldev *dev)
1239 {
1240 struct b43_phy_g *phy = dev->phy.g;
1241 u16 tmp;
1242 u8 noise[4];
1243 u8 i, j;
1244 s32 average;
1245
1246 /* Bottom half of Link Quality calculation. */
1247
1248 if (dev->phy.type != B43_PHYTYPE_G)
1249 return;
1250
1251 /* Possible race condition: It might be possible that the user
1252 * changed to a different channel in the meantime since we
1253 * started the calculation. We ignore that fact, since it's
1254 * not really that much of a problem. The background noise is
1255 * an estimation only anyway. Slightly wrong results will get damped
1256 * by the averaging of the 8 sample rounds. Additionally the
1257 * value is shortlived. So it will be replaced by the next noise
1258 * calculation round soon. */
1259
1260 B43_WARN_ON(!dev->noisecalc.calculation_running);
1261 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1262 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1263 noise[2] == 0x7F || noise[3] == 0x7F)
1264 goto generate_new;
1265
1266 /* Get the noise samples. */
1267 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1268 i = dev->noisecalc.nr_samples;
1269 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1270 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1271 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1272 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1273 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1274 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1275 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1276 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1277 dev->noisecalc.nr_samples++;
1278 if (dev->noisecalc.nr_samples == 8) {
1279 /* Calculate the Link Quality by the noise samples. */
1280 average = 0;
1281 for (i = 0; i < 8; i++) {
1282 for (j = 0; j < 4; j++)
1283 average += dev->noisecalc.samples[i][j];
1284 }
1285 average /= (8 * 4);
1286 average *= 125;
1287 average += 64;
1288 average /= 128;
1289 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1290 tmp = (tmp / 128) & 0x1F;
1291 if (tmp >= 8)
1292 average += 2;
1293 else
1294 average -= 25;
1295 if (tmp == 8)
1296 average -= 72;
1297 else
1298 average -= 48;
1299
1300 dev->stats.link_noise = average;
1301 dev->noisecalc.calculation_running = 0;
1302 return;
1303 }
1304 generate_new:
1305 b43_generate_noise_sample(dev);
1306 }
1307
1308 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1309 {
1310 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1311 ///TODO: PS TBTT
1312 } else {
1313 if (1 )
1314 b43_power_saving_ctl_bits(dev, 0);
1315 }
1316 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1317 dev->dfq_valid = 1;
1318 }
1319
1320 static void handle_irq_atim_end(struct b43_wldev *dev)
1321 {
1322 if (dev->dfq_valid) {
1323 b43_write32(dev, B43_MMIO_MACCMD,
1324 b43_read32(dev, B43_MMIO_MACCMD)
1325 | B43_MACCMD_DFQ_VALID);
1326 dev->dfq_valid = 0;
1327 }
1328 }
1329
1330 static void handle_irq_pmq(struct b43_wldev *dev)
1331 {
1332 u32 tmp;
1333
1334 //TODO: AP mode.
1335
1336 while (1) {
1337 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1338 if (!(tmp & 0x00000008))
1339 break;
1340 }
1341 /* 16bit write is odd, but correct. */
1342 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1343 }
1344
1345 static void b43_write_template_common(struct b43_wldev *dev,
1346 const u8 *data, u16 size,
1347 u16 ram_offset,
1348 u16 shm_size_offset, u8 rate)
1349 {
1350 u32 i, tmp;
1351 struct b43_plcp_hdr4 plcp;
1352
1353 plcp.data = 0;
1354 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1355 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1356 ram_offset += sizeof(u32);
1357 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1358 * So leave the first two bytes of the next write blank.
1359 */
1360 tmp = (u32) (data[0]) << 16;
1361 tmp |= (u32) (data[1]) << 24;
1362 b43_ram_write(dev, ram_offset, tmp);
1363 ram_offset += sizeof(u32);
1364 for (i = 2; i < size; i += sizeof(u32)) {
1365 tmp = (u32) (data[i + 0]);
1366 if (i + 1 < size)
1367 tmp |= (u32) (data[i + 1]) << 8;
1368 if (i + 2 < size)
1369 tmp |= (u32) (data[i + 2]) << 16;
1370 if (i + 3 < size)
1371 tmp |= (u32) (data[i + 3]) << 24;
1372 b43_ram_write(dev, ram_offset + i - 2, tmp);
1373 }
1374 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1375 size + sizeof(struct b43_plcp_hdr6));
1376 }
1377
1378 /* Check if the use of the antenna that ieee80211 told us to
1379 * use is possible. This will fall back to DEFAULT.
1380 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1381 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1382 u8 antenna_nr)
1383 {
1384 u8 antenna_mask;
1385
1386 if (antenna_nr == 0) {
1387 /* Zero means "use default antenna". That's always OK. */
1388 return 0;
1389 }
1390
1391 /* Get the mask of available antennas. */
1392 if (dev->phy.gmode)
1393 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1394 else
1395 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1396
1397 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1398 /* This antenna is not available. Fall back to default. */
1399 return 0;
1400 }
1401
1402 return antenna_nr;
1403 }
1404
1405 /* Convert a b43 antenna number value to the PHY TX control value. */
1406 static u16 b43_antenna_to_phyctl(int antenna)
1407 {
1408 switch (antenna) {
1409 case B43_ANTENNA0:
1410 return B43_TXH_PHY_ANT0;
1411 case B43_ANTENNA1:
1412 return B43_TXH_PHY_ANT1;
1413 case B43_ANTENNA2:
1414 return B43_TXH_PHY_ANT2;
1415 case B43_ANTENNA3:
1416 return B43_TXH_PHY_ANT3;
1417 case B43_ANTENNA_AUTO0:
1418 case B43_ANTENNA_AUTO1:
1419 return B43_TXH_PHY_ANT01AUTO;
1420 }
1421 B43_WARN_ON(1);
1422 return 0;
1423 }
1424
1425 static void b43_write_beacon_template(struct b43_wldev *dev,
1426 u16 ram_offset,
1427 u16 shm_size_offset)
1428 {
1429 unsigned int i, len, variable_len;
1430 const struct ieee80211_mgmt *bcn;
1431 const u8 *ie;
1432 bool tim_found = 0;
1433 unsigned int rate;
1434 u16 ctl;
1435 int antenna;
1436 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1437
1438 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1439 len = min((size_t) dev->wl->current_beacon->len,
1440 0x200 - sizeof(struct b43_plcp_hdr6));
1441 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1442
1443 b43_write_template_common(dev, (const u8 *)bcn,
1444 len, ram_offset, shm_size_offset, rate);
1445
1446 /* Write the PHY TX control parameters. */
1447 antenna = B43_ANTENNA_DEFAULT;
1448 antenna = b43_antenna_to_phyctl(antenna);
1449 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1450 /* We can't send beacons with short preamble. Would get PHY errors. */
1451 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1452 ctl &= ~B43_TXH_PHY_ANT;
1453 ctl &= ~B43_TXH_PHY_ENC;
1454 ctl |= antenna;
1455 if (b43_is_cck_rate(rate))
1456 ctl |= B43_TXH_PHY_ENC_CCK;
1457 else
1458 ctl |= B43_TXH_PHY_ENC_OFDM;
1459 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1460
1461 /* Find the position of the TIM and the DTIM_period value
1462 * and write them to SHM. */
1463 ie = bcn->u.beacon.variable;
1464 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1465 for (i = 0; i < variable_len - 2; ) {
1466 uint8_t ie_id, ie_len;
1467
1468 ie_id = ie[i];
1469 ie_len = ie[i + 1];
1470 if (ie_id == 5) {
1471 u16 tim_position;
1472 u16 dtim_period;
1473 /* This is the TIM Information Element */
1474
1475 /* Check whether the ie_len is in the beacon data range. */
1476 if (variable_len < ie_len + 2 + i)
1477 break;
1478 /* A valid TIM is at least 4 bytes long. */
1479 if (ie_len < 4)
1480 break;
1481 tim_found = 1;
1482
1483 tim_position = sizeof(struct b43_plcp_hdr6);
1484 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1485 tim_position += i;
1486
1487 dtim_period = ie[i + 3];
1488
1489 b43_shm_write16(dev, B43_SHM_SHARED,
1490 B43_SHM_SH_TIMBPOS, tim_position);
1491 b43_shm_write16(dev, B43_SHM_SHARED,
1492 B43_SHM_SH_DTIMPER, dtim_period);
1493 break;
1494 }
1495 i += ie_len + 2;
1496 }
1497 if (!tim_found) {
1498 /*
1499 * If ucode wants to modify TIM do it behind the beacon, this
1500 * will happen, for example, when doing mesh networking.
1501 */
1502 b43_shm_write16(dev, B43_SHM_SHARED,
1503 B43_SHM_SH_TIMBPOS,
1504 len + sizeof(struct b43_plcp_hdr6));
1505 b43_shm_write16(dev, B43_SHM_SHARED,
1506 B43_SHM_SH_DTIMPER, 0);
1507 }
1508 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1509 }
1510
1511 static void b43_upload_beacon0(struct b43_wldev *dev)
1512 {
1513 struct b43_wl *wl = dev->wl;
1514
1515 if (wl->beacon0_uploaded)
1516 return;
1517 b43_write_beacon_template(dev, 0x68, 0x18);
1518 wl->beacon0_uploaded = 1;
1519 }
1520
1521 static void b43_upload_beacon1(struct b43_wldev *dev)
1522 {
1523 struct b43_wl *wl = dev->wl;
1524
1525 if (wl->beacon1_uploaded)
1526 return;
1527 b43_write_beacon_template(dev, 0x468, 0x1A);
1528 wl->beacon1_uploaded = 1;
1529 }
1530
1531 static void handle_irq_beacon(struct b43_wldev *dev)
1532 {
1533 struct b43_wl *wl = dev->wl;
1534 u32 cmd, beacon0_valid, beacon1_valid;
1535
1536 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1537 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
1538 return;
1539
1540 /* This is the bottom half of the asynchronous beacon update. */
1541
1542 /* Ignore interrupt in the future. */
1543 dev->irq_mask &= ~B43_IRQ_BEACON;
1544
1545 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1546 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1547 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1548
1549 /* Schedule interrupt manually, if busy. */
1550 if (beacon0_valid && beacon1_valid) {
1551 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1552 dev->irq_mask |= B43_IRQ_BEACON;
1553 return;
1554 }
1555
1556 if (unlikely(wl->beacon_templates_virgin)) {
1557 /* We never uploaded a beacon before.
1558 * Upload both templates now, but only mark one valid. */
1559 wl->beacon_templates_virgin = 0;
1560 b43_upload_beacon0(dev);
1561 b43_upload_beacon1(dev);
1562 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1563 cmd |= B43_MACCMD_BEACON0_VALID;
1564 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1565 } else {
1566 if (!beacon0_valid) {
1567 b43_upload_beacon0(dev);
1568 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1569 cmd |= B43_MACCMD_BEACON0_VALID;
1570 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1571 } else if (!beacon1_valid) {
1572 b43_upload_beacon1(dev);
1573 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1574 cmd |= B43_MACCMD_BEACON1_VALID;
1575 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1576 }
1577 }
1578 }
1579
1580 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1581 {
1582 u32 old_irq_mask = dev->irq_mask;
1583
1584 /* update beacon right away or defer to irq */
1585 handle_irq_beacon(dev);
1586 if (old_irq_mask != dev->irq_mask) {
1587 /* The handler updated the IRQ mask. */
1588 B43_WARN_ON(!dev->irq_mask);
1589 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1590 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1591 } else {
1592 /* Device interrupts are currently disabled. That means
1593 * we just ran the hardirq handler and scheduled the
1594 * IRQ thread. The thread will write the IRQ mask when
1595 * it finished, so there's nothing to do here. Writing
1596 * the mask _here_ would incorrectly re-enable IRQs. */
1597 }
1598 }
1599 }
1600
1601 static void b43_beacon_update_trigger_work(struct work_struct *work)
1602 {
1603 struct b43_wl *wl = container_of(work, struct b43_wl,
1604 beacon_update_trigger);
1605 struct b43_wldev *dev;
1606
1607 mutex_lock(&wl->mutex);
1608 dev = wl->current_dev;
1609 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1610 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
1611 /* wl->mutex is enough. */
1612 b43_do_beacon_update_trigger_work(dev);
1613 mmiowb();
1614 } else {
1615 spin_lock_irq(&wl->hardirq_lock);
1616 b43_do_beacon_update_trigger_work(dev);
1617 mmiowb();
1618 spin_unlock_irq(&wl->hardirq_lock);
1619 }
1620 }
1621 mutex_unlock(&wl->mutex);
1622 }
1623
1624 /* Asynchronously update the packet templates in template RAM.
1625 * Locking: Requires wl->mutex to be locked. */
1626 static void b43_update_templates(struct b43_wl *wl)
1627 {
1628 struct sk_buff *beacon;
1629
1630 /* This is the top half of the ansynchronous beacon update.
1631 * The bottom half is the beacon IRQ.
1632 * Beacon update must be asynchronous to avoid sending an
1633 * invalid beacon. This can happen for example, if the firmware
1634 * transmits a beacon while we are updating it. */
1635
1636 /* We could modify the existing beacon and set the aid bit in
1637 * the TIM field, but that would probably require resizing and
1638 * moving of data within the beacon template.
1639 * Simply request a new beacon and let mac80211 do the hard work. */
1640 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1641 if (unlikely(!beacon))
1642 return;
1643
1644 if (wl->current_beacon)
1645 dev_kfree_skb_any(wl->current_beacon);
1646 wl->current_beacon = beacon;
1647 wl->beacon0_uploaded = 0;
1648 wl->beacon1_uploaded = 0;
1649 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1650 }
1651
1652 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1653 {
1654 b43_time_lock(dev);
1655 if (dev->dev->id.revision >= 3) {
1656 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1657 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1658 } else {
1659 b43_write16(dev, 0x606, (beacon_int >> 6));
1660 b43_write16(dev, 0x610, beacon_int);
1661 }
1662 b43_time_unlock(dev);
1663 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1664 }
1665
1666 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1667 {
1668 u16 reason;
1669
1670 /* Read the register that contains the reason code for the panic. */
1671 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1672 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1673
1674 switch (reason) {
1675 default:
1676 b43dbg(dev->wl, "The panic reason is unknown.\n");
1677 /* fallthrough */
1678 case B43_FWPANIC_DIE:
1679 /* Do not restart the controller or firmware.
1680 * The device is nonfunctional from now on.
1681 * Restarting would result in this panic to trigger again,
1682 * so we avoid that recursion. */
1683 break;
1684 case B43_FWPANIC_RESTART:
1685 b43_controller_restart(dev, "Microcode panic");
1686 break;
1687 }
1688 }
1689
1690 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1691 {
1692 unsigned int i, cnt;
1693 u16 reason, marker_id, marker_line;
1694 __le16 *buf;
1695
1696 /* The proprietary firmware doesn't have this IRQ. */
1697 if (!dev->fw.opensource)
1698 return;
1699
1700 /* Read the register that contains the reason code for this IRQ. */
1701 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1702
1703 switch (reason) {
1704 case B43_DEBUGIRQ_PANIC:
1705 b43_handle_firmware_panic(dev);
1706 break;
1707 case B43_DEBUGIRQ_DUMP_SHM:
1708 if (!B43_DEBUG)
1709 break; /* Only with driver debugging enabled. */
1710 buf = kmalloc(4096, GFP_ATOMIC);
1711 if (!buf) {
1712 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1713 goto out;
1714 }
1715 for (i = 0; i < 4096; i += 2) {
1716 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1717 buf[i / 2] = cpu_to_le16(tmp);
1718 }
1719 b43info(dev->wl, "Shared memory dump:\n");
1720 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1721 16, 2, buf, 4096, 1);
1722 kfree(buf);
1723 break;
1724 case B43_DEBUGIRQ_DUMP_REGS:
1725 if (!B43_DEBUG)
1726 break; /* Only with driver debugging enabled. */
1727 b43info(dev->wl, "Microcode register dump:\n");
1728 for (i = 0, cnt = 0; i < 64; i++) {
1729 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1730 if (cnt == 0)
1731 printk(KERN_INFO);
1732 printk("r%02u: 0x%04X ", i, tmp);
1733 cnt++;
1734 if (cnt == 6) {
1735 printk("\n");
1736 cnt = 0;
1737 }
1738 }
1739 printk("\n");
1740 break;
1741 case B43_DEBUGIRQ_MARKER:
1742 if (!B43_DEBUG)
1743 break; /* Only with driver debugging enabled. */
1744 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1745 B43_MARKER_ID_REG);
1746 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1747 B43_MARKER_LINE_REG);
1748 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1749 "at line number %u\n",
1750 marker_id, marker_line);
1751 break;
1752 default:
1753 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1754 reason);
1755 }
1756 out:
1757 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1758 b43_shm_write16(dev, B43_SHM_SCRATCH,
1759 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1760 }
1761
1762 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1763 {
1764 u32 reason;
1765 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1766 u32 merged_dma_reason = 0;
1767 int i;
1768
1769 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1770 return;
1771
1772 reason = dev->irq_reason;
1773 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1774 dma_reason[i] = dev->dma_reason[i];
1775 merged_dma_reason |= dma_reason[i];
1776 }
1777
1778 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1779 b43err(dev->wl, "MAC transmission error\n");
1780
1781 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1782 b43err(dev->wl, "PHY transmission error\n");
1783 rmb();
1784 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1785 atomic_set(&dev->phy.txerr_cnt,
1786 B43_PHY_TX_BADNESS_LIMIT);
1787 b43err(dev->wl, "Too many PHY TX errors, "
1788 "restarting the controller\n");
1789 b43_controller_restart(dev, "PHY TX errors");
1790 }
1791 }
1792
1793 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1794 B43_DMAIRQ_NONFATALMASK))) {
1795 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1796 b43err(dev->wl, "Fatal DMA error: "
1797 "0x%08X, 0x%08X, 0x%08X, "
1798 "0x%08X, 0x%08X, 0x%08X\n",
1799 dma_reason[0], dma_reason[1],
1800 dma_reason[2], dma_reason[3],
1801 dma_reason[4], dma_reason[5]);
1802 b43err(dev->wl, "This device does not support DMA "
1803 "on your system. It will now be switched to PIO.\n");
1804 /* Fall back to PIO transfers if we get fatal DMA errors! */
1805 dev->use_pio = 1;
1806 b43_controller_restart(dev, "DMA error");
1807 return;
1808 }
1809 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1810 b43err(dev->wl, "DMA error: "
1811 "0x%08X, 0x%08X, 0x%08X, "
1812 "0x%08X, 0x%08X, 0x%08X\n",
1813 dma_reason[0], dma_reason[1],
1814 dma_reason[2], dma_reason[3],
1815 dma_reason[4], dma_reason[5]);
1816 }
1817 }
1818
1819 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1820 handle_irq_ucode_debug(dev);
1821 if (reason & B43_IRQ_TBTT_INDI)
1822 handle_irq_tbtt_indication(dev);
1823 if (reason & B43_IRQ_ATIM_END)
1824 handle_irq_atim_end(dev);
1825 if (reason & B43_IRQ_BEACON)
1826 handle_irq_beacon(dev);
1827 if (reason & B43_IRQ_PMQ)
1828 handle_irq_pmq(dev);
1829 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1830 ;/* TODO */
1831 if (reason & B43_IRQ_NOISESAMPLE_OK)
1832 handle_irq_noise(dev);
1833
1834 /* Check the DMA reason registers for received data. */
1835 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1836 if (b43_using_pio_transfers(dev))
1837 b43_pio_rx(dev->pio.rx_queue);
1838 else
1839 b43_dma_rx(dev->dma.rx_ring);
1840 }
1841 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1842 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1843 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1844 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1845 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1846
1847 if (reason & B43_IRQ_TX_OK)
1848 handle_irq_transmit_status(dev);
1849
1850 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1851 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1852
1853 #if B43_DEBUG
1854 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1855 dev->irq_count++;
1856 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1857 if (reason & (1 << i))
1858 dev->irq_bit_count[i]++;
1859 }
1860 }
1861 #endif
1862 }
1863
1864 /* Interrupt thread handler. Handles device interrupts in thread context. */
1865 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1866 {
1867 struct b43_wldev *dev = dev_id;
1868
1869 mutex_lock(&dev->wl->mutex);
1870 b43_do_interrupt_thread(dev);
1871 mmiowb();
1872 mutex_unlock(&dev->wl->mutex);
1873
1874 return IRQ_HANDLED;
1875 }
1876
1877 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1878 {
1879 u32 reason;
1880
1881 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1882 * On SDIO, this runs under wl->mutex. */
1883
1884 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1885 if (reason == 0xffffffff) /* shared IRQ */
1886 return IRQ_NONE;
1887 reason &= dev->irq_mask;
1888 if (!reason)
1889 return IRQ_HANDLED;
1890
1891 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1892 & 0x0001DC00;
1893 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1894 & 0x0000DC00;
1895 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1896 & 0x0000DC00;
1897 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1898 & 0x0001DC00;
1899 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1900 & 0x0000DC00;
1901 /* Unused ring
1902 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1903 & 0x0000DC00;
1904 */
1905
1906 /* ACK the interrupt. */
1907 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1908 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1909 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1910 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1911 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1912 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1913 /* Unused ring
1914 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1915 */
1916
1917 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
1918 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
1919 /* Save the reason bitmasks for the IRQ thread handler. */
1920 dev->irq_reason = reason;
1921
1922 return IRQ_WAKE_THREAD;
1923 }
1924
1925 /* Interrupt handler top-half. This runs with interrupts disabled. */
1926 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1927 {
1928 struct b43_wldev *dev = dev_id;
1929 irqreturn_t ret;
1930
1931 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
1932 return IRQ_NONE;
1933
1934 spin_lock(&dev->wl->hardirq_lock);
1935 ret = b43_do_interrupt(dev);
1936 mmiowb();
1937 spin_unlock(&dev->wl->hardirq_lock);
1938
1939 return ret;
1940 }
1941
1942 /* SDIO interrupt handler. This runs in process context. */
1943 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
1944 {
1945 struct b43_wl *wl = dev->wl;
1946 irqreturn_t ret;
1947
1948 mutex_lock(&wl->mutex);
1949
1950 ret = b43_do_interrupt(dev);
1951 if (ret == IRQ_WAKE_THREAD)
1952 b43_do_interrupt_thread(dev);
1953
1954 mutex_unlock(&wl->mutex);
1955 }
1956
1957 void b43_do_release_fw(struct b43_firmware_file *fw)
1958 {
1959 release_firmware(fw->data);
1960 fw->data = NULL;
1961 fw->filename = NULL;
1962 }
1963
1964 static void b43_release_firmware(struct b43_wldev *dev)
1965 {
1966 b43_do_release_fw(&dev->fw.ucode);
1967 b43_do_release_fw(&dev->fw.pcm);
1968 b43_do_release_fw(&dev->fw.initvals);
1969 b43_do_release_fw(&dev->fw.initvals_band);
1970 }
1971
1972 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1973 {
1974 const char text[] =
1975 "You must go to " \
1976 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
1977 "and download the correct firmware for this driver version. " \
1978 "Please carefully read all instructions on this website.\n";
1979
1980 if (error)
1981 b43err(wl, text);
1982 else
1983 b43warn(wl, text);
1984 }
1985
1986 int b43_do_request_fw(struct b43_request_fw_context *ctx,
1987 const char *name,
1988 struct b43_firmware_file *fw)
1989 {
1990 const struct firmware *blob;
1991 struct b43_fw_header *hdr;
1992 u32 size;
1993 int err;
1994
1995 if (!name) {
1996 /* Don't fetch anything. Free possibly cached firmware. */
1997 b43_do_release_fw(fw);
1998 return 0;
1999 }
2000 if (fw->filename) {
2001 if ((fw->type == ctx->req_type) &&
2002 (strcmp(fw->filename, name) == 0))
2003 return 0; /* Already have this fw. */
2004 /* Free the cached firmware first. */
2005 b43_do_release_fw(fw);
2006 }
2007
2008 switch (ctx->req_type) {
2009 case B43_FWTYPE_PROPRIETARY:
2010 snprintf(ctx->fwname, sizeof(ctx->fwname),
2011 "b43%s/%s.fw",
2012 modparam_fwpostfix, name);
2013 break;
2014 case B43_FWTYPE_OPENSOURCE:
2015 snprintf(ctx->fwname, sizeof(ctx->fwname),
2016 "b43-open%s/%s.fw",
2017 modparam_fwpostfix, name);
2018 break;
2019 default:
2020 B43_WARN_ON(1);
2021 return -ENOSYS;
2022 }
2023 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
2024 if (err == -ENOENT) {
2025 snprintf(ctx->errors[ctx->req_type],
2026 sizeof(ctx->errors[ctx->req_type]),
2027 "Firmware file \"%s\" not found\n", ctx->fwname);
2028 return err;
2029 } else if (err) {
2030 snprintf(ctx->errors[ctx->req_type],
2031 sizeof(ctx->errors[ctx->req_type]),
2032 "Firmware file \"%s\" request failed (err=%d)\n",
2033 ctx->fwname, err);
2034 return err;
2035 }
2036 if (blob->size < sizeof(struct b43_fw_header))
2037 goto err_format;
2038 hdr = (struct b43_fw_header *)(blob->data);
2039 switch (hdr->type) {
2040 case B43_FW_TYPE_UCODE:
2041 case B43_FW_TYPE_PCM:
2042 size = be32_to_cpu(hdr->size);
2043 if (size != blob->size - sizeof(struct b43_fw_header))
2044 goto err_format;
2045 /* fallthrough */
2046 case B43_FW_TYPE_IV:
2047 if (hdr->ver != 1)
2048 goto err_format;
2049 break;
2050 default:
2051 goto err_format;
2052 }
2053
2054 fw->data = blob;
2055 fw->filename = name;
2056 fw->type = ctx->req_type;
2057
2058 return 0;
2059
2060 err_format:
2061 snprintf(ctx->errors[ctx->req_type],
2062 sizeof(ctx->errors[ctx->req_type]),
2063 "Firmware file \"%s\" format error.\n", ctx->fwname);
2064 release_firmware(blob);
2065
2066 return -EPROTO;
2067 }
2068
2069 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2070 {
2071 struct b43_wldev *dev = ctx->dev;
2072 struct b43_firmware *fw = &ctx->dev->fw;
2073 const u8 rev = ctx->dev->dev->id.revision;
2074 const char *filename;
2075 u32 tmshigh;
2076 int err;
2077
2078 /* Get microcode */
2079 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
2080 if ((rev >= 5) && (rev <= 10))
2081 filename = "ucode5";
2082 else if ((rev >= 11) && (rev <= 12))
2083 filename = "ucode11";
2084 else if (rev == 13)
2085 filename = "ucode13";
2086 else if (rev == 14)
2087 filename = "ucode14";
2088 else if (rev >= 15)
2089 filename = "ucode15";
2090 else
2091 goto err_no_ucode;
2092 err = b43_do_request_fw(ctx, filename, &fw->ucode);
2093 if (err)
2094 goto err_load;
2095
2096 /* Get PCM code */
2097 if ((rev >= 5) && (rev <= 10))
2098 filename = "pcm5";
2099 else if (rev >= 11)
2100 filename = NULL;
2101 else
2102 goto err_no_pcm;
2103 fw->pcm_request_failed = 0;
2104 err = b43_do_request_fw(ctx, filename, &fw->pcm);
2105 if (err == -ENOENT) {
2106 /* We did not find a PCM file? Not fatal, but
2107 * core rev <= 10 must do without hwcrypto then. */
2108 fw->pcm_request_failed = 1;
2109 } else if (err)
2110 goto err_load;
2111
2112 /* Get initvals */
2113 switch (dev->phy.type) {
2114 case B43_PHYTYPE_A:
2115 if ((rev >= 5) && (rev <= 10)) {
2116 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2117 filename = "a0g1initvals5";
2118 else
2119 filename = "a0g0initvals5";
2120 } else
2121 goto err_no_initvals;
2122 break;
2123 case B43_PHYTYPE_G:
2124 if ((rev >= 5) && (rev <= 10))
2125 filename = "b0g0initvals5";
2126 else if (rev >= 13)
2127 filename = "b0g0initvals13";
2128 else
2129 goto err_no_initvals;
2130 break;
2131 case B43_PHYTYPE_N:
2132 if ((rev >= 11) && (rev <= 12))
2133 filename = "n0initvals11";
2134 else
2135 goto err_no_initvals;
2136 break;
2137 case B43_PHYTYPE_LP:
2138 if (rev == 13)
2139 filename = "lp0initvals13";
2140 else if (rev == 14)
2141 filename = "lp0initvals14";
2142 else if (rev >= 15)
2143 filename = "lp0initvals15";
2144 else
2145 goto err_no_initvals;
2146 break;
2147 default:
2148 goto err_no_initvals;
2149 }
2150 err = b43_do_request_fw(ctx, filename, &fw->initvals);
2151 if (err)
2152 goto err_load;
2153
2154 /* Get bandswitch initvals */
2155 switch (dev->phy.type) {
2156 case B43_PHYTYPE_A:
2157 if ((rev >= 5) && (rev <= 10)) {
2158 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2159 filename = "a0g1bsinitvals5";
2160 else
2161 filename = "a0g0bsinitvals5";
2162 } else if (rev >= 11)
2163 filename = NULL;
2164 else
2165 goto err_no_initvals;
2166 break;
2167 case B43_PHYTYPE_G:
2168 if ((rev >= 5) && (rev <= 10))
2169 filename = "b0g0bsinitvals5";
2170 else if (rev >= 11)
2171 filename = NULL;
2172 else
2173 goto err_no_initvals;
2174 break;
2175 case B43_PHYTYPE_N:
2176 if ((rev >= 11) && (rev <= 12))
2177 filename = "n0bsinitvals11";
2178 else
2179 goto err_no_initvals;
2180 break;
2181 case B43_PHYTYPE_LP:
2182 if (rev == 13)
2183 filename = "lp0bsinitvals13";
2184 else if (rev == 14)
2185 filename = "lp0bsinitvals14";
2186 else if (rev >= 15)
2187 filename = "lp0bsinitvals15";
2188 else
2189 goto err_no_initvals;
2190 break;
2191 default:
2192 goto err_no_initvals;
2193 }
2194 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
2195 if (err)
2196 goto err_load;
2197
2198 return 0;
2199
2200 err_no_ucode:
2201 err = ctx->fatal_failure = -EOPNOTSUPP;
2202 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2203 "is required for your device (wl-core rev %u)\n", rev);
2204 goto error;
2205
2206 err_no_pcm:
2207 err = ctx->fatal_failure = -EOPNOTSUPP;
2208 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2209 "is required for your device (wl-core rev %u)\n", rev);
2210 goto error;
2211
2212 err_no_initvals:
2213 err = ctx->fatal_failure = -EOPNOTSUPP;
2214 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2215 "is required for your device (wl-core rev %u)\n", rev);
2216 goto error;
2217
2218 err_load:
2219 /* We failed to load this firmware image. The error message
2220 * already is in ctx->errors. Return and let our caller decide
2221 * what to do. */
2222 goto error;
2223
2224 error:
2225 b43_release_firmware(dev);
2226 return err;
2227 }
2228
2229 static int b43_request_firmware(struct b43_wldev *dev)
2230 {
2231 struct b43_request_fw_context *ctx;
2232 unsigned int i;
2233 int err;
2234 const char *errmsg;
2235
2236 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2237 if (!ctx)
2238 return -ENOMEM;
2239 ctx->dev = dev;
2240
2241 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2242 err = b43_try_request_fw(ctx);
2243 if (!err)
2244 goto out; /* Successfully loaded it. */
2245 err = ctx->fatal_failure;
2246 if (err)
2247 goto out;
2248
2249 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2250 err = b43_try_request_fw(ctx);
2251 if (!err)
2252 goto out; /* Successfully loaded it. */
2253 err = ctx->fatal_failure;
2254 if (err)
2255 goto out;
2256
2257 /* Could not find a usable firmware. Print the errors. */
2258 for (i = 0; i < B43_NR_FWTYPES; i++) {
2259 errmsg = ctx->errors[i];
2260 if (strlen(errmsg))
2261 b43err(dev->wl, errmsg);
2262 }
2263 b43_print_fw_helptext(dev->wl, 1);
2264 err = -ENOENT;
2265
2266 out:
2267 kfree(ctx);
2268 return err;
2269 }
2270
2271 static int b43_upload_microcode(struct b43_wldev *dev)
2272 {
2273 const size_t hdr_len = sizeof(struct b43_fw_header);
2274 const __be32 *data;
2275 unsigned int i, len;
2276 u16 fwrev, fwpatch, fwdate, fwtime;
2277 u32 tmp, macctl;
2278 int err = 0;
2279
2280 /* Jump the microcode PSM to offset 0 */
2281 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2282 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2283 macctl |= B43_MACCTL_PSM_JMP0;
2284 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2285 /* Zero out all microcode PSM registers and shared memory. */
2286 for (i = 0; i < 64; i++)
2287 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2288 for (i = 0; i < 4096; i += 2)
2289 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2290
2291 /* Upload Microcode. */
2292 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2293 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2294 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2295 for (i = 0; i < len; i++) {
2296 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2297 udelay(10);
2298 }
2299
2300 if (dev->fw.pcm.data) {
2301 /* Upload PCM data. */
2302 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2303 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2304 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2305 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2306 /* No need for autoinc bit in SHM_HW */
2307 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2308 for (i = 0; i < len; i++) {
2309 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2310 udelay(10);
2311 }
2312 }
2313
2314 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2315
2316 /* Start the microcode PSM */
2317 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2318 macctl &= ~B43_MACCTL_PSM_JMP0;
2319 macctl |= B43_MACCTL_PSM_RUN;
2320 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2321
2322 /* Wait for the microcode to load and respond */
2323 i = 0;
2324 while (1) {
2325 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2326 if (tmp == B43_IRQ_MAC_SUSPENDED)
2327 break;
2328 i++;
2329 if (i >= 20) {
2330 b43err(dev->wl, "Microcode not responding\n");
2331 b43_print_fw_helptext(dev->wl, 1);
2332 err = -ENODEV;
2333 goto error;
2334 }
2335 msleep(50);
2336 }
2337 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2338
2339 /* Get and check the revisions. */
2340 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2341 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2342 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2343 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2344
2345 if (fwrev <= 0x128) {
2346 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2347 "binary drivers older than version 4.x is unsupported. "
2348 "You must upgrade your firmware files.\n");
2349 b43_print_fw_helptext(dev->wl, 1);
2350 err = -EOPNOTSUPP;
2351 goto error;
2352 }
2353 dev->fw.rev = fwrev;
2354 dev->fw.patch = fwpatch;
2355 dev->fw.opensource = (fwdate == 0xFFFF);
2356
2357 /* Default to use-all-queues. */
2358 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2359 dev->qos_enabled = !!modparam_qos;
2360 /* Default to firmware/hardware crypto acceleration. */
2361 dev->hwcrypto_enabled = 1;
2362
2363 if (dev->fw.opensource) {
2364 u16 fwcapa;
2365
2366 /* Patchlevel info is encoded in the "time" field. */
2367 dev->fw.patch = fwtime;
2368 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2369 dev->fw.rev, dev->fw.patch);
2370
2371 fwcapa = b43_fwcapa_read(dev);
2372 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2373 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2374 /* Disable hardware crypto and fall back to software crypto. */
2375 dev->hwcrypto_enabled = 0;
2376 }
2377 if (!(fwcapa & B43_FWCAPA_QOS)) {
2378 b43info(dev->wl, "QoS not supported by firmware\n");
2379 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2380 * ieee80211_unregister to make sure the networking core can
2381 * properly free possible resources. */
2382 dev->wl->hw->queues = 1;
2383 dev->qos_enabled = 0;
2384 }
2385 } else {
2386 b43info(dev->wl, "Loading firmware version %u.%u "
2387 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2388 fwrev, fwpatch,
2389 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2390 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2391 if (dev->fw.pcm_request_failed) {
2392 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2393 "Hardware accelerated cryptography is disabled.\n");
2394 b43_print_fw_helptext(dev->wl, 0);
2395 }
2396 }
2397
2398 if (b43_is_old_txhdr_format(dev)) {
2399 /* We're over the deadline, but we keep support for old fw
2400 * until it turns out to be in major conflict with something new. */
2401 b43warn(dev->wl, "You are using an old firmware image. "
2402 "Support for old firmware will be removed soon "
2403 "(official deadline was July 2008).\n");
2404 b43_print_fw_helptext(dev->wl, 0);
2405 }
2406
2407 return 0;
2408
2409 error:
2410 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2411 macctl &= ~B43_MACCTL_PSM_RUN;
2412 macctl |= B43_MACCTL_PSM_JMP0;
2413 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2414
2415 return err;
2416 }
2417
2418 static int b43_write_initvals(struct b43_wldev *dev,
2419 const struct b43_iv *ivals,
2420 size_t count,
2421 size_t array_size)
2422 {
2423 const struct b43_iv *iv;
2424 u16 offset;
2425 size_t i;
2426 bool bit32;
2427
2428 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2429 iv = ivals;
2430 for (i = 0; i < count; i++) {
2431 if (array_size < sizeof(iv->offset_size))
2432 goto err_format;
2433 array_size -= sizeof(iv->offset_size);
2434 offset = be16_to_cpu(iv->offset_size);
2435 bit32 = !!(offset & B43_IV_32BIT);
2436 offset &= B43_IV_OFFSET_MASK;
2437 if (offset >= 0x1000)
2438 goto err_format;
2439 if (bit32) {
2440 u32 value;
2441
2442 if (array_size < sizeof(iv->data.d32))
2443 goto err_format;
2444 array_size -= sizeof(iv->data.d32);
2445
2446 value = get_unaligned_be32(&iv->data.d32);
2447 b43_write32(dev, offset, value);
2448
2449 iv = (const struct b43_iv *)((const uint8_t *)iv +
2450 sizeof(__be16) +
2451 sizeof(__be32));
2452 } else {
2453 u16 value;
2454
2455 if (array_size < sizeof(iv->data.d16))
2456 goto err_format;
2457 array_size -= sizeof(iv->data.d16);
2458
2459 value = be16_to_cpu(iv->data.d16);
2460 b43_write16(dev, offset, value);
2461
2462 iv = (const struct b43_iv *)((const uint8_t *)iv +
2463 sizeof(__be16) +
2464 sizeof(__be16));
2465 }
2466 }
2467 if (array_size)
2468 goto err_format;
2469
2470 return 0;
2471
2472 err_format:
2473 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2474 b43_print_fw_helptext(dev->wl, 1);
2475
2476 return -EPROTO;
2477 }
2478
2479 static int b43_upload_initvals(struct b43_wldev *dev)
2480 {
2481 const size_t hdr_len = sizeof(struct b43_fw_header);
2482 const struct b43_fw_header *hdr;
2483 struct b43_firmware *fw = &dev->fw;
2484 const struct b43_iv *ivals;
2485 size_t count;
2486 int err;
2487
2488 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2489 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2490 count = be32_to_cpu(hdr->size);
2491 err = b43_write_initvals(dev, ivals, count,
2492 fw->initvals.data->size - hdr_len);
2493 if (err)
2494 goto out;
2495 if (fw->initvals_band.data) {
2496 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2497 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2498 count = be32_to_cpu(hdr->size);
2499 err = b43_write_initvals(dev, ivals, count,
2500 fw->initvals_band.data->size - hdr_len);
2501 if (err)
2502 goto out;
2503 }
2504 out:
2505
2506 return err;
2507 }
2508
2509 /* Initialize the GPIOs
2510 * http://bcm-specs.sipsolutions.net/GPIO
2511 */
2512 static int b43_gpio_init(struct b43_wldev *dev)
2513 {
2514 struct ssb_bus *bus = dev->dev->bus;
2515 struct ssb_device *gpiodev, *pcidev = NULL;
2516 u32 mask, set;
2517
2518 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2519 & ~B43_MACCTL_GPOUTSMSK);
2520
2521 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2522 | 0x000F);
2523
2524 mask = 0x0000001F;
2525 set = 0x0000000F;
2526 if (dev->dev->bus->chip_id == 0x4301) {
2527 mask |= 0x0060;
2528 set |= 0x0060;
2529 }
2530 if (0 ) {
2531 b43_write16(dev, B43_MMIO_GPIO_MASK,
2532 b43_read16(dev, B43_MMIO_GPIO_MASK)
2533 | 0x0100);
2534 mask |= 0x0180;
2535 set |= 0x0180;
2536 }
2537 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2538 b43_write16(dev, B43_MMIO_GPIO_MASK,
2539 b43_read16(dev, B43_MMIO_GPIO_MASK)
2540 | 0x0200);
2541 mask |= 0x0200;
2542 set |= 0x0200;
2543 }
2544 if (dev->dev->id.revision >= 2)
2545 mask |= 0x0010;
2546
2547 #ifdef CONFIG_SSB_DRIVER_PCICORE
2548 pcidev = bus->pcicore.dev;
2549 #endif
2550 gpiodev = bus->chipco.dev ? : pcidev;
2551 if (!gpiodev)
2552 return 0;
2553 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2554 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2555 & mask) | set);
2556
2557 return 0;
2558 }
2559
2560 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2561 static void b43_gpio_cleanup(struct b43_wldev *dev)
2562 {
2563 struct ssb_bus *bus = dev->dev->bus;
2564 struct ssb_device *gpiodev, *pcidev = NULL;
2565
2566 #ifdef CONFIG_SSB_DRIVER_PCICORE
2567 pcidev = bus->pcicore.dev;
2568 #endif
2569 gpiodev = bus->chipco.dev ? : pcidev;
2570 if (!gpiodev)
2571 return;
2572 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2573 }
2574
2575 /* http://bcm-specs.sipsolutions.net/EnableMac */
2576 void b43_mac_enable(struct b43_wldev *dev)
2577 {
2578 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2579 u16 fwstate;
2580
2581 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2582 B43_SHM_SH_UCODESTAT);
2583 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2584 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2585 b43err(dev->wl, "b43_mac_enable(): The firmware "
2586 "should be suspended, but current state is %u\n",
2587 fwstate);
2588 }
2589 }
2590
2591 dev->mac_suspended--;
2592 B43_WARN_ON(dev->mac_suspended < 0);
2593 if (dev->mac_suspended == 0) {
2594 b43_write32(dev, B43_MMIO_MACCTL,
2595 b43_read32(dev, B43_MMIO_MACCTL)
2596 | B43_MACCTL_ENABLED);
2597 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2598 B43_IRQ_MAC_SUSPENDED);
2599 /* Commit writes */
2600 b43_read32(dev, B43_MMIO_MACCTL);
2601 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2602 b43_power_saving_ctl_bits(dev, 0);
2603 }
2604 }
2605
2606 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2607 void b43_mac_suspend(struct b43_wldev *dev)
2608 {
2609 int i;
2610 u32 tmp;
2611
2612 might_sleep();
2613 B43_WARN_ON(dev->mac_suspended < 0);
2614
2615 if (dev->mac_suspended == 0) {
2616 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2617 b43_write32(dev, B43_MMIO_MACCTL,
2618 b43_read32(dev, B43_MMIO_MACCTL)
2619 & ~B43_MACCTL_ENABLED);
2620 /* force pci to flush the write */
2621 b43_read32(dev, B43_MMIO_MACCTL);
2622 for (i = 35; i; i--) {
2623 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2624 if (tmp & B43_IRQ_MAC_SUSPENDED)
2625 goto out;
2626 udelay(10);
2627 }
2628 /* Hm, it seems this will take some time. Use msleep(). */
2629 for (i = 40; i; i--) {
2630 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2631 if (tmp & B43_IRQ_MAC_SUSPENDED)
2632 goto out;
2633 msleep(1);
2634 }
2635 b43err(dev->wl, "MAC suspend failed\n");
2636 }
2637 out:
2638 dev->mac_suspended++;
2639 }
2640
2641 static void b43_adjust_opmode(struct b43_wldev *dev)
2642 {
2643 struct b43_wl *wl = dev->wl;
2644 u32 ctl;
2645 u16 cfp_pretbtt;
2646
2647 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2648 /* Reset status to STA infrastructure mode. */
2649 ctl &= ~B43_MACCTL_AP;
2650 ctl &= ~B43_MACCTL_KEEP_CTL;
2651 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2652 ctl &= ~B43_MACCTL_KEEP_BAD;
2653 ctl &= ~B43_MACCTL_PROMISC;
2654 ctl &= ~B43_MACCTL_BEACPROMISC;
2655 ctl |= B43_MACCTL_INFRA;
2656
2657 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2658 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2659 ctl |= B43_MACCTL_AP;
2660 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2661 ctl &= ~B43_MACCTL_INFRA;
2662
2663 if (wl->filter_flags & FIF_CONTROL)
2664 ctl |= B43_MACCTL_KEEP_CTL;
2665 if (wl->filter_flags & FIF_FCSFAIL)
2666 ctl |= B43_MACCTL_KEEP_BAD;
2667 if (wl->filter_flags & FIF_PLCPFAIL)
2668 ctl |= B43_MACCTL_KEEP_BADPLCP;
2669 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2670 ctl |= B43_MACCTL_PROMISC;
2671 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2672 ctl |= B43_MACCTL_BEACPROMISC;
2673
2674 if (dev->dev->id.revision <= 4)
2675 ctl |= B43_MACCTL_PROMISC;
2676
2677 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2678
2679 cfp_pretbtt = 2;
2680 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2681 if (dev->dev->bus->chip_id == 0x4306 &&
2682 dev->dev->bus->chip_rev == 3)
2683 cfp_pretbtt = 100;
2684 else
2685 cfp_pretbtt = 50;
2686 }
2687 b43_write16(dev, 0x612, cfp_pretbtt);
2688
2689 if (0 /* ctl & B43_MACCTL_AP */) {
2690 b43_write32(dev, B43_MMIO_MACCTL,
2691 b43_read32(dev, B43_MMIO_MACCTL)
2692 & ~B43_MACCTL_DISCPMQ);
2693 } else {
2694 b43_write32(dev, B43_MMIO_MACCTL,
2695 b43_read32(dev, B43_MMIO_MACCTL)
2696 | B43_MACCTL_DISCPMQ);
2697 }
2698 }
2699
2700 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2701 {
2702 u16 offset;
2703
2704 if (is_ofdm) {
2705 offset = 0x480;
2706 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2707 } else {
2708 offset = 0x4C0;
2709 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2710 }
2711 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2712 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2713 }
2714
2715 static void b43_rate_memory_init(struct b43_wldev *dev)
2716 {
2717 switch (dev->phy.type) {
2718 case B43_PHYTYPE_A:
2719 case B43_PHYTYPE_G:
2720 case B43_PHYTYPE_N:
2721 case B43_PHYTYPE_LP:
2722 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2723 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2724 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2725 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2726 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2727 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2728 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2729 if (dev->phy.type == B43_PHYTYPE_A)
2730 break;
2731 /* fallthrough */
2732 case B43_PHYTYPE_B:
2733 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2734 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2735 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2736 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2737 break;
2738 default:
2739 B43_WARN_ON(1);
2740 }
2741 }
2742
2743 /* Set the default values for the PHY TX Control Words. */
2744 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2745 {
2746 u16 ctl = 0;
2747
2748 ctl |= B43_TXH_PHY_ENC_CCK;
2749 ctl |= B43_TXH_PHY_ANT01AUTO;
2750 ctl |= B43_TXH_PHY_TXPWR;
2751
2752 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2753 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2754 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2755 }
2756
2757 /* Set the TX-Antenna for management frames sent by firmware. */
2758 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2759 {
2760 u16 ant;
2761 u16 tmp;
2762
2763 ant = b43_antenna_to_phyctl(antenna);
2764
2765 /* For ACK/CTS */
2766 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2767 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2768 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2769 /* For Probe Resposes */
2770 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2771 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2772 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2773 }
2774
2775 /* This is the opposite of b43_chip_init() */
2776 static void b43_chip_exit(struct b43_wldev *dev)
2777 {
2778 b43_phy_exit(dev);
2779 b43_gpio_cleanup(dev);
2780 /* firmware is released later */
2781 }
2782
2783 /* Initialize the chip
2784 * http://bcm-specs.sipsolutions.net/ChipInit
2785 */
2786 static int b43_chip_init(struct b43_wldev *dev)
2787 {
2788 struct b43_phy *phy = &dev->phy;
2789 int err;
2790 u32 value32, macctl;
2791 u16 value16;
2792
2793 /* Initialize the MAC control */
2794 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2795 if (dev->phy.gmode)
2796 macctl |= B43_MACCTL_GMODE;
2797 macctl |= B43_MACCTL_INFRA;
2798 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2799
2800 err = b43_request_firmware(dev);
2801 if (err)
2802 goto out;
2803 err = b43_upload_microcode(dev);
2804 if (err)
2805 goto out; /* firmware is released later */
2806
2807 err = b43_gpio_init(dev);
2808 if (err)
2809 goto out; /* firmware is released later */
2810
2811 err = b43_upload_initvals(dev);
2812 if (err)
2813 goto err_gpio_clean;
2814
2815 /* Turn the Analog on and initialize the PHY. */
2816 phy->ops->switch_analog(dev, 1);
2817 err = b43_phy_init(dev);
2818 if (err)
2819 goto err_gpio_clean;
2820
2821 /* Disable Interference Mitigation. */
2822 if (phy->ops->interf_mitigation)
2823 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
2824
2825 /* Select the antennae */
2826 if (phy->ops->set_rx_antenna)
2827 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2828 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2829
2830 if (phy->type == B43_PHYTYPE_B) {
2831 value16 = b43_read16(dev, 0x005E);
2832 value16 |= 0x0004;
2833 b43_write16(dev, 0x005E, value16);
2834 }
2835 b43_write32(dev, 0x0100, 0x01000000);
2836 if (dev->dev->id.revision < 5)
2837 b43_write32(dev, 0x010C, 0x01000000);
2838
2839 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2840 & ~B43_MACCTL_INFRA);
2841 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2842 | B43_MACCTL_INFRA);
2843
2844 /* Probe Response Timeout value */
2845 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2846
2847 /* Initially set the wireless operation mode. */
2848 b43_adjust_opmode(dev);
2849
2850 if (dev->dev->id.revision < 3) {
2851 b43_write16(dev, 0x060E, 0x0000);
2852 b43_write16(dev, 0x0610, 0x8000);
2853 b43_write16(dev, 0x0604, 0x0000);
2854 b43_write16(dev, 0x0606, 0x0200);
2855 } else {
2856 b43_write32(dev, 0x0188, 0x80000000);
2857 b43_write32(dev, 0x018C, 0x02000000);
2858 }
2859 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2860 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2861 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2862 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2863 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2864 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2865 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2866
2867 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2868 value32 |= 0x00100000;
2869 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2870
2871 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2872 dev->dev->bus->chipco.fast_pwrup_delay);
2873
2874 err = 0;
2875 b43dbg(dev->wl, "Chip initialized\n");
2876 out:
2877 return err;
2878
2879 err_gpio_clean:
2880 b43_gpio_cleanup(dev);
2881 return err;
2882 }
2883
2884 static void b43_periodic_every60sec(struct b43_wldev *dev)
2885 {
2886 const struct b43_phy_operations *ops = dev->phy.ops;
2887
2888 if (ops->pwork_60sec)
2889 ops->pwork_60sec(dev);
2890
2891 /* Force check the TX power emission now. */
2892 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
2893 }
2894
2895 static void b43_periodic_every30sec(struct b43_wldev *dev)
2896 {
2897 /* Update device statistics. */
2898 b43_calculate_link_quality(dev);
2899 }
2900
2901 static void b43_periodic_every15sec(struct b43_wldev *dev)
2902 {
2903 struct b43_phy *phy = &dev->phy;
2904 u16 wdr;
2905
2906 if (dev->fw.opensource) {
2907 /* Check if the firmware is still alive.
2908 * It will reset the watchdog counter to 0 in its idle loop. */
2909 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2910 if (unlikely(wdr)) {
2911 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2912 b43_controller_restart(dev, "Firmware watchdog");
2913 return;
2914 } else {
2915 b43_shm_write16(dev, B43_SHM_SCRATCH,
2916 B43_WATCHDOG_REG, 1);
2917 }
2918 }
2919
2920 if (phy->ops->pwork_15sec)
2921 phy->ops->pwork_15sec(dev);
2922
2923 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2924 wmb();
2925
2926 #if B43_DEBUG
2927 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
2928 unsigned int i;
2929
2930 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
2931 dev->irq_count / 15,
2932 dev->tx_count / 15,
2933 dev->rx_count / 15);
2934 dev->irq_count = 0;
2935 dev->tx_count = 0;
2936 dev->rx_count = 0;
2937 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
2938 if (dev->irq_bit_count[i]) {
2939 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
2940 dev->irq_bit_count[i] / 15, i, (1 << i));
2941 dev->irq_bit_count[i] = 0;
2942 }
2943 }
2944 }
2945 #endif
2946 }
2947
2948 static void do_periodic_work(struct b43_wldev *dev)
2949 {
2950 unsigned int state;
2951
2952 state = dev->periodic_state;
2953 if (state % 4 == 0)
2954 b43_periodic_every60sec(dev);
2955 if (state % 2 == 0)
2956 b43_periodic_every30sec(dev);
2957 b43_periodic_every15sec(dev);
2958 }
2959
2960 /* Periodic work locking policy:
2961 * The whole periodic work handler is protected by
2962 * wl->mutex. If another lock is needed somewhere in the
2963 * pwork callchain, it's acquired in-place, where it's needed.
2964 */
2965 static void b43_periodic_work_handler(struct work_struct *work)
2966 {
2967 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2968 periodic_work.work);
2969 struct b43_wl *wl = dev->wl;
2970 unsigned long delay;
2971
2972 mutex_lock(&wl->mutex);
2973
2974 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2975 goto out;
2976 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2977 goto out_requeue;
2978
2979 do_periodic_work(dev);
2980
2981 dev->periodic_state++;
2982 out_requeue:
2983 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2984 delay = msecs_to_jiffies(50);
2985 else
2986 delay = round_jiffies_relative(HZ * 15);
2987 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
2988 out:
2989 mutex_unlock(&wl->mutex);
2990 }
2991
2992 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2993 {
2994 struct delayed_work *work = &dev->periodic_work;
2995
2996 dev->periodic_state = 0;
2997 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2998 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
2999 }
3000
3001 /* Check if communication with the device works correctly. */
3002 static int b43_validate_chipaccess(struct b43_wldev *dev)
3003 {
3004 u32 v, backup0, backup4;
3005
3006 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3007 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3008
3009 /* Check for read/write and endianness problems. */
3010 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3011 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3012 goto error;
3013 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3014 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3015 goto error;
3016
3017 /* Check if unaligned 32bit SHM_SHARED access works properly.
3018 * However, don't bail out on failure, because it's noncritical. */
3019 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3020 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3021 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3022 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3023 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3024 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3025 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3026 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3027 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3028 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3029 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3030 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3031
3032 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3033 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3034
3035 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
3036 /* The 32bit register shadows the two 16bit registers
3037 * with update sideeffects. Validate this. */
3038 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3039 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3040 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3041 goto error;
3042 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3043 goto error;
3044 }
3045 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3046
3047 v = b43_read32(dev, B43_MMIO_MACCTL);
3048 v |= B43_MACCTL_GMODE;
3049 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3050 goto error;
3051
3052 return 0;
3053 error:
3054 b43err(dev->wl, "Failed to validate the chipaccess\n");
3055 return -ENODEV;
3056 }
3057
3058 static void b43_security_init(struct b43_wldev *dev)
3059 {
3060 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3061 /* KTP is a word address, but we address SHM bytewise.
3062 * So multiply by two.
3063 */
3064 dev->ktp *= 2;
3065 /* Number of RCMTA address slots */
3066 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3067 /* Clear the key memory. */
3068 b43_clear_keys(dev);
3069 }
3070
3071 #ifdef CONFIG_B43_HWRNG
3072 static int b43_rng_read(struct hwrng *rng, u32 *data)
3073 {
3074 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3075 struct b43_wldev *dev;
3076 int count = -ENODEV;
3077
3078 mutex_lock(&wl->mutex);
3079 dev = wl->current_dev;
3080 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3081 *data = b43_read16(dev, B43_MMIO_RNG);
3082 count = sizeof(u16);
3083 }
3084 mutex_unlock(&wl->mutex);
3085
3086 return count;
3087 }
3088 #endif /* CONFIG_B43_HWRNG */
3089
3090 static void b43_rng_exit(struct b43_wl *wl)
3091 {
3092 #ifdef CONFIG_B43_HWRNG
3093 if (wl->rng_initialized)
3094 hwrng_unregister(&wl->rng);
3095 #endif /* CONFIG_B43_HWRNG */
3096 }
3097
3098 static int b43_rng_init(struct b43_wl *wl)
3099 {
3100 int err = 0;
3101
3102 #ifdef CONFIG_B43_HWRNG
3103 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3104 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3105 wl->rng.name = wl->rng_name;
3106 wl->rng.data_read = b43_rng_read;
3107 wl->rng.priv = (unsigned long)wl;
3108 wl->rng_initialized = 1;
3109 err = hwrng_register(&wl->rng);
3110 if (err) {
3111 wl->rng_initialized = 0;
3112 b43err(wl, "Failed to register the random "
3113 "number generator (%d)\n", err);
3114 }
3115 #endif /* CONFIG_B43_HWRNG */
3116
3117 return err;
3118 }
3119
3120 static void b43_tx_work(struct work_struct *work)
3121 {
3122 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3123 struct b43_wldev *dev;
3124 struct sk_buff *skb;
3125 int err = 0;
3126
3127 mutex_lock(&wl->mutex);
3128 dev = wl->current_dev;
3129 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3130 mutex_unlock(&wl->mutex);
3131 return;
3132 }
3133
3134 while (skb_queue_len(&wl->tx_queue)) {
3135 skb = skb_dequeue(&wl->tx_queue);
3136
3137 if (b43_using_pio_transfers(dev))
3138 err = b43_pio_tx(dev, skb);
3139 else
3140 err = b43_dma_tx(dev, skb);
3141 if (unlikely(err))
3142 dev_kfree_skb(skb); /* Drop it */
3143 }
3144
3145 #if B43_DEBUG
3146 dev->tx_count++;
3147 #endif
3148 mutex_unlock(&wl->mutex);
3149 }
3150
3151 static int b43_op_tx(struct ieee80211_hw *hw,
3152 struct sk_buff *skb)
3153 {
3154 struct b43_wl *wl = hw_to_b43_wl(hw);
3155
3156 if (unlikely(skb->len < 2 + 2 + 6)) {
3157 /* Too short, this can't be a valid frame. */
3158 dev_kfree_skb_any(skb);
3159 return NETDEV_TX_OK;
3160 }
3161 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3162
3163 skb_queue_tail(&wl->tx_queue, skb);
3164 ieee80211_queue_work(wl->hw, &wl->tx_work);
3165
3166 return NETDEV_TX_OK;
3167 }
3168
3169 static void b43_qos_params_upload(struct b43_wldev *dev,
3170 const struct ieee80211_tx_queue_params *p,
3171 u16 shm_offset)
3172 {
3173 u16 params[B43_NR_QOSPARAMS];
3174 int bslots, tmp;
3175 unsigned int i;
3176
3177 if (!dev->qos_enabled)
3178 return;
3179
3180 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3181
3182 memset(&params, 0, sizeof(params));
3183
3184 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3185 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3186 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3187 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3188 params[B43_QOSPARAM_AIFS] = p->aifs;
3189 params[B43_QOSPARAM_BSLOTS] = bslots;
3190 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3191
3192 for (i = 0; i < ARRAY_SIZE(params); i++) {
3193 if (i == B43_QOSPARAM_STATUS) {
3194 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3195 shm_offset + (i * 2));
3196 /* Mark the parameters as updated. */
3197 tmp |= 0x100;
3198 b43_shm_write16(dev, B43_SHM_SHARED,
3199 shm_offset + (i * 2),
3200 tmp);
3201 } else {
3202 b43_shm_write16(dev, B43_SHM_SHARED,
3203 shm_offset + (i * 2),
3204 params[i]);
3205 }
3206 }
3207 }
3208
3209 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3210 static const u16 b43_qos_shm_offsets[] = {
3211 /* [mac80211-queue-nr] = SHM_OFFSET, */
3212 [0] = B43_QOS_VOICE,
3213 [1] = B43_QOS_VIDEO,
3214 [2] = B43_QOS_BESTEFFORT,
3215 [3] = B43_QOS_BACKGROUND,
3216 };
3217
3218 /* Update all QOS parameters in hardware. */
3219 static void b43_qos_upload_all(struct b43_wldev *dev)
3220 {
3221 struct b43_wl *wl = dev->wl;
3222 struct b43_qos_params *params;
3223 unsigned int i;
3224
3225 if (!dev->qos_enabled)
3226 return;
3227
3228 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3229 ARRAY_SIZE(wl->qos_params));
3230
3231 b43_mac_suspend(dev);
3232 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3233 params = &(wl->qos_params[i]);
3234 b43_qos_params_upload(dev, &(params->p),
3235 b43_qos_shm_offsets[i]);
3236 }
3237 b43_mac_enable(dev);
3238 }
3239
3240 static void b43_qos_clear(struct b43_wl *wl)
3241 {
3242 struct b43_qos_params *params;
3243 unsigned int i;
3244
3245 /* Initialize QoS parameters to sane defaults. */
3246
3247 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3248 ARRAY_SIZE(wl->qos_params));
3249
3250 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3251 params = &(wl->qos_params[i]);
3252
3253 switch (b43_qos_shm_offsets[i]) {
3254 case B43_QOS_VOICE:
3255 params->p.txop = 0;
3256 params->p.aifs = 2;
3257 params->p.cw_min = 0x0001;
3258 params->p.cw_max = 0x0001;
3259 break;
3260 case B43_QOS_VIDEO:
3261 params->p.txop = 0;
3262 params->p.aifs = 2;
3263 params->p.cw_min = 0x0001;
3264 params->p.cw_max = 0x0001;
3265 break;
3266 case B43_QOS_BESTEFFORT:
3267 params->p.txop = 0;
3268 params->p.aifs = 3;
3269 params->p.cw_min = 0x0001;
3270 params->p.cw_max = 0x03FF;
3271 break;
3272 case B43_QOS_BACKGROUND:
3273 params->p.txop = 0;
3274 params->p.aifs = 7;
3275 params->p.cw_min = 0x0001;
3276 params->p.cw_max = 0x03FF;
3277 break;
3278 default:
3279 B43_WARN_ON(1);
3280 }
3281 }
3282 }
3283
3284 /* Initialize the core's QOS capabilities */
3285 static void b43_qos_init(struct b43_wldev *dev)
3286 {
3287 if (!dev->qos_enabled) {
3288 /* Disable QOS support. */
3289 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3290 b43_write16(dev, B43_MMIO_IFSCTL,
3291 b43_read16(dev, B43_MMIO_IFSCTL)
3292 & ~B43_MMIO_IFSCTL_USE_EDCF);
3293 b43dbg(dev->wl, "QoS disabled\n");
3294 return;
3295 }
3296
3297 /* Upload the current QOS parameters. */
3298 b43_qos_upload_all(dev);
3299
3300 /* Enable QOS support. */
3301 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3302 b43_write16(dev, B43_MMIO_IFSCTL,
3303 b43_read16(dev, B43_MMIO_IFSCTL)
3304 | B43_MMIO_IFSCTL_USE_EDCF);
3305 b43dbg(dev->wl, "QoS enabled\n");
3306 }
3307
3308 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3309 const struct ieee80211_tx_queue_params *params)
3310 {
3311 struct b43_wl *wl = hw_to_b43_wl(hw);
3312 struct b43_wldev *dev;
3313 unsigned int queue = (unsigned int)_queue;
3314 int err = -ENODEV;
3315
3316 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3317 /* Queue not available or don't support setting
3318 * params on this queue. Return success to not
3319 * confuse mac80211. */
3320 return 0;
3321 }
3322 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3323 ARRAY_SIZE(wl->qos_params));
3324
3325 mutex_lock(&wl->mutex);
3326 dev = wl->current_dev;
3327 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3328 goto out_unlock;
3329
3330 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3331 b43_mac_suspend(dev);
3332 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3333 b43_qos_shm_offsets[queue]);
3334 b43_mac_enable(dev);
3335 err = 0;
3336
3337 out_unlock:
3338 mutex_unlock(&wl->mutex);
3339
3340 return err;
3341 }
3342
3343 static int b43_op_get_stats(struct ieee80211_hw *hw,
3344 struct ieee80211_low_level_stats *stats)
3345 {
3346 struct b43_wl *wl = hw_to_b43_wl(hw);
3347
3348 mutex_lock(&wl->mutex);
3349 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3350 mutex_unlock(&wl->mutex);
3351
3352 return 0;
3353 }
3354
3355 static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3356 {
3357 struct b43_wl *wl = hw_to_b43_wl(hw);
3358 struct b43_wldev *dev;
3359 u64 tsf;
3360
3361 mutex_lock(&wl->mutex);
3362 dev = wl->current_dev;
3363
3364 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3365 b43_tsf_read(dev, &tsf);
3366 else
3367 tsf = 0;
3368
3369 mutex_unlock(&wl->mutex);
3370
3371 return tsf;
3372 }
3373
3374 static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3375 {
3376 struct b43_wl *wl = hw_to_b43_wl(hw);
3377 struct b43_wldev *dev;
3378
3379 mutex_lock(&wl->mutex);
3380 dev = wl->current_dev;
3381
3382 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3383 b43_tsf_write(dev, tsf);
3384
3385 mutex_unlock(&wl->mutex);
3386 }
3387
3388 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3389 {
3390 struct ssb_device *sdev = dev->dev;
3391 u32 tmslow;
3392
3393 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3394 tmslow &= ~B43_TMSLOW_GMODE;
3395 tmslow |= B43_TMSLOW_PHYRESET;
3396 tmslow |= SSB_TMSLOW_FGC;
3397 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3398 msleep(1);
3399
3400 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3401 tmslow &= ~SSB_TMSLOW_FGC;
3402 tmslow |= B43_TMSLOW_PHYRESET;
3403 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3404 msleep(1);
3405 }
3406
3407 static const char *band_to_string(enum ieee80211_band band)
3408 {
3409 switch (band) {
3410 case IEEE80211_BAND_5GHZ:
3411 return "5";
3412 case IEEE80211_BAND_2GHZ:
3413 return "2.4";
3414 default:
3415 break;
3416 }
3417 B43_WARN_ON(1);
3418 return "";
3419 }
3420
3421 /* Expects wl->mutex locked */
3422 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3423 {
3424 struct b43_wldev *up_dev = NULL;
3425 struct b43_wldev *down_dev;
3426 struct b43_wldev *d;
3427 int err;
3428 bool uninitialized_var(gmode);
3429 int prev_status;
3430
3431 /* Find a device and PHY which supports the band. */
3432 list_for_each_entry(d, &wl->devlist, list) {
3433 switch (chan->band) {
3434 case IEEE80211_BAND_5GHZ:
3435 if (d->phy.supports_5ghz) {
3436 up_dev = d;
3437 gmode = 0;
3438 }
3439 break;
3440 case IEEE80211_BAND_2GHZ:
3441 if (d->phy.supports_2ghz) {
3442 up_dev = d;
3443 gmode = 1;
3444 }
3445 break;
3446 default:
3447 B43_WARN_ON(1);
3448 return -EINVAL;
3449 }
3450 if (up_dev)
3451 break;
3452 }
3453 if (!up_dev) {
3454 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3455 band_to_string(chan->band));
3456 return -ENODEV;
3457 }
3458 if ((up_dev == wl->current_dev) &&
3459 (!!wl->current_dev->phy.gmode == !!gmode)) {
3460 /* This device is already running. */
3461 return 0;
3462 }
3463 b43dbg(wl, "Switching to %s-GHz band\n",
3464 band_to_string(chan->band));
3465 down_dev = wl->current_dev;
3466
3467 prev_status = b43_status(down_dev);
3468 /* Shutdown the currently running core. */
3469 if (prev_status >= B43_STAT_STARTED)
3470 down_dev = b43_wireless_core_stop(down_dev);
3471 if (prev_status >= B43_STAT_INITIALIZED)
3472 b43_wireless_core_exit(down_dev);
3473
3474 if (down_dev != up_dev) {
3475 /* We switch to a different core, so we put PHY into
3476 * RESET on the old core. */
3477 b43_put_phy_into_reset(down_dev);
3478 }
3479
3480 /* Now start the new core. */
3481 up_dev->phy.gmode = gmode;
3482 if (prev_status >= B43_STAT_INITIALIZED) {
3483 err = b43_wireless_core_init(up_dev);
3484 if (err) {
3485 b43err(wl, "Fatal: Could not initialize device for "
3486 "selected %s-GHz band\n",
3487 band_to_string(chan->band));
3488 goto init_failure;
3489 }
3490 }
3491 if (prev_status >= B43_STAT_STARTED) {
3492 err = b43_wireless_core_start(up_dev);
3493 if (err) {
3494 b43err(wl, "Fatal: Coult not start device for "
3495 "selected %s-GHz band\n",
3496 band_to_string(chan->band));
3497 b43_wireless_core_exit(up_dev);
3498 goto init_failure;
3499 }
3500 }
3501 B43_WARN_ON(b43_status(up_dev) != prev_status);
3502
3503 wl->current_dev = up_dev;
3504
3505 return 0;
3506 init_failure:
3507 /* Whoops, failed to init the new core. No core is operating now. */
3508 wl->current_dev = NULL;
3509 return err;
3510 }
3511
3512 /* Write the short and long frame retry limit values. */
3513 static void b43_set_retry_limits(struct b43_wldev *dev,
3514 unsigned int short_retry,
3515 unsigned int long_retry)
3516 {
3517 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3518 * the chip-internal counter. */
3519 short_retry = min(short_retry, (unsigned int)0xF);
3520 long_retry = min(long_retry, (unsigned int)0xF);
3521
3522 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3523 short_retry);
3524 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3525 long_retry);
3526 }
3527
3528 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3529 {
3530 struct b43_wl *wl = hw_to_b43_wl(hw);
3531 struct b43_wldev *dev;
3532 struct b43_phy *phy;
3533 struct ieee80211_conf *conf = &hw->conf;
3534 int antenna;
3535 int err = 0;
3536
3537 mutex_lock(&wl->mutex);
3538
3539 /* Switch the band (if necessary). This might change the active core. */
3540 err = b43_switch_band(wl, conf->channel);
3541 if (err)
3542 goto out_unlock_mutex;
3543 dev = wl->current_dev;
3544 phy = &dev->phy;
3545
3546 if (conf_is_ht(conf))
3547 phy->is_40mhz =
3548 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3549 else
3550 phy->is_40mhz = false;
3551
3552 b43_mac_suspend(dev);
3553
3554 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3555 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3556 conf->long_frame_max_tx_count);
3557 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3558 if (!changed)
3559 goto out_mac_enable;
3560
3561 /* Switch to the requested channel.
3562 * The firmware takes care of races with the TX handler. */
3563 if (conf->channel->hw_value != phy->channel)
3564 b43_switch_channel(dev, conf->channel->hw_value);
3565
3566 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
3567
3568 /* Adjust the desired TX power level. */
3569 if (conf->power_level != 0) {
3570 if (conf->power_level != phy->desired_txpower) {
3571 phy->desired_txpower = conf->power_level;
3572 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3573 B43_TXPWR_IGNORE_TSSI);
3574 }
3575 }
3576
3577 /* Antennas for RX and management frame TX. */
3578 antenna = B43_ANTENNA_DEFAULT;
3579 b43_mgmtframe_txantenna(dev, antenna);
3580 antenna = B43_ANTENNA_DEFAULT;
3581 if (phy->ops->set_rx_antenna)
3582 phy->ops->set_rx_antenna(dev, antenna);
3583
3584 if (wl->radio_enabled != phy->radio_on) {
3585 if (wl->radio_enabled) {
3586 b43_software_rfkill(dev, false);
3587 b43info(dev->wl, "Radio turned on by software\n");
3588 if (!dev->radio_hw_enable) {
3589 b43info(dev->wl, "The hardware RF-kill button "
3590 "still turns the radio physically off. "
3591 "Press the button to turn it on.\n");
3592 }
3593 } else {
3594 b43_software_rfkill(dev, true);
3595 b43info(dev->wl, "Radio turned off by software\n");
3596 }
3597 }
3598
3599 out_mac_enable:
3600 b43_mac_enable(dev);
3601 out_unlock_mutex:
3602 mutex_unlock(&wl->mutex);
3603
3604 return err;
3605 }
3606
3607 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3608 {
3609 struct ieee80211_supported_band *sband =
3610 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3611 struct ieee80211_rate *rate;
3612 int i;
3613 u16 basic, direct, offset, basic_offset, rateptr;
3614
3615 for (i = 0; i < sband->n_bitrates; i++) {
3616 rate = &sband->bitrates[i];
3617
3618 if (b43_is_cck_rate(rate->hw_value)) {
3619 direct = B43_SHM_SH_CCKDIRECT;
3620 basic = B43_SHM_SH_CCKBASIC;
3621 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3622 offset &= 0xF;
3623 } else {
3624 direct = B43_SHM_SH_OFDMDIRECT;
3625 basic = B43_SHM_SH_OFDMBASIC;
3626 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3627 offset &= 0xF;
3628 }
3629
3630 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3631
3632 if (b43_is_cck_rate(rate->hw_value)) {
3633 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3634 basic_offset &= 0xF;
3635 } else {
3636 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3637 basic_offset &= 0xF;
3638 }
3639
3640 /*
3641 * Get the pointer that we need to point to
3642 * from the direct map
3643 */
3644 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3645 direct + 2 * basic_offset);
3646 /* and write it to the basic map */
3647 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3648 rateptr);
3649 }
3650 }
3651
3652 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3653 struct ieee80211_vif *vif,
3654 struct ieee80211_bss_conf *conf,
3655 u32 changed)
3656 {
3657 struct b43_wl *wl = hw_to_b43_wl(hw);
3658 struct b43_wldev *dev;
3659
3660 mutex_lock(&wl->mutex);
3661
3662 dev = wl->current_dev;
3663 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3664 goto out_unlock_mutex;
3665
3666 B43_WARN_ON(wl->vif != vif);
3667
3668 if (changed & BSS_CHANGED_BSSID) {
3669 if (conf->bssid)
3670 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3671 else
3672 memset(wl->bssid, 0, ETH_ALEN);
3673 }
3674
3675 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3676 if (changed & BSS_CHANGED_BEACON &&
3677 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3678 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3679 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3680 b43_update_templates(wl);
3681
3682 if (changed & BSS_CHANGED_BSSID)
3683 b43_write_mac_bssid_templates(dev);
3684 }
3685
3686 b43_mac_suspend(dev);
3687
3688 /* Update templates for AP/mesh mode. */
3689 if (changed & BSS_CHANGED_BEACON_INT &&
3690 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3691 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3692 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3693 b43_set_beacon_int(dev, conf->beacon_int);
3694
3695 if (changed & BSS_CHANGED_BASIC_RATES)
3696 b43_update_basic_rates(dev, conf->basic_rates);
3697
3698 if (changed & BSS_CHANGED_ERP_SLOT) {
3699 if (conf->use_short_slot)
3700 b43_short_slot_timing_enable(dev);
3701 else
3702 b43_short_slot_timing_disable(dev);
3703 }
3704
3705 b43_mac_enable(dev);
3706 out_unlock_mutex:
3707 mutex_unlock(&wl->mutex);
3708 }
3709
3710 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3711 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3712 struct ieee80211_key_conf *key)
3713 {
3714 struct b43_wl *wl = hw_to_b43_wl(hw);
3715 struct b43_wldev *dev;
3716 u8 algorithm;
3717 u8 index;
3718 int err;
3719 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3720
3721 if (modparam_nohwcrypt)
3722 return -ENOSPC; /* User disabled HW-crypto */
3723
3724 mutex_lock(&wl->mutex);
3725
3726 dev = wl->current_dev;
3727 err = -ENODEV;
3728 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3729 goto out_unlock;
3730
3731 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
3732 /* We don't have firmware for the crypto engine.
3733 * Must use software-crypto. */
3734 err = -EOPNOTSUPP;
3735 goto out_unlock;
3736 }
3737
3738 err = -EINVAL;
3739 switch (key->alg) {
3740 case ALG_WEP:
3741 if (key->keylen == WLAN_KEY_LEN_WEP40)
3742 algorithm = B43_SEC_ALGO_WEP40;
3743 else
3744 algorithm = B43_SEC_ALGO_WEP104;
3745 break;
3746 case ALG_TKIP:
3747 algorithm = B43_SEC_ALGO_TKIP;
3748 break;
3749 case ALG_CCMP:
3750 algorithm = B43_SEC_ALGO_AES;
3751 break;
3752 default:
3753 B43_WARN_ON(1);
3754 goto out_unlock;
3755 }
3756 index = (u8) (key->keyidx);
3757 if (index > 3)
3758 goto out_unlock;
3759
3760 switch (cmd) {
3761 case SET_KEY:
3762 if (algorithm == B43_SEC_ALGO_TKIP &&
3763 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
3764 !modparam_hwtkip)) {
3765 /* We support only pairwise key */
3766 err = -EOPNOTSUPP;
3767 goto out_unlock;
3768 }
3769
3770 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
3771 if (WARN_ON(!sta)) {
3772 err = -EOPNOTSUPP;
3773 goto out_unlock;
3774 }
3775 /* Pairwise key with an assigned MAC address. */
3776 err = b43_key_write(dev, -1, algorithm,
3777 key->key, key->keylen,
3778 sta->addr, key);
3779 } else {
3780 /* Group key */
3781 err = b43_key_write(dev, index, algorithm,
3782 key->key, key->keylen, NULL, key);
3783 }
3784 if (err)
3785 goto out_unlock;
3786
3787 if (algorithm == B43_SEC_ALGO_WEP40 ||
3788 algorithm == B43_SEC_ALGO_WEP104) {
3789 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3790 } else {
3791 b43_hf_write(dev,
3792 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3793 }
3794 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3795 if (algorithm == B43_SEC_ALGO_TKIP)
3796 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3797 break;
3798 case DISABLE_KEY: {
3799 err = b43_key_clear(dev, key->hw_key_idx);
3800 if (err)
3801 goto out_unlock;
3802 break;
3803 }
3804 default:
3805 B43_WARN_ON(1);
3806 }
3807
3808 out_unlock:
3809 if (!err) {
3810 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3811 "mac: %pM\n",
3812 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3813 sta ? sta->addr : bcast_addr);
3814 b43_dump_keymemory(dev);
3815 }
3816 mutex_unlock(&wl->mutex);
3817
3818 return err;
3819 }
3820
3821 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3822 unsigned int changed, unsigned int *fflags,
3823 u64 multicast)
3824 {
3825 struct b43_wl *wl = hw_to_b43_wl(hw);
3826 struct b43_wldev *dev;
3827
3828 mutex_lock(&wl->mutex);
3829 dev = wl->current_dev;
3830 if (!dev) {
3831 *fflags = 0;
3832 goto out_unlock;
3833 }
3834
3835 *fflags &= FIF_PROMISC_IN_BSS |
3836 FIF_ALLMULTI |
3837 FIF_FCSFAIL |
3838 FIF_PLCPFAIL |
3839 FIF_CONTROL |
3840 FIF_OTHER_BSS |
3841 FIF_BCN_PRBRESP_PROMISC;
3842
3843 changed &= FIF_PROMISC_IN_BSS |
3844 FIF_ALLMULTI |
3845 FIF_FCSFAIL |
3846 FIF_PLCPFAIL |
3847 FIF_CONTROL |
3848 FIF_OTHER_BSS |
3849 FIF_BCN_PRBRESP_PROMISC;
3850
3851 wl->filter_flags = *fflags;
3852
3853 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3854 b43_adjust_opmode(dev);
3855
3856 out_unlock:
3857 mutex_unlock(&wl->mutex);
3858 }
3859
3860 /* Locking: wl->mutex
3861 * Returns the current dev. This might be different from the passed in dev,
3862 * because the core might be gone away while we unlocked the mutex. */
3863 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
3864 {
3865 struct b43_wl *wl = dev->wl;
3866 struct b43_wldev *orig_dev;
3867 u32 mask;
3868
3869 redo:
3870 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3871 return dev;
3872
3873 /* Cancel work. Unlock to avoid deadlocks. */
3874 mutex_unlock(&wl->mutex);
3875 cancel_delayed_work_sync(&dev->periodic_work);
3876 cancel_work_sync(&wl->tx_work);
3877 mutex_lock(&wl->mutex);
3878 dev = wl->current_dev;
3879 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
3880 /* Whoops, aliens ate up the device while we were unlocked. */
3881 return dev;
3882 }
3883
3884 /* Disable interrupts on the device. */
3885 b43_set_status(dev, B43_STAT_INITIALIZED);
3886 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
3887 /* wl->mutex is locked. That is enough. */
3888 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3889 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3890 } else {
3891 spin_lock_irq(&wl->hardirq_lock);
3892 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3893 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3894 spin_unlock_irq(&wl->hardirq_lock);
3895 }
3896 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
3897 orig_dev = dev;
3898 mutex_unlock(&wl->mutex);
3899 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
3900 b43_sdio_free_irq(dev);
3901 } else {
3902 synchronize_irq(dev->dev->irq);
3903 free_irq(dev->dev->irq, dev);
3904 }
3905 mutex_lock(&wl->mutex);
3906 dev = wl->current_dev;
3907 if (!dev)
3908 return dev;
3909 if (dev != orig_dev) {
3910 if (b43_status(dev) >= B43_STAT_STARTED)
3911 goto redo;
3912 return dev;
3913 }
3914 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
3915 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
3916
3917 /* Drain the TX queue */
3918 while (skb_queue_len(&wl->tx_queue))
3919 dev_kfree_skb(skb_dequeue(&wl->tx_queue));
3920
3921 b43_mac_suspend(dev);
3922 b43_leds_exit(dev);
3923 b43dbg(wl, "Wireless interface stopped\n");
3924
3925 return dev;
3926 }
3927
3928 /* Locking: wl->mutex */
3929 static int b43_wireless_core_start(struct b43_wldev *dev)
3930 {
3931 int err;
3932
3933 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3934
3935 drain_txstatus_queue(dev);
3936 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
3937 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
3938 if (err) {
3939 b43err(dev->wl, "Cannot request SDIO IRQ\n");
3940 goto out;
3941 }
3942 } else {
3943 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3944 b43_interrupt_thread_handler,
3945 IRQF_SHARED, KBUILD_MODNAME, dev);
3946 if (err) {
3947 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3948 goto out;
3949 }
3950 }
3951
3952 /* We are ready to run. */
3953 ieee80211_wake_queues(dev->wl->hw);
3954 b43_set_status(dev, B43_STAT_STARTED);
3955
3956 /* Start data flow (TX/RX). */
3957 b43_mac_enable(dev);
3958 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
3959
3960 /* Start maintainance work */
3961 b43_periodic_tasks_setup(dev);
3962
3963 b43_leds_init(dev);
3964
3965 b43dbg(dev->wl, "Wireless interface started\n");
3966 out:
3967 return err;
3968 }
3969
3970 /* Get PHY and RADIO versioning numbers */
3971 static int b43_phy_versioning(struct b43_wldev *dev)
3972 {
3973 struct b43_phy *phy = &dev->phy;
3974 u32 tmp;
3975 u8 analog_type;
3976 u8 phy_type;
3977 u8 phy_rev;
3978 u16 radio_manuf;
3979 u16 radio_ver;
3980 u16 radio_rev;
3981 int unsupported = 0;
3982
3983 /* Get PHY versioning */
3984 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3985 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3986 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3987 phy_rev = (tmp & B43_PHYVER_VERSION);
3988 switch (phy_type) {
3989 case B43_PHYTYPE_A:
3990 if (phy_rev >= 4)
3991 unsupported = 1;
3992 break;
3993 case B43_PHYTYPE_B:
3994 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3995 && phy_rev != 7)
3996 unsupported = 1;
3997 break;
3998 case B43_PHYTYPE_G:
3999 if (phy_rev > 9)
4000 unsupported = 1;
4001 break;
4002 #ifdef CONFIG_B43_NPHY
4003 case B43_PHYTYPE_N:
4004 if (phy_rev > 4)
4005 unsupported = 1;
4006 break;
4007 #endif
4008 #ifdef CONFIG_B43_PHY_LP
4009 case B43_PHYTYPE_LP:
4010 if (phy_rev > 2)
4011 unsupported = 1;
4012 break;
4013 #endif
4014 default:
4015 unsupported = 1;
4016 };
4017 if (unsupported) {
4018 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4019 "(Analog %u, Type %u, Revision %u)\n",
4020 analog_type, phy_type, phy_rev);
4021 return -EOPNOTSUPP;
4022 }
4023 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4024 analog_type, phy_type, phy_rev);
4025
4026 /* Get RADIO versioning */
4027 if (dev->dev->bus->chip_id == 0x4317) {
4028 if (dev->dev->bus->chip_rev == 0)
4029 tmp = 0x3205017F;
4030 else if (dev->dev->bus->chip_rev == 1)
4031 tmp = 0x4205017F;
4032 else
4033 tmp = 0x5205017F;
4034 } else {
4035 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
4036 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4037 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
4038 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
4039 }
4040 radio_manuf = (tmp & 0x00000FFF);
4041 radio_ver = (tmp & 0x0FFFF000) >> 12;
4042 radio_rev = (tmp & 0xF0000000) >> 28;
4043 if (radio_manuf != 0x17F /* Broadcom */)
4044 unsupported = 1;
4045 switch (phy_type) {
4046 case B43_PHYTYPE_A:
4047 if (radio_ver != 0x2060)
4048 unsupported = 1;
4049 if (radio_rev != 1)
4050 unsupported = 1;
4051 if (radio_manuf != 0x17F)
4052 unsupported = 1;
4053 break;
4054 case B43_PHYTYPE_B:
4055 if ((radio_ver & 0xFFF0) != 0x2050)
4056 unsupported = 1;
4057 break;
4058 case B43_PHYTYPE_G:
4059 if (radio_ver != 0x2050)
4060 unsupported = 1;
4061 break;
4062 case B43_PHYTYPE_N:
4063 if (radio_ver != 0x2055 && radio_ver != 0x2056)
4064 unsupported = 1;
4065 break;
4066 case B43_PHYTYPE_LP:
4067 if (radio_ver != 0x2062 && radio_ver != 0x2063)
4068 unsupported = 1;
4069 break;
4070 default:
4071 B43_WARN_ON(1);
4072 }
4073 if (unsupported) {
4074 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4075 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4076 radio_manuf, radio_ver, radio_rev);
4077 return -EOPNOTSUPP;
4078 }
4079 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4080 radio_manuf, radio_ver, radio_rev);
4081
4082 phy->radio_manuf = radio_manuf;
4083 phy->radio_ver = radio_ver;
4084 phy->radio_rev = radio_rev;
4085
4086 phy->analog = analog_type;
4087 phy->type = phy_type;
4088 phy->rev = phy_rev;
4089
4090 return 0;
4091 }
4092
4093 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4094 struct b43_phy *phy)
4095 {
4096 phy->hardware_power_control = !!modparam_hwpctl;
4097 phy->next_txpwr_check_time = jiffies;
4098 /* PHY TX errors counter. */
4099 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4100
4101 #if B43_DEBUG
4102 phy->phy_locked = 0;
4103 phy->radio_locked = 0;
4104 #endif
4105 }
4106
4107 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4108 {
4109 dev->dfq_valid = 0;
4110
4111 /* Assume the radio is enabled. If it's not enabled, the state will
4112 * immediately get fixed on the first periodic work run. */
4113 dev->radio_hw_enable = 1;
4114
4115 /* Stats */
4116 memset(&dev->stats, 0, sizeof(dev->stats));
4117
4118 setup_struct_phy_for_init(dev, &dev->phy);
4119
4120 /* IRQ related flags */
4121 dev->irq_reason = 0;
4122 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4123 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4124 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4125 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4126
4127 dev->mac_suspended = 1;
4128
4129 /* Noise calculation context */
4130 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4131 }
4132
4133 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4134 {
4135 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
4136 u64 hf;
4137
4138 if (!modparam_btcoex)
4139 return;
4140 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4141 return;
4142 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4143 return;
4144
4145 hf = b43_hf_read(dev);
4146 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4147 hf |= B43_HF_BTCOEXALT;
4148 else
4149 hf |= B43_HF_BTCOEX;
4150 b43_hf_write(dev, hf);
4151 }
4152
4153 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4154 {
4155 if (!modparam_btcoex)
4156 return;
4157 //TODO
4158 }
4159
4160 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4161 {
4162 #ifdef CONFIG_SSB_DRIVER_PCICORE
4163 struct ssb_bus *bus = dev->dev->bus;
4164 u32 tmp;
4165
4166 if (bus->pcicore.dev &&
4167 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
4168 bus->pcicore.dev->id.revision <= 5) {
4169 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
4170 switch (bus->bustype) {
4171 case SSB_BUSTYPE_PCI:
4172 case SSB_BUSTYPE_PCMCIA:
4173 tmp &= ~SSB_IMCFGLO_REQTO;
4174 tmp &= ~SSB_IMCFGLO_SERTO;
4175 tmp |= 0x32;
4176 break;
4177 case SSB_BUSTYPE_SSB:
4178 tmp &= ~SSB_IMCFGLO_REQTO;
4179 tmp &= ~SSB_IMCFGLO_SERTO;
4180 tmp |= 0x53;
4181 break;
4182 default:
4183 break;
4184 }
4185 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
4186 }
4187 #endif /* CONFIG_SSB_DRIVER_PCICORE */
4188 }
4189
4190 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4191 {
4192 u16 pu_delay;
4193
4194 /* The time value is in microseconds. */
4195 if (dev->phy.type == B43_PHYTYPE_A)
4196 pu_delay = 3700;
4197 else
4198 pu_delay = 1050;
4199 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4200 pu_delay = 500;
4201 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4202 pu_delay = max(pu_delay, (u16)2400);
4203
4204 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4205 }
4206
4207 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4208 static void b43_set_pretbtt(struct b43_wldev *dev)
4209 {
4210 u16 pretbtt;
4211
4212 /* The time value is in microseconds. */
4213 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4214 pretbtt = 2;
4215 } else {
4216 if (dev->phy.type == B43_PHYTYPE_A)
4217 pretbtt = 120;
4218 else
4219 pretbtt = 250;
4220 }
4221 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4222 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4223 }
4224
4225 /* Shutdown a wireless core */
4226 /* Locking: wl->mutex */
4227 static void b43_wireless_core_exit(struct b43_wldev *dev)
4228 {
4229 u32 macctl;
4230
4231 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4232 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4233 return;
4234 b43_set_status(dev, B43_STAT_UNINIT);
4235
4236 /* Stop the microcode PSM. */
4237 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4238 macctl &= ~B43_MACCTL_PSM_RUN;
4239 macctl |= B43_MACCTL_PSM_JMP0;
4240 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4241
4242 b43_dma_free(dev);
4243 b43_pio_free(dev);
4244 b43_chip_exit(dev);
4245 dev->phy.ops->switch_analog(dev, 0);
4246 if (dev->wl->current_beacon) {
4247 dev_kfree_skb_any(dev->wl->current_beacon);
4248 dev->wl->current_beacon = NULL;
4249 }
4250
4251 ssb_device_disable(dev->dev, 0);
4252 ssb_bus_may_powerdown(dev->dev->bus);
4253 }
4254
4255 /* Initialize a wireless core */
4256 static int b43_wireless_core_init(struct b43_wldev *dev)
4257 {
4258 struct ssb_bus *bus = dev->dev->bus;
4259 struct ssb_sprom *sprom = &bus->sprom;
4260 struct b43_phy *phy = &dev->phy;
4261 int err;
4262 u64 hf;
4263 u32 tmp;
4264
4265 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4266
4267 err = ssb_bus_powerup(bus, 0);
4268 if (err)
4269 goto out;
4270 if (!ssb_device_is_enabled(dev->dev)) {
4271 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4272 b43_wireless_core_reset(dev, tmp);
4273 }
4274
4275 /* Reset all data structures. */
4276 setup_struct_wldev_for_init(dev);
4277 phy->ops->prepare_structs(dev);
4278
4279 /* Enable IRQ routing to this device. */
4280 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4281
4282 b43_imcfglo_timeouts_workaround(dev);
4283 b43_bluetooth_coext_disable(dev);
4284 if (phy->ops->prepare_hardware) {
4285 err = phy->ops->prepare_hardware(dev);
4286 if (err)
4287 goto err_busdown;
4288 }
4289 err = b43_chip_init(dev);
4290 if (err)
4291 goto err_busdown;
4292 b43_shm_write16(dev, B43_SHM_SHARED,
4293 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4294 hf = b43_hf_read(dev);
4295 if (phy->type == B43_PHYTYPE_G) {
4296 hf |= B43_HF_SYMW;
4297 if (phy->rev == 1)
4298 hf |= B43_HF_GDCW;
4299 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4300 hf |= B43_HF_OFDMPABOOST;
4301 }
4302 if (phy->radio_ver == 0x2050) {
4303 if (phy->radio_rev == 6)
4304 hf |= B43_HF_4318TSSI;
4305 if (phy->radio_rev < 6)
4306 hf |= B43_HF_VCORECALC;
4307 }
4308 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4309 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4310 #ifdef CONFIG_SSB_DRIVER_PCICORE
4311 if ((bus->bustype == SSB_BUSTYPE_PCI) &&
4312 (bus->pcicore.dev->id.revision <= 10))
4313 hf |= B43_HF_PCISCW;
4314 #endif
4315 hf &= ~B43_HF_SKCFPUP;
4316 b43_hf_write(dev, hf);
4317
4318 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4319 B43_DEFAULT_LONG_RETRY_LIMIT);
4320 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4321 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4322
4323 /* Disable sending probe responses from firmware.
4324 * Setting the MaxTime to one usec will always trigger
4325 * a timeout, so we never send any probe resp.
4326 * A timeout of zero is infinite. */
4327 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4328
4329 b43_rate_memory_init(dev);
4330 b43_set_phytxctl_defaults(dev);
4331
4332 /* Minimum Contention Window */
4333 if (phy->type == B43_PHYTYPE_B)
4334 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4335 else
4336 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4337 /* Maximum Contention Window */
4338 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4339
4340 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) ||
4341 (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) ||
4342 dev->use_pio) {
4343 dev->__using_pio_transfers = 1;
4344 err = b43_pio_init(dev);
4345 } else {
4346 dev->__using_pio_transfers = 0;
4347 err = b43_dma_init(dev);
4348 }
4349 if (err)
4350 goto err_chip_exit;
4351 b43_qos_init(dev);
4352 b43_set_synth_pu_delay(dev, 1);
4353 b43_bluetooth_coext_enable(dev);
4354
4355 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4356 b43_upload_card_macaddress(dev);
4357 b43_security_init(dev);
4358
4359 ieee80211_wake_queues(dev->wl->hw);
4360
4361 b43_set_status(dev, B43_STAT_INITIALIZED);
4362
4363 out:
4364 return err;
4365
4366 err_chip_exit:
4367 b43_chip_exit(dev);
4368 err_busdown:
4369 ssb_bus_may_powerdown(bus);
4370 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4371 return err;
4372 }
4373
4374 static int b43_op_add_interface(struct ieee80211_hw *hw,
4375 struct ieee80211_vif *vif)
4376 {
4377 struct b43_wl *wl = hw_to_b43_wl(hw);
4378 struct b43_wldev *dev;
4379 int err = -EOPNOTSUPP;
4380
4381 /* TODO: allow WDS/AP devices to coexist */
4382
4383 if (vif->type != NL80211_IFTYPE_AP &&
4384 vif->type != NL80211_IFTYPE_MESH_POINT &&
4385 vif->type != NL80211_IFTYPE_STATION &&
4386 vif->type != NL80211_IFTYPE_WDS &&
4387 vif->type != NL80211_IFTYPE_ADHOC)
4388 return -EOPNOTSUPP;
4389
4390 mutex_lock(&wl->mutex);
4391 if (wl->operating)
4392 goto out_mutex_unlock;
4393
4394 b43dbg(wl, "Adding Interface type %d\n", vif->type);
4395
4396 dev = wl->current_dev;
4397 wl->operating = 1;
4398 wl->vif = vif;
4399 wl->if_type = vif->type;
4400 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4401
4402 b43_adjust_opmode(dev);
4403 b43_set_pretbtt(dev);
4404 b43_set_synth_pu_delay(dev, 0);
4405 b43_upload_card_macaddress(dev);
4406
4407 err = 0;
4408 out_mutex_unlock:
4409 mutex_unlock(&wl->mutex);
4410
4411 return err;
4412 }
4413
4414 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4415 struct ieee80211_vif *vif)
4416 {
4417 struct b43_wl *wl = hw_to_b43_wl(hw);
4418 struct b43_wldev *dev = wl->current_dev;
4419
4420 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4421
4422 mutex_lock(&wl->mutex);
4423
4424 B43_WARN_ON(!wl->operating);
4425 B43_WARN_ON(wl->vif != vif);
4426 wl->vif = NULL;
4427
4428 wl->operating = 0;
4429
4430 b43_adjust_opmode(dev);
4431 memset(wl->mac_addr, 0, ETH_ALEN);
4432 b43_upload_card_macaddress(dev);
4433
4434 mutex_unlock(&wl->mutex);
4435 }
4436
4437 static int b43_op_start(struct ieee80211_hw *hw)
4438 {
4439 struct b43_wl *wl = hw_to_b43_wl(hw);
4440 struct b43_wldev *dev = wl->current_dev;
4441 int did_init = 0;
4442 int err = 0;
4443
4444 /* Kill all old instance specific information to make sure
4445 * the card won't use it in the short timeframe between start
4446 * and mac80211 reconfiguring it. */
4447 memset(wl->bssid, 0, ETH_ALEN);
4448 memset(wl->mac_addr, 0, ETH_ALEN);
4449 wl->filter_flags = 0;
4450 wl->radiotap_enabled = 0;
4451 b43_qos_clear(wl);
4452 wl->beacon0_uploaded = 0;
4453 wl->beacon1_uploaded = 0;
4454 wl->beacon_templates_virgin = 1;
4455 wl->radio_enabled = 1;
4456
4457 mutex_lock(&wl->mutex);
4458
4459 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4460 err = b43_wireless_core_init(dev);
4461 if (err)
4462 goto out_mutex_unlock;
4463 did_init = 1;
4464 }
4465
4466 if (b43_status(dev) < B43_STAT_STARTED) {
4467 err = b43_wireless_core_start(dev);
4468 if (err) {
4469 if (did_init)
4470 b43_wireless_core_exit(dev);
4471 goto out_mutex_unlock;
4472 }
4473 }
4474
4475 wiphy_rfkill_start_polling(hw->wiphy);
4476
4477 out_mutex_unlock:
4478 mutex_unlock(&wl->mutex);
4479
4480 return err;
4481 }
4482
4483 static void b43_op_stop(struct ieee80211_hw *hw)
4484 {
4485 struct b43_wl *wl = hw_to_b43_wl(hw);
4486 struct b43_wldev *dev = wl->current_dev;
4487
4488 cancel_work_sync(&(wl->beacon_update_trigger));
4489
4490 mutex_lock(&wl->mutex);
4491 if (b43_status(dev) >= B43_STAT_STARTED) {
4492 dev = b43_wireless_core_stop(dev);
4493 if (!dev)
4494 goto out_unlock;
4495 }
4496 b43_wireless_core_exit(dev);
4497 wl->radio_enabled = 0;
4498
4499 out_unlock:
4500 mutex_unlock(&wl->mutex);
4501
4502 cancel_work_sync(&(wl->txpower_adjust_work));
4503 }
4504
4505 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4506 struct ieee80211_sta *sta, bool set)
4507 {
4508 struct b43_wl *wl = hw_to_b43_wl(hw);
4509
4510 b43_update_templates(wl);
4511
4512 return 0;
4513 }
4514
4515 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4516 struct ieee80211_vif *vif,
4517 enum sta_notify_cmd notify_cmd,
4518 struct ieee80211_sta *sta)
4519 {
4520 struct b43_wl *wl = hw_to_b43_wl(hw);
4521
4522 B43_WARN_ON(!vif || wl->vif != vif);
4523 }
4524
4525 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4526 {
4527 struct b43_wl *wl = hw_to_b43_wl(hw);
4528 struct b43_wldev *dev;
4529
4530 mutex_lock(&wl->mutex);
4531 dev = wl->current_dev;
4532 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4533 /* Disable CFP update during scan on other channels. */
4534 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4535 }
4536 mutex_unlock(&wl->mutex);
4537 }
4538
4539 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4540 {
4541 struct b43_wl *wl = hw_to_b43_wl(hw);
4542 struct b43_wldev *dev;
4543
4544 mutex_lock(&wl->mutex);
4545 dev = wl->current_dev;
4546 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4547 /* Re-enable CFP update. */
4548 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4549 }
4550 mutex_unlock(&wl->mutex);
4551 }
4552
4553 static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4554 struct survey_info *survey)
4555 {
4556 struct b43_wl *wl = hw_to_b43_wl(hw);
4557 struct b43_wldev *dev = wl->current_dev;
4558 struct ieee80211_conf *conf = &hw->conf;
4559
4560 if (idx != 0)
4561 return -ENOENT;
4562
4563 survey->channel = conf->channel;
4564 survey->filled = SURVEY_INFO_NOISE_DBM;
4565 survey->noise = dev->stats.link_noise;
4566
4567 return 0;
4568 }
4569
4570 static const struct ieee80211_ops b43_hw_ops = {
4571 .tx = b43_op_tx,
4572 .conf_tx = b43_op_conf_tx,
4573 .add_interface = b43_op_add_interface,
4574 .remove_interface = b43_op_remove_interface,
4575 .config = b43_op_config,
4576 .bss_info_changed = b43_op_bss_info_changed,
4577 .configure_filter = b43_op_configure_filter,
4578 .set_key = b43_op_set_key,
4579 .update_tkip_key = b43_op_update_tkip_key,
4580 .get_stats = b43_op_get_stats,
4581 .get_tsf = b43_op_get_tsf,
4582 .set_tsf = b43_op_set_tsf,
4583 .start = b43_op_start,
4584 .stop = b43_op_stop,
4585 .set_tim = b43_op_beacon_set_tim,
4586 .sta_notify = b43_op_sta_notify,
4587 .sw_scan_start = b43_op_sw_scan_start_notifier,
4588 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
4589 .get_survey = b43_op_get_survey,
4590 .rfkill_poll = b43_rfkill_poll,
4591 };
4592
4593 /* Hard-reset the chip. Do not call this directly.
4594 * Use b43_controller_restart()
4595 */
4596 static void b43_chip_reset(struct work_struct *work)
4597 {
4598 struct b43_wldev *dev =
4599 container_of(work, struct b43_wldev, restart_work);
4600 struct b43_wl *wl = dev->wl;
4601 int err = 0;
4602 int prev_status;
4603
4604 mutex_lock(&wl->mutex);
4605
4606 prev_status = b43_status(dev);
4607 /* Bring the device down... */
4608 if (prev_status >= B43_STAT_STARTED) {
4609 dev = b43_wireless_core_stop(dev);
4610 if (!dev) {
4611 err = -ENODEV;
4612 goto out;
4613 }
4614 }
4615 if (prev_status >= B43_STAT_INITIALIZED)
4616 b43_wireless_core_exit(dev);
4617
4618 /* ...and up again. */
4619 if (prev_status >= B43_STAT_INITIALIZED) {
4620 err = b43_wireless_core_init(dev);
4621 if (err)
4622 goto out;
4623 }
4624 if (prev_status >= B43_STAT_STARTED) {
4625 err = b43_wireless_core_start(dev);
4626 if (err) {
4627 b43_wireless_core_exit(dev);
4628 goto out;
4629 }
4630 }
4631 out:
4632 if (err)
4633 wl->current_dev = NULL; /* Failed to init the dev. */
4634 mutex_unlock(&wl->mutex);
4635 if (err)
4636 b43err(wl, "Controller restart FAILED\n");
4637 else
4638 b43info(wl, "Controller restarted\n");
4639 }
4640
4641 static int b43_setup_bands(struct b43_wldev *dev,
4642 bool have_2ghz_phy, bool have_5ghz_phy)
4643 {
4644 struct ieee80211_hw *hw = dev->wl->hw;
4645
4646 if (have_2ghz_phy)
4647 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4648 if (dev->phy.type == B43_PHYTYPE_N) {
4649 if (have_5ghz_phy)
4650 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4651 } else {
4652 if (have_5ghz_phy)
4653 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4654 }
4655
4656 dev->phy.supports_2ghz = have_2ghz_phy;
4657 dev->phy.supports_5ghz = have_5ghz_phy;
4658
4659 return 0;
4660 }
4661
4662 static void b43_wireless_core_detach(struct b43_wldev *dev)
4663 {
4664 /* We release firmware that late to not be required to re-request
4665 * is all the time when we reinit the core. */
4666 b43_release_firmware(dev);
4667 b43_phy_free(dev);
4668 }
4669
4670 static int b43_wireless_core_attach(struct b43_wldev *dev)
4671 {
4672 struct b43_wl *wl = dev->wl;
4673 struct ssb_bus *bus = dev->dev->bus;
4674 struct pci_dev *pdev = (bus->bustype == SSB_BUSTYPE_PCI) ? bus->host_pci : NULL;
4675 int err;
4676 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4677 u32 tmp;
4678
4679 /* Do NOT do any device initialization here.
4680 * Do it in wireless_core_init() instead.
4681 * This function is for gathering basic information about the HW, only.
4682 * Also some structs may be set up here. But most likely you want to have
4683 * that in core_init(), too.
4684 */
4685
4686 err = ssb_bus_powerup(bus, 0);
4687 if (err) {
4688 b43err(wl, "Bus powerup failed\n");
4689 goto out;
4690 }
4691 /* Get the PHY type. */
4692 if (dev->dev->id.revision >= 5) {
4693 u32 tmshigh;
4694
4695 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
4696 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4697 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4698 } else
4699 B43_WARN_ON(1);
4700
4701 dev->phy.gmode = have_2ghz_phy;
4702 dev->phy.radio_on = 1;
4703 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4704 b43_wireless_core_reset(dev, tmp);
4705
4706 err = b43_phy_versioning(dev);
4707 if (err)
4708 goto err_powerdown;
4709 /* Check if this device supports multiband. */
4710 if (!pdev ||
4711 (pdev->device != 0x4312 &&
4712 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4713 /* No multiband support. */
4714 have_2ghz_phy = 0;
4715 have_5ghz_phy = 0;
4716 switch (dev->phy.type) {
4717 case B43_PHYTYPE_A:
4718 have_5ghz_phy = 1;
4719 break;
4720 case B43_PHYTYPE_LP:
4721 case B43_PHYTYPE_G:
4722 case B43_PHYTYPE_N:
4723 have_2ghz_phy = 1;
4724 break;
4725 default:
4726 B43_WARN_ON(1);
4727 }
4728 }
4729 if (dev->phy.type == B43_PHYTYPE_A) {
4730 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4731 err = -EOPNOTSUPP;
4732 goto err_powerdown;
4733 }
4734 if (1 /* disable A-PHY */) {
4735 if (dev->phy.type != B43_PHYTYPE_N &&
4736 dev->phy.type != B43_PHYTYPE_LP) {
4737 have_2ghz_phy = 1;
4738 have_5ghz_phy = 0;
4739 }
4740 }
4741
4742 err = b43_phy_allocate(dev);
4743 if (err)
4744 goto err_powerdown;
4745
4746 dev->phy.gmode = have_2ghz_phy;
4747 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4748 b43_wireless_core_reset(dev, tmp);
4749
4750 err = b43_validate_chipaccess(dev);
4751 if (err)
4752 goto err_phy_free;
4753 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4754 if (err)
4755 goto err_phy_free;
4756
4757 /* Now set some default "current_dev" */
4758 if (!wl->current_dev)
4759 wl->current_dev = dev;
4760 INIT_WORK(&dev->restart_work, b43_chip_reset);
4761
4762 dev->phy.ops->switch_analog(dev, 0);
4763 ssb_device_disable(dev->dev, 0);
4764 ssb_bus_may_powerdown(bus);
4765
4766 out:
4767 return err;
4768
4769 err_phy_free:
4770 b43_phy_free(dev);
4771 err_powerdown:
4772 ssb_bus_may_powerdown(bus);
4773 return err;
4774 }
4775
4776 static void b43_one_core_detach(struct ssb_device *dev)
4777 {
4778 struct b43_wldev *wldev;
4779 struct b43_wl *wl;
4780
4781 /* Do not cancel ieee80211-workqueue based work here.
4782 * See comment in b43_remove(). */
4783
4784 wldev = ssb_get_drvdata(dev);
4785 wl = wldev->wl;
4786 b43_debugfs_remove_device(wldev);
4787 b43_wireless_core_detach(wldev);
4788 list_del(&wldev->list);
4789 wl->nr_devs--;
4790 ssb_set_drvdata(dev, NULL);
4791 kfree(wldev);
4792 }
4793
4794 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4795 {
4796 struct b43_wldev *wldev;
4797 struct pci_dev *pdev;
4798 int err = -ENOMEM;
4799
4800 if (!list_empty(&wl->devlist)) {
4801 /* We are not the first core on this chip. */
4802 pdev = (dev->bus->bustype == SSB_BUSTYPE_PCI) ? dev->bus->host_pci : NULL;
4803 /* Only special chips support more than one wireless
4804 * core, although some of the other chips have more than
4805 * one wireless core as well. Check for this and
4806 * bail out early.
4807 */
4808 if (!pdev ||
4809 ((pdev->device != 0x4321) &&
4810 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4811 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4812 return -ENODEV;
4813 }
4814 }
4815
4816 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4817 if (!wldev)
4818 goto out;
4819
4820 wldev->use_pio = b43_modparam_pio;
4821 wldev->dev = dev;
4822 wldev->wl = wl;
4823 b43_set_status(wldev, B43_STAT_UNINIT);
4824 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4825 INIT_LIST_HEAD(&wldev->list);
4826
4827 err = b43_wireless_core_attach(wldev);
4828 if (err)
4829 goto err_kfree_wldev;
4830
4831 list_add(&wldev->list, &wl->devlist);
4832 wl->nr_devs++;
4833 ssb_set_drvdata(dev, wldev);
4834 b43_debugfs_add_device(wldev);
4835
4836 out:
4837 return err;
4838
4839 err_kfree_wldev:
4840 kfree(wldev);
4841 return err;
4842 }
4843
4844 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4845 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4846 (pdev->device == _device) && \
4847 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4848 (pdev->subsystem_device == _subdevice) )
4849
4850 static void b43_sprom_fixup(struct ssb_bus *bus)
4851 {
4852 struct pci_dev *pdev;
4853
4854 /* boardflags workarounds */
4855 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4856 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4857 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4858 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4859 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4860 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4861 if (bus->bustype == SSB_BUSTYPE_PCI) {
4862 pdev = bus->host_pci;
4863 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4864 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
4865 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
4866 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4867 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
4868 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4869 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
4870 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4871 }
4872 }
4873
4874 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4875 {
4876 struct ieee80211_hw *hw = wl->hw;
4877
4878 ssb_set_devtypedata(dev, NULL);
4879 ieee80211_free_hw(hw);
4880 }
4881
4882 static int b43_wireless_init(struct ssb_device *dev)
4883 {
4884 struct ssb_sprom *sprom = &dev->bus->sprom;
4885 struct ieee80211_hw *hw;
4886 struct b43_wl *wl;
4887 int err = -ENOMEM;
4888
4889 b43_sprom_fixup(dev->bus);
4890
4891 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4892 if (!hw) {
4893 b43err(NULL, "Could not allocate ieee80211 device\n");
4894 goto out;
4895 }
4896 wl = hw_to_b43_wl(hw);
4897
4898 /* fill hw info */
4899 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
4900 IEEE80211_HW_SIGNAL_DBM;
4901
4902 hw->wiphy->interface_modes =
4903 BIT(NL80211_IFTYPE_AP) |
4904 BIT(NL80211_IFTYPE_MESH_POINT) |
4905 BIT(NL80211_IFTYPE_STATION) |
4906 BIT(NL80211_IFTYPE_WDS) |
4907 BIT(NL80211_IFTYPE_ADHOC);
4908
4909 hw->queues = modparam_qos ? 4 : 1;
4910 wl->mac80211_initially_registered_queues = hw->queues;
4911 hw->max_rates = 2;
4912 SET_IEEE80211_DEV(hw, dev->dev);
4913 if (is_valid_ether_addr(sprom->et1mac))
4914 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4915 else
4916 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4917
4918 /* Initialize struct b43_wl */
4919 wl->hw = hw;
4920 mutex_init(&wl->mutex);
4921 spin_lock_init(&wl->hardirq_lock);
4922 INIT_LIST_HEAD(&wl->devlist);
4923 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
4924 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
4925 INIT_WORK(&wl->tx_work, b43_tx_work);
4926 skb_queue_head_init(&wl->tx_queue);
4927
4928 ssb_set_devtypedata(dev, wl);
4929 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
4930 dev->bus->chip_id, dev->id.revision);
4931 err = 0;
4932 out:
4933 return err;
4934 }
4935
4936 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4937 {
4938 struct b43_wl *wl;
4939 int err;
4940 int first = 0;
4941
4942 wl = ssb_get_devtypedata(dev);
4943 if (!wl) {
4944 /* Probing the first core. Must setup common struct b43_wl */
4945 first = 1;
4946 err = b43_wireless_init(dev);
4947 if (err)
4948 goto out;
4949 wl = ssb_get_devtypedata(dev);
4950 B43_WARN_ON(!wl);
4951 }
4952 err = b43_one_core_attach(dev, wl);
4953 if (err)
4954 goto err_wireless_exit;
4955
4956 if (first) {
4957 err = ieee80211_register_hw(wl->hw);
4958 if (err)
4959 goto err_one_core_detach;
4960 b43_leds_register(wl->current_dev);
4961 b43_rng_init(wl);
4962 }
4963
4964 out:
4965 return err;
4966
4967 err_one_core_detach:
4968 b43_one_core_detach(dev);
4969 err_wireless_exit:
4970 if (first)
4971 b43_wireless_exit(dev, wl);
4972 return err;
4973 }
4974
4975 static void b43_remove(struct ssb_device *dev)
4976 {
4977 struct b43_wl *wl = ssb_get_devtypedata(dev);
4978 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4979
4980 /* We must cancel any work here before unregistering from ieee80211,
4981 * as the ieee80211 unreg will destroy the workqueue. */
4982 cancel_work_sync(&wldev->restart_work);
4983
4984 B43_WARN_ON(!wl);
4985 if (wl->current_dev == wldev) {
4986 /* Restore the queues count before unregistering, because firmware detect
4987 * might have modified it. Restoring is important, so the networking
4988 * stack can properly free resources. */
4989 wl->hw->queues = wl->mac80211_initially_registered_queues;
4990 b43_leds_stop(wldev);
4991 ieee80211_unregister_hw(wl->hw);
4992 }
4993
4994 b43_one_core_detach(dev);
4995
4996 if (list_empty(&wl->devlist)) {
4997 b43_rng_exit(wl);
4998 b43_leds_unregister(wl);
4999 /* Last core on the chip unregistered.
5000 * We can destroy common struct b43_wl.
5001 */
5002 b43_wireless_exit(dev, wl);
5003 }
5004 }
5005
5006 /* Perform a hardware reset. This can be called from any context. */
5007 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5008 {
5009 /* Must avoid requeueing, if we are in shutdown. */
5010 if (b43_status(dev) < B43_STAT_INITIALIZED)
5011 return;
5012 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5013 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5014 }
5015
5016 static struct ssb_driver b43_ssb_driver = {
5017 .name = KBUILD_MODNAME,
5018 .id_table = b43_ssb_tbl,
5019 .probe = b43_probe,
5020 .remove = b43_remove,
5021 };
5022
5023 static void b43_print_driverinfo(void)
5024 {
5025 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5026 *feat_leds = "", *feat_sdio = "";
5027
5028 #ifdef CONFIG_B43_PCI_AUTOSELECT
5029 feat_pci = "P";
5030 #endif
5031 #ifdef CONFIG_B43_PCMCIA
5032 feat_pcmcia = "M";
5033 #endif
5034 #ifdef CONFIG_B43_NPHY
5035 feat_nphy = "N";
5036 #endif
5037 #ifdef CONFIG_B43_LEDS
5038 feat_leds = "L";
5039 #endif
5040 #ifdef CONFIG_B43_SDIO
5041 feat_sdio = "S";
5042 #endif
5043 printk(KERN_INFO "Broadcom 43xx driver loaded "
5044 "[ Features: %s%s%s%s%s, Firmware-ID: "
5045 B43_SUPPORTED_FIRMWARE_ID " ]\n",
5046 feat_pci, feat_pcmcia, feat_nphy,
5047 feat_leds, feat_sdio);
5048 }
5049
5050 static int __init b43_init(void)
5051 {
5052 int err;
5053
5054 b43_debugfs_init();
5055 err = b43_pcmcia_init();
5056 if (err)
5057 goto err_dfs_exit;
5058 err = b43_sdio_init();
5059 if (err)
5060 goto err_pcmcia_exit;
5061 err = ssb_driver_register(&b43_ssb_driver);
5062 if (err)
5063 goto err_sdio_exit;
5064 b43_print_driverinfo();
5065
5066 return err;
5067
5068 err_sdio_exit:
5069 b43_sdio_exit();
5070 err_pcmcia_exit:
5071 b43_pcmcia_exit();
5072 err_dfs_exit:
5073 b43_debugfs_exit();
5074 return err;
5075 }
5076
5077 static void __exit b43_exit(void)
5078 {
5079 ssb_driver_unregister(&b43_ssb_driver);
5080 b43_sdio_exit();
5081 b43_pcmcia_exit();
5082 b43_debugfs_exit();
5083 }
5084
5085 module_init(b43_init)
5086 module_exit(b43_exit)
Tomato firmware and modifications.