2 * Copyright (c) 2008-2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
35 #define ATHEROS_VENDOR_ID 0x168c
37 #define AR5416_DEVID_PCI 0x0023
38 #define AR5416_DEVID_PCIE 0x0024
39 #define AR9160_DEVID_PCI 0x0027
40 #define AR9280_DEVID_PCI 0x0029
41 #define AR9280_DEVID_PCIE 0x002a
42 #define AR9285_DEVID_PCIE 0x002b
43 #define AR2427_DEVID_PCIE 0x002c
44 #define AR9287_DEVID_PCI 0x002d
45 #define AR9287_DEVID_PCIE 0x002e
46 #define AR9300_DEVID_PCIE 0x0030
48 #define AR5416_AR9100_DEVID 0x000b
50 #define AR_SUBVENDOR_ID_NOG 0x0e11
51 #define AR_SUBVENDOR_ID_NEW_A 0x7065
52 #define AR5416_MAGIC 0x19641014
54 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
55 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
56 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
58 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
60 #define ATH_DEFAULT_NOISE_FLOOR -95
62 #define ATH9K_RSSI_BAD -128
64 /* Register read/write primitives */
65 #define REG_WRITE(_ah, _reg, _val) \
66 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
68 #define REG_READ(_ah, _reg) \
69 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
71 #define ENABLE_REGWRITE_BUFFER(_ah) \
73 if (AR_SREV_9271(_ah)) \
74 ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
77 #define DISABLE_REGWRITE_BUFFER(_ah) \
79 if (AR_SREV_9271(_ah)) \
80 ath9k_hw_common(_ah)->ops->disable_write_buffer((_ah)); \
83 #define REGWRITE_BUFFER_FLUSH(_ah) \
85 if (AR_SREV_9271(_ah)) \
86 ath9k_hw_common(_ah)->ops->write_flush((_ah)); \
89 #define SM(_v, _f) (((_v) << _f##_S) & _f)
90 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
91 #define REG_RMW(_a, _r, _set, _clr) \
92 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
93 #define REG_RMW_FIELD(_a, _r, _f, _v) \
95 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
96 #define REG_READ_FIELD(_a, _r, _f) \
97 (((REG_READ(_a, _r) & _f) >> _f##_S))
98 #define REG_SET_BIT(_a, _r, _f) \
99 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
100 #define REG_CLR_BIT(_a, _r, _f) \
101 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
103 #define DO_DELAY(x) do { \
104 if ((++(x) % 64) == 0) \
108 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
110 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
111 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
112 INI_RA((iniarray), r, (column))); \
117 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
118 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
119 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
120 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
121 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
122 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
123 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
125 #define AR_GPIOD_MASK 0x00001FFF
126 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
128 #define BASE_ACTIVATE_DELAY 100
129 #define RTC_PLL_SETTLE_DELAY 100
130 #define COEF_SCALE_S 24
131 #define HT40_CHANNEL_CENTER_SHIFT 10
133 #define ATH9K_ANTENNA0_CHAINMASK 0x1
134 #define ATH9K_ANTENNA1_CHAINMASK 0x2
136 #define ATH9K_NUM_DMA_DEBUG_REGS 8
137 #define ATH9K_NUM_QUEUES 10
139 #define MAX_RATE_POWER 63
140 #define AH_WAIT_TIMEOUT 100000 /* (us) */
141 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
142 #define AH_TIME_QUANTUM 10
143 #define AR_KEYTABLE_SIZE 128
144 #define POWER_UP_TIME 10000
145 #define SPUR_RSSI_THRESH 40
147 #define CAB_TIMEOUT_VAL 10
148 #define BEACON_TIMEOUT_VAL 10
149 #define MIN_BEACON_TIMEOUT_VAL 1
152 #define INIT_CONFIG_STATUS 0x00000000
153 #define INIT_RSSI_THR 0x00000700
154 #define INIT_BCON_CNTRL_REG 0x00000000
156 #define TU_TO_USEC(_tu) ((_tu) << 10)
158 #define ATH9K_HW_RX_HP_QDEPTH 16
159 #define ATH9K_HW_RX_LP_QDEPTH 128
161 #define PAPRD_GAIN_TABLE_ENTRIES 32
162 #define PAPRD_TABLE_SZ 24
164 enum ath_ini_subsys
{
174 ATH9K_MODE_11NA_HT20
,
175 ATH9K_MODE_11NG_HT20
,
176 ATH9K_MODE_11NA_HT40PLUS
,
177 ATH9K_MODE_11NA_HT40MINUS
,
178 ATH9K_MODE_11NG_HT40PLUS
,
179 ATH9K_MODE_11NG_HT40MINUS
,
184 ATH9K_HW_CAP_MIC_AESCCM
= BIT(0),
185 ATH9K_HW_CAP_MIC_CKIP
= BIT(1),
186 ATH9K_HW_CAP_MIC_TKIP
= BIT(2),
187 ATH9K_HW_CAP_CIPHER_AESCCM
= BIT(3),
188 ATH9K_HW_CAP_CIPHER_CKIP
= BIT(4),
189 ATH9K_HW_CAP_CIPHER_TKIP
= BIT(5),
190 ATH9K_HW_CAP_VEOL
= BIT(6),
191 ATH9K_HW_CAP_BSSIDMASK
= BIT(7),
192 ATH9K_HW_CAP_MCAST_KEYSEARCH
= BIT(8),
193 ATH9K_HW_CAP_HT
= BIT(9),
194 ATH9K_HW_CAP_GTT
= BIT(10),
195 ATH9K_HW_CAP_FASTCC
= BIT(11),
196 ATH9K_HW_CAP_RFSILENT
= BIT(12),
197 ATH9K_HW_CAP_CST
= BIT(13),
198 ATH9K_HW_CAP_ENHANCEDPM
= BIT(14),
199 ATH9K_HW_CAP_AUTOSLEEP
= BIT(15),
200 ATH9K_HW_CAP_4KB_SPLITTRANS
= BIT(16),
201 ATH9K_HW_CAP_EDMA
= BIT(17),
202 ATH9K_HW_CAP_RAC_SUPPORTED
= BIT(18),
203 ATH9K_HW_CAP_LDPC
= BIT(19),
204 ATH9K_HW_CAP_FASTCLOCK
= BIT(20),
205 ATH9K_HW_CAP_SGI_20
= BIT(21),
206 ATH9K_HW_CAP_PAPRD
= BIT(22),
209 struct ath9k_hw_capabilities
{
210 u32 hw_caps
; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
211 DECLARE_BITMAP(wireless_modes
, ATH9K_MODE_MAX
); /* ATH9K_MODE_* */
214 u16 low_5ghz_chan
, high_5ghz_chan
;
215 u16 low_2ghz_chan
, high_2ghz_chan
;
219 u16 tx_triglevel_max
;
231 struct ath9k_ops_config
{
232 int dma_beacon_response_time
;
233 int sw_beacon_response_time
;
234 int additional_swba_backoff
;
236 u32 cwm_ignore_extcca
;
237 u8 pcie_powersave_enable
;
238 bool pcieSerDesWrite
;
249 int serialize_regmode
;
250 bool rx_intr_mitigation
;
251 bool tx_intr_mitigation
;
252 #define SPUR_DISABLE 0
253 #define SPUR_ENABLE_IOCTL 1
254 #define SPUR_ENABLE_EEPROM 2
255 #define AR_EEPROM_MODAL_SPURS 5
256 #define AR_SPUR_5413_1 1640
257 #define AR_SPUR_5413_2 1200
258 #define AR_NO_SPUR 0x8000
259 #define AR_BASE_FREQ_2GHZ 2300
260 #define AR_BASE_FREQ_5GHZ 4900
261 #define AR_SPUR_FEEQ_BOUND_HT40 19
262 #define AR_SPUR_FEEQ_BOUND_HT20 10
264 u16 spurchans
[AR_EEPROM_MODAL_SPURS
][2];
266 u16 ani_poll_interval
; /* ANI poll interval in ms */
270 ATH9K_INT_RX
= 0x00000001,
271 ATH9K_INT_RXDESC
= 0x00000002,
272 ATH9K_INT_RXHP
= 0x00000001,
273 ATH9K_INT_RXLP
= 0x00000002,
274 ATH9K_INT_RXNOFRM
= 0x00000008,
275 ATH9K_INT_RXEOL
= 0x00000010,
276 ATH9K_INT_RXORN
= 0x00000020,
277 ATH9K_INT_TX
= 0x00000040,
278 ATH9K_INT_TXDESC
= 0x00000080,
279 ATH9K_INT_TIM_TIMER
= 0x00000100,
280 ATH9K_INT_BB_WATCHDOG
= 0x00000400,
281 ATH9K_INT_TXURN
= 0x00000800,
282 ATH9K_INT_MIB
= 0x00001000,
283 ATH9K_INT_RXPHY
= 0x00004000,
284 ATH9K_INT_RXKCM
= 0x00008000,
285 ATH9K_INT_SWBA
= 0x00010000,
286 ATH9K_INT_BMISS
= 0x00040000,
287 ATH9K_INT_BNR
= 0x00100000,
288 ATH9K_INT_TIM
= 0x00200000,
289 ATH9K_INT_DTIM
= 0x00400000,
290 ATH9K_INT_DTIMSYNC
= 0x00800000,
291 ATH9K_INT_GPIO
= 0x01000000,
292 ATH9K_INT_CABEND
= 0x02000000,
293 ATH9K_INT_TSFOOR
= 0x04000000,
294 ATH9K_INT_GENTIMER
= 0x08000000,
295 ATH9K_INT_CST
= 0x10000000,
296 ATH9K_INT_GTT
= 0x20000000,
297 ATH9K_INT_FATAL
= 0x40000000,
298 ATH9K_INT_GLOBAL
= 0x80000000,
299 ATH9K_INT_BMISC
= ATH9K_INT_TIM
|
304 ATH9K_INT_COMMON
= ATH9K_INT_RXNOFRM
|
316 ATH9K_INT_NOCARD
= 0xffffffff
319 #define CHANNEL_CW_INT 0x00002
320 #define CHANNEL_CCK 0x00020
321 #define CHANNEL_OFDM 0x00040
322 #define CHANNEL_2GHZ 0x00080
323 #define CHANNEL_5GHZ 0x00100
324 #define CHANNEL_PASSIVE 0x00200
325 #define CHANNEL_DYN 0x00400
326 #define CHANNEL_HALF 0x04000
327 #define CHANNEL_QUARTER 0x08000
328 #define CHANNEL_HT20 0x10000
329 #define CHANNEL_HT40PLUS 0x20000
330 #define CHANNEL_HT40MINUS 0x40000
332 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
333 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
334 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
335 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
336 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
337 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
338 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
339 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
340 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
341 #define CHANNEL_ALL \
350 struct ath9k_hw_cal_data
{
356 int16_t rawNoiseFloor
;
359 u16 small_signal_gain
[AR9300_MAX_CHAINS
];
360 u32 pa_table
[AR9300_MAX_CHAINS
][PAPRD_TABLE_SZ
];
361 struct ath9k_nfcal_hist nfCalHist
[NUM_NF_READINGS
];
364 struct ath9k_channel
{
365 struct ieee80211_channel
*chan
;
371 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
372 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
373 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
374 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
375 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
376 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
377 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
378 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
379 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
380 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
381 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
382 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
384 /* These macros check chanmode and not channelFlags */
385 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
386 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
387 ((_c)->chanmode == CHANNEL_G_HT20))
388 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
389 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
390 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
391 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
392 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
394 enum ath9k_power_mode
{
397 ATH9K_PM_NETWORK_SLEEP
,
401 enum ath9k_tp_scale
{
402 ATH9K_TP_SCALE_MAX
= 0,
410 SER_REG_MODE_OFF
= 0,
412 SER_REG_MODE_AUTO
= 2,
415 enum ath9k_rx_qtype
{
421 struct ath9k_beacon_state
{
425 #define ATH9K_BEACON_PERIOD 0x0000ffff
426 #define ATH9K_BEACON_ENA 0x00800000
427 #define ATH9K_BEACON_RESET_TSF 0x01000000
428 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
431 u16 bs_cfpmaxduration
;
434 u16 bs_bmissthreshold
;
435 u32 bs_sleepduration
;
436 u32 bs_tsfoor_threshold
;
439 struct chan_centers
{
446 ATH9K_RESET_POWER_ON
,
451 struct ath9k_hw_version
{
463 /* Generic TSF timer definitions */
465 #define ATH_MAX_GEN_TIMER 16
467 #define AR_GENTMR_BIT(_index) (1 << (_index))
470 * Using de Bruijin sequence to look up 1's index in a 32 bit number
471 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
473 #define debruijn32 0x077CB531U
475 struct ath_gen_timer_configuration
{
482 struct ath_gen_timer
{
483 void (*trigger
)(void *arg
);
484 void (*overflow
)(void *arg
);
489 struct ath_gen_timer_table
{
490 u32 gen_timer_index
[32];
491 struct ath_gen_timer
*timers
[ATH_MAX_GEN_TIMER
];
493 unsigned long timer_bits
;
499 * struct ath_hw_private_ops - callbacks used internally by hardware code
501 * This structure contains private callbacks designed to only be used internally
502 * by the hardware core.
504 * @init_cal_settings: setup types of calibrations supported
505 * @init_cal: starts actual calibration
507 * @init_mode_regs: Initializes mode registers
508 * @init_mode_gain_regs: Initialize TX/RX gain registers
509 * @macversion_supported: If this specific mac revision is supported
511 * @rf_set_freq: change frequency
512 * @spur_mitigate_freq: spur mitigation
513 * @rf_alloc_ext_banks:
514 * @rf_free_ext_banks:
516 * @compute_pll_control: compute the PLL control value to use for
517 * AR_RTC_PLL_CONTROL for a given channel
518 * @setup_calibration: set up calibration
519 * @iscal_supported: used to query if a type of calibration is supported
521 * @ani_reset: reset ANI parameters to default values
522 * @ani_lower_immunity: lower the noise immunity level. The level controls
523 * the power-based packet detection on hardware. If a power jump is
524 * detected the adapter takes it as an indication that a packet has
525 * arrived. The level ranges from 0-5. Each level corresponds to a
526 * few dB more of noise immunity. If you have a strong time-varying
527 * interference that is causing false detections (OFDM timing errors or
528 * CCK timing errors) the level can be increased.
529 * @ani_cache_ini_regs: cache the values for ANI from the initial
530 * register settings through the register initialization.
532 struct ath_hw_private_ops
{
533 /* Calibration ops */
534 void (*init_cal_settings
)(struct ath_hw
*ah
);
535 bool (*init_cal
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
537 void (*init_mode_regs
)(struct ath_hw
*ah
);
538 void (*init_mode_gain_regs
)(struct ath_hw
*ah
);
539 bool (*macversion_supported
)(u32 macversion
);
540 void (*setup_calibration
)(struct ath_hw
*ah
,
541 struct ath9k_cal_list
*currCal
);
542 bool (*iscal_supported
)(struct ath_hw
*ah
,
543 enum ath9k_cal_types calType
);
546 int (*rf_set_freq
)(struct ath_hw
*ah
,
547 struct ath9k_channel
*chan
);
548 void (*spur_mitigate_freq
)(struct ath_hw
*ah
,
549 struct ath9k_channel
*chan
);
550 int (*rf_alloc_ext_banks
)(struct ath_hw
*ah
);
551 void (*rf_free_ext_banks
)(struct ath_hw
*ah
);
552 bool (*set_rf_regs
)(struct ath_hw
*ah
,
553 struct ath9k_channel
*chan
,
555 void (*set_channel_regs
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
556 void (*init_bb
)(struct ath_hw
*ah
,
557 struct ath9k_channel
*chan
);
558 int (*process_ini
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
559 void (*olc_init
)(struct ath_hw
*ah
);
560 void (*set_rfmode
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
561 void (*mark_phy_inactive
)(struct ath_hw
*ah
);
562 void (*set_delta_slope
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
563 bool (*rfbus_req
)(struct ath_hw
*ah
);
564 void (*rfbus_done
)(struct ath_hw
*ah
);
565 void (*enable_rfkill
)(struct ath_hw
*ah
);
566 void (*restore_chainmask
)(struct ath_hw
*ah
);
567 void (*set_diversity
)(struct ath_hw
*ah
, bool value
);
568 u32 (*compute_pll_control
)(struct ath_hw
*ah
,
569 struct ath9k_channel
*chan
);
570 bool (*ani_control
)(struct ath_hw
*ah
, enum ath9k_ani_cmd cmd
,
572 void (*do_getnf
)(struct ath_hw
*ah
, int16_t nfarray
[NUM_NF_READINGS
]);
575 void (*ani_reset
)(struct ath_hw
*ah
, bool is_scanning
);
576 void (*ani_lower_immunity
)(struct ath_hw
*ah
);
577 void (*ani_cache_ini_regs
)(struct ath_hw
*ah
);
581 * struct ath_hw_ops - callbacks used by hardware code and driver code
583 * This structure contains callbacks designed to to be used internally by
584 * hardware code and also by the lower level driver.
586 * @config_pci_powersave:
587 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
589 * @ani_proc_mib_event: process MIB events, this would happen upon specific ANI
590 * thresholds being reached or having overflowed.
591 * @ani_monitor: called periodically by the core driver to collect
592 * MIB stats and adjust ANI if specific thresholds have been reached.
595 void (*config_pci_powersave
)(struct ath_hw
*ah
,
598 void (*rx_enable
)(struct ath_hw
*ah
);
599 void (*set_desc_link
)(void *ds
, u32 link
);
600 void (*get_desc_link
)(void *ds
, u32
**link
);
601 bool (*calibrate
)(struct ath_hw
*ah
,
602 struct ath9k_channel
*chan
,
605 bool (*get_isr
)(struct ath_hw
*ah
, enum ath9k_int
*masked
);
606 void (*fill_txdesc
)(struct ath_hw
*ah
, void *ds
, u32 seglen
,
607 bool is_firstseg
, bool is_is_lastseg
,
608 const void *ds0
, dma_addr_t buf_addr
,
610 int (*proc_txdesc
)(struct ath_hw
*ah
, void *ds
,
611 struct ath_tx_status
*ts
);
612 void (*set11n_txdesc
)(struct ath_hw
*ah
, void *ds
,
613 u32 pktLen
, enum ath9k_pkt_type type
,
614 u32 txPower
, u32 keyIx
,
615 enum ath9k_key_type keyType
,
617 void (*set11n_ratescenario
)(struct ath_hw
*ah
, void *ds
,
619 u32 durUpdateEn
, u32 rtsctsRate
,
621 struct ath9k_11n_rate_series series
[],
622 u32 nseries
, u32 flags
);
623 void (*set11n_aggr_first
)(struct ath_hw
*ah
, void *ds
,
625 void (*set11n_aggr_middle
)(struct ath_hw
*ah
, void *ds
,
627 void (*set11n_aggr_last
)(struct ath_hw
*ah
, void *ds
);
628 void (*clr11n_aggr
)(struct ath_hw
*ah
, void *ds
);
629 void (*set11n_burstduration
)(struct ath_hw
*ah
, void *ds
,
631 void (*set11n_virtualmorefrag
)(struct ath_hw
*ah
, void *ds
,
634 void (*ani_proc_mib_event
)(struct ath_hw
*ah
);
635 void (*ani_monitor
)(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
638 struct ath_nf_limits
{
645 struct ieee80211_hw
*hw
;
646 struct ath_common common
;
647 struct ath9k_hw_version hw_version
;
648 struct ath9k_ops_config config
;
649 struct ath9k_hw_capabilities caps
;
650 struct ath9k_channel channels
[38];
651 struct ath9k_channel
*curchan
;
654 struct ar5416_eeprom_def def
;
655 struct ar5416_eeprom_4k map4k
;
656 struct ar9287_eeprom map9287
;
657 struct ar9300_eeprom ar9300_eep
;
659 const struct eeprom_ops
*eep_ops
;
663 bool need_an_top2_fixup
;
667 struct ath_nf_limits nf_2g
;
668 struct ath_nf_limits nf_5g
;
676 enum nl80211_iftype opmode
;
677 enum ath9k_power_mode power_mode
;
679 struct ath9k_hw_cal_data
*caldata
;
680 struct ath9k_pacal_info pacal_info
;
681 struct ar5416Stats stats
;
682 struct ath9k_tx_queue_info txq
[ATH9K_NUM_TX_QUEUES
];
684 int16_t curchan_rad_index
;
685 enum ath9k_int imask
;
687 u32 txok_interrupt_mask
;
688 u32 txerr_interrupt_mask
;
689 u32 txdesc_interrupt_mask
;
690 u32 txeol_interrupt_mask
;
691 u32 txurn_interrupt_mask
;
696 enum ath9k_cal_types supp_cals
;
697 struct ath9k_cal_list iq_caldata
;
698 struct ath9k_cal_list adcgain_caldata
;
699 struct ath9k_cal_list adcdc_calinitdata
;
700 struct ath9k_cal_list adcdc_caldata
;
701 struct ath9k_cal_list tempCompCalData
;
702 struct ath9k_cal_list
*cal_list
;
703 struct ath9k_cal_list
*cal_list_last
;
704 struct ath9k_cal_list
*cal_list_curr
;
705 #define totalPowerMeasI meas0.unsign
706 #define totalPowerMeasQ meas1.unsign
707 #define totalIqCorrMeas meas2.sign
708 #define totalAdcIOddPhase meas0.unsign
709 #define totalAdcIEvenPhase meas1.unsign
710 #define totalAdcQOddPhase meas2.unsign
711 #define totalAdcQEvenPhase meas3.unsign
712 #define totalAdcDcOffsetIOddPhase meas0.sign
713 #define totalAdcDcOffsetIEvenPhase meas1.sign
714 #define totalAdcDcOffsetQOddPhase meas2.sign
715 #define totalAdcDcOffsetQEvenPhase meas3.sign
717 u32 unsign
[AR5416_MAX_CHAINS
];
718 int32_t sign
[AR5416_MAX_CHAINS
];
721 u32 unsign
[AR5416_MAX_CHAINS
];
722 int32_t sign
[AR5416_MAX_CHAINS
];
725 u32 unsign
[AR5416_MAX_CHAINS
];
726 int32_t sign
[AR5416_MAX_CHAINS
];
729 u32 unsign
[AR5416_MAX_CHAINS
];
730 int32_t sign
[AR5416_MAX_CHAINS
];
734 u32 sta_id1_defaults
;
740 } enable_32kHz_clock
;
742 /* Private to hardware code */
743 struct ath_hw_private_ops private_ops
;
744 /* Accessed by the lower level driver */
745 struct ath_hw_ops ops
;
747 /* Used to program the radio on non single-chip devices */
748 u32
*analogBank0Data
;
749 u32
*analogBank1Data
;
750 u32
*analogBank2Data
;
751 u32
*analogBank3Data
;
752 u32
*analogBank6Data
;
753 u32
*analogBank6TPCData
;
754 u32
*analogBank7Data
;
759 int16_t txpower_indexoffset
;
768 struct ar5416AniState
*curani
;
769 struct ar5416AniState ani
[255];
770 int totalSizeDesired
[5];
774 enum ath9k_ani_cmd ani_function
;
776 /* Bluetooth coexistance */
777 struct ath_btcoex_hw btcoex_hw
;
783 u32 originalGain
[22];
788 struct ar5416IniArray iniModes
;
789 struct ar5416IniArray iniCommon
;
790 struct ar5416IniArray iniBank0
;
791 struct ar5416IniArray iniBB_RfGain
;
792 struct ar5416IniArray iniBank1
;
793 struct ar5416IniArray iniBank2
;
794 struct ar5416IniArray iniBank3
;
795 struct ar5416IniArray iniBank6
;
796 struct ar5416IniArray iniBank6TPC
;
797 struct ar5416IniArray iniBank7
;
798 struct ar5416IniArray iniAddac
;
799 struct ar5416IniArray iniPcieSerdes
;
800 struct ar5416IniArray iniPcieSerdesLowPower
;
801 struct ar5416IniArray iniModesAdditional
;
802 struct ar5416IniArray iniModesRxGain
;
803 struct ar5416IniArray iniModesTxGain
;
804 struct ar5416IniArray iniModes_9271_1_0_only
;
805 struct ar5416IniArray iniCckfirNormal
;
806 struct ar5416IniArray iniCckfirJapan2484
;
807 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271
;
808 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271
;
809 struct ar5416IniArray iniModes_9271_ANI_reg
;
810 struct ar5416IniArray iniModes_high_power_tx_gain_9271
;
811 struct ar5416IniArray iniModes_normal_power_tx_gain_9271
;
813 struct ar5416IniArray iniMac
[ATH_INI_NUM_SPLIT
];
814 struct ar5416IniArray iniBB
[ATH_INI_NUM_SPLIT
];
815 struct ar5416IniArray iniRadio
[ATH_INI_NUM_SPLIT
];
816 struct ar5416IniArray iniSOC
[ATH_INI_NUM_SPLIT
];
818 u32 intr_gen_timer_trigger
;
819 u32 intr_gen_timer_thresh
;
820 struct ath_gen_timer_table hw_gen_timers
;
822 struct ar9003_txs
*ts_ring
;
829 u32 bb_watchdog_last_status
;
830 u32 bb_watchdog_timeout_ms
; /* in ms, 0 to disable */
832 u32 paprd_gain_table_entries
[PAPRD_GAIN_TABLE_ENTRIES
];
833 u8 paprd_gain_table_index
[PAPRD_GAIN_TABLE_ENTRIES
];
835 * Store the permanent value of Reg 0x4004in WARegVal
836 * so we dont have to R/M/W. We should not be reading
837 * this register when in sleep states.
842 static inline struct ath_common
*ath9k_hw_common(struct ath_hw
*ah
)
847 static inline struct ath_regulatory
*ath9k_hw_regulatory(struct ath_hw
*ah
)
849 return &(ath9k_hw_common(ah
)->regulatory
);
852 static inline struct ath_hw_private_ops
*ath9k_hw_private_ops(struct ath_hw
*ah
)
854 return &ah
->private_ops
;
857 static inline struct ath_hw_ops
*ath9k_hw_ops(struct ath_hw
*ah
)
862 static inline int sign_extend(int val
, const int nbits
)
864 int order
= BIT(nbits
-1);
865 return (val
^ order
) - order
;
868 /* Initialization, Detach, Reset */
869 const char *ath9k_hw_probe(u16 vendorid
, u16 devid
);
870 void ath9k_hw_deinit(struct ath_hw
*ah
);
871 int ath9k_hw_init(struct ath_hw
*ah
);
872 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
873 struct ath9k_hw_cal_data
*caldata
, bool bChannelChange
);
874 int ath9k_hw_fill_cap_info(struct ath_hw
*ah
);
875 u32
ath9k_regd_get_ctl(struct ath_regulatory
*reg
, struct ath9k_channel
*chan
);
877 /* Key Cache Management */
878 bool ath9k_hw_keyreset(struct ath_hw
*ah
, u16 entry
);
879 bool ath9k_hw_set_keycache_entry(struct ath_hw
*ah
, u16 entry
,
880 const struct ath9k_keyval
*k
,
883 /* GPIO / RFKILL / Antennae */
884 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
);
885 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
);
886 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
888 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
);
889 u32
ath9k_hw_getdefantenna(struct ath_hw
*ah
);
890 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
);
892 /* General Operation */
893 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
);
894 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
);
895 bool ath9k_get_channel_edges(struct ath_hw
*ah
, u16 flags
, u16
*low
, u16
*high
);
896 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
898 u32 frameLen
, u16 rateix
, bool shortPreamble
);
899 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
900 struct ath9k_channel
*chan
,
901 struct chan_centers
*centers
);
902 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
);
903 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
);
904 bool ath9k_hw_phy_disable(struct ath_hw
*ah
);
905 bool ath9k_hw_disable(struct ath_hw
*ah
);
906 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
);
907 void ath9k_hw_setopmode(struct ath_hw
*ah
);
908 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
);
909 void ath9k_hw_setbssidmask(struct ath_hw
*ah
);
910 void ath9k_hw_write_associd(struct ath_hw
*ah
);
911 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
);
912 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
);
913 void ath9k_hw_reset_tsf(struct ath_hw
*ah
);
914 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
);
915 void ath9k_hw_init_global_settings(struct ath_hw
*ah
);
916 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
);
917 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
);
918 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
919 const struct ath9k_beacon_state
*bs
);
920 bool ath9k_hw_check_alive(struct ath_hw
*ah
);
922 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
);
924 /* Generic hw timer primitives */
925 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
926 void (*trigger
)(void *),
927 void (*overflow
)(void *),
930 void ath9k_hw_gen_timer_start(struct ath_hw
*ah
,
931 struct ath_gen_timer
*timer
,
934 void ath9k_hw_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
);
936 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
);
937 void ath_gen_timer_isr(struct ath_hw
*hw
);
938 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
);
940 void ath9k_hw_name(struct ath_hw
*ah
, char *hw_name
, size_t len
);
943 void ath9k_hw_htc_resetinit(struct ath_hw
*ah
);
946 void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
, u32 coef_scaled
,
947 u32
*coef_mantissa
, u32
*coef_exponent
);
950 * Code Specific to AR5008, AR9001 or AR9002,
951 * we stuff these here to avoid callbacks for AR9003.
953 void ar9002_hw_cck_chan14_spread(struct ath_hw
*ah
);
954 int ar9002_hw_rf_claim(struct ath_hw
*ah
);
955 void ar9002_hw_enable_async_fifo(struct ath_hw
*ah
);
956 void ar9002_hw_update_async_fifo(struct ath_hw
*ah
);
957 void ar9002_hw_enable_wep_aggregation(struct ath_hw
*ah
);
960 * Code specific to AR9003, we stuff these here to avoid callbacks
963 void ar9003_hw_bb_watchdog_config(struct ath_hw
*ah
);
964 void ar9003_hw_bb_watchdog_read(struct ath_hw
*ah
);
965 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw
*ah
);
966 void ar9003_paprd_enable(struct ath_hw
*ah
, bool val
);
967 void ar9003_paprd_populate_single_table(struct ath_hw
*ah
,
968 struct ath9k_hw_cal_data
*caldata
,
970 int ar9003_paprd_create_curve(struct ath_hw
*ah
,
971 struct ath9k_hw_cal_data
*caldata
, int chain
);
972 int ar9003_paprd_setup_gain_table(struct ath_hw
*ah
, int chain
);
973 int ar9003_paprd_init_table(struct ath_hw
*ah
);
974 bool ar9003_paprd_is_done(struct ath_hw
*ah
);
975 void ar9003_hw_set_paprd_txdesc(struct ath_hw
*ah
, void *ds
, u8 chains
);
977 /* Hardware family op attach helpers */
978 void ar5008_hw_attach_phy_ops(struct ath_hw
*ah
);
979 void ar9002_hw_attach_phy_ops(struct ath_hw
*ah
);
980 void ar9003_hw_attach_phy_ops(struct ath_hw
*ah
);
982 void ar9002_hw_attach_calib_ops(struct ath_hw
*ah
);
983 void ar9003_hw_attach_calib_ops(struct ath_hw
*ah
);
985 void ar9002_hw_attach_ops(struct ath_hw
*ah
);
986 void ar9003_hw_attach_ops(struct ath_hw
*ah
);
989 * ANI work can be shared between all families but a next
990 * generation implementation of ANI will be used only for AR9003 only
991 * for now as the other families still need to be tested with the same
992 * next generation ANI. Feel free to start testing it though for the
993 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
995 extern int modparam_force_new_ani
;
996 void ath9k_hw_attach_ani_ops_old(struct ath_hw
*ah
);
997 void ath9k_hw_attach_ani_ops_new(struct ath_hw
*ah
);
999 #define ATH_PCIE_CAP_LINK_CTRL 0x70
1000 #define ATH_PCIE_CAP_LINK_L0S 1
1001 #define ATH_PCIE_CAP_LINK_L1 2
1003 #define ATH9K_CLOCK_RATE_CCK 22
1004 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1005 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1006 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44