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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / wireless / ath / ath5k / phy.c
blob7543a96d5b1deacd765fab260f60b6cafdc59dd1
1 /*
2 * PHY functions
3 *
4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25
26 #include "ath5k.h"
27 #include "reg.h"
28 #include "base.h"
29 #include "rfbuffer.h"
30 #include "rfgain.h"
31
32 /*
33 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
34 */
35 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
36 const struct ath5k_rf_reg *rf_regs,
37 u32 val, u8 reg_id, bool set)
38 {
39 const struct ath5k_rf_reg *rfreg = NULL;
40 u8 offset, bank, num_bits, col, position;
41 u16 entry;
42 u32 mask, data, last_bit, bits_shifted, first_bit;
43 u32 *rfb;
44 s32 bits_left;
45 int i;
46
47 data = 0;
48 rfb = ah->ah_rf_banks;
49
50 for (i = 0; i < ah->ah_rf_regs_count; i++) {
51 if (rf_regs[i].index == reg_id) {
52 rfreg = &rf_regs[i];
53 break;
54 }
55 }
56
57 if (rfb == NULL || rfreg == NULL) {
58 ATH5K_PRINTF("Rf register not found!\n");
59 /* should not happen */
60 return 0;
61 }
62
63 bank = rfreg->bank;
64 num_bits = rfreg->field.len;
65 first_bit = rfreg->field.pos;
66 col = rfreg->field.col;
67
68 /* first_bit is an offset from bank's
69 * start. Since we have all banks on
70 * the same array, we use this offset
71 * to mark each bank's start */
72 offset = ah->ah_offset[bank];
73
74 /* Boundary check */
75 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
76 ATH5K_PRINTF("invalid values at offset %u\n", offset);
77 return 0;
78 }
79
80 entry = ((first_bit - 1) / 8) + offset;
81 position = (first_bit - 1) % 8;
82
83 if (set)
84 data = ath5k_hw_bitswap(val, num_bits);
85
86 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
87 position = 0, entry++) {
88
89 last_bit = (position + bits_left > 8) ? 8 :
90 position + bits_left;
91
92 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
93 (col * 8);
94
95 if (set) {
96 rfb[entry] &= ~mask;
97 rfb[entry] |= ((data << position) << (col * 8)) & mask;
98 data >>= (8 - position);
99 } else {
100 data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
101 << bits_shifted;
102 bits_shifted += last_bit - position;
103 }
104
105 bits_left -= 8 - position;
106 }
107
108 data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
109
110 return data;
111 }
112
113 /**********************\
114 * RF Gain optimization *
115 \**********************/
116
117 /*
118 * This code is used to optimize rf gain on different environments
119 * (temperature mostly) based on feedback from a power detector.
120 *
121 * It's only used on RF5111 and RF5112, later RF chips seem to have
122 * auto adjustment on hw -notice they have a much smaller BANK 7 and
123 * no gain optimization ladder-.
124 *
125 * For more infos check out this patent doc
126 * http://www.freepatentsonline.com/7400691.html
127 *
128 * This paper describes power drops as seen on the receiver due to
129 * probe packets
130 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
131 * %20of%20Power%20Control.pdf
132 *
133 * And this is the MadWiFi bug entry related to the above
134 * http://madwifi-project.org/ticket/1659
135 * with various measurements and diagrams
136 *
137 * TODO: Deal with power drops due to probes by setting an apropriate
138 * tx power on the probe packets ! Make this part of the calibration process.
139 */
140
141 /* Initialize ah_gain durring attach */
142 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
143 {
144 /* Initialize the gain optimization values */
145 switch (ah->ah_radio) {
146 case AR5K_RF5111:
147 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
148 ah->ah_gain.g_low = 20;
149 ah->ah_gain.g_high = 35;
150 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
151 break;
152 case AR5K_RF5112:
153 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
154 ah->ah_gain.g_low = 20;
155 ah->ah_gain.g_high = 85;
156 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
157 break;
158 default:
159 return -EINVAL;
160 }
161
162 return 0;
163 }
164
165 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
166 {
167
168 /* Skip if gain calibration is inactive or
169 * we already handle a probe request */
170 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
171 return;
172
173 /* Send the packet with 2dB below max power as
174 * patent doc suggest */
175 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
176 AR5K_PHY_PAPD_PROBE_TXPOWER) |
177 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
178
179 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
180
181 }
182
183 /* Calculate gain_F measurement correction
184 * based on the current step for RF5112 rev. 2 */
185 static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
186 {
187 u32 mix, step;
188 u32 *rf;
189 const struct ath5k_gain_opt *go;
190 const struct ath5k_gain_opt_step *g_step;
191 const struct ath5k_rf_reg *rf_regs;
192
193 /* Only RF5112 Rev. 2 supports it */
194 if ((ah->ah_radio != AR5K_RF5112) ||
195 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
196 return 0;
197
198 go = &rfgain_opt_5112;
199 rf_regs = rf_regs_5112a;
200 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
201
202 g_step = &go->go_step[ah->ah_gain.g_step_idx];
203
204 if (ah->ah_rf_banks == NULL)
205 return 0;
206
207 rf = ah->ah_rf_banks;
208 ah->ah_gain.g_f_corr = 0;
209
210 /* No VGA (Variable Gain Amplifier) override, skip */
211 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
212 return 0;
213
214 /* Mix gain stepping */
215 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
216
217 /* Mix gain override */
218 mix = g_step->gos_param[0];
219
220 switch (mix) {
221 case 3:
222 ah->ah_gain.g_f_corr = step * 2;
223 break;
224 case 2:
225 ah->ah_gain.g_f_corr = (step - 5) * 2;
226 break;
227 case 1:
228 ah->ah_gain.g_f_corr = step;
229 break;
230 default:
231 ah->ah_gain.g_f_corr = 0;
232 break;
233 }
234
235 return ah->ah_gain.g_f_corr;
236 }
237
238 /* Check if current gain_F measurement is in the range of our
239 * power detector windows. If we get a measurement outside range
240 * we know it's not accurate (detectors can't measure anything outside
241 * their detection window) so we must ignore it */
242 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
243 {
244 const struct ath5k_rf_reg *rf_regs;
245 u32 step, mix_ovr, level[4];
246 u32 *rf;
247
248 if (ah->ah_rf_banks == NULL)
249 return false;
250
251 rf = ah->ah_rf_banks;
252
253 if (ah->ah_radio == AR5K_RF5111) {
254
255 rf_regs = rf_regs_5111;
256 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
257
258 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
259 false);
260
261 level[0] = 0;
262 level[1] = (step == 63) ? 50 : step + 4;
263 level[2] = (step != 63) ? 64 : level[0];
264 level[3] = level[2] + 50 ;
265
266 ah->ah_gain.g_high = level[3] -
267 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
268 ah->ah_gain.g_low = level[0] +
269 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
270 } else {
271
272 rf_regs = rf_regs_5112;
273 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
274
275 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
276 false);
277
278 level[0] = level[2] = 0;
279
280 if (mix_ovr == 1) {
281 level[1] = level[3] = 83;
282 } else {
283 level[1] = level[3] = 107;
284 ah->ah_gain.g_high = 55;
285 }
286 }
287
288 return (ah->ah_gain.g_current >= level[0] &&
289 ah->ah_gain.g_current <= level[1]) ||
290 (ah->ah_gain.g_current >= level[2] &&
291 ah->ah_gain.g_current <= level[3]);
292 }
293
294 /* Perform gain_F adjustment by choosing the right set
295 * of parameters from rf gain optimization ladder */
296 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
297 {
298 const struct ath5k_gain_opt *go;
299 const struct ath5k_gain_opt_step *g_step;
300 int ret = 0;
301
302 switch (ah->ah_radio) {
303 case AR5K_RF5111:
304 go = &rfgain_opt_5111;
305 break;
306 case AR5K_RF5112:
307 go = &rfgain_opt_5112;
308 break;
309 default:
310 return 0;
311 }
312
313 g_step = &go->go_step[ah->ah_gain.g_step_idx];
314
315 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
316
317 /* Reached maximum */
318 if (ah->ah_gain.g_step_idx == 0)
319 return -1;
320
321 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
322 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
323 ah->ah_gain.g_step_idx > 0;
324 g_step = &go->go_step[ah->ah_gain.g_step_idx])
325 ah->ah_gain.g_target -= 2 *
326 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
327 g_step->gos_gain);
328
329 ret = 1;
330 goto done;
331 }
332
333 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
334
335 /* Reached minimum */
336 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
337 return -2;
338
339 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
340 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
341 ah->ah_gain.g_step_idx < go->go_steps_count-1;
342 g_step = &go->go_step[ah->ah_gain.g_step_idx])
343 ah->ah_gain.g_target -= 2 *
344 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
345 g_step->gos_gain);
346
347 ret = 2;
348 goto done;
349 }
350
351 done:
352 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
353 "ret %d, gain step %u, current gain %u, target gain %u\n",
354 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
355 ah->ah_gain.g_target);
356
357 return ret;
358 }
359
360 /* Main callback for thermal rf gain calibration engine
361 * Check for a new gain reading and schedule an adjustment
362 * if needed.
363 *
364 * TODO: Use sw interrupt to schedule reset if gain_F needs
365 * adjustment */
366 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
367 {
368 u32 data, type;
369 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
370
371 if (ah->ah_rf_banks == NULL ||
372 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
373 return AR5K_RFGAIN_INACTIVE;
374
375 /* No check requested, either engine is inactive
376 * or an adjustment is already requested */
377 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
378 goto done;
379
380 /* Read the PAPD (Peak to Average Power Detector)
381 * register */
382 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
383
384 /* No probe is scheduled, read gain_F measurement */
385 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
386 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
387 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
388
389 /* If tx packet is CCK correct the gain_F measurement
390 * by cck ofdm gain delta */
391 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
392 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
393 ah->ah_gain.g_current +=
394 ee->ee_cck_ofdm_gain_delta;
395 else
396 ah->ah_gain.g_current +=
397 AR5K_GAIN_CCK_PROBE_CORR;
398 }
399
400 /* Further correct gain_F measurement for
401 * RF5112A radios */
402 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
403 ath5k_hw_rf_gainf_corr(ah);
404 ah->ah_gain.g_current =
405 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
406 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
407 0;
408 }
409
410 /* Check if measurement is ok and if we need
411 * to adjust gain, schedule a gain adjustment,
412 * else switch back to the acive state */
413 if (ath5k_hw_rf_check_gainf_readback(ah) &&
414 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
415 ath5k_hw_rf_gainf_adjust(ah)) {
416 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
417 } else {
418 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
419 }
420 }
421
422 done:
423 return ah->ah_gain.g_state;
424 }
425
426 /* Write initial rf gain table to set the RF sensitivity
427 * this one works on all RF chips and has nothing to do
428 * with gain_F calibration */
429 int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
430 {
431 const struct ath5k_ini_rfgain *ath5k_rfg;
432 unsigned int i, size;
433
434 switch (ah->ah_radio) {
435 case AR5K_RF5111:
436 ath5k_rfg = rfgain_5111;
437 size = ARRAY_SIZE(rfgain_5111);
438 break;
439 case AR5K_RF5112:
440 ath5k_rfg = rfgain_5112;
441 size = ARRAY_SIZE(rfgain_5112);
442 break;
443 case AR5K_RF2413:
444 ath5k_rfg = rfgain_2413;
445 size = ARRAY_SIZE(rfgain_2413);
446 break;
447 case AR5K_RF2316:
448 ath5k_rfg = rfgain_2316;
449 size = ARRAY_SIZE(rfgain_2316);
450 break;
451 case AR5K_RF5413:
452 ath5k_rfg = rfgain_5413;
453 size = ARRAY_SIZE(rfgain_5413);
454 break;
455 case AR5K_RF2317:
456 case AR5K_RF2425:
457 ath5k_rfg = rfgain_2425;
458 size = ARRAY_SIZE(rfgain_2425);
459 break;
460 default:
461 return -EINVAL;
462 }
463
464 switch (freq) {
465 case AR5K_INI_RFGAIN_2GHZ:
466 case AR5K_INI_RFGAIN_5GHZ:
467 break;
468 default:
469 return -EINVAL;
470 }
471
472 for (i = 0; i < size; i++) {
473 AR5K_REG_WAIT(i);
474 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
475 (u32)ath5k_rfg[i].rfg_register);
476 }
477
478 return 0;
479 }
480
481
482
483 /********************\
484 * RF Registers setup *
485 \********************/
486
487
488 /*
489 * Setup RF registers by writing rf buffer on hw
490 */
491 int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
492 unsigned int mode)
493 {
494 const struct ath5k_rf_reg *rf_regs;
495 const struct ath5k_ini_rfbuffer *ini_rfb;
496 const struct ath5k_gain_opt *go = NULL;
497 const struct ath5k_gain_opt_step *g_step;
498 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
499 u8 ee_mode = 0;
500 u32 *rfb;
501 int i, obdb = -1, bank = -1;
502
503 switch (ah->ah_radio) {
504 case AR5K_RF5111:
505 rf_regs = rf_regs_5111;
506 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
507 ini_rfb = rfb_5111;
508 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
509 go = &rfgain_opt_5111;
510 break;
511 case AR5K_RF5112:
512 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
513 rf_regs = rf_regs_5112a;
514 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
515 ini_rfb = rfb_5112a;
516 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
517 } else {
518 rf_regs = rf_regs_5112;
519 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
520 ini_rfb = rfb_5112;
521 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
522 }
523 go = &rfgain_opt_5112;
524 break;
525 case AR5K_RF2413:
526 rf_regs = rf_regs_2413;
527 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
528 ini_rfb = rfb_2413;
529 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
530 break;
531 case AR5K_RF2316:
532 rf_regs = rf_regs_2316;
533 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
534 ini_rfb = rfb_2316;
535 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
536 break;
537 case AR5K_RF5413:
538 rf_regs = rf_regs_5413;
539 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
540 ini_rfb = rfb_5413;
541 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
542 break;
543 case AR5K_RF2317:
544 rf_regs = rf_regs_2425;
545 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
546 ini_rfb = rfb_2317;
547 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
548 break;
549 case AR5K_RF2425:
550 rf_regs = rf_regs_2425;
551 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
552 if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
553 ini_rfb = rfb_2425;
554 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
555 } else {
556 ini_rfb = rfb_2417;
557 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
558 }
559 break;
560 default:
561 return -EINVAL;
562 }
563
564 /* If it's the first time we set rf buffer, allocate
565 * ah->ah_rf_banks based on ah->ah_rf_banks_size
566 * we set above */
567 if (ah->ah_rf_banks == NULL) {
568 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
569 GFP_KERNEL);
570 if (ah->ah_rf_banks == NULL) {
571 ATH5K_ERR(ah->ah_sc, "out of memory\n");
572 return -ENOMEM;
573 }
574 }
575
576 /* Copy values to modify them */
577 rfb = ah->ah_rf_banks;
578
579 for (i = 0; i < ah->ah_rf_banks_size; i++) {
580 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
581 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
582 return -EINVAL;
583 }
584
585 /* Bank changed, write down the offset */
586 if (bank != ini_rfb[i].rfb_bank) {
587 bank = ini_rfb[i].rfb_bank;
588 ah->ah_offset[bank] = i;
589 }
590
591 rfb[i] = ini_rfb[i].rfb_mode_data[mode];
592 }
593
594 /* Set Output and Driver bias current (OB/DB) */
595 if (channel->hw_value & CHANNEL_2GHZ) {
596
597 if (channel->hw_value & CHANNEL_CCK)
598 ee_mode = AR5K_EEPROM_MODE_11B;
599 else
600 ee_mode = AR5K_EEPROM_MODE_11G;
601
602 /* For RF511X/RF211X combination we
603 * use b_OB and b_DB parameters stored
604 * in eeprom on ee->ee_ob[ee_mode][0]
605 *
606 * For all other chips we use OB/DB for 2Ghz
607 * stored in the b/g modal section just like
608 * 802.11a on ee->ee_ob[ee_mode][1] */
609 if ((ah->ah_radio == AR5K_RF5111) ||
610 (ah->ah_radio == AR5K_RF5112))
611 obdb = 0;
612 else
613 obdb = 1;
614
615 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
616 AR5K_RF_OB_2GHZ, true);
617
618 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
619 AR5K_RF_DB_2GHZ, true);
620
621 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
622 } else if ((channel->hw_value & CHANNEL_5GHZ) ||
623 (ah->ah_radio == AR5K_RF5111)) {
624
625 /* For 11a, Turbo and XR we need to choose
626 * OB/DB based on frequency range */
627 ee_mode = AR5K_EEPROM_MODE_11A;
628 obdb = channel->center_freq >= 5725 ? 3 :
629 (channel->center_freq >= 5500 ? 2 :
630 (channel->center_freq >= 5260 ? 1 :
631 (channel->center_freq > 4000 ? 0 : -1)));
632
633 if (obdb < 0)
634 return -EINVAL;
635
636 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
637 AR5K_RF_OB_5GHZ, true);
638
639 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
640 AR5K_RF_DB_5GHZ, true);
641 }
642
643 g_step = &go->go_step[ah->ah_gain.g_step_idx];
644
645 /* Bank Modifications (chip-specific) */
646 if (ah->ah_radio == AR5K_RF5111) {
647
648 /* Set gain_F settings according to current step */
649 if (channel->hw_value & CHANNEL_OFDM) {
650
651 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
652 AR5K_PHY_FRAME_CTL_TX_CLIP,
653 g_step->gos_param[0]);
654
655 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
656 AR5K_RF_PWD_90, true);
657
658 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
659 AR5K_RF_PWD_84, true);
660
661 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
662 AR5K_RF_RFGAIN_SEL, true);
663
664 /* We programmed gain_F parameters, switch back
665 * to active state */
666 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
667
668 }
669
670 /* Bank 6/7 setup */
671
672 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
673 AR5K_RF_PWD_XPD, true);
674
675 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
676 AR5K_RF_XPD_GAIN, true);
677
678 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
679 AR5K_RF_GAIN_I, true);
680
681 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
682 AR5K_RF_PLO_SEL, true);
683
684 /* TODO: Half/quarter channel support */
685 }
686
687 if (ah->ah_radio == AR5K_RF5112) {
688
689 /* Set gain_F settings according to current step */
690 if (channel->hw_value & CHANNEL_OFDM) {
691
692 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
693 AR5K_RF_MIXGAIN_OVR, true);
694
695 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
696 AR5K_RF_PWD_138, true);
697
698 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
699 AR5K_RF_PWD_137, true);
700
701 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
702 AR5K_RF_PWD_136, true);
703
704 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
705 AR5K_RF_PWD_132, true);
706
707 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
708 AR5K_RF_PWD_131, true);
709
710 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
711 AR5K_RF_PWD_130, true);
712
713 /* We programmed gain_F parameters, switch back
714 * to active state */
715 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
716 }
717
718 /* Bank 6/7 setup */
719
720 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
721 AR5K_RF_XPD_SEL, true);
722
723 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
724 /* Rev. 1 supports only one xpd */
725 ath5k_hw_rfb_op(ah, rf_regs,
726 ee->ee_x_gain[ee_mode],
727 AR5K_RF_XPD_GAIN, true);
728
729 } else {
730 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
731 if (ee->ee_pd_gains[ee_mode] > 1) {
732 ath5k_hw_rfb_op(ah, rf_regs,
733 pdg_curve_to_idx[0],
734 AR5K_RF_PD_GAIN_LO, true);
735 ath5k_hw_rfb_op(ah, rf_regs,
736 pdg_curve_to_idx[1],
737 AR5K_RF_PD_GAIN_HI, true);
738 } else {
739 ath5k_hw_rfb_op(ah, rf_regs,
740 pdg_curve_to_idx[0],
741 AR5K_RF_PD_GAIN_LO, true);
742 ath5k_hw_rfb_op(ah, rf_regs,
743 pdg_curve_to_idx[0],
744 AR5K_RF_PD_GAIN_HI, true);
745 }
746
747 /* Lower synth voltage on Rev 2 */
748 ath5k_hw_rfb_op(ah, rf_regs, 2,
749 AR5K_RF_HIGH_VC_CP, true);
750
751 ath5k_hw_rfb_op(ah, rf_regs, 2,
752 AR5K_RF_MID_VC_CP, true);
753
754 ath5k_hw_rfb_op(ah, rf_regs, 2,
755 AR5K_RF_LOW_VC_CP, true);
756
757 ath5k_hw_rfb_op(ah, rf_regs, 2,
758 AR5K_RF_PUSH_UP, true);
759
760 /* Decrease power consumption on 5213+ BaseBand */
761 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
762 ath5k_hw_rfb_op(ah, rf_regs, 1,
763 AR5K_RF_PAD2GND, true);
764
765 ath5k_hw_rfb_op(ah, rf_regs, 1,
766 AR5K_RF_XB2_LVL, true);
767
768 ath5k_hw_rfb_op(ah, rf_regs, 1,
769 AR5K_RF_XB5_LVL, true);
770
771 ath5k_hw_rfb_op(ah, rf_regs, 1,
772 AR5K_RF_PWD_167, true);
773
774 ath5k_hw_rfb_op(ah, rf_regs, 1,
775 AR5K_RF_PWD_166, true);
776 }
777 }
778
779 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
780 AR5K_RF_GAIN_I, true);
781
782 /* TODO: Half/quarter channel support */
783
784 }
785
786 if (ah->ah_radio == AR5K_RF5413 &&
787 channel->hw_value & CHANNEL_2GHZ) {
788
789 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
790 true);
791
792 /* Set optimum value for early revisions (on pci-e chips) */
793 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
794 ah->ah_mac_srev < AR5K_SREV_AR5413)
795 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
796 AR5K_RF_PWD_ICLOBUF_2G, true);
797
798 }
799
800 /* Write RF banks on hw */
801 for (i = 0; i < ah->ah_rf_banks_size; i++) {
802 AR5K_REG_WAIT(i);
803 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
804 }
805
806 return 0;
807 }
808
809
810 /**************************\
811 PHY/RF channel functions
812 \**************************/
813
814 /*
815 * Check if a channel is supported
816 */
817 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
818 {
819 /* Check if the channel is in our supported range */
820 if (flags & CHANNEL_2GHZ) {
821 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
822 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
823 return true;
824 } else if (flags & CHANNEL_5GHZ)
825 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
826 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
827 return true;
828
829 return false;
830 }
831
832 /*
833 * Convertion needed for RF5110
834 */
835 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
836 {
837 u32 athchan;
838
839 /*
840 * Convert IEEE channel/MHz to an internal channel value used
841 * by the AR5210 chipset. This has not been verified with
842 * newer chipsets like the AR5212A who have a completely
843 * different RF/PHY part.
844 */
845 athchan = (ath5k_hw_bitswap(
846 (ieee80211_frequency_to_channel(
847 channel->center_freq) - 24) / 2, 5)
848 << 1) | (1 << 6) | 0x1;
849 return athchan;
850 }
851
852 /*
853 * Set channel on RF5110
854 */
855 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
856 struct ieee80211_channel *channel)
857 {
858 u32 data;
859
860 /*
861 * Set the channel and wait
862 */
863 data = ath5k_hw_rf5110_chan2athchan(channel);
864 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
865 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
866 mdelay(1);
867
868 return 0;
869 }
870
871 /*
872 * Convertion needed for 5111
873 */
874 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
875 struct ath5k_athchan_2ghz *athchan)
876 {
877 int channel;
878
879 /* Cast this value to catch negative channel numbers (>= -19) */
880 channel = (int)ieee;
881
882 /*
883 * Map 2GHz IEEE channel to 5GHz Atheros channel
884 */
885 if (channel <= 13) {
886 athchan->a2_athchan = 115 + channel;
887 athchan->a2_flags = 0x46;
888 } else if (channel == 14) {
889 athchan->a2_athchan = 124;
890 athchan->a2_flags = 0x44;
891 } else if (channel >= 15 && channel <= 26) {
892 athchan->a2_athchan = ((channel - 14) * 4) + 132;
893 athchan->a2_flags = 0x46;
894 } else
895 return -EINVAL;
896
897 return 0;
898 }
899
900 /*
901 * Set channel on 5111
902 */
903 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
904 struct ieee80211_channel *channel)
905 {
906 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
907 unsigned int ath5k_channel =
908 ieee80211_frequency_to_channel(channel->center_freq);
909 u32 data0, data1, clock;
910 int ret;
911
912 /*
913 * Set the channel on the RF5111 radio
914 */
915 data0 = data1 = 0;
916
917 if (channel->hw_value & CHANNEL_2GHZ) {
918 /* Map 2GHz channel to 5GHz Atheros channel ID */
919 ret = ath5k_hw_rf5111_chan2athchan(
920 ieee80211_frequency_to_channel(channel->center_freq),
921 &ath5k_channel_2ghz);
922 if (ret)
923 return ret;
924
925 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
926 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
927 << 5) | (1 << 4);
928 }
929
930 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
931 clock = 1;
932 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
933 (clock << 1) | (1 << 10) | 1;
934 } else {
935 clock = 0;
936 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
937 << 2) | (clock << 1) | (1 << 10) | 1;
938 }
939
940 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
941 AR5K_RF_BUFFER);
942 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
943 AR5K_RF_BUFFER_CONTROL_3);
944
945 return 0;
946 }
947
948 /*
949 * Set channel on 5112 and newer
950 */
951 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
952 struct ieee80211_channel *channel)
953 {
954 u32 data, data0, data1, data2;
955 u16 c;
956
957 data = data0 = data1 = data2 = 0;
958 c = channel->center_freq;
959
960 if (c < 4800) {
961 if (!((c - 2224) % 5)) {
962 data0 = ((2 * (c - 704)) - 3040) / 10;
963 data1 = 1;
964 } else if (!((c - 2192) % 5)) {
965 data0 = ((2 * (c - 672)) - 3040) / 10;
966 data1 = 0;
967 } else
968 return -EINVAL;
969
970 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
971 } else if ((c % 5) != 2 || c > 5435) {
972 if (!(c % 20) && c >= 5120) {
973 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
974 data2 = ath5k_hw_bitswap(3, 2);
975 } else if (!(c % 10)) {
976 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
977 data2 = ath5k_hw_bitswap(2, 2);
978 } else if (!(c % 5)) {
979 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
980 data2 = ath5k_hw_bitswap(1, 2);
981 } else
982 return -EINVAL;
983 } else {
984 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
985 data2 = ath5k_hw_bitswap(0, 2);
986 }
987
988 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
989
990 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
991 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
992
993 return 0;
994 }
995
996 /*
997 * Set the channel on the RF2425
998 */
999 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1000 struct ieee80211_channel *channel)
1001 {
1002 u32 data, data0, data2;
1003 u16 c;
1004
1005 data = data0 = data2 = 0;
1006 c = channel->center_freq;
1007
1008 if (c < 4800) {
1009 data0 = ath5k_hw_bitswap((c - 2272), 8);
1010 data2 = 0;
1011 /* ? 5GHz ? */
1012 } else if ((c % 5) != 2 || c > 5435) {
1013 if (!(c % 20) && c < 5120)
1014 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1015 else if (!(c % 10))
1016 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1017 else if (!(c % 5))
1018 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1019 else
1020 return -EINVAL;
1021 data2 = ath5k_hw_bitswap(1, 2);
1022 } else {
1023 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1024 data2 = ath5k_hw_bitswap(0, 2);
1025 }
1026
1027 data = (data0 << 4) | data2 << 2 | 0x1001;
1028
1029 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1030 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1031
1032 return 0;
1033 }
1034
1035 /*
1036 * Set a channel on the radio chip
1037 */
1038 int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
1039 {
1040 int ret;
1041 /*
1042 * Check bounds supported by the PHY (we don't care about regultory
1043 * restrictions at this point). Note: hw_value already has the band
1044 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1045 * of the band by that */
1046 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1047 ATH5K_ERR(ah->ah_sc,
1048 "channel frequency (%u MHz) out of supported "
1049 "band range\n",
1050 channel->center_freq);
1051 return -EINVAL;
1052 }
1053
1054 /*
1055 * Set the channel and wait
1056 */
1057 switch (ah->ah_radio) {
1058 case AR5K_RF5110:
1059 ret = ath5k_hw_rf5110_channel(ah, channel);
1060 break;
1061 case AR5K_RF5111:
1062 ret = ath5k_hw_rf5111_channel(ah, channel);
1063 break;
1064 case AR5K_RF2425:
1065 ret = ath5k_hw_rf2425_channel(ah, channel);
1066 break;
1067 default:
1068 ret = ath5k_hw_rf5112_channel(ah, channel);
1069 break;
1070 }
1071
1072 if (ret)
1073 return ret;
1074
1075 /* Set JAPAN setting for channel 14 */
1076 if (channel->center_freq == 2484) {
1077 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1078 AR5K_PHY_CCKTXCTL_JAPAN);
1079 } else {
1080 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1081 AR5K_PHY_CCKTXCTL_WORLD);
1082 }
1083
1084 ah->ah_current_channel = channel;
1085 ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
1086
1087 return 0;
1088 }
1089
1090 /*****************\
1091 PHY calibration
1092 \*****************/
1093
1094 static int sign_extend(int val, const int nbits)
1095 {
1096 int order = BIT(nbits-1);
1097 return (val ^ order) - order;
1098 }
1099
1100 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
1101 {
1102 s32 val;
1103
1104 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1105 return sign_extend(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 9);
1106 }
1107
1108 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
1109 {
1110 int i;
1111
1112 ah->ah_nfcal_hist.index = 0;
1113 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++)
1114 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1115 }
1116
1117 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
1118 {
1119 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
1120 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1);
1121 hist->nfval[hist->index] = noise_floor;
1122 }
1123
1124 static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1125 {
1126 s16 sort[ATH5K_NF_CAL_HIST_MAX];
1127 s16 tmp;
1128 int i, j;
1129
1130 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
1131 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
1132 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
1133 if (sort[j] > sort[j-1]) {
1134 tmp = sort[j];
1135 sort[j] = sort[j-1];
1136 sort[j-1] = tmp;
1137 }
1138 }
1139 }
1140 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
1141 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1142 "cal %d:%d\n", i, sort[i]);
1143 }
1144 return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2];
1145 }
1146
1147 /*
1148 * When we tell the hardware to perform a noise floor calibration
1149 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
1150 * sample-and-hold the minimum noise level seen at the antennas.
1151 * This value is then stored in a ring buffer of recently measured
1152 * noise floor values so we have a moving window of the last few
1153 * samples.
1154 *
1155 * The median of the values in the history is then loaded into the
1156 * hardware for its own use for RSSI and CCA measurements.
1157 */
1158 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1159 {
1160 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1161 u32 val;
1162 s16 nf, threshold;
1163 u8 ee_mode;
1164
1165 /* keep last value if calibration hasn't completed */
1166 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
1167 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1168 "NF did not complete in calibration window\n");
1169
1170 return;
1171 }
1172
1173 switch (ah->ah_current_channel->hw_value & CHANNEL_MODES) {
1174 case CHANNEL_A:
1175 case CHANNEL_T:
1176 case CHANNEL_XR:
1177 ee_mode = AR5K_EEPROM_MODE_11A;
1178 break;
1179 case CHANNEL_G:
1180 case CHANNEL_TG:
1181 ee_mode = AR5K_EEPROM_MODE_11G;
1182 break;
1183 default:
1184 case CHANNEL_B:
1185 ee_mode = AR5K_EEPROM_MODE_11B;
1186 break;
1187 }
1188
1189
1190 /* completed NF calibration, test threshold */
1191 nf = ath5k_hw_read_measured_noise_floor(ah);
1192 threshold = ee->ee_noise_floor_thr[ee_mode];
1193
1194 if (nf > threshold) {
1195 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1196 "noise floor failure detected; "
1197 "read %d, threshold %d\n",
1198 nf, threshold);
1199
1200 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1201 }
1202
1203 ath5k_hw_update_nfcal_hist(ah, nf);
1204 nf = ath5k_hw_get_median_noise_floor(ah);
1205
1206 /* load noise floor (in .5 dBm) so the hardware will use it */
1207 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
1208 val |= (nf * 2) & AR5K_PHY_NF_M;
1209 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1210
1211 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1212 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE));
1213
1214 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1215 0, false);
1216
1217 /*
1218 * Load a high max CCA Power value (-50 dBm in .5 dBm units)
1219 * so that we're not capped by the median we just loaded.
1220 * This will be used as the initial value for the next noise
1221 * floor calibration.
1222 */
1223 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);
1224 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1225 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1226 AR5K_PHY_AGCCTL_NF_EN |
1227 AR5K_PHY_AGCCTL_NF_NOUPDATE |
1228 AR5K_PHY_AGCCTL_NF);
1229
1230 ah->ah_noise_floor = nf;
1231
1232 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1233 "noise floor calibrated: %d\n", nf);
1234 }
1235
1236 /*
1237 * Perform a PHY calibration on RF5110
1238 * -Fix BPSK/QAM Constellation (I/Q correction)
1239 */
1240 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1241 struct ieee80211_channel *channel)
1242 {
1243 u32 phy_sig, phy_agc, phy_sat, beacon;
1244 int ret;
1245
1246 /*
1247 * Disable beacons and RX/TX queues, wait
1248 */
1249 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1250 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1251 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1252 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1253
1254 mdelay(2);
1255
1256 /*
1257 * Set the channel (with AGC turned off)
1258 */
1259 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1260 udelay(10);
1261 ret = ath5k_hw_channel(ah, channel);
1262
1263 /*
1264 * Activate PHY and wait
1265 */
1266 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1267 mdelay(1);
1268
1269 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1270
1271 if (ret)
1272 return ret;
1273
1274 /*
1275 * Calibrate the radio chip
1276 */
1277
1278 /* Remember normal state */
1279 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1280 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1281 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1282
1283 /* Update radio registers */
1284 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1285 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1286
1287 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1288 AR5K_PHY_AGCCOARSE_LO)) |
1289 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1290 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1291
1292 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1293 AR5K_PHY_ADCSAT_THR)) |
1294 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1295 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1296
1297 udelay(20);
1298
1299 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1300 udelay(10);
1301 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1302 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1303
1304 mdelay(1);
1305
1306 /*
1307 * Enable calibration and wait until completion
1308 */
1309 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1310
1311 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1312 AR5K_PHY_AGCCTL_CAL, 0, false);
1313
1314 /* Reset to normal state */
1315 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1316 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1317 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1318
1319 if (ret) {
1320 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
1321 channel->center_freq);
1322 return ret;
1323 }
1324
1325 /*
1326 * Re-enable RX/TX and beacons
1327 */
1328 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1329 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1330 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1331
1332 return 0;
1333 }
1334
1335 /*
1336 * Perform I/Q calibration on RF5111/5112 and newer chips
1337 */
1338 static int
1339 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
1340 {
1341 u32 i_pwr, q_pwr;
1342 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1343 int i;
1344
1345 if (!ah->ah_calibration ||
1346 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1347 return 0;
1348
1349 /* Calibration has finished, get the results and re-run */
1350 for (i = 0; i <= 10; i++) {
1351 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1352 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1353 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1354 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1355 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr);
1356 if (i_pwr && q_pwr)
1357 break;
1358 }
1359
1360 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
1361
1362 if (ah->ah_version == AR5K_AR5211)
1363 q_coffd = q_pwr >> 6;
1364 else
1365 q_coffd = q_pwr >> 7;
1366
1367 /* protect against divide by 0 and loss of sign bits */
1368 if (i_coffd == 0 || q_coffd < 2)
1369 return -1;
1370
1371 i_coff = (-iq_corr) / i_coffd;
1372 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
1373
1374 if (ah->ah_version == AR5K_AR5211)
1375 q_coff = (i_pwr / q_coffd) - 64;
1376 else
1377 q_coff = (i_pwr / q_coffd) - 128;
1378 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */
1379
1380 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1381 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
1382 i_coff, q_coff, i_coffd, q_coffd);
1383
1384 /* Commit new I/Q values (set enable bit last to match HAL sources) */
1385 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff);
1386 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff);
1387 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1388
1389 /* Re-enable calibration -if we don't we'll commit
1390 * the same values again and again */
1391 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1392 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1393 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1394
1395 return 0;
1396 }
1397
1398 /*
1399 * Perform a PHY calibration
1400 */
1401 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1402 struct ieee80211_channel *channel)
1403 {
1404 int ret;
1405
1406 if (ah->ah_radio == AR5K_RF5110)
1407 ret = ath5k_hw_rf5110_calibrate(ah, channel);
1408 else {
1409 ret = ath5k_hw_rf511x_iq_calibrate(ah);
1410 ath5k_hw_request_rfgain_probe(ah);
1411 }
1412
1413 return ret;
1414 }
1415
1416 /***************************\
1417 * Spur mitigation functions *
1418 \***************************/
1419
1420 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1421 struct ieee80211_channel *channel)
1422 {
1423 u8 refclk_freq;
1424
1425 if ((ah->ah_radio == AR5K_RF5112) ||
1426 (ah->ah_radio == AR5K_RF5413) ||
1427 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
1428 refclk_freq = 40;
1429 else
1430 refclk_freq = 32;
1431
1432 if ((channel->center_freq % refclk_freq != 0) &&
1433 ((channel->center_freq % refclk_freq < 10) ||
1434 (channel->center_freq % refclk_freq > 22)))
1435 return true;
1436 else
1437 return false;
1438 }
1439
1440 void
1441 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1442 struct ieee80211_channel *channel)
1443 {
1444 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1445 u32 mag_mask[4] = {0, 0, 0, 0};
1446 u32 pilot_mask[2] = {0, 0};
1447 /* Note: fbin values are scaled up by 2 */
1448 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
1449 s32 spur_delta_phase, spur_freq_sigma_delta;
1450 s32 spur_offset, num_symbols_x16;
1451 u8 num_symbol_offsets, i, freq_band;
1452
1453 /* Convert current frequency to fbin value (the same way channels
1454 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
1455 * up by 2 so we can compare it later */
1456 if (channel->hw_value & CHANNEL_2GHZ) {
1457 chan_fbin = (channel->center_freq - 2300) * 10;
1458 freq_band = AR5K_EEPROM_BAND_2GHZ;
1459 } else {
1460 chan_fbin = (channel->center_freq - 4900) * 10;
1461 freq_band = AR5K_EEPROM_BAND_5GHZ;
1462 }
1463
1464 /* Check if any spur_chan_fbin from EEPROM is
1465 * within our current channel's spur detection range */
1466 spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
1467 spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
1468 if (channel->hw_value & CHANNEL_TURBO)
1469 spur_detection_window *= 2;
1470
1471 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1472 spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
1473
1474 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
1475 * so it's zero if we got nothing from EEPROM */
1476 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
1477 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1478 break;
1479 }
1480
1481 if ((chan_fbin - spur_detection_window <=
1482 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
1483 (chan_fbin + spur_detection_window >=
1484 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
1485 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1486 break;
1487 }
1488 }
1489
1490 /* We need to enable spur filter for this channel */
1491 if (spur_chan_fbin) {
1492 spur_offset = spur_chan_fbin - chan_fbin;
1493 /*
1494 * Calculate deltas:
1495 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
1496 * spur_delta_phase -> spur_offset / chip_freq << 11
1497 * Note: Both values have 100KHz resolution
1498 */
1499 switch (channel->hw_value) {
1500 case CHANNEL_A:
1501 /* Both sample_freq and chip_freq are 40MHz */
1502 spur_delta_phase = (spur_offset << 17) / 25;
1503 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1504 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1505 break;
1506 case CHANNEL_G:
1507 /* sample_freq -> 40MHz chip_freq -> 44MHz
1508 * (for b compatibility) */
1509 spur_freq_sigma_delta = (spur_offset << 8) / 55;
1510 spur_delta_phase = (spur_offset << 17) / 25;
1511 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1512 break;
1513 case CHANNEL_T:
1514 case CHANNEL_TG:
1515 /* Both sample_freq and chip_freq are 80MHz */
1516 spur_delta_phase = (spur_offset << 16) / 25;
1517 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1518 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz;
1519 break;
1520 default:
1521 return;
1522 }
1523
1524 /* Calculate pilot and magnitude masks */
1525
1526 /* Scale up spur_offset by 1000 to switch to 100HZ resolution
1527 * and divide by symbol_width to find how many symbols we have
1528 * Note: number of symbols is scaled up by 16 */
1529 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
1530
1531 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
1532 if (!(num_symbols_x16 & 0xF))
1533 /* _X_ */
1534 num_symbol_offsets = 3;
1535 else
1536 /* _xx_ */
1537 num_symbol_offsets = 4;
1538
1539 for (i = 0; i < num_symbol_offsets; i++) {
1540
1541 /* Calculate pilot mask */
1542 s32 curr_sym_off =
1543 (num_symbols_x16 / 16) + i + 25;
1544
1545 /* Pilot magnitude mask seems to be a way to
1546 * declare the boundaries for our detection
1547 * window or something, it's 2 for the middle
1548 * value(s) where the symbol is expected to be
1549 * and 1 on the boundary values */
1550 u8 plt_mag_map =
1551 (i == 0 || i == (num_symbol_offsets - 1))
1552 ? 1 : 2;
1553
1554 if (curr_sym_off >= 0 && curr_sym_off <= 32) {
1555 if (curr_sym_off <= 25)
1556 pilot_mask[0] |= 1 << curr_sym_off;
1557 else if (curr_sym_off >= 27)
1558 pilot_mask[0] |= 1 << (curr_sym_off - 1);
1559 } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
1560 pilot_mask[1] |= 1 << (curr_sym_off - 33);
1561
1562 /* Calculate magnitude mask (for viterbi decoder) */
1563 if (curr_sym_off >= -1 && curr_sym_off <= 14)
1564 mag_mask[0] |=
1565 plt_mag_map << (curr_sym_off + 1) * 2;
1566 else if (curr_sym_off >= 15 && curr_sym_off <= 30)
1567 mag_mask[1] |=
1568 plt_mag_map << (curr_sym_off - 15) * 2;
1569 else if (curr_sym_off >= 31 && curr_sym_off <= 46)
1570 mag_mask[2] |=
1571 plt_mag_map << (curr_sym_off - 31) * 2;
1572 else if (curr_sym_off >= 46 && curr_sym_off <= 53)
1573 mag_mask[3] |=
1574 plt_mag_map << (curr_sym_off - 47) * 2;
1575
1576 }
1577
1578 /* Write settings on hw to enable spur filter */
1579 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1580 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
1581 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1582 AR5K_PHY_IQ_PILOT_MASK_EN |
1583 AR5K_PHY_IQ_CHAN_MASK_EN |
1584 AR5K_PHY_IQ_SPUR_FILT_EN);
1585
1586 /* Set delta phase and freq sigma delta */
1587 ath5k_hw_reg_write(ah,
1588 AR5K_REG_SM(spur_delta_phase,
1589 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
1590 AR5K_REG_SM(spur_freq_sigma_delta,
1591 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
1592 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
1593 AR5K_PHY_TIMING_11);
1594
1595 /* Write pilot masks */
1596 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
1597 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1598 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1599 pilot_mask[1]);
1600
1601 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
1602 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1603 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1604 pilot_mask[1]);
1605
1606 /* Write magnitude masks */
1607 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
1608 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
1609 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
1610 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1611 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1612 mag_mask[3]);
1613
1614 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
1615 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
1616 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
1617 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1618 AR5K_PHY_BIN_MASK2_4_MASK_4,
1619 mag_mask[3]);
1620
1621 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
1622 AR5K_PHY_IQ_SPUR_FILT_EN) {
1623 /* Clean up spur mitigation settings and disable fliter */
1624 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1625 AR5K_PHY_BIN_MASK_CTL_RATE, 0);
1626 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
1627 AR5K_PHY_IQ_PILOT_MASK_EN |
1628 AR5K_PHY_IQ_CHAN_MASK_EN |
1629 AR5K_PHY_IQ_SPUR_FILT_EN);
1630 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
1631
1632 /* Clear pilot masks */
1633 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
1634 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1635 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1636 0);
1637
1638 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
1639 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1640 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1641 0);
1642
1643 /* Clear magnitude masks */
1644 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
1645 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
1646 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
1647 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1648 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1649 0);
1650
1651 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
1652 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
1653 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
1654 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1655 AR5K_PHY_BIN_MASK2_4_MASK_4,
1656 0);
1657 }
1658 }
1659
1660 /********************\
1661 Misc PHY functions
1662 \********************/
1663
1664 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
1665 {
1666 /*Just a try M.F.*/
1667 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
1668
1669 return 0;
1670 }
1671
1672 /*
1673 * Get the PHY Chip revision
1674 */
1675 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
1676 {
1677 unsigned int i;
1678 u32 srev;
1679 u16 ret;
1680
1681 /*
1682 * Set the radio chip access register
1683 */
1684 switch (chan) {
1685 case CHANNEL_2GHZ:
1686 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
1687 break;
1688 case CHANNEL_5GHZ:
1689 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1690 break;
1691 default:
1692 return 0;
1693 }
1694
1695 mdelay(2);
1696
1697 /* ...wait until PHY is ready and read the selected radio revision */
1698 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
1699
1700 for (i = 0; i < 8; i++)
1701 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
1702
1703 if (ah->ah_version == AR5K_AR5210) {
1704 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
1705 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
1706 } else {
1707 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
1708 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
1709 ((srev & 0x0f) << 4), 8);
1710 }
1711
1712 /* Reset to the 5GHz mode */
1713 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1714
1715 return ret;
1716 }
1717
1718 /*****************\
1719 * Antenna control *
1720 \*****************/
1721
1722 static void /*TODO:Boundary check*/
1723 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
1724 {
1725 if (ah->ah_version != AR5K_AR5210)
1726 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
1727 }
1728
1729 /*
1730 * Enable/disable fast rx antenna diversity
1731 */
1732 static void
1733 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
1734 {
1735 switch (ee_mode) {
1736 case AR5K_EEPROM_MODE_11G:
1737 case AR5K_EEPROM_MODE_11A:
1738 if (enable)
1739 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
1740 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1741 else
1742 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1743 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1744 break;
1745 case AR5K_EEPROM_MODE_11B:
1746 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1747 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1748 break;
1749 default:
1750 return;
1751 }
1752
1753 if (enable) {
1754 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1755 AR5K_PHY_RESTART_DIV_GC, 4);
1756
1757 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1758 AR5K_PHY_FAST_ANT_DIV_EN);
1759 } else {
1760 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1761 AR5K_PHY_RESTART_DIV_GC, 0);
1762
1763 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1764 AR5K_PHY_FAST_ANT_DIV_EN);
1765 }
1766 }
1767
1768 void
1769 ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode)
1770 {
1771 u8 ant0, ant1;
1772
1773 /*
1774 * In case a fixed antenna was set as default
1775 * use the same switch table twice.
1776 */
1777 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A)
1778 ant0 = ant1 = AR5K_ANT_SWTABLE_A;
1779 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B)
1780 ant0 = ant1 = AR5K_ANT_SWTABLE_B;
1781 else {
1782 ant0 = AR5K_ANT_SWTABLE_A;
1783 ant1 = AR5K_ANT_SWTABLE_B;
1784 }
1785
1786 /* Set antenna idle switch table */
1787 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
1788 AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
1789 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] |
1790 AR5K_PHY_ANT_CTL_TXRX_EN));
1791
1792 /* Set antenna switch tables */
1793 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0],
1794 AR5K_PHY_ANT_SWITCH_TABLE_0);
1795 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1],
1796 AR5K_PHY_ANT_SWITCH_TABLE_1);
1797 }
1798
1799 /*
1800 * Set antenna operating mode
1801 */
1802 void
1803 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
1804 {
1805 struct ieee80211_channel *channel = ah->ah_current_channel;
1806 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
1807 bool use_def_for_sg;
1808 u8 def_ant, tx_ant, ee_mode;
1809 u32 sta_id1 = 0;
1810
1811 /* if channel is not initialized yet we can't set the antennas
1812 * so just store the mode. it will be set on the next reset */
1813 if (channel == NULL) {
1814 ah->ah_ant_mode = ant_mode;
1815 return;
1816 }
1817
1818 def_ant = ah->ah_def_ant;
1819
1820 switch (channel->hw_value & CHANNEL_MODES) {
1821 case CHANNEL_A:
1822 case CHANNEL_T:
1823 case CHANNEL_XR:
1824 ee_mode = AR5K_EEPROM_MODE_11A;
1825 break;
1826 case CHANNEL_G:
1827 case CHANNEL_TG:
1828 ee_mode = AR5K_EEPROM_MODE_11G;
1829 break;
1830 case CHANNEL_B:
1831 ee_mode = AR5K_EEPROM_MODE_11B;
1832 break;
1833 default:
1834 ATH5K_ERR(ah->ah_sc,
1835 "invalid channel: %d\n", channel->center_freq);
1836 return;
1837 }
1838
1839 switch (ant_mode) {
1840 case AR5K_ANTMODE_DEFAULT:
1841 tx_ant = 0;
1842 use_def_for_tx = false;
1843 update_def_on_tx = false;
1844 use_def_for_rts = false;
1845 use_def_for_sg = false;
1846 fast_div = true;
1847 break;
1848 case AR5K_ANTMODE_FIXED_A:
1849 def_ant = 1;
1850 tx_ant = 1;
1851 use_def_for_tx = true;
1852 update_def_on_tx = false;
1853 use_def_for_rts = true;
1854 use_def_for_sg = true;
1855 fast_div = false;
1856 break;
1857 case AR5K_ANTMODE_FIXED_B:
1858 def_ant = 2;
1859 tx_ant = 2;
1860 use_def_for_tx = true;
1861 update_def_on_tx = false;
1862 use_def_for_rts = true;
1863 use_def_for_sg = true;
1864 fast_div = false;
1865 break;
1866 case AR5K_ANTMODE_SINGLE_AP:
1867 def_ant = 1; /* updated on tx */
1868 tx_ant = 0;
1869 use_def_for_tx = true;
1870 update_def_on_tx = true;
1871 use_def_for_rts = true;
1872 use_def_for_sg = true;
1873 fast_div = true;
1874 break;
1875 case AR5K_ANTMODE_SECTOR_AP:
1876 tx_ant = 1; /* variable */
1877 use_def_for_tx = false;
1878 update_def_on_tx = false;
1879 use_def_for_rts = true;
1880 use_def_for_sg = false;
1881 fast_div = false;
1882 break;
1883 case AR5K_ANTMODE_SECTOR_STA:
1884 tx_ant = 1; /* variable */
1885 use_def_for_tx = true;
1886 update_def_on_tx = false;
1887 use_def_for_rts = true;
1888 use_def_for_sg = false;
1889 fast_div = true;
1890 break;
1891 case AR5K_ANTMODE_DEBUG:
1892 def_ant = 1;
1893 tx_ant = 2;
1894 use_def_for_tx = false;
1895 update_def_on_tx = false;
1896 use_def_for_rts = false;
1897 use_def_for_sg = false;
1898 fast_div = false;
1899 break;
1900 default:
1901 return;
1902 }
1903
1904 ah->ah_tx_ant = tx_ant;
1905 ah->ah_ant_mode = ant_mode;
1906 ah->ah_def_ant = def_ant;
1907
1908 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
1909 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
1910 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
1911 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
1912
1913 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
1914
1915 if (sta_id1)
1916 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
1917
1918 ath5k_hw_set_antenna_switch(ah, ee_mode);
1919 /* Note: set diversity before default antenna
1920 * because it won't work correctly */
1921 ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
1922 ath5k_hw_set_def_antenna(ah, def_ant);
1923 }
1924
1925
1926 /****************\
1927 * TX power setup *
1928 \****************/
1929
1930 /*
1931 * Helper functions
1932 */
1933
1934 /*
1935 * Do linear interpolation between two given (x, y) points
1936 */
1937 static s16
1938 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
1939 s16 y_left, s16 y_right)
1940 {
1941 s16 ratio, result;
1942
1943 /* Avoid divide by zero and skip interpolation
1944 * if we have the same point */
1945 if ((x_left == x_right) || (y_left == y_right))
1946 return y_left;
1947
1948 /*
1949 * Since we use ints and not fps, we need to scale up in
1950 * order to get a sane ratio value (or else we 'll eg. get
1951 * always 1 instead of 1.25, 1.75 etc). We scale up by 100
1952 * to have some accuracy both for 0.5 and 0.25 steps.
1953 */
1954 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left));
1955
1956 /* Now scale down to be in range */
1957 result = y_left + (ratio * (target - x_left) / 100);
1958
1959 return result;
1960 }
1961
1962 /*
1963 * Find vertical boundary (min pwr) for the linear PCDAC curve.
1964 *
1965 * Since we have the top of the curve and we draw the line below
1966 * until we reach 1 (1 pcdac step) we need to know which point
1967 * (x value) that is so that we don't go below y axis and have negative
1968 * pcdac values when creating the curve, or fill the table with zeroes.
1969 */
1970 static s16
1971 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
1972 const s16 *pwrL, const s16 *pwrR)
1973 {
1974 s8 tmp;
1975 s16 min_pwrL, min_pwrR;
1976 s16 pwr_i;
1977
1978 /* Some vendors write the same pcdac value twice !!! */
1979 if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
1980 return max(pwrL[0], pwrR[0]);
1981
1982 if (pwrL[0] == pwrL[1])
1983 min_pwrL = pwrL[0];
1984 else {
1985 pwr_i = pwrL[0];
1986 do {
1987 pwr_i--;
1988 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
1989 pwrL[0], pwrL[1],
1990 stepL[0], stepL[1]);
1991 } while (tmp > 1);
1992
1993 min_pwrL = pwr_i;
1994 }
1995
1996 if (pwrR[0] == pwrR[1])
1997 min_pwrR = pwrR[0];
1998 else {
1999 pwr_i = pwrR[0];
2000 do {
2001 pwr_i--;
2002 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2003 pwrR[0], pwrR[1],
2004 stepR[0], stepR[1]);
2005 } while (tmp > 1);
2006
2007 min_pwrR = pwr_i;
2008 }
2009
2010 /* Keep the right boundary so that it works for both curves */
2011 return max(min_pwrL, min_pwrR);
2012 }
2013
2014 /*
2015 * Interpolate (pwr,vpd) points to create a Power to PDADC or a
2016 * Power to PCDAC curve.
2017 *
2018 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
2019 * steps (offsets) on y axis. Power can go up to 31.5dB and max
2020 * PCDAC/PDADC step for each curve is 64 but we can write more than
2021 * one curves on hw so we can go up to 128 (which is the max step we
2022 * can write on the final table).
2023 *
2024 * We write y values (PCDAC/PDADC steps) on hw.
2025 */
2026 static void
2027 ath5k_create_power_curve(s16 pmin, s16 pmax,
2028 const s16 *pwr, const u8 *vpd,
2029 u8 num_points,
2030 u8 *vpd_table, u8 type)
2031 {
2032 u8 idx[2] = { 0, 1 };
2033 s16 pwr_i = 2*pmin;
2034 int i;
2035
2036 if (num_points < 2)
2037 return;
2038
2039 /* We want the whole line, so adjust boundaries
2040 * to cover the entire power range. Note that
2041 * power values are already 0.25dB so no need
2042 * to multiply pwr_i by 2 */
2043 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
2044 pwr_i = pmin;
2045 pmin = 0;
2046 pmax = 63;
2047 }
2048
2049 /* Find surrounding turning points (TPs)
2050 * and interpolate between them */
2051 for (i = 0; (i <= (u16) (pmax - pmin)) &&
2052 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2053
2054 /* We passed the right TP, move to the next set of TPs
2055 * if we pass the last TP, extrapolate above using the last
2056 * two TPs for ratio */
2057 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
2058 idx[0]++;
2059 idx[1]++;
2060 }
2061
2062 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
2063 pwr[idx[0]], pwr[idx[1]],
2064 vpd[idx[0]], vpd[idx[1]]);
2065
2066 /* Increase by 0.5dB
2067 * (0.25 dB units) */
2068 pwr_i += 2;
2069 }
2070 }
2071
2072 /*
2073 * Get the surrounding per-channel power calibration piers
2074 * for a given frequency so that we can interpolate between
2075 * them and come up with an apropriate dataset for our current
2076 * channel.
2077 */
2078 static void
2079 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
2080 struct ieee80211_channel *channel,
2081 struct ath5k_chan_pcal_info **pcinfo_l,
2082 struct ath5k_chan_pcal_info **pcinfo_r)
2083 {
2084 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2085 struct ath5k_chan_pcal_info *pcinfo;
2086 u8 idx_l, idx_r;
2087 u8 mode, max, i;
2088 u32 target = channel->center_freq;
2089
2090 idx_l = 0;
2091 idx_r = 0;
2092
2093 if (!(channel->hw_value & CHANNEL_OFDM)) {
2094 pcinfo = ee->ee_pwr_cal_b;
2095 mode = AR5K_EEPROM_MODE_11B;
2096 } else if (channel->hw_value & CHANNEL_2GHZ) {
2097 pcinfo = ee->ee_pwr_cal_g;
2098 mode = AR5K_EEPROM_MODE_11G;
2099 } else {
2100 pcinfo = ee->ee_pwr_cal_a;
2101 mode = AR5K_EEPROM_MODE_11A;
2102 }
2103 max = ee->ee_n_piers[mode] - 1;
2104
2105 /* Frequency is below our calibrated
2106 * range. Use the lowest power curve
2107 * we have */
2108 if (target < pcinfo[0].freq) {
2109 idx_l = idx_r = 0;
2110 goto done;
2111 }
2112
2113 /* Frequency is above our calibrated
2114 * range. Use the highest power curve
2115 * we have */
2116 if (target > pcinfo[max].freq) {
2117 idx_l = idx_r = max;
2118 goto done;
2119 }
2120
2121 /* Frequency is inside our calibrated
2122 * channel range. Pick the surrounding
2123 * calibration piers so that we can
2124 * interpolate */
2125 for (i = 0; i <= max; i++) {
2126
2127 /* Frequency matches one of our calibration
2128 * piers, no need to interpolate, just use
2129 * that calibration pier */
2130 if (pcinfo[i].freq == target) {
2131 idx_l = idx_r = i;
2132 goto done;
2133 }
2134
2135 /* We found a calibration pier that's above
2136 * frequency, use this pier and the previous
2137 * one to interpolate */
2138 if (target < pcinfo[i].freq) {
2139 idx_r = i;
2140 idx_l = idx_r - 1;
2141 goto done;
2142 }
2143 }
2144
2145 done:
2146 *pcinfo_l = &pcinfo[idx_l];
2147 *pcinfo_r = &pcinfo[idx_r];
2148 }
2149
2150 /*
2151 * Get the surrounding per-rate power calibration data
2152 * for a given frequency and interpolate between power
2153 * values to set max target power supported by hw for
2154 * each rate.
2155 */
2156 static void
2157 ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
2158 struct ieee80211_channel *channel,
2159 struct ath5k_rate_pcal_info *rates)
2160 {
2161 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2162 struct ath5k_rate_pcal_info *rpinfo;
2163 u8 idx_l, idx_r;
2164 u8 mode, max, i;
2165 u32 target = channel->center_freq;
2166
2167 idx_l = 0;
2168 idx_r = 0;
2169
2170 if (!(channel->hw_value & CHANNEL_OFDM)) {
2171 rpinfo = ee->ee_rate_tpwr_b;
2172 mode = AR5K_EEPROM_MODE_11B;
2173 } else if (channel->hw_value & CHANNEL_2GHZ) {
2174 rpinfo = ee->ee_rate_tpwr_g;
2175 mode = AR5K_EEPROM_MODE_11G;
2176 } else {
2177 rpinfo = ee->ee_rate_tpwr_a;
2178 mode = AR5K_EEPROM_MODE_11A;
2179 }
2180 max = ee->ee_rate_target_pwr_num[mode] - 1;
2181
2182 /* Get the surrounding calibration
2183 * piers - same as above */
2184 if (target < rpinfo[0].freq) {
2185 idx_l = idx_r = 0;
2186 goto done;
2187 }
2188
2189 if (target > rpinfo[max].freq) {
2190 idx_l = idx_r = max;
2191 goto done;
2192 }
2193
2194 for (i = 0; i <= max; i++) {
2195
2196 if (rpinfo[i].freq == target) {
2197 idx_l = idx_r = i;
2198 goto done;
2199 }
2200
2201 if (target < rpinfo[i].freq) {
2202 idx_r = i;
2203 idx_l = idx_r - 1;
2204 goto done;
2205 }
2206 }
2207
2208 done:
2209 /* Now interpolate power value, based on the frequency */
2210 rates->freq = target;
2211
2212 rates->target_power_6to24 =
2213 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2214 rpinfo[idx_r].freq,
2215 rpinfo[idx_l].target_power_6to24,
2216 rpinfo[idx_r].target_power_6to24);
2217
2218 rates->target_power_36 =
2219 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2220 rpinfo[idx_r].freq,
2221 rpinfo[idx_l].target_power_36,
2222 rpinfo[idx_r].target_power_36);
2223
2224 rates->target_power_48 =
2225 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2226 rpinfo[idx_r].freq,
2227 rpinfo[idx_l].target_power_48,
2228 rpinfo[idx_r].target_power_48);
2229
2230 rates->target_power_54 =
2231 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2232 rpinfo[idx_r].freq,
2233 rpinfo[idx_l].target_power_54,
2234 rpinfo[idx_r].target_power_54);
2235 }
2236
2237 /*
2238 * Get the max edge power for this channel if
2239 * we have such data from EEPROM's Conformance Test
2240 * Limits (CTL), and limit max power if needed.
2241 */
2242 static void
2243 ath5k_get_max_ctl_power(struct ath5k_hw *ah,
2244 struct ieee80211_channel *channel)
2245 {
2246 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2247 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2248 struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
2249 u8 *ctl_val = ee->ee_ctl;
2250 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
2251 s16 edge_pwr = 0;
2252 u8 rep_idx;
2253 u8 i, ctl_mode;
2254 u8 ctl_idx = 0xFF;
2255 u32 target = channel->center_freq;
2256
2257 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
2258
2259 switch (channel->hw_value & CHANNEL_MODES) {
2260 case CHANNEL_A:
2261 ctl_mode |= AR5K_CTL_11A;
2262 break;
2263 case CHANNEL_G:
2264 ctl_mode |= AR5K_CTL_11G;
2265 break;
2266 case CHANNEL_B:
2267 ctl_mode |= AR5K_CTL_11B;
2268 break;
2269 case CHANNEL_T:
2270 ctl_mode |= AR5K_CTL_TURBO;
2271 break;
2272 case CHANNEL_TG:
2273 ctl_mode |= AR5K_CTL_TURBOG;
2274 break;
2275 case CHANNEL_XR:
2276 /* Fall through */
2277 default:
2278 return;
2279 }
2280
2281 for (i = 0; i < ee->ee_ctls; i++) {
2282 if (ctl_val[i] == ctl_mode) {
2283 ctl_idx = i;
2284 break;
2285 }
2286 }
2287
2288 /* If we have a CTL dataset available grab it and find the
2289 * edge power for our frequency */
2290 if (ctl_idx == 0xFF)
2291 return;
2292
2293 /* Edge powers are sorted by frequency from lower
2294 * to higher. Each CTL corresponds to 8 edge power
2295 * measurements. */
2296 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
2297
2298 /* Don't do boundaries check because we
2299 * might have more that one bands defined
2300 * for this mode */
2301
2302 /* Get the edge power that's closer to our
2303 * frequency */
2304 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
2305 rep_idx += i;
2306 if (target <= rep[rep_idx].freq)
2307 edge_pwr = (s16) rep[rep_idx].edge;
2308 }
2309
2310 if (edge_pwr)
2311 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr);
2312 }
2313
2314
2315 /*
2316 * Power to PCDAC table functions
2317 */
2318
2319 /*
2320 * Fill Power to PCDAC table on RF5111
2321 *
2322 * No further processing is needed for RF5111, the only thing we have to
2323 * do is fill the values below and above calibration range since eeprom data
2324 * may not cover the entire PCDAC table.
2325 */
2326 static void
2327 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2328 s16 *table_max)
2329 {
2330 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2331 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0];
2332 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
2333 s16 min_pwr, max_pwr;
2334
2335 /* Get table boundaries */
2336 min_pwr = table_min[0];
2337 pcdac_0 = pcdac_tmp[0];
2338
2339 max_pwr = table_max[0];
2340 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
2341
2342 /* Extrapolate below minimum using pcdac_0 */
2343 pcdac_i = 0;
2344 for (i = 0; i < min_pwr; i++)
2345 pcdac_out[pcdac_i++] = pcdac_0;
2346
2347 /* Copy values from pcdac_tmp */
2348 pwr_idx = min_pwr;
2349 for (i = 0 ; pwr_idx <= max_pwr &&
2350 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
2351 pcdac_out[pcdac_i++] = pcdac_tmp[i];
2352 pwr_idx++;
2353 }
2354
2355 /* Extrapolate above maximum */
2356 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
2357 pcdac_out[pcdac_i++] = pcdac_n;
2358
2359 }
2360
2361 /*
2362 * Combine available XPD Curves and fill Linear Power to PCDAC table
2363 * on RF5112
2364 *
2365 * RFX112 can have up to 2 curves (one for low txpower range and one for
2366 * higher txpower range). We need to put them both on pcdac_out and place
2367 * them in the correct location. In case we only have one curve available
2368 * just fit it on pcdac_out (it's supposed to cover the entire range of
2369 * available pwr levels since it's always the higher power curve). Extrapolate
2370 * below and above final table if needed.
2371 */
2372 static void
2373 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2374 s16 *table_max, u8 pdcurves)
2375 {
2376 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2377 u8 *pcdac_low_pwr;
2378 u8 *pcdac_high_pwr;
2379 u8 *pcdac_tmp;
2380 u8 pwr;
2381 s16 max_pwr_idx;
2382 s16 min_pwr_idx;
2383 s16 mid_pwr_idx = 0;
2384 /* Edge flag turs on the 7nth bit on the PCDAC
2385 * to delcare the higher power curve (force values
2386 * to be greater than 64). If we only have one curve
2387 * we don't need to set this, if we have 2 curves and
2388 * fill the table backwards this can also be used to
2389 * switch from higher power curve to lower power curve */
2390 u8 edge_flag;
2391 int i;
2392
2393 /* When we have only one curve available
2394 * that's the higher power curve. If we have
2395 * two curves the first is the high power curve
2396 * and the next is the low power curve. */
2397 if (pdcurves > 1) {
2398 pcdac_low_pwr = ah->ah_txpower.tmpL[1];
2399 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2400 mid_pwr_idx = table_max[1] - table_min[1] - 1;
2401 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2402
2403 /* If table size goes beyond 31.5dB, keep the
2404 * upper 31.5dB range when setting tx power.
2405 * Note: 126 = 31.5 dB in quarter dB steps */
2406 if (table_max[0] - table_min[1] > 126)
2407 min_pwr_idx = table_max[0] - 126;
2408 else
2409 min_pwr_idx = table_min[1];
2410
2411 /* Since we fill table backwards
2412 * start from high power curve */
2413 pcdac_tmp = pcdac_high_pwr;
2414
2415 edge_flag = 0x40;
2416 } else {
2417 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
2418 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2419 min_pwr_idx = table_min[0];
2420 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2421 pcdac_tmp = pcdac_high_pwr;
2422 edge_flag = 0;
2423 }
2424
2425 /* This is used when setting tx power*/
2426 ah->ah_txpower.txp_min_idx = min_pwr_idx/2;
2427
2428 /* Fill Power to PCDAC table backwards */
2429 pwr = max_pwr_idx;
2430 for (i = 63; i >= 0; i--) {
2431 /* Entering lower power range, reset
2432 * edge flag and set pcdac_tmp to lower
2433 * power curve.*/
2434 if (edge_flag == 0x40 &&
2435 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
2436 edge_flag = 0x00;
2437 pcdac_tmp = pcdac_low_pwr;
2438 pwr = mid_pwr_idx/2;
2439 }
2440
2441 /* Don't go below 1, extrapolate below if we have
2442 * already swithced to the lower power curve -or
2443 * we only have one curve and edge_flag is zero
2444 * anyway */
2445 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
2446 while (i >= 0) {
2447 pcdac_out[i] = pcdac_out[i + 1];
2448 i--;
2449 }
2450 break;
2451 }
2452
2453 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
2454
2455 /* Extrapolate above if pcdac is greater than
2456 * 126 -this can happen because we OR pcdac_out
2457 * value with edge_flag on high power curve */
2458 if (pcdac_out[i] > 126)
2459 pcdac_out[i] = 126;
2460
2461 /* Decrease by a 0.5dB step */
2462 pwr--;
2463 }
2464 }
2465
2466 /* Write PCDAC values on hw */
2467 static void
2468 ath5k_setup_pcdac_table(struct ath5k_hw *ah)
2469 {
2470 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2471 int i;
2472
2473 /*
2474 * Write TX power values
2475 */
2476 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2477 ath5k_hw_reg_write(ah,
2478 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) |
2479 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16),
2480 AR5K_PHY_PCDAC_TXPOWER(i));
2481 }
2482 }
2483
2484
2485 /*
2486 * Power to PDADC table functions
2487 */
2488
2489 /*
2490 * Set the gain boundaries and create final Power to PDADC table
2491 *
2492 * We can have up to 4 pd curves, we need to do a simmilar process
2493 * as we do for RF5112. This time we don't have an edge_flag but we
2494 * set the gain boundaries on a separate register.
2495 */
2496 static void
2497 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2498 s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
2499 {
2500 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
2501 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2502 u8 *pdadc_tmp;
2503 s16 pdadc_0;
2504 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
2505 u8 pd_gain_overlap;
2506
2507 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
2508 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
2509
2510 /* Create final PDADC table */
2511 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
2512 pdadc_tmp = ah->ah_txpower.tmpL[pdg];
2513
2514 if (pdg == pdcurves - 1)
2515 /* 2 dB boundary stretch for last
2516 * (higher power) curve */
2517 gain_boundaries[pdg] = pwr_max[pdg] + 4;
2518 else
2519 /* Set gain boundary in the middle
2520 * between this curve and the next one */
2521 gain_boundaries[pdg] =
2522 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
2523
2524 /* Sanity check in case our 2 db stretch got out of
2525 * range. */
2526 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
2527 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
2528
2529 /* For the first curve (lower power)
2530 * start from 0 dB */
2531 if (pdg == 0)
2532 pdadc_0 = 0;
2533 else
2534 /* For the other curves use the gain overlap */
2535 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
2536 pd_gain_overlap;
2537
2538 /* Force each power step to be at least 0.5 dB */
2539 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
2540 pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
2541 else
2542 pwr_step = 1;
2543
2544 /* If pdadc_0 is negative, we need to extrapolate
2545 * below this pdgain by a number of pwr_steps */
2546 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
2547 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
2548 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
2549 pdadc_0++;
2550 }
2551
2552 /* Set last pwr level, using gain boundaries */
2553 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
2554 /* Limit it to be inside pwr range */
2555 table_size = pwr_max[pdg] - pwr_min[pdg];
2556 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
2557
2558 /* Fill pdadc_out table */
2559 while (pdadc_0 < max_idx && pdadc_i < 128)
2560 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
2561
2562 /* Need to extrapolate above this pdgain? */
2563 if (pdadc_n <= max_idx)
2564 continue;
2565
2566 /* Force each power step to be at least 0.5 dB */
2567 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
2568 pwr_step = pdadc_tmp[table_size - 1] -
2569 pdadc_tmp[table_size - 2];
2570 else
2571 pwr_step = 1;
2572
2573 /* Extrapolate above */
2574 while ((pdadc_0 < (s16) pdadc_n) &&
2575 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
2576 s16 tmp = pdadc_tmp[table_size - 1] +
2577 (pdadc_0 - max_idx) * pwr_step;
2578 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
2579 pdadc_0++;
2580 }
2581 }
2582
2583 while (pdg < AR5K_EEPROM_N_PD_GAINS) {
2584 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
2585 pdg++;
2586 }
2587
2588 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
2589 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
2590 pdadc_i++;
2591 }
2592
2593 /* Set gain boundaries */
2594 ath5k_hw_reg_write(ah,
2595 AR5K_REG_SM(pd_gain_overlap,
2596 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
2597 AR5K_REG_SM(gain_boundaries[0],
2598 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
2599 AR5K_REG_SM(gain_boundaries[1],
2600 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
2601 AR5K_REG_SM(gain_boundaries[2],
2602 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
2603 AR5K_REG_SM(gain_boundaries[3],
2604 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
2605 AR5K_PHY_TPC_RG5);
2606
2607 /* Used for setting rate power table */
2608 ah->ah_txpower.txp_min_idx = pwr_min[0];
2609
2610 }
2611
2612 /* Write PDADC values on hw */
2613 static void
2614 ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah,
2615 u8 pdcurves, u8 *pdg_to_idx)
2616 {
2617 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2618 u32 reg;
2619 u8 i;
2620
2621 /* Select the right pdgain curves */
2622
2623 /* Clear current settings */
2624 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
2625 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
2626 AR5K_PHY_TPC_RG1_PDGAIN_2 |
2627 AR5K_PHY_TPC_RG1_PDGAIN_3 |
2628 AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2629
2630 /*
2631 * Use pd_gains curve from eeprom
2632 *
2633 * This overrides the default setting from initvals
2634 * in case some vendors (e.g. Zcomax) don't use the default
2635 * curves. If we don't honor their settings we 'll get a
2636 * 5dB (1 * gain overlap ?) drop.
2637 */
2638 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2639
2640 switch (pdcurves) {
2641 case 3:
2642 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
2643 /* Fall through */
2644 case 2:
2645 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
2646 /* Fall through */
2647 case 1:
2648 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
2649 break;
2650 }
2651 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
2652
2653 /*
2654 * Write TX power values
2655 */
2656 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2657 ath5k_hw_reg_write(ah,
2658 ((pdadc_out[4*i + 0] & 0xff) << 0) |
2659 ((pdadc_out[4*i + 1] & 0xff) << 8) |
2660 ((pdadc_out[4*i + 2] & 0xff) << 16) |
2661 ((pdadc_out[4*i + 3] & 0xff) << 24),
2662 AR5K_PHY_PDADC_TXPOWER(i));
2663 }
2664 }
2665
2666
2667 /*
2668 * Common code for PCDAC/PDADC tables
2669 */
2670
2671 /*
2672 * This is the main function that uses all of the above
2673 * to set PCDAC/PDADC table on hw for the current channel.
2674 * This table is used for tx power calibration on the basband,
2675 * without it we get weird tx power levels and in some cases
2676 * distorted spectral mask
2677 */
2678 static int
2679 ath5k_setup_channel_powertable(struct ath5k_hw *ah,
2680 struct ieee80211_channel *channel,
2681 u8 ee_mode, u8 type)
2682 {
2683 struct ath5k_pdgain_info *pdg_L, *pdg_R;
2684 struct ath5k_chan_pcal_info *pcinfo_L;
2685 struct ath5k_chan_pcal_info *pcinfo_R;
2686 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2687 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
2688 s16 table_min[AR5K_EEPROM_N_PD_GAINS];
2689 s16 table_max[AR5K_EEPROM_N_PD_GAINS];
2690 u8 *tmpL;
2691 u8 *tmpR;
2692 u32 target = channel->center_freq;
2693 int pdg, i;
2694
2695 /* Get surounding freq piers for this channel */
2696 ath5k_get_chan_pcal_surrounding_piers(ah, channel,
2697 &pcinfo_L,
2698 &pcinfo_R);
2699
2700 /* Loop over pd gain curves on
2701 * surounding freq piers by index */
2702 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
2703
2704 /* Fill curves in reverse order
2705 * from lower power (max gain)
2706 * to higher power. Use curve -> idx
2707 * backmapping we did on eeprom init */
2708 u8 idx = pdg_curve_to_idx[pdg];
2709
2710 /* Grab the needed curves by index */
2711 pdg_L = &pcinfo_L->pd_curves[idx];
2712 pdg_R = &pcinfo_R->pd_curves[idx];
2713
2714 /* Initialize the temp tables */
2715 tmpL = ah->ah_txpower.tmpL[pdg];
2716 tmpR = ah->ah_txpower.tmpR[pdg];
2717
2718 /* Set curve's x boundaries and create
2719 * curves so that they cover the same
2720 * range (if we don't do that one table
2721 * will have values on some range and the
2722 * other one won't have any so interpolation
2723 * will fail) */
2724 table_min[pdg] = min(pdg_L->pd_pwr[0],
2725 pdg_R->pd_pwr[0]) / 2;
2726
2727 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2728 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
2729
2730 /* Now create the curves on surrounding channels
2731 * and interpolate if needed to get the final
2732 * curve for this gain on this channel */
2733 switch (type) {
2734 case AR5K_PWRTABLE_LINEAR_PCDAC:
2735 /* Override min/max so that we don't loose
2736 * accuracy (don't divide by 2) */
2737 table_min[pdg] = min(pdg_L->pd_pwr[0],
2738 pdg_R->pd_pwr[0]);
2739
2740 table_max[pdg] =
2741 max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2742 pdg_R->pd_pwr[pdg_R->pd_points - 1]);
2743
2744 /* Override minimum so that we don't get
2745 * out of bounds while extrapolating
2746 * below. Don't do this when we have 2
2747 * curves and we are on the high power curve
2748 * because table_min is ok in this case */
2749 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
2750
2751 table_min[pdg] =
2752 ath5k_get_linear_pcdac_min(pdg_L->pd_step,
2753 pdg_R->pd_step,
2754 pdg_L->pd_pwr,
2755 pdg_R->pd_pwr);
2756
2757 /* Don't go too low because we will
2758 * miss the upper part of the curve.
2759 * Note: 126 = 31.5dB (max power supported)
2760 * in 0.25dB units */
2761 if (table_max[pdg] - table_min[pdg] > 126)
2762 table_min[pdg] = table_max[pdg] - 126;
2763 }
2764
2765 /* Fall through */
2766 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2767 case AR5K_PWRTABLE_PWR_TO_PDADC:
2768
2769 ath5k_create_power_curve(table_min[pdg],
2770 table_max[pdg],
2771 pdg_L->pd_pwr,
2772 pdg_L->pd_step,
2773 pdg_L->pd_points, tmpL, type);
2774
2775 /* We are in a calibration
2776 * pier, no need to interpolate
2777 * between freq piers */
2778 if (pcinfo_L == pcinfo_R)
2779 continue;
2780
2781 ath5k_create_power_curve(table_min[pdg],
2782 table_max[pdg],
2783 pdg_R->pd_pwr,
2784 pdg_R->pd_step,
2785 pdg_R->pd_points, tmpR, type);
2786 break;
2787 default:
2788 return -EINVAL;
2789 }
2790
2791 /* Interpolate between curves
2792 * of surounding freq piers to
2793 * get the final curve for this
2794 * pd gain. Re-use tmpL for interpolation
2795 * output */
2796 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
2797 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2798 tmpL[i] = (u8) ath5k_get_interpolated_value(target,
2799 (s16) pcinfo_L->freq,
2800 (s16) pcinfo_R->freq,
2801 (s16) tmpL[i],
2802 (s16) tmpR[i]);
2803 }
2804 }
2805
2806 /* Now we have a set of curves for this
2807 * channel on tmpL (x range is table_max - table_min
2808 * and y values are tmpL[pdg][]) sorted in the same
2809 * order as EEPROM (because we've used the backmapping).
2810 * So for RF5112 it's from higher power to lower power
2811 * and for RF2413 it's from lower power to higher power.
2812 * For RF5111 we only have one curve. */
2813
2814 /* Fill min and max power levels for this
2815 * channel by interpolating the values on
2816 * surounding channels to complete the dataset */
2817 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
2818 (s16) pcinfo_L->freq,
2819 (s16) pcinfo_R->freq,
2820 pcinfo_L->min_pwr, pcinfo_R->min_pwr);
2821
2822 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
2823 (s16) pcinfo_L->freq,
2824 (s16) pcinfo_R->freq,
2825 pcinfo_L->max_pwr, pcinfo_R->max_pwr);
2826
2827 /* We are ready to go, fill PCDAC/PDADC
2828 * table and write settings on hardware */
2829 switch (type) {
2830 case AR5K_PWRTABLE_LINEAR_PCDAC:
2831 /* For RF5112 we can have one or two curves
2832 * and each curve covers a certain power lvl
2833 * range so we need to do some more processing */
2834 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
2835 ee->ee_pd_gains[ee_mode]);
2836
2837 /* Set txp.offset so that we can
2838 * match max power value with max
2839 * table index */
2840 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
2841
2842 /* Write settings on hw */
2843 ath5k_setup_pcdac_table(ah);
2844 break;
2845 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2846 /* We are done for RF5111 since it has only
2847 * one curve, just fit the curve on the table */
2848 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
2849
2850 /* No rate powertable adjustment for RF5111 */
2851 ah->ah_txpower.txp_min_idx = 0;
2852 ah->ah_txpower.txp_offset = 0;
2853
2854 /* Write settings on hw */
2855 ath5k_setup_pcdac_table(ah);
2856 break;
2857 case AR5K_PWRTABLE_PWR_TO_PDADC:
2858 /* Set PDADC boundaries and fill
2859 * final PDADC table */
2860 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
2861 ee->ee_pd_gains[ee_mode]);
2862
2863 /* Write settings on hw */
2864 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx);
2865
2866 /* Set txp.offset, note that table_min
2867 * can be negative */
2868 ah->ah_txpower.txp_offset = table_min[0];
2869 break;
2870 default:
2871 return -EINVAL;
2872 }
2873
2874 return 0;
2875 }
2876
2877
2878 /*
2879 * Per-rate tx power setting
2880 *
2881 * This is the code that sets the desired tx power (below
2882 * maximum) on hw for each rate (we also have TPC that sets
2883 * power per packet). We do that by providing an index on the
2884 * PCDAC/PDADC table we set up.
2885 */
2886
2887 /*
2888 * Set rate power table
2889 *
2890 * For now we only limit txpower based on maximum tx power
2891 * supported by hw (what's inside rate_info). We need to limit
2892 * this even more, based on regulatory domain etc.
2893 *
2894 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
2895 * and is indexed as follows:
2896 * rates[0] - rates[7] -> OFDM rates
2897 * rates[8] - rates[14] -> CCK rates
2898 * rates[15] -> XR rates (they all have the same power)
2899 */
2900 static void
2901 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
2902 struct ath5k_rate_pcal_info *rate_info,
2903 u8 ee_mode)
2904 {
2905 unsigned int i;
2906 u16 *rates;
2907
2908 /* max_pwr is power level we got from driver/user in 0.5dB
2909 * units, switch to 0.25dB units so we can compare */
2910 max_pwr *= 2;
2911 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
2912
2913 /* apply rate limits */
2914 rates = ah->ah_txpower.txp_rates_power_table;
2915
2916 /* OFDM rates 6 to 24Mb/s */
2917 for (i = 0; i < 5; i++)
2918 rates[i] = min(max_pwr, rate_info->target_power_6to24);
2919
2920 /* Rest OFDM rates */
2921 rates[5] = min(rates[0], rate_info->target_power_36);
2922 rates[6] = min(rates[0], rate_info->target_power_48);
2923 rates[7] = min(rates[0], rate_info->target_power_54);
2924
2925 /* CCK rates */
2926 /* 1L */
2927 rates[8] = min(rates[0], rate_info->target_power_6to24);
2928 /* 2L */
2929 rates[9] = min(rates[0], rate_info->target_power_36);
2930 /* 2S */
2931 rates[10] = min(rates[0], rate_info->target_power_36);
2932 /* 5L */
2933 rates[11] = min(rates[0], rate_info->target_power_48);
2934 /* 5S */
2935 rates[12] = min(rates[0], rate_info->target_power_48);
2936 /* 11L */
2937 rates[13] = min(rates[0], rate_info->target_power_54);
2938 /* 11S */
2939 rates[14] = min(rates[0], rate_info->target_power_54);
2940
2941 /* XR rates */
2942 rates[15] = min(rates[0], rate_info->target_power_6to24);
2943
2944 /* CCK rates have different peak to average ratio
2945 * so we have to tweak their power so that gainf
2946 * correction works ok. For this we use OFDM to
2947 * CCK delta from eeprom */
2948 if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
2949 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
2950 for (i = 8; i <= 15; i++)
2951 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
2952
2953 /* Now that we have all rates setup use table offset to
2954 * match the power range set by user with the power indices
2955 * on PCDAC/PDADC table */
2956 for (i = 0; i < 16; i++) {
2957 rates[i] += ah->ah_txpower.txp_offset;
2958 /* Don't get out of bounds */
2959 if (rates[i] > 63)
2960 rates[i] = 63;
2961 }
2962
2963 /* Min/max in 0.25dB units */
2964 ah->ah_txpower.txp_min_pwr = 2 * rates[7];
2965 ah->ah_txpower.txp_max_pwr = 2 * rates[0];
2966 ah->ah_txpower.txp_ofdm = rates[7];
2967 }
2968
2969
2970 /*
2971 * Set transmition power
2972 */
2973 int
2974 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
2975 u8 ee_mode, u8 txpower)
2976 {
2977 struct ath5k_rate_pcal_info rate_info;
2978 u8 type;
2979 int ret;
2980
2981 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
2982 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
2983 return -EINVAL;
2984 }
2985
2986 /* Reset TX power values */
2987 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
2988 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
2989 ah->ah_txpower.txp_min_pwr = 0;
2990 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
2991
2992 /* Initialize TX power table */
2993 switch (ah->ah_radio) {
2994 case AR5K_RF5111:
2995 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
2996 break;
2997 case AR5K_RF5112:
2998 type = AR5K_PWRTABLE_LINEAR_PCDAC;
2999 break;
3000 case AR5K_RF2413:
3001 case AR5K_RF5413:
3002 case AR5K_RF2316:
3003 case AR5K_RF2317:
3004 case AR5K_RF2425:
3005 type = AR5K_PWRTABLE_PWR_TO_PDADC;
3006 break;
3007 default:
3008 return -EINVAL;
3009 }
3010
3011 ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type);
3012 if (ret)
3013 return ret;
3014
3015 /* Limit max power if we have a CTL available */
3016 ath5k_get_max_ctl_power(ah, channel);
3017
3018
3019
3020
3021
3022 /* Get surounding channels for per-rate power table
3023 * calibration */
3024 ath5k_get_rate_pcal_data(ah, channel, &rate_info);
3025
3026 /* Setup rate power table */
3027 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
3028
3029 /* Write rate power table on hw */
3030 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
3031 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
3032 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
3033
3034 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
3035 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
3036 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
3037
3038 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
3039 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
3040 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
3041
3042 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
3043 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
3044 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
3045
3046 if (ah->ah_txpower.txp_tpc) {
3047 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
3048 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3049
3050 ath5k_hw_reg_write(ah,
3051 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
3052 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
3053 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
3054 AR5K_TPC);
3055 } else {
3056 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
3057 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3058 }
3059
3060 return 0;
3061 }
3062
3063 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
3064 {
3065 /*Just a try M.F.*/
3066 struct ieee80211_channel *channel = ah->ah_current_channel;
3067 u8 ee_mode;
3068
3069 switch (channel->hw_value & CHANNEL_MODES) {
3070 case CHANNEL_A:
3071 case CHANNEL_T:
3072 case CHANNEL_XR:
3073 ee_mode = AR5K_EEPROM_MODE_11A;
3074 break;
3075 case CHANNEL_G:
3076 case CHANNEL_TG:
3077 ee_mode = AR5K_EEPROM_MODE_11G;
3078 break;
3079 case CHANNEL_B:
3080 ee_mode = AR5K_EEPROM_MODE_11B;
3081 break;
3082 default:
3083 ATH5K_ERR(ah->ah_sc,
3084 "invalid channel: %d\n", channel->center_freq);
3085 return -EINVAL;
3086 }
3087
3088 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
3089 "changing txpower to %d\n", txpower);
3090
3091 return ath5k_hw_txpower(ah, channel, ee_mode, txpower);
3092 }
Tomato firmware and modifications.