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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / wireless / ath / ath5k / base.c
bloba87df2205efa3ac1792a135ae0509a1b4997cecd
1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
46 #include <linux/if.h>
47 #include <linux/io.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/pci-aspm.h>
52 #include <linux/ethtool.h>
53 #include <linux/uaccess.h>
54 #include <linux/slab.h>
55
56 #include <net/ieee80211_radiotap.h>
57
58 #include <asm/unaligned.h>
59
60 #include "base.h"
61 #include "reg.h"
62 #include "debug.h"
63 #include "ani.h"
64
65 static int modparam_nohwcrypt;
66 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
67 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
68
69 static int modparam_all_channels;
70 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
71 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
72
73
74 /******************\
75 * Internal defines *
76 \******************/
77
78 /* Module info */
79 MODULE_AUTHOR("Jiri Slaby");
80 MODULE_AUTHOR("Nick Kossifidis");
81 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
82 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
83 MODULE_LICENSE("Dual BSD/GPL");
84 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
85
86
87 /* Known PCI ids */
88 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
89 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
90 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
91 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
92 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
93 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
94 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
95 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
97 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
103 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
104 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
105 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
106 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
107 { 0 }
108 };
109 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
110
111 /* Known SREVs */
112 static const struct ath5k_srev_name srev_names[] = {
113 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
114 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
115 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
116 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
117 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
118 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
119 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
120 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
121 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
122 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
123 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
124 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
125 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
126 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
127 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
128 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
129 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
130 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
131 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
132 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
133 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
134 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
135 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
136 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
137 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
138 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
139 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
140 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
141 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
142 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
143 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
144 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
145 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
146 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
147 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
148 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
149 };
150
151 static const struct ieee80211_rate ath5k_rates[] = {
152 { .bitrate = 10,
153 .hw_value = ATH5K_RATE_CODE_1M, },
154 { .bitrate = 20,
155 .hw_value = ATH5K_RATE_CODE_2M,
156 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
157 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
158 { .bitrate = 55,
159 .hw_value = ATH5K_RATE_CODE_5_5M,
160 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
161 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
162 { .bitrate = 110,
163 .hw_value = ATH5K_RATE_CODE_11M,
164 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
165 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
166 { .bitrate = 60,
167 .hw_value = ATH5K_RATE_CODE_6M,
168 .flags = 0 },
169 { .bitrate = 90,
170 .hw_value = ATH5K_RATE_CODE_9M,
171 .flags = 0 },
172 { .bitrate = 120,
173 .hw_value = ATH5K_RATE_CODE_12M,
174 .flags = 0 },
175 { .bitrate = 180,
176 .hw_value = ATH5K_RATE_CODE_18M,
177 .flags = 0 },
178 { .bitrate = 240,
179 .hw_value = ATH5K_RATE_CODE_24M,
180 .flags = 0 },
181 { .bitrate = 360,
182 .hw_value = ATH5K_RATE_CODE_36M,
183 .flags = 0 },
184 { .bitrate = 480,
185 .hw_value = ATH5K_RATE_CODE_48M,
186 .flags = 0 },
187 { .bitrate = 540,
188 .hw_value = ATH5K_RATE_CODE_54M,
189 .flags = 0 },
190 /* XR missing */
191 };
192
193 /*
194 * Prototypes - PCI stack related functions
195 */
196 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
197 const struct pci_device_id *id);
198 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
199 #ifdef CONFIG_PM_SLEEP
200 static int ath5k_pci_suspend(struct device *dev);
201 static int ath5k_pci_resume(struct device *dev);
202
203 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
204 #define ATH5K_PM_OPS (&ath5k_pm_ops)
205 #else
206 #define ATH5K_PM_OPS NULL
207 #endif /* CONFIG_PM_SLEEP */
208
209 static struct pci_driver ath5k_pci_driver = {
210 .name = KBUILD_MODNAME,
211 .id_table = ath5k_pci_id_table,
212 .probe = ath5k_pci_probe,
213 .remove = __devexit_p(ath5k_pci_remove),
214 .driver.pm = ATH5K_PM_OPS,
215 };
216
217
218
219 /*
220 * Prototypes - MAC 802.11 stack related functions
221 */
222 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
223 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
224 struct ath5k_txq *txq);
225 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
226 static int ath5k_start(struct ieee80211_hw *hw);
227 static void ath5k_stop(struct ieee80211_hw *hw);
228 static int ath5k_add_interface(struct ieee80211_hw *hw,
229 struct ieee80211_vif *vif);
230 static void ath5k_remove_interface(struct ieee80211_hw *hw,
231 struct ieee80211_vif *vif);
232 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
233 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
234 struct netdev_hw_addr_list *mc_list);
235 static void ath5k_configure_filter(struct ieee80211_hw *hw,
236 unsigned int changed_flags,
237 unsigned int *new_flags,
238 u64 multicast);
239 static int ath5k_set_key(struct ieee80211_hw *hw,
240 enum set_key_cmd cmd,
241 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
242 struct ieee80211_key_conf *key);
243 static int ath5k_get_stats(struct ieee80211_hw *hw,
244 struct ieee80211_low_level_stats *stats);
245 static int ath5k_get_survey(struct ieee80211_hw *hw,
246 int idx, struct survey_info *survey);
247 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
248 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
249 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
250 static int ath5k_beacon_update(struct ieee80211_hw *hw,
251 struct ieee80211_vif *vif);
252 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
253 struct ieee80211_vif *vif,
254 struct ieee80211_bss_conf *bss_conf,
255 u32 changes);
256 static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
257 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
258 static void ath5k_set_coverage_class(struct ieee80211_hw *hw,
259 u8 coverage_class);
260
261 static const struct ieee80211_ops ath5k_hw_ops = {
262 .tx = ath5k_tx,
263 .start = ath5k_start,
264 .stop = ath5k_stop,
265 .add_interface = ath5k_add_interface,
266 .remove_interface = ath5k_remove_interface,
267 .config = ath5k_config,
268 .prepare_multicast = ath5k_prepare_multicast,
269 .configure_filter = ath5k_configure_filter,
270 .set_key = ath5k_set_key,
271 .get_stats = ath5k_get_stats,
272 .get_survey = ath5k_get_survey,
273 .conf_tx = NULL,
274 .get_tsf = ath5k_get_tsf,
275 .set_tsf = ath5k_set_tsf,
276 .reset_tsf = ath5k_reset_tsf,
277 .bss_info_changed = ath5k_bss_info_changed,
278 .sw_scan_start = ath5k_sw_scan_start,
279 .sw_scan_complete = ath5k_sw_scan_complete,
280 .set_coverage_class = ath5k_set_coverage_class,
281 };
282
283 /*
284 * Prototypes - Internal functions
285 */
286 /* Attach detach */
287 static int ath5k_attach(struct pci_dev *pdev,
288 struct ieee80211_hw *hw);
289 static void ath5k_detach(struct pci_dev *pdev,
290 struct ieee80211_hw *hw);
291 /* Channel/mode setup */
292 static inline short ath5k_ieee2mhz(short chan);
293 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
294 struct ieee80211_channel *channels,
295 unsigned int mode,
296 unsigned int max);
297 static int ath5k_setup_bands(struct ieee80211_hw *hw);
298 static int ath5k_chan_set(struct ath5k_softc *sc,
299 struct ieee80211_channel *chan);
300 static void ath5k_setcurmode(struct ath5k_softc *sc,
301 unsigned int mode);
302 static void ath5k_mode_setup(struct ath5k_softc *sc);
303
304 /* Descriptor setup */
305 static int ath5k_desc_alloc(struct ath5k_softc *sc,
306 struct pci_dev *pdev);
307 static void ath5k_desc_free(struct ath5k_softc *sc,
308 struct pci_dev *pdev);
309 /* Buffers setup */
310 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
311 struct ath5k_buf *bf);
312 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
313 struct ath5k_buf *bf,
314 struct ath5k_txq *txq, int padsize);
315
316 static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
317 struct ath5k_buf *bf)
318 {
319 BUG_ON(!bf);
320 if (!bf->skb)
321 return;
322 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
323 PCI_DMA_TODEVICE);
324 dev_kfree_skb_any(bf->skb);
325 bf->skb = NULL;
326 bf->skbaddr = 0;
327 bf->desc->ds_data = 0;
328 }
329
330 static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
331 struct ath5k_buf *bf)
332 {
333 struct ath5k_hw *ah = sc->ah;
334 struct ath_common *common = ath5k_hw_common(ah);
335
336 BUG_ON(!bf);
337 if (!bf->skb)
338 return;
339 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
340 PCI_DMA_FROMDEVICE);
341 dev_kfree_skb_any(bf->skb);
342 bf->skb = NULL;
343 bf->skbaddr = 0;
344 bf->desc->ds_data = 0;
345 }
346
347
348 /* Queues setup */
349 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
350 int qtype, int subtype);
351 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
352 static int ath5k_beaconq_config(struct ath5k_softc *sc);
353 static void ath5k_txq_drainq(struct ath5k_softc *sc,
354 struct ath5k_txq *txq);
355 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
356 static void ath5k_txq_release(struct ath5k_softc *sc);
357 /* Rx handling */
358 static int ath5k_rx_start(struct ath5k_softc *sc);
359 static void ath5k_rx_stop(struct ath5k_softc *sc);
360 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
361 struct sk_buff *skb,
362 struct ath5k_rx_status *rs);
363 static void ath5k_tasklet_rx(unsigned long data);
364 /* Tx handling */
365 static void ath5k_tx_processq(struct ath5k_softc *sc,
366 struct ath5k_txq *txq);
367 static void ath5k_tasklet_tx(unsigned long data);
368 /* Beacon handling */
369 static int ath5k_beacon_setup(struct ath5k_softc *sc,
370 struct ath5k_buf *bf);
371 static void ath5k_beacon_send(struct ath5k_softc *sc);
372 static void ath5k_beacon_config(struct ath5k_softc *sc);
373 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
374 static void ath5k_tasklet_beacon(unsigned long data);
375 static void ath5k_tasklet_ani(unsigned long data);
376
377 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
378 {
379 u64 tsf = ath5k_hw_get_tsf64(ah);
380
381 if ((tsf & 0x7fff) < rstamp)
382 tsf -= 0x8000;
383
384 return (tsf & ~0x7fff) | rstamp;
385 }
386
387 /* Interrupt handling */
388 static int ath5k_init(struct ath5k_softc *sc);
389 static int ath5k_stop_locked(struct ath5k_softc *sc);
390 static int ath5k_stop_hw(struct ath5k_softc *sc);
391 static irqreturn_t ath5k_intr(int irq, void *dev_id);
392 static void ath5k_reset_work(struct work_struct *work);
393
394 static void ath5k_tasklet_calibrate(unsigned long data);
395
396 /*
397 * Module init/exit functions
398 */
399 static int __init
400 init_ath5k_pci(void)
401 {
402 int ret;
403
404 ath5k_debug_init();
405
406 ret = pci_register_driver(&ath5k_pci_driver);
407 if (ret) {
408 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
409 return ret;
410 }
411
412 return 0;
413 }
414
415 static void __exit
416 exit_ath5k_pci(void)
417 {
418 pci_unregister_driver(&ath5k_pci_driver);
419
420 ath5k_debug_finish();
421 }
422
423 module_init(init_ath5k_pci);
424 module_exit(exit_ath5k_pci);
425
426
427 /********************\
428 * PCI Initialization *
429 \********************/
430
431 static const char *
432 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
433 {
434 const char *name = "xxxxx";
435 unsigned int i;
436
437 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
438 if (srev_names[i].sr_type != type)
439 continue;
440
441 if ((val & 0xf0) == srev_names[i].sr_val)
442 name = srev_names[i].sr_name;
443
444 if ((val & 0xff) == srev_names[i].sr_val) {
445 name = srev_names[i].sr_name;
446 break;
447 }
448 }
449
450 return name;
451 }
452 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
453 {
454 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
455 return ath5k_hw_reg_read(ah, reg_offset);
456 }
457
458 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
459 {
460 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
461 ath5k_hw_reg_write(ah, val, reg_offset);
462 }
463
464 static const struct ath_ops ath5k_common_ops = {
465 .read = ath5k_ioread32,
466 .write = ath5k_iowrite32,
467 };
468
469 static int __devinit
470 ath5k_pci_probe(struct pci_dev *pdev,
471 const struct pci_device_id *id)
472 {
473 void __iomem *mem;
474 struct ath5k_softc *sc;
475 struct ath_common *common;
476 struct ieee80211_hw *hw;
477 int ret;
478 u8 csz;
479
480 /*
481 * L0s needs to be disabled on all ath5k cards.
482 *
483 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
484 * by default in the future in 2.6.36) this will also mean both L1 and
485 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
486 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
487 * though but cannot currently undue the effect of a blacklist, for
488 * details you can read pcie_aspm_sanity_check() and see how it adjusts
489 * the device link capability.
490 *
491 * It may be possible in the future to implement some PCI API to allow
492 * drivers to override blacklists for pre 1.1 PCIe but for now it is
493 * best to accept that both L0s and L1 will be disabled completely for
494 * distributions shipping with CONFIG_PCIEASPM rather than having this
495 * issue present. Motivation for adding this new API will be to help
496 * with power consumption for some of these devices.
497 */
498 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
499
500 ret = pci_enable_device(pdev);
501 if (ret) {
502 dev_err(&pdev->dev, "can't enable device\n");
503 goto err;
504 }
505
506 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
507 if (ret) {
508 dev_err(&pdev->dev, "32-bit DMA not available\n");
509 goto err_dis;
510 }
511
512 /*
513 * Cache line size is used to size and align various
514 * structures used to communicate with the hardware.
515 */
516 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
517 if (csz == 0) {
518 /*
519 * Linux 2.4.18 (at least) writes the cache line size
520 * register as a 16-bit wide register which is wrong.
521 * We must have this setup properly for rx buffer
522 * DMA to work so force a reasonable value here if it
523 * comes up zero.
524 */
525 csz = L1_CACHE_BYTES >> 2;
526 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
527 }
528 /*
529 * The default setting of latency timer yields poor results,
530 * set it to the value used by other systems. It may be worth
531 * tweaking this setting more.
532 */
533 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
534
535 /* Enable bus mastering */
536 pci_set_master(pdev);
537
538 /*
539 * Disable the RETRY_TIMEOUT register (0x41) to keep
540 * PCI Tx retries from interfering with C3 CPU state.
541 */
542 pci_write_config_byte(pdev, 0x41, 0);
543
544 ret = pci_request_region(pdev, 0, "ath5k");
545 if (ret) {
546 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
547 goto err_dis;
548 }
549
550 mem = pci_iomap(pdev, 0, 0);
551 if (!mem) {
552 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
553 ret = -EIO;
554 goto err_reg;
555 }
556
557 /*
558 * Allocate hw (mac80211 main struct)
559 * and hw->priv (driver private data)
560 */
561 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
562 if (hw == NULL) {
563 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
564 ret = -ENOMEM;
565 goto err_map;
566 }
567
568 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
569
570 /* Initialize driver private data */
571 SET_IEEE80211_DEV(hw, &pdev->dev);
572 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
573 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
574 IEEE80211_HW_SIGNAL_DBM;
575
576 hw->wiphy->interface_modes =
577 BIT(NL80211_IFTYPE_AP) |
578 BIT(NL80211_IFTYPE_STATION) |
579 BIT(NL80211_IFTYPE_ADHOC) |
580 BIT(NL80211_IFTYPE_MESH_POINT);
581
582 hw->extra_tx_headroom = 2;
583 hw->channel_change_time = 5000;
584 sc = hw->priv;
585 sc->hw = hw;
586 sc->pdev = pdev;
587
588 ath5k_debug_init_device(sc);
589
590 /*
591 * Mark the device as detached to avoid processing
592 * interrupts until setup is complete.
593 */
594 __set_bit(ATH_STAT_INVALID, sc->status);
595
596 sc->iobase = mem; /* So we can unmap it on detach */
597 sc->opmode = NL80211_IFTYPE_STATION;
598 sc->bintval = 1000;
599 mutex_init(&sc->lock);
600 spin_lock_init(&sc->rxbuflock);
601 spin_lock_init(&sc->txbuflock);
602 spin_lock_init(&sc->block);
603
604 /* Set private data */
605 pci_set_drvdata(pdev, sc);
606
607 /* Setup interrupt handler */
608 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
609 if (ret) {
610 ATH5K_ERR(sc, "request_irq failed\n");
611 goto err_free;
612 }
613
614 /*If we passed the test malloc a ath5k_hw struct*/
615 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
616 if (!sc->ah) {
617 ret = -ENOMEM;
618 ATH5K_ERR(sc, "out of memory\n");
619 goto err_irq;
620 }
621
622 sc->ah->ah_sc = sc;
623 sc->ah->ah_iobase = sc->iobase;
624 common = ath5k_hw_common(sc->ah);
625 common->ops = &ath5k_common_ops;
626 common->ah = sc->ah;
627 common->hw = hw;
628 common->cachelsz = csz << 2; /* convert to bytes */
629
630 /* Initialize device */
631 ret = ath5k_hw_attach(sc);
632 if (ret) {
633 goto err_free_ah;
634 }
635
636 /* set up multi-rate retry capabilities */
637 if (sc->ah->ah_version == AR5K_AR5212) {
638 hw->max_rates = 4;
639 hw->max_rate_tries = 11;
640 }
641
642 /* Finish private driver data initialization */
643 ret = ath5k_attach(pdev, hw);
644 if (ret)
645 goto err_ah;
646
647 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
648 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
649 sc->ah->ah_mac_srev,
650 sc->ah->ah_phy_revision);
651
652 if (!sc->ah->ah_single_chip) {
653 /* Single chip radio (!RF5111) */
654 if (sc->ah->ah_radio_5ghz_revision &&
655 !sc->ah->ah_radio_2ghz_revision) {
656 /* No 5GHz support -> report 2GHz radio */
657 if (!test_bit(AR5K_MODE_11A,
658 sc->ah->ah_capabilities.cap_mode)) {
659 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
660 ath5k_chip_name(AR5K_VERSION_RAD,
661 sc->ah->ah_radio_5ghz_revision),
662 sc->ah->ah_radio_5ghz_revision);
663 /* No 2GHz support (5110 and some
664 * 5Ghz only cards) -> report 5Ghz radio */
665 } else if (!test_bit(AR5K_MODE_11B,
666 sc->ah->ah_capabilities.cap_mode)) {
667 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
668 ath5k_chip_name(AR5K_VERSION_RAD,
669 sc->ah->ah_radio_5ghz_revision),
670 sc->ah->ah_radio_5ghz_revision);
671 /* Multiband radio */
672 } else {
673 ATH5K_INFO(sc, "RF%s multiband radio found"
674 " (0x%x)\n",
675 ath5k_chip_name(AR5K_VERSION_RAD,
676 sc->ah->ah_radio_5ghz_revision),
677 sc->ah->ah_radio_5ghz_revision);
678 }
679 }
680 /* Multi chip radio (RF5111 - RF2111) ->
681 * report both 2GHz/5GHz radios */
682 else if (sc->ah->ah_radio_5ghz_revision &&
683 sc->ah->ah_radio_2ghz_revision){
684 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
685 ath5k_chip_name(AR5K_VERSION_RAD,
686 sc->ah->ah_radio_5ghz_revision),
687 sc->ah->ah_radio_5ghz_revision);
688 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
689 ath5k_chip_name(AR5K_VERSION_RAD,
690 sc->ah->ah_radio_2ghz_revision),
691 sc->ah->ah_radio_2ghz_revision);
692 }
693 }
694
695
696 /* ready to process interrupts */
697 __clear_bit(ATH_STAT_INVALID, sc->status);
698
699 return 0;
700 err_ah:
701 ath5k_hw_detach(sc->ah);
702 err_irq:
703 free_irq(pdev->irq, sc);
704 err_free_ah:
705 kfree(sc->ah);
706 err_free:
707 ieee80211_free_hw(hw);
708 err_map:
709 pci_iounmap(pdev, mem);
710 err_reg:
711 pci_release_region(pdev, 0);
712 err_dis:
713 pci_disable_device(pdev);
714 err:
715 return ret;
716 }
717
718 static void __devexit
719 ath5k_pci_remove(struct pci_dev *pdev)
720 {
721 struct ath5k_softc *sc = pci_get_drvdata(pdev);
722
723 ath5k_debug_finish_device(sc);
724 ath5k_detach(pdev, sc->hw);
725 ath5k_hw_detach(sc->ah);
726 kfree(sc->ah);
727 free_irq(pdev->irq, sc);
728 pci_iounmap(pdev, sc->iobase);
729 pci_release_region(pdev, 0);
730 pci_disable_device(pdev);
731 ieee80211_free_hw(sc->hw);
732 }
733
734 #ifdef CONFIG_PM_SLEEP
735 static int ath5k_pci_suspend(struct device *dev)
736 {
737 struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
738
739 ath5k_led_off(sc);
740 return 0;
741 }
742
743 static int ath5k_pci_resume(struct device *dev)
744 {
745 struct pci_dev *pdev = to_pci_dev(dev);
746 struct ath5k_softc *sc = pci_get_drvdata(pdev);
747
748 /*
749 * Suspend/Resume resets the PCI configuration space, so we have to
750 * re-disable the RETRY_TIMEOUT register (0x41) to keep
751 * PCI Tx retries from interfering with C3 CPU state
752 */
753 pci_write_config_byte(pdev, 0x41, 0);
754
755 ath5k_led_enable(sc);
756 return 0;
757 }
758 #endif /* CONFIG_PM_SLEEP */
759
760
761 /***********************\
762 * Driver Initialization *
763 \***********************/
764
765 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
766 {
767 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
768 struct ath5k_softc *sc = hw->priv;
769 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
770
771 return ath_reg_notifier_apply(wiphy, request, regulatory);
772 }
773
774 static int
775 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
776 {
777 struct ath5k_softc *sc = hw->priv;
778 struct ath5k_hw *ah = sc->ah;
779 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
780 u8 mac[ETH_ALEN] = {};
781 int ret;
782
783 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
784
785 /*
786 * Check if the MAC has multi-rate retry support.
787 * We do this by trying to setup a fake extended
788 * descriptor. MAC's that don't have support will
789 * return false w/o doing anything. MAC's that do
790 * support it will return true w/o doing anything.
791 */
792 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
793
794 if (ret < 0)
795 goto err;
796 if (ret > 0)
797 __set_bit(ATH_STAT_MRRETRY, sc->status);
798
799 /*
800 * Collect the channel list. The 802.11 layer
801 * is resposible for filtering this list based
802 * on settings like the phy mode and regulatory
803 * domain restrictions.
804 */
805 ret = ath5k_setup_bands(hw);
806 if (ret) {
807 ATH5K_ERR(sc, "can't get channels\n");
808 goto err;
809 }
810
811 /* NB: setup here so ath5k_rate_update is happy */
812 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
813 ath5k_setcurmode(sc, AR5K_MODE_11A);
814 else
815 ath5k_setcurmode(sc, AR5K_MODE_11B);
816
817 /*
818 * Allocate tx+rx descriptors and populate the lists.
819 */
820 ret = ath5k_desc_alloc(sc, pdev);
821 if (ret) {
822 ATH5K_ERR(sc, "can't allocate descriptors\n");
823 goto err;
824 }
825
826 /*
827 * Allocate hardware transmit queues: one queue for
828 * beacon frames and one data queue for each QoS
829 * priority. Note that hw functions handle reseting
830 * these queues at the needed time.
831 */
832 ret = ath5k_beaconq_setup(ah);
833 if (ret < 0) {
834 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
835 goto err_desc;
836 }
837 sc->bhalq = ret;
838 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
839 if (IS_ERR(sc->cabq)) {
840 ATH5K_ERR(sc, "can't setup cab queue\n");
841 ret = PTR_ERR(sc->cabq);
842 goto err_bhal;
843 }
844
845 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
846 if (IS_ERR(sc->txq)) {
847 ATH5K_ERR(sc, "can't setup xmit queue\n");
848 ret = PTR_ERR(sc->txq);
849 goto err_queues;
850 }
851
852 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
853 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
854 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
855 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
856 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
857
858 INIT_WORK(&sc->reset_work, ath5k_reset_work);
859
860 ret = ath5k_eeprom_read_mac(ah, mac);
861 if (ret) {
862 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
863 sc->pdev->device);
864 goto err_queues;
865 }
866
867 SET_IEEE80211_PERM_ADDR(hw, mac);
868 /* All MAC address bits matter for ACKs */
869 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
870 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
871
872 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
873 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
874 if (ret) {
875 ATH5K_ERR(sc, "can't initialize regulatory system\n");
876 goto err_queues;
877 }
878
879 ret = ieee80211_register_hw(hw);
880 if (ret) {
881 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
882 goto err_queues;
883 }
884
885 if (!ath_is_world_regd(regulatory))
886 regulatory_hint(hw->wiphy, regulatory->alpha2);
887
888 ath5k_init_leds(sc);
889
890 ath5k_sysfs_register(sc);
891
892 return 0;
893 err_queues:
894 ath5k_txq_release(sc);
895 err_bhal:
896 ath5k_hw_release_tx_queue(ah, sc->bhalq);
897 err_desc:
898 ath5k_desc_free(sc, pdev);
899 err:
900 return ret;
901 }
902
903 static void
904 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
905 {
906 struct ath5k_softc *sc = hw->priv;
907
908 ieee80211_unregister_hw(hw);
909 ath5k_desc_free(sc, pdev);
910 ath5k_txq_release(sc);
911 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
912 ath5k_unregister_leds(sc);
913
914 ath5k_sysfs_unregister(sc);
915 /*
916 * NB: can't reclaim these until after ieee80211_ifdetach
917 * returns because we'll get called back to reclaim node
918 * state and potentially want to use them.
919 */
920 }
921
922
923
924
925 /********************\
926 * Channel/mode setup *
927 \********************/
928
929 /*
930 * Convert IEEE channel number to MHz frequency.
931 */
932 static inline short
933 ath5k_ieee2mhz(short chan)
934 {
935 if (chan <= 14 || chan >= 27)
936 return ieee80211chan2mhz(chan);
937 else
938 return 2212 + chan * 20;
939 }
940
941 /*
942 * Returns true for the channel numbers used without all_channels modparam.
943 */
944 static bool ath5k_is_standard_channel(short chan)
945 {
946 return ((chan <= 14) ||
947 /* UNII 1,2 */
948 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
949 /* midband */
950 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
951 /* UNII-3 */
952 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
953 }
954
955 static unsigned int
956 ath5k_copy_channels(struct ath5k_hw *ah,
957 struct ieee80211_channel *channels,
958 unsigned int mode,
959 unsigned int max)
960 {
961 unsigned int i, count, size, chfreq, freq, ch;
962
963 if (!test_bit(mode, ah->ah_modes))
964 return 0;
965
966 switch (mode) {
967 case AR5K_MODE_11A:
968 case AR5K_MODE_11A_TURBO:
969 /* 1..220, but 2GHz frequencies are filtered by check_channel */
970 size = 220 ;
971 chfreq = CHANNEL_5GHZ;
972 break;
973 case AR5K_MODE_11B:
974 case AR5K_MODE_11G:
975 case AR5K_MODE_11G_TURBO:
976 size = 26;
977 chfreq = CHANNEL_2GHZ;
978 break;
979 default:
980 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
981 return 0;
982 }
983
984 for (i = 0, count = 0; i < size && max > 0; i++) {
985 ch = i + 1 ;
986 freq = ath5k_ieee2mhz(ch);
987
988 /* Check if channel is supported by the chipset */
989 if (!ath5k_channel_ok(ah, freq, chfreq))
990 continue;
991
992 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
993 continue;
994
995 /* Write channel info and increment counter */
996 channels[count].center_freq = freq;
997 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
998 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
999 switch (mode) {
1000 case AR5K_MODE_11A:
1001 case AR5K_MODE_11G:
1002 channels[count].hw_value = chfreq | CHANNEL_OFDM;
1003 break;
1004 case AR5K_MODE_11A_TURBO:
1005 case AR5K_MODE_11G_TURBO:
1006 channels[count].hw_value = chfreq |
1007 CHANNEL_OFDM | CHANNEL_TURBO;
1008 break;
1009 case AR5K_MODE_11B:
1010 channels[count].hw_value = CHANNEL_B;
1011 }
1012
1013 count++;
1014 max--;
1015 }
1016
1017 return count;
1018 }
1019
1020 static void
1021 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1022 {
1023 u8 i;
1024
1025 for (i = 0; i < AR5K_MAX_RATES; i++)
1026 sc->rate_idx[b->band][i] = -1;
1027
1028 for (i = 0; i < b->n_bitrates; i++) {
1029 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1030 if (b->bitrates[i].hw_value_short)
1031 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1032 }
1033 }
1034
1035 static int
1036 ath5k_setup_bands(struct ieee80211_hw *hw)
1037 {
1038 struct ath5k_softc *sc = hw->priv;
1039 struct ath5k_hw *ah = sc->ah;
1040 struct ieee80211_supported_band *sband;
1041 int max_c, count_c = 0;
1042 int i;
1043
1044 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
1045 max_c = ARRAY_SIZE(sc->channels);
1046
1047 /* 2GHz band */
1048 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1049 sband->band = IEEE80211_BAND_2GHZ;
1050 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
1051
1052 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1053 /* G mode */
1054 memcpy(sband->bitrates, &ath5k_rates[0],
1055 sizeof(struct ieee80211_rate) * 12);
1056 sband->n_bitrates = 12;
1057
1058 sband->channels = sc->channels;
1059 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1060 AR5K_MODE_11G, max_c);
1061
1062 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1063 count_c = sband->n_channels;
1064 max_c -= count_c;
1065 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1066 /* B mode */
1067 memcpy(sband->bitrates, &ath5k_rates[0],
1068 sizeof(struct ieee80211_rate) * 4);
1069 sband->n_bitrates = 4;
1070
1071 /* 5211 only supports B rates and uses 4bit rate codes
1072 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1073 * fix them up here:
1074 */
1075 if (ah->ah_version == AR5K_AR5211) {
1076 for (i = 0; i < 4; i++) {
1077 sband->bitrates[i].hw_value =
1078 sband->bitrates[i].hw_value & 0xF;
1079 sband->bitrates[i].hw_value_short =
1080 sband->bitrates[i].hw_value_short & 0xF;
1081 }
1082 }
1083
1084 sband->channels = sc->channels;
1085 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1086 AR5K_MODE_11B, max_c);
1087
1088 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1089 count_c = sband->n_channels;
1090 max_c -= count_c;
1091 }
1092 ath5k_setup_rate_idx(sc, sband);
1093
1094 /* 5GHz band, A mode */
1095 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1096 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1097 sband->band = IEEE80211_BAND_5GHZ;
1098 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1099
1100 memcpy(sband->bitrates, &ath5k_rates[4],
1101 sizeof(struct ieee80211_rate) * 8);
1102 sband->n_bitrates = 8;
1103
1104 sband->channels = &sc->channels[count_c];
1105 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1106 AR5K_MODE_11A, max_c);
1107
1108 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1109 }
1110 ath5k_setup_rate_idx(sc, sband);
1111
1112 ath5k_debug_dump_bands(sc);
1113
1114 return 0;
1115 }
1116
1117 /*
1118 * Set/change channels. We always reset the chip.
1119 * To accomplish this we must first cleanup any pending DMA,
1120 * then restart stuff after a la ath5k_init.
1121 *
1122 * Called with sc->lock.
1123 */
1124 static int
1125 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1126 {
1127 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1128 "channel set, resetting (%u -> %u MHz)\n",
1129 sc->curchan->center_freq, chan->center_freq);
1130
1131 /*
1132 * To switch channels clear any pending DMA operations;
1133 * wait long enough for the RX fifo to drain, reset the
1134 * hardware at the new frequency, and then re-enable
1135 * the relevant bits of the h/w.
1136 */
1137 return ath5k_reset(sc, chan);
1138 }
1139
1140 static void
1141 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1142 {
1143 sc->curmode = mode;
1144
1145 if (mode == AR5K_MODE_11A) {
1146 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1147 } else {
1148 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1149 }
1150 }
1151
1152 static void
1153 ath5k_mode_setup(struct ath5k_softc *sc)
1154 {
1155 struct ath5k_hw *ah = sc->ah;
1156 u32 rfilt;
1157
1158 /* configure rx filter */
1159 rfilt = sc->filter_flags;
1160 ath5k_hw_set_rx_filter(ah, rfilt);
1161
1162 if (ath5k_hw_hasbssidmask(ah))
1163 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1164
1165 /* configure operational mode */
1166 ath5k_hw_set_opmode(ah, sc->opmode);
1167
1168 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
1169 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1170 }
1171
1172 static inline int
1173 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1174 {
1175 int rix;
1176
1177 /* return base rate on errors */
1178 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1179 "hw_rix out of bounds: %x\n", hw_rix))
1180 return 0;
1181
1182 rix = sc->rate_idx[sc->curband->band][hw_rix];
1183 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1184 rix = 0;
1185
1186 return rix;
1187 }
1188
1189 /***************\
1190 * Buffers setup *
1191 \***************/
1192
1193 static
1194 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1195 {
1196 struct ath_common *common = ath5k_hw_common(sc->ah);
1197 struct sk_buff *skb;
1198
1199 /*
1200 * Allocate buffer with headroom_needed space for the
1201 * fake physical layer header at the start.
1202 */
1203 skb = ath_rxbuf_alloc(common,
1204 common->rx_bufsize,
1205 GFP_ATOMIC);
1206
1207 if (!skb) {
1208 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1209 common->rx_bufsize);
1210 return NULL;
1211 }
1212
1213 *skb_addr = pci_map_single(sc->pdev,
1214 skb->data, common->rx_bufsize,
1215 PCI_DMA_FROMDEVICE);
1216 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1217 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1218 dev_kfree_skb(skb);
1219 return NULL;
1220 }
1221 return skb;
1222 }
1223
1224 static int
1225 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1226 {
1227 struct ath5k_hw *ah = sc->ah;
1228 struct sk_buff *skb = bf->skb;
1229 struct ath5k_desc *ds;
1230 int ret;
1231
1232 if (!skb) {
1233 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1234 if (!skb)
1235 return -ENOMEM;
1236 bf->skb = skb;
1237 }
1238
1239 /*
1240 * Setup descriptors. For receive we always terminate
1241 * the descriptor list with a self-linked entry so we'll
1242 * not get overrun under high load (as can happen with a
1243 * 5212 when ANI processing enables PHY error frames).
1244 *
1245 * To ensure the last descriptor is self-linked we create
1246 * each descriptor as self-linked and add it to the end. As
1247 * each additional descriptor is added the previous self-linked
1248 * entry is "fixed" naturally. This should be safe even
1249 * if DMA is happening. When processing RX interrupts we
1250 * never remove/process the last, self-linked, entry on the
1251 * descriptor list. This ensures the hardware always has
1252 * someplace to write a new frame.
1253 */
1254 ds = bf->desc;
1255 ds->ds_link = bf->daddr; /* link to self */
1256 ds->ds_data = bf->skbaddr;
1257 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
1258 if (ret) {
1259 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
1260 return ret;
1261 }
1262
1263 if (sc->rxlink != NULL)
1264 *sc->rxlink = bf->daddr;
1265 sc->rxlink = &ds->ds_link;
1266 return 0;
1267 }
1268
1269 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1270 {
1271 struct ieee80211_hdr *hdr;
1272 enum ath5k_pkt_type htype;
1273 __le16 fc;
1274
1275 hdr = (struct ieee80211_hdr *)skb->data;
1276 fc = hdr->frame_control;
1277
1278 if (ieee80211_is_beacon(fc))
1279 htype = AR5K_PKT_TYPE_BEACON;
1280 else if (ieee80211_is_probe_resp(fc))
1281 htype = AR5K_PKT_TYPE_PROBE_RESP;
1282 else if (ieee80211_is_atim(fc))
1283 htype = AR5K_PKT_TYPE_ATIM;
1284 else if (ieee80211_is_pspoll(fc))
1285 htype = AR5K_PKT_TYPE_PSPOLL;
1286 else
1287 htype = AR5K_PKT_TYPE_NORMAL;
1288
1289 return htype;
1290 }
1291
1292 static int
1293 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1294 struct ath5k_txq *txq, int padsize)
1295 {
1296 struct ath5k_hw *ah = sc->ah;
1297 struct ath5k_desc *ds = bf->desc;
1298 struct sk_buff *skb = bf->skb;
1299 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1300 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1301 struct ieee80211_rate *rate;
1302 unsigned int mrr_rate[3], mrr_tries[3];
1303 int i, ret;
1304 u16 hw_rate;
1305 u16 cts_rate = 0;
1306 u16 duration = 0;
1307 u8 rc_flags;
1308
1309 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1310
1311 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1312 PCI_DMA_TODEVICE);
1313
1314 rate = ieee80211_get_tx_rate(sc->hw, info);
1315 if (!rate) {
1316 ret = -EINVAL;
1317 goto err_unmap;
1318 }
1319
1320 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1321 flags |= AR5K_TXDESC_NOACK;
1322
1323 rc_flags = info->control.rates[0].flags;
1324 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1325 rate->hw_value_short : rate->hw_value;
1326
1327 pktlen = skb->len;
1328
1329 if (info->control.hw_key) {
1330 keyidx = info->control.hw_key->hw_key_idx;
1331 pktlen += info->control.hw_key->icv_len;
1332 }
1333 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1334 flags |= AR5K_TXDESC_RTSENA;
1335 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1336 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1337 sc->vif, pktlen, info));
1338 }
1339 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1340 flags |= AR5K_TXDESC_CTSENA;
1341 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1342 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1343 sc->vif, pktlen, info));
1344 }
1345 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1346 ieee80211_get_hdrlen_from_skb(skb), padsize,
1347 get_hw_packet_type(skb),
1348 (sc->power_level * 2),
1349 hw_rate,
1350 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
1351 cts_rate, duration);
1352 if (ret)
1353 goto err_unmap;
1354
1355 memset(mrr_rate, 0, sizeof(mrr_rate));
1356 memset(mrr_tries, 0, sizeof(mrr_tries));
1357 for (i = 0; i < 3; i++) {
1358 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1359 if (!rate)
1360 break;
1361
1362 mrr_rate[i] = rate->hw_value;
1363 mrr_tries[i] = info->control.rates[i + 1].count;
1364 }
1365
1366 ath5k_hw_setup_mrr_tx_desc(ah, ds,
1367 mrr_rate[0], mrr_tries[0],
1368 mrr_rate[1], mrr_tries[1],
1369 mrr_rate[2], mrr_tries[2]);
1370
1371 ds->ds_link = 0;
1372 ds->ds_data = bf->skbaddr;
1373
1374 spin_lock_bh(&txq->lock);
1375 list_add_tail(&bf->list, &txq->q);
1376 if (txq->link == NULL) /* is this first packet? */
1377 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1378 else /* no, so only link it */
1379 *txq->link = bf->daddr;
1380
1381 txq->link = &ds->ds_link;
1382 ath5k_hw_start_tx_dma(ah, txq->qnum);
1383 mmiowb();
1384 spin_unlock_bh(&txq->lock);
1385
1386 return 0;
1387 err_unmap:
1388 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1389 return ret;
1390 }
1391
1392 /*******************\
1393 * Descriptors setup *
1394 \*******************/
1395
1396 static int
1397 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1398 {
1399 struct ath5k_desc *ds;
1400 struct ath5k_buf *bf;
1401 dma_addr_t da;
1402 unsigned int i;
1403 int ret;
1404
1405 /* allocate descriptors */
1406 sc->desc_len = sizeof(struct ath5k_desc) *
1407 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1408 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1409 if (sc->desc == NULL) {
1410 ATH5K_ERR(sc, "can't allocate descriptors\n");
1411 ret = -ENOMEM;
1412 goto err;
1413 }
1414 ds = sc->desc;
1415 da = sc->desc_daddr;
1416 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1417 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1418
1419 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1420 sizeof(struct ath5k_buf), GFP_KERNEL);
1421 if (bf == NULL) {
1422 ATH5K_ERR(sc, "can't allocate bufptr\n");
1423 ret = -ENOMEM;
1424 goto err_free;
1425 }
1426 sc->bufptr = bf;
1427
1428 INIT_LIST_HEAD(&sc->rxbuf);
1429 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1430 bf->desc = ds;
1431 bf->daddr = da;
1432 list_add_tail(&bf->list, &sc->rxbuf);
1433 }
1434
1435 INIT_LIST_HEAD(&sc->txbuf);
1436 sc->txbuf_len = ATH_TXBUF;
1437 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1438 da += sizeof(*ds)) {
1439 bf->desc = ds;
1440 bf->daddr = da;
1441 list_add_tail(&bf->list, &sc->txbuf);
1442 }
1443
1444 /* beacon buffer */
1445 bf->desc = ds;
1446 bf->daddr = da;
1447 sc->bbuf = bf;
1448
1449 return 0;
1450 err_free:
1451 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1452 err:
1453 sc->desc = NULL;
1454 return ret;
1455 }
1456
1457 static void
1458 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1459 {
1460 struct ath5k_buf *bf;
1461
1462 ath5k_txbuf_free_skb(sc, sc->bbuf);
1463 list_for_each_entry(bf, &sc->txbuf, list)
1464 ath5k_txbuf_free_skb(sc, bf);
1465 list_for_each_entry(bf, &sc->rxbuf, list)
1466 ath5k_rxbuf_free_skb(sc, bf);
1467
1468 /* Free memory associated with all descriptors */
1469 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1470 sc->desc = NULL;
1471 sc->desc_daddr = 0;
1472
1473 kfree(sc->bufptr);
1474 sc->bufptr = NULL;
1475 sc->bbuf = NULL;
1476 }
1477
1478
1479
1480
1481
1482 /**************\
1483 * Queues setup *
1484 \**************/
1485
1486 static struct ath5k_txq *
1487 ath5k_txq_setup(struct ath5k_softc *sc,
1488 int qtype, int subtype)
1489 {
1490 struct ath5k_hw *ah = sc->ah;
1491 struct ath5k_txq *txq;
1492 struct ath5k_txq_info qi = {
1493 .tqi_subtype = subtype,
1494 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1495 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1496 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1497 };
1498 int qnum;
1499
1500 /*
1501 * Enable interrupts only for EOL and DESC conditions.
1502 * We mark tx descriptors to receive a DESC interrupt
1503 * when a tx queue gets deep; otherwise waiting for the
1504 * EOL to reap descriptors. Note that this is done to
1505 * reduce interrupt load and this only defers reaping
1506 * descriptors, never transmitting frames. Aside from
1507 * reducing interrupts this also permits more concurrency.
1508 * The only potential downside is if the tx queue backs
1509 * up in which case the top half of the kernel may backup
1510 * due to a lack of tx descriptors.
1511 */
1512 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1513 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1514 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1515 if (qnum < 0) {
1516 /*
1517 * NB: don't print a message, this happens
1518 * normally on parts with too few tx queues
1519 */
1520 return ERR_PTR(qnum);
1521 }
1522 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1523 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1524 qnum, ARRAY_SIZE(sc->txqs));
1525 ath5k_hw_release_tx_queue(ah, qnum);
1526 return ERR_PTR(-EINVAL);
1527 }
1528 txq = &sc->txqs[qnum];
1529 if (!txq->setup) {
1530 txq->qnum = qnum;
1531 txq->link = NULL;
1532 INIT_LIST_HEAD(&txq->q);
1533 spin_lock_init(&txq->lock);
1534 txq->setup = true;
1535 }
1536 return &sc->txqs[qnum];
1537 }
1538
1539 static int
1540 ath5k_beaconq_setup(struct ath5k_hw *ah)
1541 {
1542 struct ath5k_txq_info qi = {
1543 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1544 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1545 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1546 /* NB: for dynamic turbo, don't enable any other interrupts */
1547 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1548 };
1549
1550 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1551 }
1552
1553 static int
1554 ath5k_beaconq_config(struct ath5k_softc *sc)
1555 {
1556 struct ath5k_hw *ah = sc->ah;
1557 struct ath5k_txq_info qi;
1558 int ret;
1559
1560 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1561 if (ret)
1562 goto err;
1563
1564 if (sc->opmode == NL80211_IFTYPE_AP ||
1565 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1566 /*
1567 * Always burst out beacon and CAB traffic
1568 * (aifs = cwmin = cwmax = 0)
1569 */
1570 qi.tqi_aifs = 0;
1571 qi.tqi_cw_min = 0;
1572 qi.tqi_cw_max = 0;
1573 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1574 /*
1575 * Adhoc mode; backoff between 0 and (2 * cw_min).
1576 */
1577 qi.tqi_aifs = 0;
1578 qi.tqi_cw_min = 0;
1579 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1580 }
1581
1582 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1583 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1584 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1585
1586 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1587 if (ret) {
1588 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1589 "hardware queue!\n", __func__);
1590 goto err;
1591 }
1592 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1593 if (ret)
1594 goto err;
1595
1596 /* reconfigure cabq with ready time to 80% of beacon_interval */
1597 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1598 if (ret)
1599 goto err;
1600
1601 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1602 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1603 if (ret)
1604 goto err;
1605
1606 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1607 err:
1608 return ret;
1609 }
1610
1611 static void
1612 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1613 {
1614 struct ath5k_buf *bf, *bf0;
1615
1616 /*
1617 * NB: this assumes output has been stopped and
1618 * we do not need to block ath5k_tx_tasklet
1619 */
1620 spin_lock_bh(&txq->lock);
1621 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1622 ath5k_debug_printtxbuf(sc, bf);
1623
1624 ath5k_txbuf_free_skb(sc, bf);
1625
1626 spin_lock_bh(&sc->txbuflock);
1627 list_move_tail(&bf->list, &sc->txbuf);
1628 sc->txbuf_len++;
1629 spin_unlock_bh(&sc->txbuflock);
1630 }
1631 txq->link = NULL;
1632 spin_unlock_bh(&txq->lock);
1633 }
1634
1635 /*
1636 * Drain the transmit queues and reclaim resources.
1637 */
1638 static void
1639 ath5k_txq_cleanup(struct ath5k_softc *sc)
1640 {
1641 struct ath5k_hw *ah = sc->ah;
1642 unsigned int i;
1643
1644 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1645 /* don't touch the hardware if marked invalid */
1646 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1647 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1648 ath5k_hw_get_txdp(ah, sc->bhalq));
1649 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1650 if (sc->txqs[i].setup) {
1651 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1652 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1653 "link %p\n",
1654 sc->txqs[i].qnum,
1655 ath5k_hw_get_txdp(ah,
1656 sc->txqs[i].qnum),
1657 sc->txqs[i].link);
1658 }
1659 }
1660
1661 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1662 if (sc->txqs[i].setup)
1663 ath5k_txq_drainq(sc, &sc->txqs[i]);
1664 }
1665
1666 static void
1667 ath5k_txq_release(struct ath5k_softc *sc)
1668 {
1669 struct ath5k_txq *txq = sc->txqs;
1670 unsigned int i;
1671
1672 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1673 if (txq->setup) {
1674 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1675 txq->setup = false;
1676 }
1677 }
1678
1679
1680
1681
1682 /*************\
1683 * RX Handling *
1684 \*************/
1685
1686 /*
1687 * Enable the receive h/w following a reset.
1688 */
1689 static int
1690 ath5k_rx_start(struct ath5k_softc *sc)
1691 {
1692 struct ath5k_hw *ah = sc->ah;
1693 struct ath_common *common = ath5k_hw_common(ah);
1694 struct ath5k_buf *bf;
1695 int ret;
1696
1697 common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
1698
1699 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1700 common->cachelsz, common->rx_bufsize);
1701
1702 spin_lock_bh(&sc->rxbuflock);
1703 sc->rxlink = NULL;
1704 list_for_each_entry(bf, &sc->rxbuf, list) {
1705 ret = ath5k_rxbuf_setup(sc, bf);
1706 if (ret != 0) {
1707 spin_unlock_bh(&sc->rxbuflock);
1708 goto err;
1709 }
1710 }
1711 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1712 ath5k_hw_set_rxdp(ah, bf->daddr);
1713 spin_unlock_bh(&sc->rxbuflock);
1714
1715 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1716 ath5k_mode_setup(sc); /* set filters, etc. */
1717 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1718
1719 return 0;
1720 err:
1721 return ret;
1722 }
1723
1724 /*
1725 * Disable the receive h/w in preparation for a reset.
1726 */
1727 static void
1728 ath5k_rx_stop(struct ath5k_softc *sc)
1729 {
1730 struct ath5k_hw *ah = sc->ah;
1731
1732 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1733 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1734 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1735
1736 ath5k_debug_printrxbuffs(sc, ah);
1737 }
1738
1739 static unsigned int
1740 ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1741 struct ath5k_rx_status *rs)
1742 {
1743 struct ath5k_hw *ah = sc->ah;
1744 struct ath_common *common = ath5k_hw_common(ah);
1745 struct ieee80211_hdr *hdr = (void *)skb->data;
1746 unsigned int keyix, hlen;
1747
1748 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1749 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1750 return RX_FLAG_DECRYPTED;
1751
1752 /* Apparently when a default key is used to decrypt the packet
1753 the hw does not set the index used to decrypt. In such cases
1754 get the index from the packet. */
1755 hlen = ieee80211_hdrlen(hdr->frame_control);
1756 if (ieee80211_has_protected(hdr->frame_control) &&
1757 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1758 skb->len >= hlen + 4) {
1759 keyix = skb->data[hlen + 3] >> 6;
1760
1761 if (test_bit(keyix, common->keymap))
1762 return RX_FLAG_DECRYPTED;
1763 }
1764
1765 return 0;
1766 }
1767
1768
1769 static void
1770 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1771 struct ieee80211_rx_status *rxs)
1772 {
1773 struct ath_common *common = ath5k_hw_common(sc->ah);
1774 u64 tsf, bc_tstamp;
1775 u32 hw_tu;
1776 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1777
1778 if (ieee80211_is_beacon(mgmt->frame_control) &&
1779 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1780 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1781 tsf = ath5k_hw_get_tsf64(sc->ah);
1782 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1783 hw_tu = TSF_TO_TU(tsf);
1784
1785 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1786 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1787 (unsigned long long)bc_tstamp,
1788 (unsigned long long)rxs->mactime,
1789 (unsigned long long)(rxs->mactime - bc_tstamp),
1790 (unsigned long long)tsf);
1791
1792 /*
1793 * Sometimes the HW will give us a wrong tstamp in the rx
1794 * status, causing the timestamp extension to go wrong.
1795 * (This seems to happen especially with beacon frames bigger
1796 * than 78 byte (incl. FCS))
1797 * But we know that the receive timestamp must be later than the
1798 * timestamp of the beacon since HW must have synced to that.
1799 *
1800 * NOTE: here we assume mactime to be after the frame was
1801 * received, not like mac80211 which defines it at the start.
1802 */
1803 if (bc_tstamp > rxs->mactime) {
1804 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1805 "fixing mactime from %llx to %llx\n",
1806 (unsigned long long)rxs->mactime,
1807 (unsigned long long)tsf);
1808 rxs->mactime = tsf;
1809 }
1810
1811 /*
1812 * Local TSF might have moved higher than our beacon timers,
1813 * in that case we have to update them to continue sending
1814 * beacons. This also takes care of synchronizing beacon sending
1815 * times with other stations.
1816 */
1817 if (hw_tu >= sc->nexttbtt)
1818 ath5k_beacon_update_timers(sc, bc_tstamp);
1819 }
1820 }
1821
1822 static void
1823 ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1824 {
1825 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1826 struct ath5k_hw *ah = sc->ah;
1827 struct ath_common *common = ath5k_hw_common(ah);
1828
1829 /* only beacons from our BSSID */
1830 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1831 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1832 return;
1833
1834 ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
1835 rssi);
1836
1837 /* in IBSS mode we should keep RSSI statistics per neighbour */
1838 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1839 }
1840
1841 /*
1842 * Compute padding position. skb must contains an IEEE 802.11 frame
1843 */
1844 static int ath5k_common_padpos(struct sk_buff *skb)
1845 {
1846 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1847 __le16 frame_control = hdr->frame_control;
1848 int padpos = 24;
1849
1850 if (ieee80211_has_a4(frame_control)) {
1851 padpos += ETH_ALEN;
1852 }
1853 if (ieee80211_is_data_qos(frame_control)) {
1854 padpos += IEEE80211_QOS_CTL_LEN;
1855 }
1856
1857 return padpos;
1858 }
1859
1860 /*
1861 * This function expects a 802.11 frame and returns the number of
1862 * bytes added, or -1 if we don't have enought header room.
1863 */
1864
1865 static int ath5k_add_padding(struct sk_buff *skb)
1866 {
1867 int padpos = ath5k_common_padpos(skb);
1868 int padsize = padpos & 3;
1869
1870 if (padsize && skb->len>padpos) {
1871
1872 if (skb_headroom(skb) < padsize)
1873 return -1;
1874
1875 skb_push(skb, padsize);
1876 memmove(skb->data, skb->data+padsize, padpos);
1877 return padsize;
1878 }
1879
1880 return 0;
1881 }
1882
1883 /*
1884 * This function expects a 802.11 frame and returns the number of
1885 * bytes removed
1886 */
1887
1888 static int ath5k_remove_padding(struct sk_buff *skb)
1889 {
1890 int padpos = ath5k_common_padpos(skb);
1891 int padsize = padpos & 3;
1892
1893 if (padsize && skb->len>=padpos+padsize) {
1894 memmove(skb->data + padsize, skb->data, padpos);
1895 skb_pull(skb, padsize);
1896 return padsize;
1897 }
1898
1899 return 0;
1900 }
1901
1902 static void
1903 ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1904 struct ath5k_rx_status *rs)
1905 {
1906 struct ieee80211_rx_status *rxs;
1907
1908 /* The MAC header is padded to have 32-bit boundary if the
1909 * packet payload is non-zero. The general calculation for
1910 * padsize would take into account odd header lengths:
1911 * padsize = (4 - hdrlen % 4) % 4; However, since only
1912 * even-length headers are used, padding can only be 0 or 2
1913 * bytes and we can optimize this a bit. In addition, we must
1914 * not try to remove padding from short control frames that do
1915 * not have payload. */
1916 ath5k_remove_padding(skb);
1917
1918 rxs = IEEE80211_SKB_RXCB(skb);
1919
1920 rxs->flag = 0;
1921 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1922 rxs->flag |= RX_FLAG_MMIC_ERROR;
1923
1924 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1925 rxs->flag |= RX_FLAG_TSFT;
1926
1927 rxs->freq = sc->curchan->center_freq;
1928 rxs->band = sc->curband->band;
1929
1930 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
1931
1932 rxs->antenna = rs->rs_antenna;
1933
1934 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1935 sc->stats.antenna_rx[rs->rs_antenna]++;
1936 else
1937 sc->stats.antenna_rx[0]++; /* invalid */
1938
1939 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1940 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
1941
1942 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1943 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1944 rxs->flag |= RX_FLAG_SHORTPRE;
1945
1946 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1947
1948 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
1949
1950 /* check beacons in IBSS mode */
1951 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1952 ath5k_check_ibss_tsf(sc, skb, rxs);
1953
1954 ieee80211_rx(sc->hw, skb);
1955 }
1956
1957 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1958 *
1959 * Check if we want to further process this frame or not. Also update
1960 * statistics. Return true if we want this frame, false if not.
1961 */
1962 static bool
1963 ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
1964 {
1965 sc->stats.rx_all_count++;
1966
1967 if (unlikely(rs->rs_status)) {
1968 if (rs->rs_status & AR5K_RXERR_CRC)
1969 sc->stats.rxerr_crc++;
1970 if (rs->rs_status & AR5K_RXERR_FIFO)
1971 sc->stats.rxerr_fifo++;
1972 if (rs->rs_status & AR5K_RXERR_PHY) {
1973 sc->stats.rxerr_phy++;
1974 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1975 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1976 return false;
1977 }
1978 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1979 sc->stats.rxerr_decrypt++;
1980 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1981 !(rs->rs_status & AR5K_RXERR_CRC))
1982 return true;
1983 }
1984 if (rs->rs_status & AR5K_RXERR_MIC) {
1985 sc->stats.rxerr_mic++;
1986 return true;
1987 }
1988
1989 /* let crypto-error packets fall through in MNTR */
1990 if ((rs->rs_status & ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1991 sc->opmode != NL80211_IFTYPE_MONITOR)
1992 return false;
1993 }
1994
1995 if (unlikely(rs->rs_more)) {
1996 sc->stats.rxerr_jumbo++;
1997 return false;
1998 }
1999 return true;
2000 }
2001
2002 static void
2003 ath5k_tasklet_rx(unsigned long data)
2004 {
2005 struct ath5k_rx_status rs = {};
2006 struct sk_buff *skb, *next_skb;
2007 dma_addr_t next_skb_addr;
2008 struct ath5k_softc *sc = (void *)data;
2009 struct ath5k_hw *ah = sc->ah;
2010 struct ath_common *common = ath5k_hw_common(ah);
2011 struct ath5k_buf *bf;
2012 struct ath5k_desc *ds;
2013 int ret;
2014
2015 spin_lock(&sc->rxbuflock);
2016 if (list_empty(&sc->rxbuf)) {
2017 ATH5K_WARN(sc, "empty rx buf pool\n");
2018 goto unlock;
2019 }
2020 do {
2021 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
2022 BUG_ON(bf->skb == NULL);
2023 skb = bf->skb;
2024 ds = bf->desc;
2025
2026 /* bail if HW is still using self-linked descriptor */
2027 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
2028 break;
2029
2030 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
2031 if (unlikely(ret == -EINPROGRESS))
2032 break;
2033 else if (unlikely(ret)) {
2034 ATH5K_ERR(sc, "error in processing rx descriptor\n");
2035 sc->stats.rxerr_proc++;
2036 break;
2037 }
2038
2039 if (ath5k_receive_frame_ok(sc, &rs)) {
2040 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
2041
2042 /*
2043 * If we can't replace bf->skb with a new skb under
2044 * memory pressure, just skip this packet
2045 */
2046 if (!next_skb)
2047 goto next;
2048
2049 pci_unmap_single(sc->pdev, bf->skbaddr,
2050 common->rx_bufsize,
2051 PCI_DMA_FROMDEVICE);
2052
2053 skb_put(skb, rs.rs_datalen);
2054
2055 ath5k_receive_frame(sc, skb, &rs);
2056
2057 bf->skb = next_skb;
2058 bf->skbaddr = next_skb_addr;
2059 }
2060 next:
2061 list_move_tail(&bf->list, &sc->rxbuf);
2062 } while (ath5k_rxbuf_setup(sc, bf) == 0);
2063 unlock:
2064 spin_unlock(&sc->rxbuflock);
2065 }
2066
2067
2068 /*************\
2069 * TX Handling *
2070 \*************/
2071
2072 static void
2073 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
2074 {
2075 struct ath5k_tx_status ts = {};
2076 struct ath5k_buf *bf, *bf0;
2077 struct ath5k_desc *ds;
2078 struct sk_buff *skb;
2079 struct ieee80211_tx_info *info;
2080 int i, ret;
2081
2082 spin_lock(&txq->lock);
2083 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
2084 ds = bf->desc;
2085
2086 /*
2087 * It's possible that the hardware can say the buffer is
2088 * completed when it hasn't yet loaded the ds_link from
2089 * host memory and moved on. If there are more TX
2090 * descriptors in the queue, wait for TXDP to change
2091 * before processing this one.
2092 */
2093 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) == bf->daddr &&
2094 !list_is_last(&bf->list, &txq->q))
2095 break;
2096
2097 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
2098 if (unlikely(ret == -EINPROGRESS))
2099 break;
2100 else if (unlikely(ret)) {
2101 ATH5K_ERR(sc, "error %d while processing queue %u\n",
2102 ret, txq->qnum);
2103 break;
2104 }
2105
2106 sc->stats.tx_all_count++;
2107 skb = bf->skb;
2108 info = IEEE80211_SKB_CB(skb);
2109 bf->skb = NULL;
2110
2111 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
2112 PCI_DMA_TODEVICE);
2113
2114 ieee80211_tx_info_clear_status(info);
2115 for (i = 0; i < 4; i++) {
2116 struct ieee80211_tx_rate *r =
2117 &info->status.rates[i];
2118
2119 if (ts.ts_rate[i]) {
2120 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
2121 r->count = ts.ts_retry[i];
2122 } else {
2123 r->idx = -1;
2124 r->count = 0;
2125 }
2126 }
2127
2128 /* count the successful attempt as well */
2129 info->status.rates[ts.ts_final_idx].count++;
2130
2131 if (unlikely(ts.ts_status)) {
2132 sc->stats.ack_fail++;
2133 if (ts.ts_status & AR5K_TXERR_FILT) {
2134 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2135 sc->stats.txerr_filt++;
2136 }
2137 if (ts.ts_status & AR5K_TXERR_XRETRY)
2138 sc->stats.txerr_retry++;
2139 if (ts.ts_status & AR5K_TXERR_FIFO)
2140 sc->stats.txerr_fifo++;
2141 } else {
2142 info->flags |= IEEE80211_TX_STAT_ACK;
2143 info->status.ack_signal = ts.ts_rssi;
2144 }
2145
2146 /*
2147 * Remove MAC header padding before giving the frame
2148 * back to mac80211.
2149 */
2150 ath5k_remove_padding(skb);
2151
2152 if (ts.ts_antenna > 0 && ts.ts_antenna < 5)
2153 sc->stats.antenna_tx[ts.ts_antenna]++;
2154 else
2155 sc->stats.antenna_tx[0]++; /* invalid */
2156
2157 ieee80211_tx_status(sc->hw, skb);
2158
2159 spin_lock(&sc->txbuflock);
2160 list_move_tail(&bf->list, &sc->txbuf);
2161 sc->txbuf_len++;
2162 spin_unlock(&sc->txbuflock);
2163 }
2164 if (likely(list_empty(&txq->q)))
2165 txq->link = NULL;
2166 spin_unlock(&txq->lock);
2167 if (sc->txbuf_len > ATH_TXBUF / 5)
2168 ieee80211_wake_queues(sc->hw);
2169 }
2170
2171 static void
2172 ath5k_tasklet_tx(unsigned long data)
2173 {
2174 int i;
2175 struct ath5k_softc *sc = (void *)data;
2176
2177 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2178 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2179 ath5k_tx_processq(sc, &sc->txqs[i]);
2180 }
2181
2182
2183 /*****************\
2184 * Beacon handling *
2185 \*****************/
2186
2187 /*
2188 * Setup the beacon frame for transmit.
2189 */
2190 static int
2191 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2192 {
2193 struct sk_buff *skb = bf->skb;
2194 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2195 struct ath5k_hw *ah = sc->ah;
2196 struct ath5k_desc *ds;
2197 int ret = 0;
2198 u8 antenna;
2199 u32 flags;
2200 const int padsize = 0;
2201
2202 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2203 PCI_DMA_TODEVICE);
2204 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2205 "skbaddr %llx\n", skb, skb->data, skb->len,
2206 (unsigned long long)bf->skbaddr);
2207 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2208 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2209 return -EIO;
2210 }
2211
2212 ds = bf->desc;
2213 antenna = ah->ah_tx_ant;
2214
2215 flags = AR5K_TXDESC_NOACK;
2216 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2217 ds->ds_link = bf->daddr; /* self-linked */
2218 flags |= AR5K_TXDESC_VEOL;
2219 } else
2220 ds->ds_link = 0;
2221
2222 /*
2223 * If we use multiple antennas on AP and use
2224 * the Sectored AP scenario, switch antenna every
2225 * 4 beacons to make sure everybody hears our AP.
2226 * When a client tries to associate, hw will keep
2227 * track of the tx antenna to be used for this client
2228 * automaticaly, based on ACKed packets.
2229 *
2230 * Note: AP still listens and transmits RTS on the
2231 * default antenna which is supposed to be an omni.
2232 *
2233 * Note2: On sectored scenarios it's possible to have
2234 * multiple antennas (1omni -the default- and 14 sectors)
2235 * so if we choose to actually support this mode we need
2236 * to allow user to set how many antennas we have and tweak
2237 * the code below to send beacons on all of them.
2238 */
2239 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2240 antenna = sc->bsent & 4 ? 2 : 1;
2241
2242
2243 ds->ds_data = bf->skbaddr;
2244 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2245 ieee80211_get_hdrlen_from_skb(skb), padsize,
2246 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2247 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2248 1, AR5K_TXKEYIX_INVALID,
2249 antenna, flags, 0, 0);
2250 if (ret)
2251 goto err_unmap;
2252
2253 return 0;
2254 err_unmap:
2255 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2256 return ret;
2257 }
2258
2259 /*
2260 * Transmit a beacon frame at SWBA. Dynamic updates to the
2261 * frame contents are done as needed and the slot time is
2262 * also adjusted based on current state.
2263 *
2264 * This is called from software irq context (beacontq tasklets)
2265 * or user context from ath5k_beacon_config.
2266 */
2267 static void
2268 ath5k_beacon_send(struct ath5k_softc *sc)
2269 {
2270 struct ath5k_buf *bf = sc->bbuf;
2271 struct ath5k_hw *ah = sc->ah;
2272 struct sk_buff *skb;
2273
2274 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2275
2276 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2277 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2278 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2279 return;
2280 }
2281 /*
2282 * Check if the previous beacon has gone out. If
2283 * not don't don't try to post another, skip this
2284 * period and wait for the next. Missed beacons
2285 * indicate a problem and should not occur. If we
2286 * miss too many consecutive beacons reset the device.
2287 */
2288 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2289 sc->bmisscount++;
2290 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2291 "missed %u consecutive beacons\n", sc->bmisscount);
2292 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
2293 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2294 "stuck beacon time (%u missed)\n",
2295 sc->bmisscount);
2296 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2297 "stuck beacon, resetting\n");
2298 ieee80211_queue_work(sc->hw, &sc->reset_work);
2299 }
2300 return;
2301 }
2302 if (unlikely(sc->bmisscount != 0)) {
2303 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2304 "resume beacon xmit after %u misses\n",
2305 sc->bmisscount);
2306 sc->bmisscount = 0;
2307 }
2308
2309 /*
2310 * Stop any current dma and put the new frame on the queue.
2311 * This should never fail since we check above that no frames
2312 * are still pending on the queue.
2313 */
2314 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2315 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
2316 /* NB: hw still stops DMA, so proceed */
2317 }
2318
2319 /* refresh the beacon for AP mode */
2320 if (sc->opmode == NL80211_IFTYPE_AP)
2321 ath5k_beacon_update(sc->hw, sc->vif);
2322
2323 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2324 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2325 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2326 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2327
2328 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2329 while (skb) {
2330 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2331 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2332 }
2333
2334 sc->bsent++;
2335 }
2336
2337
2338 /**
2339 * ath5k_beacon_update_timers - update beacon timers
2340 *
2341 * @sc: struct ath5k_softc pointer we are operating on
2342 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2343 * beacon timer update based on the current HW TSF.
2344 *
2345 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2346 * of a received beacon or the current local hardware TSF and write it to the
2347 * beacon timer registers.
2348 *
2349 * This is called in a variety of situations, e.g. when a beacon is received,
2350 * when a TSF update has been detected, but also when an new IBSS is created or
2351 * when we otherwise know we have to update the timers, but we keep it in this
2352 * function to have it all together in one place.
2353 */
2354 static void
2355 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2356 {
2357 struct ath5k_hw *ah = sc->ah;
2358 u32 nexttbtt, intval, hw_tu, bc_tu;
2359 u64 hw_tsf;
2360
2361 intval = sc->bintval & AR5K_BEACON_PERIOD;
2362 if (WARN_ON(!intval))
2363 return;
2364
2365 /* beacon TSF converted to TU */
2366 bc_tu = TSF_TO_TU(bc_tsf);
2367
2368 /* current TSF converted to TU */
2369 hw_tsf = ath5k_hw_get_tsf64(ah);
2370 hw_tu = TSF_TO_TU(hw_tsf);
2371
2372 #define FUDGE 3
2373 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2374 if (bc_tsf == -1) {
2375 /*
2376 * no beacons received, called internally.
2377 * just need to refresh timers based on HW TSF.
2378 */
2379 nexttbtt = roundup(hw_tu + FUDGE, intval);
2380 } else if (bc_tsf == 0) {
2381 /*
2382 * no beacon received, probably called by ath5k_reset_tsf().
2383 * reset TSF to start with 0.
2384 */
2385 nexttbtt = intval;
2386 intval |= AR5K_BEACON_RESET_TSF;
2387 } else if (bc_tsf > hw_tsf) {
2388 /*
2389 * beacon received, SW merge happend but HW TSF not yet updated.
2390 * not possible to reconfigure timers yet, but next time we
2391 * receive a beacon with the same BSSID, the hardware will
2392 * automatically update the TSF and then we need to reconfigure
2393 * the timers.
2394 */
2395 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2396 "need to wait for HW TSF sync\n");
2397 return;
2398 } else {
2399 /*
2400 * most important case for beacon synchronization between STA.
2401 *
2402 * beacon received and HW TSF has been already updated by HW.
2403 * update next TBTT based on the TSF of the beacon, but make
2404 * sure it is ahead of our local TSF timer.
2405 */
2406 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2407 }
2408 #undef FUDGE
2409
2410 sc->nexttbtt = nexttbtt;
2411
2412 intval |= AR5K_BEACON_ENA;
2413 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2414
2415 /*
2416 * debugging output last in order to preserve the time critical aspect
2417 * of this function
2418 */
2419 if (bc_tsf == -1)
2420 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2421 "reconfigured timers based on HW TSF\n");
2422 else if (bc_tsf == 0)
2423 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2424 "reset HW TSF and timers\n");
2425 else
2426 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2427 "updated timers based on beacon TSF\n");
2428
2429 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2430 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2431 (unsigned long long) bc_tsf,
2432 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2433 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2434 intval & AR5K_BEACON_PERIOD,
2435 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2436 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2437 }
2438
2439
2440 /**
2441 * ath5k_beacon_config - Configure the beacon queues and interrupts
2442 *
2443 * @sc: struct ath5k_softc pointer we are operating on
2444 *
2445 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2446 * interrupts to detect TSF updates only.
2447 */
2448 static void
2449 ath5k_beacon_config(struct ath5k_softc *sc)
2450 {
2451 struct ath5k_hw *ah = sc->ah;
2452 unsigned long flags;
2453
2454 spin_lock_irqsave(&sc->block, flags);
2455 sc->bmisscount = 0;
2456 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2457
2458 if (sc->enable_beacon) {
2459 /*
2460 * In IBSS mode we use a self-linked tx descriptor and let the
2461 * hardware send the beacons automatically. We have to load it
2462 * only once here.
2463 * We use the SWBA interrupt only to keep track of the beacon
2464 * timers in order to detect automatic TSF updates.
2465 */
2466 ath5k_beaconq_config(sc);
2467
2468 sc->imask |= AR5K_INT_SWBA;
2469
2470 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2471 if (ath5k_hw_hasveol(ah))
2472 ath5k_beacon_send(sc);
2473 } else
2474 ath5k_beacon_update_timers(sc, -1);
2475 } else {
2476 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2477 }
2478
2479 ath5k_hw_set_imr(ah, sc->imask);
2480 mmiowb();
2481 spin_unlock_irqrestore(&sc->block, flags);
2482 }
2483
2484 static void ath5k_tasklet_beacon(unsigned long data)
2485 {
2486 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2487
2488 /*
2489 * Software beacon alert--time to send a beacon.
2490 *
2491 * In IBSS mode we use this interrupt just to
2492 * keep track of the next TBTT (target beacon
2493 * transmission time) in order to detect wether
2494 * automatic TSF updates happened.
2495 */
2496 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2497 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2498 sc->nexttbtt += sc->bintval;
2499 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2500 "SWBA nexttbtt: %x hw_tu: %x "
2501 "TSF: %llx\n",
2502 sc->nexttbtt,
2503 TSF_TO_TU(tsf),
2504 (unsigned long long) tsf);
2505 } else {
2506 spin_lock(&sc->block);
2507 ath5k_beacon_send(sc);
2508 spin_unlock(&sc->block);
2509 }
2510 }
2511
2512
2513 /********************\
2514 * Interrupt handling *
2515 \********************/
2516
2517 static int
2518 ath5k_init(struct ath5k_softc *sc)
2519 {
2520 struct ath5k_hw *ah = sc->ah;
2521 int ret, i;
2522
2523 mutex_lock(&sc->lock);
2524
2525 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2526
2527 /*
2528 * Stop anything previously setup. This is safe
2529 * no matter this is the first time through or not.
2530 */
2531 ath5k_stop_locked(sc);
2532
2533 /*
2534 * The basic interface to setting the hardware in a good
2535 * state is ``reset''. On return the hardware is known to
2536 * be powered up and with interrupts disabled. This must
2537 * be followed by initialization of the appropriate bits
2538 * and then setup of the interrupt mask.
2539 */
2540 sc->curchan = sc->hw->conf.channel;
2541 sc->curband = &sc->sbands[sc->curchan->band];
2542 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2543 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2544 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2545
2546 ret = ath5k_reset(sc, NULL);
2547 if (ret)
2548 goto done;
2549
2550 ath5k_rfkill_hw_start(ah);
2551
2552 /*
2553 * Reset the key cache since some parts do not reset the
2554 * contents on initial power up or resume from suspend.
2555 */
2556 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2557 ath5k_hw_reset_key(ah, i);
2558
2559 ath5k_hw_set_ack_bitrate_high(ah, true);
2560 ret = 0;
2561 done:
2562 mmiowb();
2563 mutex_unlock(&sc->lock);
2564 return ret;
2565 }
2566
2567 static int
2568 ath5k_stop_locked(struct ath5k_softc *sc)
2569 {
2570 struct ath5k_hw *ah = sc->ah;
2571
2572 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2573 test_bit(ATH_STAT_INVALID, sc->status));
2574
2575 /*
2576 * Shutdown the hardware and driver:
2577 * stop output from above
2578 * disable interrupts
2579 * turn off timers
2580 * turn off the radio
2581 * clear transmit machinery
2582 * clear receive machinery
2583 * drain and release tx queues
2584 * reclaim beacon resources
2585 * power down hardware
2586 *
2587 * Note that some of this work is not possible if the
2588 * hardware is gone (invalid).
2589 */
2590 ieee80211_stop_queues(sc->hw);
2591
2592 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2593 ath5k_led_off(sc);
2594 ath5k_hw_set_imr(ah, 0);
2595 synchronize_irq(sc->pdev->irq);
2596 }
2597 ath5k_txq_cleanup(sc);
2598 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2599 ath5k_rx_stop(sc);
2600 ath5k_hw_phy_disable(ah);
2601 }
2602
2603 return 0;
2604 }
2605
2606 static void stop_tasklets(struct ath5k_softc *sc)
2607 {
2608 tasklet_kill(&sc->rxtq);
2609 tasklet_kill(&sc->txtq);
2610 tasklet_kill(&sc->calib);
2611 tasklet_kill(&sc->beacontq);
2612 tasklet_kill(&sc->ani_tasklet);
2613 }
2614
2615 /*
2616 * Stop the device, grabbing the top-level lock to protect
2617 * against concurrent entry through ath5k_init (which can happen
2618 * if another thread does a system call and the thread doing the
2619 * stop is preempted).
2620 */
2621 static int
2622 ath5k_stop_hw(struct ath5k_softc *sc)
2623 {
2624 int ret;
2625
2626 mutex_lock(&sc->lock);
2627 ret = ath5k_stop_locked(sc);
2628 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2629 /*
2630 * Don't set the card in full sleep mode!
2631 *
2632 * a) When the device is in this state it must be carefully
2633 * woken up or references to registers in the PCI clock
2634 * domain may freeze the bus (and system). This varies
2635 * by chip and is mostly an issue with newer parts
2636 * (madwifi sources mentioned srev >= 0x78) that go to
2637 * sleep more quickly.
2638 *
2639 * b) On older chips full sleep results a weird behaviour
2640 * during wakeup. I tested various cards with srev < 0x78
2641 * and they don't wake up after module reload, a second
2642 * module reload is needed to bring the card up again.
2643 *
2644 * Until we figure out what's going on don't enable
2645 * full chip reset on any chip (this is what Legacy HAL
2646 * and Sam's HAL do anyway). Instead Perform a full reset
2647 * on the device (same as initial state after attach) and
2648 * leave it idle (keep MAC/BB on warm reset) */
2649 ret = ath5k_hw_on_hold(sc->ah);
2650
2651 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2652 "putting device to sleep\n");
2653 }
2654 ath5k_txbuf_free_skb(sc, sc->bbuf);
2655
2656 mmiowb();
2657 mutex_unlock(&sc->lock);
2658
2659 stop_tasklets(sc);
2660
2661 ath5k_rfkill_hw_stop(sc->ah);
2662
2663 return ret;
2664 }
2665
2666 static void
2667 ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2668 {
2669 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2670 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2671 /* run ANI only when full calibration is not active */
2672 ah->ah_cal_next_ani = jiffies +
2673 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2674 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2675
2676 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2677 ah->ah_cal_next_full = jiffies +
2678 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2679 tasklet_schedule(&ah->ah_sc->calib);
2680 }
2681 /* we could use SWI to generate enough interrupts to meet our
2682 * calibration interval requirements, if necessary:
2683 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2684 }
2685
2686 static irqreturn_t
2687 ath5k_intr(int irq, void *dev_id)
2688 {
2689 struct ath5k_softc *sc = dev_id;
2690 struct ath5k_hw *ah = sc->ah;
2691 enum ath5k_int status;
2692 unsigned int counter = 1000;
2693
2694 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2695 !ath5k_hw_is_intr_pending(ah)))
2696 return IRQ_NONE;
2697
2698 do {
2699 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2700 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2701 status, sc->imask);
2702 if (unlikely(status & AR5K_INT_FATAL)) {
2703 /*
2704 * Fatal errors are unrecoverable.
2705 * Typically these are caused by DMA errors.
2706 */
2707 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2708 "fatal int, resetting\n");
2709 ieee80211_queue_work(sc->hw, &sc->reset_work);
2710 } else if (unlikely(status & AR5K_INT_RXORN)) {
2711 /*
2712 * Receive buffers are full. Either the bus is busy or
2713 * the CPU is not fast enough to process all received
2714 * frames.
2715 * Older chipsets need a reset to come out of this
2716 * condition, but we treat it as RX for newer chips.
2717 * We don't know exactly which versions need a reset -
2718 * this guess is copied from the HAL.
2719 */
2720 sc->stats.rxorn_intr++;
2721 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2722 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2723 "rx overrun, resetting\n");
2724 ieee80211_queue_work(sc->hw, &sc->reset_work);
2725 }
2726 else
2727 tasklet_schedule(&sc->rxtq);
2728 } else {
2729 if (status & AR5K_INT_SWBA) {
2730 tasklet_hi_schedule(&sc->beacontq);
2731 }
2732 if (status & AR5K_INT_RXEOL) {
2733 /*
2734 * NB: the hardware should re-read the link when
2735 * RXE bit is written, but it doesn't work at
2736 * least on older hardware revs.
2737 */
2738 sc->stats.rxeol_intr++;
2739 }
2740 if (status & AR5K_INT_TXURN) {
2741 /* bump tx trigger level */
2742 ath5k_hw_update_tx_triglevel(ah, true);
2743 }
2744 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2745 tasklet_schedule(&sc->rxtq);
2746 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2747 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2748 tasklet_schedule(&sc->txtq);
2749 if (status & AR5K_INT_BMISS) {
2750 /* TODO */
2751 }
2752 if (status & AR5K_INT_MIB) {
2753 sc->stats.mib_intr++;
2754 ath5k_hw_update_mib_counters(ah);
2755 ath5k_ani_mib_intr(ah);
2756 }
2757 if (status & AR5K_INT_GPIO)
2758 tasklet_schedule(&sc->rf_kill.toggleq);
2759
2760 }
2761 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2762
2763 if (unlikely(!counter))
2764 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2765
2766 ath5k_intr_calibration_poll(ah);
2767
2768 return IRQ_HANDLED;
2769 }
2770
2771 /*
2772 * Periodically recalibrate the PHY to account
2773 * for temperature/environment changes.
2774 */
2775 static void
2776 ath5k_tasklet_calibrate(unsigned long data)
2777 {
2778 struct ath5k_softc *sc = (void *)data;
2779 struct ath5k_hw *ah = sc->ah;
2780
2781 /* Only full calibration for now */
2782 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2783
2784 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2785 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2786 sc->curchan->hw_value);
2787
2788 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2789 /*
2790 * Rfgain is out of bounds, reset the chip
2791 * to load new gain values.
2792 */
2793 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2794 ieee80211_queue_work(sc->hw, &sc->reset_work);
2795 }
2796 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2797 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2798 ieee80211_frequency_to_channel(
2799 sc->curchan->center_freq));
2800
2801 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
2802 * doesn't. We stop the queues so that calibration doesn't interfere
2803 * with TX and don't run it as often */
2804 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2805 ah->ah_cal_next_nf = jiffies +
2806 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
2807 ieee80211_stop_queues(sc->hw);
2808 ath5k_hw_update_noise_floor(ah);
2809 ieee80211_wake_queues(sc->hw);
2810 }
2811
2812 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2813 }
2814
2815
2816 static void
2817 ath5k_tasklet_ani(unsigned long data)
2818 {
2819 struct ath5k_softc *sc = (void *)data;
2820 struct ath5k_hw *ah = sc->ah;
2821
2822 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2823 ath5k_ani_calibration(ah);
2824 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2825 }
2826
2827
2828 /********************\
2829 * Mac80211 functions *
2830 \********************/
2831
2832 static int
2833 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2834 {
2835 struct ath5k_softc *sc = hw->priv;
2836
2837 return ath5k_tx_queue(hw, skb, sc->txq);
2838 }
2839
2840 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2841 struct ath5k_txq *txq)
2842 {
2843 struct ath5k_softc *sc = hw->priv;
2844 struct ath5k_buf *bf;
2845 unsigned long flags;
2846 int padsize;
2847
2848 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2849
2850 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2851 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2852
2853 /*
2854 * the hardware expects the header padded to 4 byte boundaries
2855 * if this is not the case we add the padding after the header
2856 */
2857 padsize = ath5k_add_padding(skb);
2858 if (padsize < 0) {
2859 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
2860 " headroom to pad");
2861 goto drop_packet;
2862 }
2863
2864 spin_lock_irqsave(&sc->txbuflock, flags);
2865 if (list_empty(&sc->txbuf)) {
2866 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2867 spin_unlock_irqrestore(&sc->txbuflock, flags);
2868 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2869 goto drop_packet;
2870 }
2871 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2872 list_del(&bf->list);
2873 sc->txbuf_len--;
2874 if (list_empty(&sc->txbuf))
2875 ieee80211_stop_queues(hw);
2876 spin_unlock_irqrestore(&sc->txbuflock, flags);
2877
2878 bf->skb = skb;
2879
2880 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
2881 bf->skb = NULL;
2882 spin_lock_irqsave(&sc->txbuflock, flags);
2883 list_add_tail(&bf->list, &sc->txbuf);
2884 sc->txbuf_len++;
2885 spin_unlock_irqrestore(&sc->txbuflock, flags);
2886 goto drop_packet;
2887 }
2888 return NETDEV_TX_OK;
2889
2890 drop_packet:
2891 dev_kfree_skb_any(skb);
2892 return NETDEV_TX_OK;
2893 }
2894
2895 /*
2896 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2897 * and change to the given channel.
2898 *
2899 * This should be called with sc->lock.
2900 */
2901 static int
2902 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2903 {
2904 struct ath5k_hw *ah = sc->ah;
2905 int ret;
2906
2907 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2908
2909 ath5k_hw_set_imr(ah, 0);
2910 synchronize_irq(sc->pdev->irq);
2911 stop_tasklets(sc);
2912
2913 if (chan) {
2914 ath5k_txq_cleanup(sc);
2915 ath5k_rx_stop(sc);
2916
2917 sc->curchan = chan;
2918 sc->curband = &sc->sbands[chan->band];
2919 }
2920 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
2921 if (ret) {
2922 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2923 goto err;
2924 }
2925
2926 ret = ath5k_rx_start(sc);
2927 if (ret) {
2928 ATH5K_ERR(sc, "can't start recv logic\n");
2929 goto err;
2930 }
2931
2932 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
2933
2934 ah->ah_cal_next_full = jiffies;
2935 ah->ah_cal_next_ani = jiffies;
2936 ah->ah_cal_next_nf = jiffies;
2937
2938 /* ath5k_chan_change(sc, c); */
2939
2940 ath5k_beacon_config(sc);
2941 /* intrs are enabled by ath5k_beacon_config */
2942
2943 ieee80211_wake_queues(sc->hw);
2944
2945 return 0;
2946 err:
2947 return ret;
2948 }
2949
2950 static void ath5k_reset_work(struct work_struct *work)
2951 {
2952 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2953 reset_work);
2954
2955 mutex_lock(&sc->lock);
2956 ath5k_reset(sc, sc->curchan);
2957 mutex_unlock(&sc->lock);
2958 }
2959
2960 static int ath5k_start(struct ieee80211_hw *hw)
2961 {
2962 return ath5k_init(hw->priv);
2963 }
2964
2965 static void ath5k_stop(struct ieee80211_hw *hw)
2966 {
2967 ath5k_stop_hw(hw->priv);
2968 }
2969
2970 static int ath5k_add_interface(struct ieee80211_hw *hw,
2971 struct ieee80211_vif *vif)
2972 {
2973 struct ath5k_softc *sc = hw->priv;
2974 int ret;
2975
2976 mutex_lock(&sc->lock);
2977 if (sc->vif) {
2978 ret = 0;
2979 goto end;
2980 }
2981
2982 sc->vif = vif;
2983
2984 switch (vif->type) {
2985 case NL80211_IFTYPE_AP:
2986 case NL80211_IFTYPE_STATION:
2987 case NL80211_IFTYPE_ADHOC:
2988 case NL80211_IFTYPE_MESH_POINT:
2989 case NL80211_IFTYPE_MONITOR:
2990 sc->opmode = vif->type;
2991 break;
2992 default:
2993 ret = -EOPNOTSUPP;
2994 goto end;
2995 }
2996
2997 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
2998
2999 ath5k_hw_set_lladdr(sc->ah, vif->addr);
3000 ath5k_mode_setup(sc);
3001
3002 ret = 0;
3003 end:
3004 mutex_unlock(&sc->lock);
3005 return ret;
3006 }
3007
3008 static void
3009 ath5k_remove_interface(struct ieee80211_hw *hw,
3010 struct ieee80211_vif *vif)
3011 {
3012 struct ath5k_softc *sc = hw->priv;
3013 u8 mac[ETH_ALEN] = {};
3014
3015 mutex_lock(&sc->lock);
3016 if (sc->vif != vif)
3017 goto end;
3018
3019 ath5k_hw_set_lladdr(sc->ah, mac);
3020 sc->vif = NULL;
3021 end:
3022 mutex_unlock(&sc->lock);
3023 }
3024
3025 /*
3026 * TODO: Phy disable/diversity etc
3027 */
3028 static int
3029 ath5k_config(struct ieee80211_hw *hw, u32 changed)
3030 {
3031 struct ath5k_softc *sc = hw->priv;
3032 struct ath5k_hw *ah = sc->ah;
3033 struct ieee80211_conf *conf = &hw->conf;
3034 int ret = 0;
3035
3036 mutex_lock(&sc->lock);
3037
3038 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
3039 ret = ath5k_chan_set(sc, conf->channel);
3040 if (ret < 0)
3041 goto unlock;
3042 }
3043
3044 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
3045 (sc->power_level != conf->power_level)) {
3046 sc->power_level = conf->power_level;
3047
3048 /* Half dB steps */
3049 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
3050 }
3051
3052 /* TODO:
3053 * 1) Move this on config_interface and handle each case
3054 * separately eg. when we have only one STA vif, use
3055 * AR5K_ANTMODE_SINGLE_AP
3056 *
3057 * 2) Allow the user to change antenna mode eg. when only
3058 * one antenna is present
3059 *
3060 * 3) Allow the user to set default/tx antenna when possible
3061 *
3062 * 4) Default mode should handle 90% of the cases, together
3063 * with fixed a/b and single AP modes we should be able to
3064 * handle 99%. Sectored modes are extreme cases and i still
3065 * haven't found a usage for them. If we decide to support them,
3066 * then we must allow the user to set how many tx antennas we
3067 * have available
3068 */
3069 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
3070
3071 unlock:
3072 mutex_unlock(&sc->lock);
3073 return ret;
3074 }
3075
3076 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
3077 struct netdev_hw_addr_list *mc_list)
3078 {
3079 u32 mfilt[2], val;
3080 u8 pos;
3081 struct netdev_hw_addr *ha;
3082
3083 mfilt[0] = 0;
3084 mfilt[1] = 1;
3085
3086 netdev_hw_addr_list_for_each(ha, mc_list) {
3087 /* calculate XOR of eight 6-bit values */
3088 val = get_unaligned_le32(ha->addr + 0);
3089 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3090 val = get_unaligned_le32(ha->addr + 3);
3091 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3092 pos &= 0x3f;
3093 mfilt[pos / 32] |= (1 << (pos % 32));
3094 /* ath5k_hw_set_mcast_filterindex(ah,
3095 * ha->addr[5]); */
3096 }
3097
3098 return ((u64)(mfilt[1]) << 32) | mfilt[0];
3099 }
3100
3101 #define SUPPORTED_FIF_FLAGS \
3102 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3103 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3104 FIF_BCN_PRBRESP_PROMISC
3105 /*
3106 * o always accept unicast, broadcast, and multicast traffic
3107 * o multicast traffic for all BSSIDs will be enabled if mac80211
3108 * says it should be
3109 * o maintain current state of phy ofdm or phy cck error reception.
3110 * If the hardware detects any of these type of errors then
3111 * ath5k_hw_get_rx_filter() will pass to us the respective
3112 * hardware filters to be able to receive these type of frames.
3113 * o probe request frames are accepted only when operating in
3114 * hostap, adhoc, or monitor modes
3115 * o enable promiscuous mode according to the interface state
3116 * o accept beacons:
3117 * - when operating in adhoc mode so the 802.11 layer creates
3118 * node table entries for peers,
3119 * - when operating in station mode for collecting rssi data when
3120 * the station is otherwise quiet, or
3121 * - when scanning
3122 */
3123 static void ath5k_configure_filter(struct ieee80211_hw *hw,
3124 unsigned int changed_flags,
3125 unsigned int *new_flags,
3126 u64 multicast)
3127 {
3128 struct ath5k_softc *sc = hw->priv;
3129 struct ath5k_hw *ah = sc->ah;
3130 u32 mfilt[2], rfilt;
3131
3132 mutex_lock(&sc->lock);
3133
3134 mfilt[0] = multicast;
3135 mfilt[1] = multicast >> 32;
3136
3137 /* Only deal with supported flags */
3138 changed_flags &= SUPPORTED_FIF_FLAGS;
3139 *new_flags &= SUPPORTED_FIF_FLAGS;
3140
3141 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3142 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3143 AR5K_RX_FILTER_MCAST);
3144
3145 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3146 if (*new_flags & FIF_PROMISC_IN_BSS) {
3147 __set_bit(ATH_STAT_PROMISC, sc->status);
3148 } else {
3149 __clear_bit(ATH_STAT_PROMISC, sc->status);
3150 }
3151 }
3152
3153 if (test_bit(ATH_STAT_PROMISC, sc->status))
3154 rfilt |= AR5K_RX_FILTER_PROM;
3155
3156 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3157 if (*new_flags & FIF_ALLMULTI) {
3158 mfilt[0] = ~0;
3159 mfilt[1] = ~0;
3160 }
3161
3162 /* This is the best we can do */
3163 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3164 rfilt |= AR5K_RX_FILTER_PHYERR;
3165
3166 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3167 * and probes for any BSSID, this needs testing */
3168 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
3169 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
3170
3171 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3172 * set we should only pass on control frames for this
3173 * station. This needs testing. I believe right now this
3174 * enables *all* control frames, which is OK.. but
3175 * but we should see if we can improve on granularity */
3176 if (*new_flags & FIF_CONTROL)
3177 rfilt |= AR5K_RX_FILTER_CONTROL;
3178
3179 /* Additional settings per mode -- this is per ath5k */
3180
3181
3182 switch (sc->opmode) {
3183 case NL80211_IFTYPE_MESH_POINT:
3184 case NL80211_IFTYPE_MONITOR:
3185 rfilt |= AR5K_RX_FILTER_CONTROL |
3186 AR5K_RX_FILTER_BEACON |
3187 AR5K_RX_FILTER_PROBEREQ |
3188 AR5K_RX_FILTER_PROM;
3189 break;
3190 case NL80211_IFTYPE_AP:
3191 case NL80211_IFTYPE_ADHOC:
3192 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3193 AR5K_RX_FILTER_BEACON;
3194 break;
3195 case NL80211_IFTYPE_STATION:
3196 if (sc->assoc)
3197 rfilt |= AR5K_RX_FILTER_BEACON;
3198 default:
3199 break;
3200 }
3201
3202 /* Set filters */
3203 ath5k_hw_set_rx_filter(ah, rfilt);
3204
3205 /* Set multicast bits */
3206 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3207 /* Set the cached hw filter flags, this will alter actually
3208 * be set in HW */
3209 sc->filter_flags = rfilt;
3210
3211 mutex_unlock(&sc->lock);
3212 }
3213
3214 static int
3215 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3216 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3217 struct ieee80211_key_conf *key)
3218 {
3219 struct ath5k_softc *sc = hw->priv;
3220 struct ath5k_hw *ah = sc->ah;
3221 struct ath_common *common = ath5k_hw_common(ah);
3222 int ret = 0;
3223
3224 if (modparam_nohwcrypt)
3225 return -EOPNOTSUPP;
3226
3227 if (sc->opmode == NL80211_IFTYPE_AP)
3228 return -EOPNOTSUPP;
3229
3230 switch (key->alg) {
3231 case ALG_WEP:
3232 case ALG_TKIP:
3233 break;
3234 case ALG_CCMP:
3235 if (sc->ah->ah_aes_support)
3236 break;
3237
3238 return -EOPNOTSUPP;
3239 default:
3240 WARN_ON(1);
3241 return -EINVAL;
3242 }
3243
3244 mutex_lock(&sc->lock);
3245
3246 switch (cmd) {
3247 case SET_KEY:
3248 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3249 sta ? sta->addr : NULL);
3250 if (ret) {
3251 ATH5K_ERR(sc, "can't set the key\n");
3252 goto unlock;
3253 }
3254 __set_bit(key->keyidx, common->keymap);
3255 key->hw_key_idx = key->keyidx;
3256 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3257 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3258 break;
3259 case DISABLE_KEY:
3260 ath5k_hw_reset_key(sc->ah, key->keyidx);
3261 __clear_bit(key->keyidx, common->keymap);
3262 break;
3263 default:
3264 ret = -EINVAL;
3265 goto unlock;
3266 }
3267
3268 unlock:
3269 mmiowb();
3270 mutex_unlock(&sc->lock);
3271 return ret;
3272 }
3273
3274 static int
3275 ath5k_get_stats(struct ieee80211_hw *hw,
3276 struct ieee80211_low_level_stats *stats)
3277 {
3278 struct ath5k_softc *sc = hw->priv;
3279
3280 /* Force update */
3281 ath5k_hw_update_mib_counters(sc->ah);
3282
3283 stats->dot11ACKFailureCount = sc->stats.ack_fail;
3284 stats->dot11RTSFailureCount = sc->stats.rts_fail;
3285 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
3286 stats->dot11FCSErrorCount = sc->stats.fcs_error;
3287
3288 return 0;
3289 }
3290
3291 static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
3292 struct survey_info *survey)
3293 {
3294 struct ath5k_softc *sc = hw->priv;
3295 struct ieee80211_conf *conf = &hw->conf;
3296
3297 if (idx != 0)
3298 return -ENOENT;
3299
3300 survey->channel = conf->channel;
3301 survey->filled = SURVEY_INFO_NOISE_DBM;
3302 survey->noise = sc->ah->ah_noise_floor;
3303
3304 return 0;
3305 }
3306
3307 static u64
3308 ath5k_get_tsf(struct ieee80211_hw *hw)
3309 {
3310 struct ath5k_softc *sc = hw->priv;
3311
3312 return ath5k_hw_get_tsf64(sc->ah);
3313 }
3314
3315 static void
3316 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3317 {
3318 struct ath5k_softc *sc = hw->priv;
3319
3320 ath5k_hw_set_tsf64(sc->ah, tsf);
3321 }
3322
3323 static void
3324 ath5k_reset_tsf(struct ieee80211_hw *hw)
3325 {
3326 struct ath5k_softc *sc = hw->priv;
3327
3328 /*
3329 * in IBSS mode we need to update the beacon timers too.
3330 * this will also reset the TSF if we call it with 0
3331 */
3332 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3333 ath5k_beacon_update_timers(sc, 0);
3334 else
3335 ath5k_hw_reset_tsf(sc->ah);
3336 }
3337
3338 /*
3339 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3340 * this is called only once at config_bss time, for AP we do it every
3341 * SWBA interrupt so that the TIM will reflect buffered frames.
3342 *
3343 * Called with the beacon lock.
3344 */
3345 static int
3346 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3347 {
3348 int ret;
3349 struct ath5k_softc *sc = hw->priv;
3350 struct sk_buff *skb;
3351
3352 if (WARN_ON(!vif)) {
3353 ret = -EINVAL;
3354 goto out;
3355 }
3356
3357 skb = ieee80211_beacon_get(hw, vif);
3358
3359 if (!skb) {
3360 ret = -ENOMEM;
3361 goto out;
3362 }
3363
3364 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3365
3366 ath5k_txbuf_free_skb(sc, sc->bbuf);
3367 sc->bbuf->skb = skb;
3368 ret = ath5k_beacon_setup(sc, sc->bbuf);
3369 if (ret)
3370 sc->bbuf->skb = NULL;
3371 out:
3372 return ret;
3373 }
3374
3375 static void
3376 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3377 {
3378 struct ath5k_softc *sc = hw->priv;
3379 struct ath5k_hw *ah = sc->ah;
3380 u32 rfilt;
3381 rfilt = ath5k_hw_get_rx_filter(ah);
3382 if (enable)
3383 rfilt |= AR5K_RX_FILTER_BEACON;
3384 else
3385 rfilt &= ~AR5K_RX_FILTER_BEACON;
3386 ath5k_hw_set_rx_filter(ah, rfilt);
3387 sc->filter_flags = rfilt;
3388 }
3389
3390 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3391 struct ieee80211_vif *vif,
3392 struct ieee80211_bss_conf *bss_conf,
3393 u32 changes)
3394 {
3395 struct ath5k_softc *sc = hw->priv;
3396 struct ath5k_hw *ah = sc->ah;
3397 struct ath_common *common = ath5k_hw_common(ah);
3398 unsigned long flags;
3399
3400 mutex_lock(&sc->lock);
3401 if (WARN_ON(sc->vif != vif))
3402 goto unlock;
3403
3404 if (changes & BSS_CHANGED_BSSID) {
3405 /* Cache for later use during resets */
3406 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3407 common->curaid = 0;
3408 ath5k_hw_set_associd(ah);
3409 mmiowb();
3410 }
3411
3412 if (changes & BSS_CHANGED_BEACON_INT)
3413 sc->bintval = bss_conf->beacon_int;
3414
3415 if (changes & BSS_CHANGED_ASSOC) {
3416 sc->assoc = bss_conf->assoc;
3417 if (sc->opmode == NL80211_IFTYPE_STATION)
3418 set_beacon_filter(hw, sc->assoc);
3419 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3420 AR5K_LED_ASSOC : AR5K_LED_INIT);
3421 if (bss_conf->assoc) {
3422 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3423 "Bss Info ASSOC %d, bssid: %pM\n",
3424 bss_conf->aid, common->curbssid);
3425 common->curaid = bss_conf->aid;
3426 ath5k_hw_set_associd(ah);
3427 /* Once ANI is available you would start it here */
3428 }
3429 }
3430
3431 if (changes & BSS_CHANGED_BEACON) {
3432 spin_lock_irqsave(&sc->block, flags);
3433 ath5k_beacon_update(hw, vif);
3434 spin_unlock_irqrestore(&sc->block, flags);
3435 }
3436
3437 if (changes & BSS_CHANGED_BEACON_ENABLED)
3438 sc->enable_beacon = bss_conf->enable_beacon;
3439
3440 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3441 BSS_CHANGED_BEACON_INT))
3442 ath5k_beacon_config(sc);
3443
3444 unlock:
3445 mutex_unlock(&sc->lock);
3446 }
3447
3448 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3449 {
3450 struct ath5k_softc *sc = hw->priv;
3451 if (!sc->assoc)
3452 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3453 }
3454
3455 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3456 {
3457 struct ath5k_softc *sc = hw->priv;
3458 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3459 AR5K_LED_ASSOC : AR5K_LED_INIT);
3460 }
3461
3462 /**
3463 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3464 *
3465 * @hw: struct ieee80211_hw pointer
3466 * @coverage_class: IEEE 802.11 coverage class number
3467 *
3468 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3469 * coverage class. The values are persistent, they are restored after device
3470 * reset.
3471 */
3472 static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3473 {
3474 struct ath5k_softc *sc = hw->priv;
3475
3476 mutex_lock(&sc->lock);
3477 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3478 mutex_unlock(&sc->lock);
3479 }
Tomato firmware and modifications.