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[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / wireless / ath / ath5k / attach.c
blobb32e28caeee2b6c730a48c2c91aefb7b5708be25
1 /*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 /*************************************\
20 * Attach/Detach Functions and helpers *
21 \*************************************/
23 #include <linux/pci.h>
24 #include <linux/slab.h>
25 #include "ath5k.h"
26 #include "reg.h"
27 #include "debug.h"
28 #include "base.h"
30 /**
31 * ath5k_hw_post - Power On Self Test helper function
33 * @ah: The &struct ath5k_hw
35 static int ath5k_hw_post(struct ath5k_hw *ah)
38 static const u32 static_pattern[4] = {
39 0x55555555, 0xaaaaaaaa,
40 0x66666666, 0x99999999
42 static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
43 int i, c;
44 u16 cur_reg;
45 u32 var_pattern;
46 u32 init_val;
47 u32 cur_val;
49 for (c = 0; c < 2; c++) {
51 cur_reg = regs[c];
53 /* Save previous value */
54 init_val = ath5k_hw_reg_read(ah, cur_reg);
56 for (i = 0; i < 256; i++) {
57 var_pattern = i << 16 | i;
58 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
59 cur_val = ath5k_hw_reg_read(ah, cur_reg);
61 if (cur_val != var_pattern) {
62 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
63 return -EAGAIN;
66 /* Found on ndiswrapper dumps */
67 var_pattern = 0x0039080f;
68 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
71 for (i = 0; i < 4; i++) {
72 var_pattern = static_pattern[i];
73 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
74 cur_val = ath5k_hw_reg_read(ah, cur_reg);
76 if (cur_val != var_pattern) {
77 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
78 return -EAGAIN;
81 /* Found on ndiswrapper dumps */
82 var_pattern = 0x003b080f;
83 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
86 /* Restore previous value */
87 ath5k_hw_reg_write(ah, init_val, cur_reg);
91 return 0;
95 /**
96 * ath5k_hw_attach - Check if hw is supported and init the needed structs
98 * @sc: The &struct ath5k_softc we got from the driver's attach function
100 * Check if the device is supported, perform a POST and initialize the needed
101 * structs. Returns -ENOMEM if we don't have memory for the needed structs,
102 * -ENODEV if the device is not supported or prints an error msg if something
103 * else went wrong.
105 int ath5k_hw_attach(struct ath5k_softc *sc)
107 struct ath5k_hw *ah = sc->ah;
108 struct ath_common *common = ath5k_hw_common(ah);
109 struct pci_dev *pdev = sc->pdev;
110 struct ath5k_eeprom_info *ee;
111 int ret;
112 u32 srev;
115 * HW information
117 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
118 ah->ah_turbo = false;
119 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
120 ah->ah_imr = 0;
121 ah->ah_atim_window = 0;
122 ah->ah_aifs = AR5K_TUNE_AIFS;
123 ah->ah_cw_min = AR5K_TUNE_CWMIN;
124 ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
125 ah->ah_software_retry = false;
126 ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT;
127 ah->ah_noise_floor = -95; /* until first NF calibration is run */
128 sc->ani_state.ani_mode = ATH5K_ANI_MODE_AUTO;
129 ah->ah_current_channel = &sc->channels[0];
132 * Find the mac version
134 srev = ath5k_hw_reg_read(ah, AR5K_SREV);
135 if (srev < AR5K_SREV_AR5311)
136 ah->ah_version = AR5K_AR5210;
137 else if (srev < AR5K_SREV_AR5212)
138 ah->ah_version = AR5K_AR5211;
139 else
140 ah->ah_version = AR5K_AR5212;
142 /*Fill the ath5k_hw struct with the needed functions*/
143 ret = ath5k_hw_init_desc_functions(ah);
144 if (ret)
145 goto err_free;
147 /* Bring device out of sleep and reset it's units */
148 ret = ath5k_hw_nic_wakeup(ah, 0, true);
149 if (ret)
150 goto err_free;
152 /* Get MAC, PHY and RADIO revisions */
153 ah->ah_mac_srev = srev;
154 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
155 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
156 0xffffffff;
157 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
158 CHANNEL_5GHZ);
159 ah->ah_phy = AR5K_PHY(0);
161 /* Try to identify radio chip based on it's srev */
162 switch (ah->ah_radio_5ghz_revision & 0xf0) {
163 case AR5K_SREV_RAD_5111:
164 ah->ah_radio = AR5K_RF5111;
165 ah->ah_single_chip = false;
166 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
167 CHANNEL_2GHZ);
168 break;
169 case AR5K_SREV_RAD_5112:
170 case AR5K_SREV_RAD_2112:
171 ah->ah_radio = AR5K_RF5112;
172 ah->ah_single_chip = false;
173 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
174 CHANNEL_2GHZ);
175 break;
176 case AR5K_SREV_RAD_2413:
177 ah->ah_radio = AR5K_RF2413;
178 ah->ah_single_chip = true;
179 break;
180 case AR5K_SREV_RAD_5413:
181 ah->ah_radio = AR5K_RF5413;
182 ah->ah_single_chip = true;
183 break;
184 case AR5K_SREV_RAD_2316:
185 ah->ah_radio = AR5K_RF2316;
186 ah->ah_single_chip = true;
187 break;
188 case AR5K_SREV_RAD_2317:
189 ah->ah_radio = AR5K_RF2317;
190 ah->ah_single_chip = true;
191 break;
192 case AR5K_SREV_RAD_5424:
193 if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
194 ah->ah_mac_version == AR5K_SREV_AR2417){
195 ah->ah_radio = AR5K_RF2425;
196 ah->ah_single_chip = true;
197 } else {
198 ah->ah_radio = AR5K_RF5413;
199 ah->ah_single_chip = true;
201 break;
202 default:
203 /* Identify radio based on mac/phy srev */
204 if (ah->ah_version == AR5K_AR5210) {
205 ah->ah_radio = AR5K_RF5110;
206 ah->ah_single_chip = false;
207 } else if (ah->ah_version == AR5K_AR5211) {
208 ah->ah_radio = AR5K_RF5111;
209 ah->ah_single_chip = false;
210 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
211 CHANNEL_2GHZ);
212 } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
213 ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
214 ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
215 ah->ah_radio = AR5K_RF2425;
216 ah->ah_single_chip = true;
217 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
218 } else if (srev == AR5K_SREV_AR5213A &&
219 ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
220 ah->ah_radio = AR5K_RF5112;
221 ah->ah_single_chip = false;
222 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
223 } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
224 ah->ah_radio = AR5K_RF2316;
225 ah->ah_single_chip = true;
226 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
227 } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
228 ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
229 ah->ah_radio = AR5K_RF5413;
230 ah->ah_single_chip = true;
231 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
232 } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
233 ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
234 ah->ah_radio = AR5K_RF2413;
235 ah->ah_single_chip = true;
236 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
237 } else {
238 ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
239 ret = -ENODEV;
240 goto err_free;
245 /* Return on unsuported chips (unsupported eeprom etc) */
246 if ((srev >= AR5K_SREV_AR5416) &&
247 (srev < AR5K_SREV_AR2425)) {
248 ATH5K_ERR(sc, "Device not yet supported.\n");
249 ret = -ENODEV;
250 goto err_free;
254 * POST
256 ret = ath5k_hw_post(ah);
257 if (ret)
258 goto err_free;
260 /* Enable pci core retry fix on Hainan (5213A) and later chips */
261 if (srev >= AR5K_SREV_AR5213A)
262 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX);
265 * Get card capabilities, calibration values etc
266 * TODO: EEPROM work
268 ret = ath5k_eeprom_init(ah);
269 if (ret) {
270 ATH5K_ERR(sc, "unable to init EEPROM\n");
271 goto err_free;
274 ee = &ah->ah_capabilities.cap_eeprom;
277 * Write PCI-E power save settings
279 if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
280 ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
281 ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
283 /* Shut off RX when elecidle is asserted */
284 ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
285 ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
287 /* If serdes programing is enabled, increase PCI-E
288 * tx power for systems with long trace from host
289 * to minicard connector. */
290 if (ee->ee_serdes)
291 ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
292 else
293 ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);
295 /* Shut off PLL and CLKREQ active in L1 */
296 ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
298 /* Preserve other settings */
299 ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
300 ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
301 ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
303 /* Reset SERDES to load new settings */
304 ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
305 mdelay(1);
308 /* Get misc capabilities */
309 ret = ath5k_hw_set_capabilities(ah);
310 if (ret) {
311 ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
312 sc->pdev->device);
313 goto err_free;
316 /* Crypto settings */
317 ah->ah_aes_support = srev >= AR5K_SREV_AR5212_V4 &&
318 (ee->ee_version >= AR5K_EEPROM_VERSION_5_0 &&
319 !AR5K_EEPROM_AES_DIS(ee->ee_misc5));
321 if (srev >= AR5K_SREV_AR2414) {
322 ah->ah_combined_mic = true;
323 AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
324 AR5K_MISC_MODE_COMBINED_MIC);
327 /* MAC address is cleared until add_interface */
328 ath5k_hw_set_lladdr(ah, (u8[ETH_ALEN]){});
330 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
331 memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN);
332 ath5k_hw_set_associd(ah);
333 ath5k_hw_set_opmode(ah, sc->opmode);
335 ath5k_hw_rfgain_opt_init(ah);
337 ath5k_hw_init_nfcal_hist(ah);
339 /* turn on HW LEDs */
340 ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);
342 return 0;
343 err_free:
344 kfree(ah);
345 return ret;
349 * ath5k_hw_detach - Free the ath5k_hw struct
351 * @ah: The &struct ath5k_hw
353 void ath5k_hw_detach(struct ath5k_hw *ah)
355 __set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
357 if (ah->ah_rf_banks != NULL)
358 kfree(ah->ah_rf_banks);
360 ath5k_eeprom_detach(ah);
362 /* assume interrupts are down */