?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / tulip / de4x5.c
blob10be7c02b4878a582820f77a08cb8a1e77f10c43
1 /* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
3
4 Copyright 1994, 1995 Digital Equipment Corporation.
5
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
8
9 The author may be reached at davies@maniac.ultranet.com.
10
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
15
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
30
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
33
34 DE425 TP/COAX EISA
35 DE434 TP PCI
36 DE435 TP/COAX/AUI PCI
37 DE450 TP/COAX/AUI PCI
38 DE500 10/100 PCI Fasternet
39
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
43
44 DC21040 (no SROM)
45 DC21041[A]
46 DC21140[A]
47 DC21142
48 DC21143
49
50 So far the driver is known to work with the following cards:
51
52 KINGSTON
53 Linksys
54 ZNYX342
55 SMC8432
56 SMC9332 (w/new SROM)
57 ZNYX31[45]
58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
59
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
63
64 TCP UDP
65 TX RX TX RX
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
70
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
74
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
81
82 Upto 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
86
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
90 address.
91
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
98
99 To utilise this ability, you have to do 8 things:
100
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
103 temporary directory.
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
106 loading by:
107
108 insmod de4x5 io=0xghh where g = bus number
109 hh = device number
110
111 NB: autoprobing for modules is now supported by default. You may just
112 use:
113
114 insmod de4x5
115
116 to load all available boards. For a specific board, still use
117 the 'io=?' above.
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
125 7) enjoy!
126
127 To unload a module, turn off the associated interface(s)
128 'ifconfig eth?? down' then 'rmmod de4x5'.
129
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
134
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
138 'dec_only=1' parameter.
139
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
146
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
149
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
153
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
158
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
168 wired IRQs.
169
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
182
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
189 limitation.
190
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
198
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
205
206 fdx for full duplex
207 autosense to set the media/speed; with the following
208 sub-parameters:
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
213
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
218
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
227
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
237
238 TO DO:
239 ------
240
241 Revision History
242 ----------------
243
244 Version Date Description
245
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
255 Fix missed frame counter value and initialisation.
256 Fixed EISA probe.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
264 Portability changes.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
283 Add new autosense algorithms for media/mode
284 selection using kernel scheduling/timing.
285 Re-formatted.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
295 Duh, put the IRQF_SHARED flag into request_interrupt().
296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
310 reported by <koen.gadeyne@barco.com> and
311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
313 reported by <csd@microplex.com> and
314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
330 Updated debug flags.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
340 <paubert@iram.es>
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
346 <paubert@iram.es>.
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
353 infoblocks.
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
356 Added IRQF_DISABLED temporary fix from
357 <mjacob@feral.com>.
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
364 direction.
365 Completed DC2114[23] autosense functions.
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
367 <robin@intercore.com
368 Fix type1_infoblock() bug introduced in 0.53, from
369 problem reports by
370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
375 newer PHY chips.
376 Fix the mess in 2.1.67.
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
378 <redhat@cococo.net>.
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
385 **Incompatible with 2.0.x from here.**
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
387 from <lma@varesearch.com>
388 Add TP, AUI and BNC cases to 21140m_autoconf() for
389 case where a 21140 under SROM control uses, e.g. AUI
390 from problem report by <delchini@lpnp09.in2p3.fr>
391 Add MII parallel detection to 2114x_autoconf() for
392 case where no autonegotiation partner exists from
393 problem report by <mlapsley@ndirect.co.uk>.
394 Add ability to force connection type directly even
395 when using SROM control from problem report by
396 <earl@exis.net>.
397 Updated the PCI interface to conform with the latest
398 version. I hope nothing is broken...
399 Add TX done interrupt modification from suggestion
400 by <Austin.Donnelly@cl.cam.ac.uk>.
401 Fix is_anc_capable() bug reported by
402 <Austin.Donnelly@cl.cam.ac.uk>.
403 Fix type[13]_infoblock() bug: during MII search, PHY
404 lp->rst not run because lp->ibn not initialised -
405 from report & fix by <paubert@iram.es>.
406 Fix probe bug with EISA & PCI cards present from
407 report by <eirik@netcom.com>.
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
409 ops from multiple bug reports and temporary fix
410 from <paubert@iram.es>.
411 Fix pci_probe() to correctly emulate the old
412 pcibios_find_class() function.
413 Add an_exception() for old ZYNX346 and fix compile
414 warning on PPC & SPARC, from <ecd@skynet.be>.
415 Fix lastPCI to correctly work with compiled in
416 kernels and modules from bug report by
417 <Zlatko.Calusic@CARNet.hr> et al.
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
419 when media is unconnected.
420 Change dev->interrupt to lp->interrupt to ensure
421 alignment for Alpha's and avoid their unaligned
422 access traps. This flag is merely for log messages:
423 should do something more definitive though...
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
426 a 21143 by <mmporter@home.com>.
427 Change PCI/EISA bus probing order.
428 0.545 28-Nov-99 Further Moto SROM bug fix from
429 <mporter@eng.mcd.mot.com>
430 Remove double checking for DEBUG_RX in de4x5_dbg_rx()
431 from report by <geert@linux-m68k.org>
432 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function
433 was causing a page fault when initializing the
434 variable 'pb', on a non de4x5 PCI device, in this
435 case a PCI bridge (DEC chip 21152). The value of
436 'pb' is now only initialized if a de4x5 chip is
437 present.
438 <france@handhelds.org>
439 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com>
440 0.548 30-Aug-03 Big 2.6 cleanup. Ported to PCI/EISA probing and
441 generic DMA APIs. Fixed DE425 support on Alpha.
442 <maz@wild-wind.fr.eu.org>
443 =========================================================================
444 */
445
446 #include <linux/module.h>
447 #include <linux/kernel.h>
448 #include <linux/string.h>
449 #include <linux/interrupt.h>
450 #include <linux/ptrace.h>
451 #include <linux/errno.h>
452 #include <linux/ioport.h>
453 #include <linux/pci.h>
454 #include <linux/eisa.h>
455 #include <linux/delay.h>
456 #include <linux/init.h>
457 #include <linux/spinlock.h>
458 #include <linux/crc32.h>
459 #include <linux/netdevice.h>
460 #include <linux/etherdevice.h>
461 #include <linux/skbuff.h>
462 #include <linux/time.h>
463 #include <linux/types.h>
464 #include <linux/unistd.h>
465 #include <linux/ctype.h>
466 #include <linux/dma-mapping.h>
467 #include <linux/moduleparam.h>
468 #include <linux/bitops.h>
469 #include <linux/gfp.h>
470
471 #include <asm/io.h>
472 #include <asm/dma.h>
473 #include <asm/byteorder.h>
474 #include <asm/unaligned.h>
475 #include <asm/uaccess.h>
476 #ifdef CONFIG_PPC_PMAC
477 #include <asm/machdep.h>
478 #endif /* CONFIG_PPC_PMAC */
479
480 #include "de4x5.h"
481
482 static const char version[] __devinitconst =
483 KERN_INFO "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
484
485 #define c_char const char
486
487 /*
488 ** MII Information
489 */
490 struct phy_table {
491 int reset; /* Hard reset required? */
492 int id; /* IEEE OUI */
493 int ta; /* One cycle TA time - 802.3u is confusing here */
494 struct { /* Non autonegotiation (parallel) speed det. */
495 int reg;
496 int mask;
497 int value;
498 } spd;
499 };
500
501 struct mii_phy {
502 int reset; /* Hard reset required? */
503 int id; /* IEEE OUI */
504 int ta; /* One cycle TA time */
505 struct { /* Non autonegotiation (parallel) speed det. */
506 int reg;
507 int mask;
508 int value;
509 } spd;
510 int addr; /* MII address for the PHY */
511 u_char *gep; /* Start of GEP sequence block in SROM */
512 u_char *rst; /* Start of reset sequence in SROM */
513 u_int mc; /* Media Capabilities */
514 u_int ana; /* NWay Advertisement */
515 u_int fdx; /* Full DupleX capabilities for each media */
516 u_int ttm; /* Transmit Threshold Mode for each media */
517 u_int mci; /* 21142 MII Connector Interrupt info */
518 };
519
520 #define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */
521
522 struct sia_phy {
523 u_char mc; /* Media Code */
524 u_char ext; /* csr13-15 valid when set */
525 int csr13; /* SIA Connectivity Register */
526 int csr14; /* SIA TX/RX Register */
527 int csr15; /* SIA General Register */
528 int gepc; /* SIA GEP Control Information */
529 int gep; /* SIA GEP Data */
530 };
531
532 /*
533 ** Define the know universe of PHY devices that can be
534 ** recognised by this driver.
535 */
536 static struct phy_table phy_info[] = {
537 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
538 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
539 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
540 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
541 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
542 };
543
544 /*
545 ** These GENERIC values assumes that the PHY devices follow 802.3u and
546 ** allow parallel detection to set the link partner ability register.
547 ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
548 */
549 #define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
550 #define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
551 #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
552
553 /*
554 ** Define special SROM detection cases
555 */
556 static c_char enet_det[][ETH_ALEN] = {
557 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
558 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
559 };
560
561 #define SMC 1
562 #define ACCTON 2
563
564 /*
565 ** SROM Repair definitions. If a broken SROM is detected a card may
566 ** use this information to help figure out what to do. This is a
567 ** "stab in the dark" and so far for SMC9332's only.
568 */
569 static c_char srom_repair_info[][100] = {
570 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
571 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
572 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
573 0x00,0x18,}
574 };
575
576
577 #ifdef DE4X5_DEBUG
578 static int de4x5_debug = DE4X5_DEBUG;
579 #else
580 /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
581 static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
582 #endif
583
584 /*
585 ** Allow per adapter set up. For modules this is simply a command line
586 ** parameter, e.g.:
587 ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
588 **
589 ** For a compiled in driver, place e.g.
590 ** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
591 ** here
592 */
593 #ifdef DE4X5_PARM
594 static char *args = DE4X5_PARM;
595 #else
596 static char *args;
597 #endif
598
599 struct parameters {
600 bool fdx;
601 int autosense;
602 };
603
604 #define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
605
606 #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
607
608 /*
609 ** Ethernet PROM defines
610 */
611 #define PROBE_LENGTH 32
612 #define ETH_PROM_SIG 0xAA5500FFUL
613
614 /*
615 ** Ethernet Info
616 */
617 #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
618 #define IEEE802_3_SZ 1518 /* Packet + CRC */
619 #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
620 #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
621 #define MIN_DAT_SZ 1 /* Minimum ethernet data length */
622 #define PKT_HDR_LEN 14 /* Addresses and data length info */
623 #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
624 #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
625
626
627 /*
628 ** EISA bus defines
629 */
630 #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
631 #define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
632
633 #define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
634
635 #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
636 #define DE4X5_NAME_LENGTH 8
637
638 static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
639
640 /*
641 ** Ethernet PROM defines for DC21040
642 */
643 #define PROBE_LENGTH 32
644 #define ETH_PROM_SIG 0xAA5500FFUL
645
646 /*
647 ** PCI Bus defines
648 */
649 #define PCI_MAX_BUS_NUM 8
650 #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
651 #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
652
653 /*
654 ** Memory Alignment. Each descriptor is 4 longwords long. To force a
655 ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
656 ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
657 ** and hence the RX descriptor ring's first entry.
658 */
659 #define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
660 #define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */
661 #define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */
662 #define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */
663 #define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */
664 #define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */
665
666 #define DE4X5_ALIGN DE4X5_ALIGN32 /* Keep the DC21040 happy... */
667 #define DE4X5_CACHE_ALIGN CAL_16LONG
668 #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
669 /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
670 #define DESC_ALIGN
671
672 #ifndef DEC_ONLY /* See README.de4x5 for using this */
673 static int dec_only;
674 #else
675 static int dec_only = 1;
676 #endif
677
678 /*
679 ** DE4X5 IRQ ENABLE/DISABLE
680 */
681 #define ENABLE_IRQs { \
682 imr |= lp->irq_en;\
683 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
684 }
685
686 #define DISABLE_IRQs {\
687 imr = inl(DE4X5_IMR);\
688 imr &= ~lp->irq_en;\
689 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
690 }
691
692 #define UNMASK_IRQs {\
693 imr |= lp->irq_mask;\
694 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
695 }
696
697 #define MASK_IRQs {\
698 imr = inl(DE4X5_IMR);\
699 imr &= ~lp->irq_mask;\
700 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
701 }
702
703 /*
704 ** DE4X5 START/STOP
705 */
706 #define START_DE4X5 {\
707 omr = inl(DE4X5_OMR);\
708 omr |= OMR_ST | OMR_SR;\
709 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
710 }
711
712 #define STOP_DE4X5 {\
713 omr = inl(DE4X5_OMR);\
714 omr &= ~(OMR_ST|OMR_SR);\
715 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
716 }
717
718 /*
719 ** DE4X5 SIA RESET
720 */
721 #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
722
723 /*
724 ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
725 */
726 #define DE4X5_AUTOSENSE_MS 250
727
728 /*
729 ** SROM Structure
730 */
731 struct de4x5_srom {
732 char sub_vendor_id[2];
733 char sub_system_id[2];
734 char reserved[12];
735 char id_block_crc;
736 char reserved2;
737 char version;
738 char num_controllers;
739 char ieee_addr[6];
740 char info[100];
741 short chksum;
742 };
743 #define SUB_VENDOR_ID 0x500a
744
745 /*
746 ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
747 ** and have sizes of both a power of 2 and a multiple of 4.
748 ** A size of 256 bytes for each buffer could be chosen because over 90% of
749 ** all packets in our network are <256 bytes long and 64 longword alignment
750 ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
751 ** descriptors are needed for machines with an ALPHA CPU.
752 */
753 #define NUM_RX_DESC 8 /* Number of RX descriptors */
754 #define NUM_TX_DESC 32 /* Number of TX descriptors */
755 #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
756 /* Multiple of 4 for DC21040 */
757 /* Allows 512 byte alignment */
758 struct de4x5_desc {
759 volatile __le32 status;
760 __le32 des1;
761 __le32 buf;
762 __le32 next;
763 DESC_ALIGN
764 };
765
766 /*
767 ** The DE4X5 private structure
768 */
769 #define DE4X5_PKT_STAT_SZ 16
770 #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
771 increase DE4X5_PKT_STAT_SZ */
772
773 struct pkt_stats {
774 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
775 u_int unicast;
776 u_int multicast;
777 u_int broadcast;
778 u_int excessive_collisions;
779 u_int tx_underruns;
780 u_int excessive_underruns;
781 u_int rx_runt_frames;
782 u_int rx_collision;
783 u_int rx_dribble;
784 u_int rx_overflow;
785 };
786
787 struct de4x5_private {
788 char adapter_name[80]; /* Adapter name */
789 u_long interrupt; /* Aligned ISR flag */
790 struct de4x5_desc *rx_ring; /* RX descriptor ring */
791 struct de4x5_desc *tx_ring; /* TX descriptor ring */
792 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
793 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
794 int rx_new, rx_old; /* RX descriptor ring pointers */
795 int tx_new, tx_old; /* TX descriptor ring pointers */
796 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
797 char frame[64]; /* Min sized packet for loopback*/
798 spinlock_t lock; /* Adapter specific spinlock */
799 struct net_device_stats stats; /* Public stats */
800 struct pkt_stats pktStats; /* Private stats counters */
801 char rxRingSize;
802 char txRingSize;
803 int bus; /* EISA or PCI */
804 int bus_num; /* PCI Bus number */
805 int device; /* Device number on PCI bus */
806 int state; /* Adapter OPENED or CLOSED */
807 int chipset; /* DC21040, DC21041 or DC21140 */
808 s32 irq_mask; /* Interrupt Mask (Enable) bits */
809 s32 irq_en; /* Summary interrupt bits */
810 int media; /* Media (eg TP), mode (eg 100B)*/
811 int c_media; /* Remember the last media conn */
812 bool fdx; /* media full duplex flag */
813 int linkOK; /* Link is OK */
814 int autosense; /* Allow/disallow autosensing */
815 bool tx_enable; /* Enable descriptor polling */
816 int setup_f; /* Setup frame filtering type */
817 int local_state; /* State within a 'media' state */
818 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
819 struct sia_phy sia; /* SIA PHY Information */
820 int active; /* Index to active PHY device */
821 int mii_cnt; /* Number of attached PHY's */
822 int timeout; /* Scheduling counter */
823 struct timer_list timer; /* Timer info for kernel */
824 int tmp; /* Temporary global per card */
825 struct {
826 u_long lock; /* Lock the cache accesses */
827 s32 csr0; /* Saved Bus Mode Register */
828 s32 csr6; /* Saved Operating Mode Reg. */
829 s32 csr7; /* Saved IRQ Mask Register */
830 s32 gep; /* Saved General Purpose Reg. */
831 s32 gepc; /* Control info for GEP */
832 s32 csr13; /* Saved SIA Connectivity Reg. */
833 s32 csr14; /* Saved SIA TX/RX Register */
834 s32 csr15; /* Saved SIA General Register */
835 int save_cnt; /* Flag if state already saved */
836 struct sk_buff_head queue; /* Save the (re-ordered) skb's */
837 } cache;
838 struct de4x5_srom srom; /* A copy of the SROM */
839 int cfrv; /* Card CFRV copy */
840 int rx_ovf; /* Check for 'RX overflow' tag */
841 bool useSROM; /* For non-DEC card use SROM */
842 bool useMII; /* Infoblock using the MII */
843 int asBitValid; /* Autosense bits in GEP? */
844 int asPolarity; /* 0 => asserted high */
845 int asBit; /* Autosense bit number in GEP */
846 int defMedium; /* SROM default medium */
847 int tcount; /* Last infoblock number */
848 int infoblock_init; /* Initialised this infoblock? */
849 int infoleaf_offset; /* SROM infoleaf for controller */
850 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
851 int infoblock_media; /* infoblock media */
852 int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */
853 u_char *rst; /* Pointer to Type 5 reset info */
854 u_char ibn; /* Infoblock number */
855 struct parameters params; /* Command line/ #defined params */
856 struct device *gendev; /* Generic device */
857 dma_addr_t dma_rings; /* DMA handle for rings */
858 int dma_size; /* Size of the DMA area */
859 char *rx_bufs; /* rx bufs on alpha, sparc, ... */
860 };
861
862 /*
863 ** To get around certain poxy cards that don't provide an SROM
864 ** for the second and more DECchip, I have to key off the first
865 ** chip's address. I'll assume there's not a bad SROM iff:
866 **
867 ** o the chipset is the same
868 ** o the bus number is the same and > 0
869 ** o the sum of all the returned hw address bytes is 0 or 0x5fa
870 **
871 ** Also have to save the irq for those cards whose hardware designers
872 ** can't follow the PCI to PCI Bridge Architecture spec.
873 */
874 static struct {
875 int chipset;
876 int bus;
877 int irq;
878 u_char addr[ETH_ALEN];
879 } last = {0,};
880
881 /*
882 ** The transmit ring full condition is described by the tx_old and tx_new
883 ** pointers by:
884 ** tx_old = tx_new Empty ring
885 ** tx_old = tx_new+1 Full ring
886 ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
887 */
888 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
889 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
890 lp->tx_old -lp->tx_new-1)
891
892 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
893
894 /*
895 ** Public Functions
896 */
897 static int de4x5_open(struct net_device *dev);
898 static netdev_tx_t de4x5_queue_pkt(struct sk_buff *skb,
899 struct net_device *dev);
900 static irqreturn_t de4x5_interrupt(int irq, void *dev_id);
901 static int de4x5_close(struct net_device *dev);
902 static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
903 static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
904 static void set_multicast_list(struct net_device *dev);
905 static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
906
907 /*
908 ** Private functions
909 */
910 static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
911 static int de4x5_init(struct net_device *dev);
912 static int de4x5_sw_reset(struct net_device *dev);
913 static int de4x5_rx(struct net_device *dev);
914 static int de4x5_tx(struct net_device *dev);
915 static void de4x5_ast(struct net_device *dev);
916 static int de4x5_txur(struct net_device *dev);
917 static int de4x5_rx_ovfc(struct net_device *dev);
918
919 static int autoconf_media(struct net_device *dev);
920 static void create_packet(struct net_device *dev, char *frame, int len);
921 static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
922 static int dc21040_autoconf(struct net_device *dev);
923 static int dc21041_autoconf(struct net_device *dev);
924 static int dc21140m_autoconf(struct net_device *dev);
925 static int dc2114x_autoconf(struct net_device *dev);
926 static int srom_autoconf(struct net_device *dev);
927 static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
928 static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
929 static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
930 static int test_for_100Mb(struct net_device *dev, int msec);
931 static int wait_for_link(struct net_device *dev);
932 static int test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec);
933 static int is_spd_100(struct net_device *dev);
934 static int is_100_up(struct net_device *dev);
935 static int is_10_up(struct net_device *dev);
936 static int is_anc_capable(struct net_device *dev);
937 static int ping_media(struct net_device *dev, int msec);
938 static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
939 static void de4x5_free_rx_buffs(struct net_device *dev);
940 static void de4x5_free_tx_buffs(struct net_device *dev);
941 static void de4x5_save_skbs(struct net_device *dev);
942 static void de4x5_rst_desc_ring(struct net_device *dev);
943 static void de4x5_cache_state(struct net_device *dev, int flag);
944 static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
945 static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
946 static struct sk_buff *de4x5_get_cache(struct net_device *dev);
947 static void de4x5_setup_intr(struct net_device *dev);
948 static void de4x5_init_connection(struct net_device *dev);
949 static int de4x5_reset_phy(struct net_device *dev);
950 static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
951 static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
952 static int test_tp(struct net_device *dev, s32 msec);
953 static int EISA_signature(char *name, struct device *device);
954 static int PCI_signature(char *name, struct de4x5_private *lp);
955 static void DevicePresent(struct net_device *dev, u_long iobase);
956 static void enet_addr_rst(u_long aprom_addr);
957 static int de4x5_bad_srom(struct de4x5_private *lp);
958 static short srom_rd(u_long address, u_char offset);
959 static void srom_latch(u_int command, u_long address);
960 static void srom_command(u_int command, u_long address);
961 static void srom_address(u_int command, u_long address, u_char offset);
962 static short srom_data(u_int command, u_long address);
963 /*static void srom_busy(u_int command, u_long address);*/
964 static void sendto_srom(u_int command, u_long addr);
965 static int getfrom_srom(u_long addr);
966 static int srom_map_media(struct net_device *dev);
967 static int srom_infoleaf_info(struct net_device *dev);
968 static void srom_init(struct net_device *dev);
969 static void srom_exec(struct net_device *dev, u_char *p);
970 static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
971 static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
972 static int mii_rdata(u_long ioaddr);
973 static void mii_wdata(int data, int len, u_long ioaddr);
974 static void mii_ta(u_long rw, u_long ioaddr);
975 static int mii_swap(int data, int len);
976 static void mii_address(u_char addr, u_long ioaddr);
977 static void sendto_mii(u32 command, int data, u_long ioaddr);
978 static int getfrom_mii(u32 command, u_long ioaddr);
979 static int mii_get_oui(u_char phyaddr, u_long ioaddr);
980 static int mii_get_phy(struct net_device *dev);
981 static void SetMulticastFilter(struct net_device *dev);
982 static int get_hw_addr(struct net_device *dev);
983 static void srom_repair(struct net_device *dev, int card);
984 static int test_bad_enet(struct net_device *dev, int status);
985 static int an_exception(struct de4x5_private *lp);
986 static char *build_setup_frame(struct net_device *dev, int mode);
987 static void disable_ast(struct net_device *dev);
988 static long de4x5_switch_mac_port(struct net_device *dev);
989 static int gep_rd(struct net_device *dev);
990 static void gep_wr(s32 data, struct net_device *dev);
991 static void yawn(struct net_device *dev, int state);
992 static void de4x5_parse_params(struct net_device *dev);
993 static void de4x5_dbg_open(struct net_device *dev);
994 static void de4x5_dbg_mii(struct net_device *dev, int k);
995 static void de4x5_dbg_media(struct net_device *dev);
996 static void de4x5_dbg_srom(struct de4x5_srom *p);
997 static void de4x5_dbg_rx(struct sk_buff *skb, int len);
998 static int de4x5_strncmp(char *a, char *b, int n);
999 static int dc21041_infoleaf(struct net_device *dev);
1000 static int dc21140_infoleaf(struct net_device *dev);
1001 static int dc21142_infoleaf(struct net_device *dev);
1002 static int dc21143_infoleaf(struct net_device *dev);
1003 static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1004 static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1005 static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1006 static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1007 static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1008 static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1009 static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1010
1011 /*
1012 ** Note now that module autoprobing is allowed under EISA and PCI. The
1013 ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
1014 ** to "do the right thing".
1015 */
1016
1017 static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
1018
1019 module_param(io, int, 0);
1020 module_param(de4x5_debug, int, 0);
1021 module_param(dec_only, int, 0);
1022 module_param(args, charp, 0);
1023
1024 MODULE_PARM_DESC(io, "de4x5 I/O base address");
1025 MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1026 MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1027 MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1028 MODULE_LICENSE("GPL");
1029
1030 /*
1031 ** List the SROM infoleaf functions and chipsets
1032 */
1033 struct InfoLeaf {
1034 int chipset;
1035 int (*fn)(struct net_device *);
1036 };
1037 static struct InfoLeaf infoleaf_array[] = {
1038 {DC21041, dc21041_infoleaf},
1039 {DC21140, dc21140_infoleaf},
1040 {DC21142, dc21142_infoleaf},
1041 {DC21143, dc21143_infoleaf}
1042 };
1043 #define INFOLEAF_SIZE ARRAY_SIZE(infoleaf_array)
1044
1045 /*
1046 ** List the SROM info block functions
1047 */
1048 static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1049 type0_infoblock,
1050 type1_infoblock,
1051 type2_infoblock,
1052 type3_infoblock,
1053 type4_infoblock,
1054 type5_infoblock,
1055 compact_infoblock
1056 };
1057
1058 #define COMPACT (ARRAY_SIZE(dc_infoblock) - 1)
1059
1060 /*
1061 ** Miscellaneous defines...
1062 */
1063 #define RESET_DE4X5 {\
1064 int i;\
1065 i=inl(DE4X5_BMR);\
1066 mdelay(1);\
1067 outl(i | BMR_SWR, DE4X5_BMR);\
1068 mdelay(1);\
1069 outl(i, DE4X5_BMR);\
1070 mdelay(1);\
1071 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1072 mdelay(1);\
1073 }
1074
1075 #define PHY_HARD_RESET {\
1076 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1077 mdelay(1); /* Assert for 1ms */\
1078 outl(0x00, DE4X5_GEP);\
1079 mdelay(2); /* Wait for 2ms */\
1080 }
1081
1082 static const struct net_device_ops de4x5_netdev_ops = {
1083 .ndo_open = de4x5_open,
1084 .ndo_stop = de4x5_close,
1085 .ndo_start_xmit = de4x5_queue_pkt,
1086 .ndo_get_stats = de4x5_get_stats,
1087 .ndo_set_multicast_list = set_multicast_list,
1088 .ndo_do_ioctl = de4x5_ioctl,
1089 .ndo_change_mtu = eth_change_mtu,
1090 .ndo_set_mac_address= eth_mac_addr,
1091 .ndo_validate_addr = eth_validate_addr,
1092 };
1093
1094
1095 static int __devinit
1096 de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
1097 {
1098 char name[DE4X5_NAME_LENGTH + 1];
1099 struct de4x5_private *lp = netdev_priv(dev);
1100 struct pci_dev *pdev = NULL;
1101 int i, status=0;
1102
1103 dev_set_drvdata(gendev, dev);
1104
1105 /* Ensure we're not sleeping */
1106 if (lp->bus == EISA) {
1107 outb(WAKEUP, PCI_CFPM);
1108 } else {
1109 pdev = to_pci_dev (gendev);
1110 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
1111 }
1112 mdelay(10);
1113
1114 RESET_DE4X5;
1115
1116 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1117 return -ENXIO; /* Hardware could not reset */
1118 }
1119
1120 /*
1121 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1122 */
1123 lp->useSROM = false;
1124 if (lp->bus == PCI) {
1125 PCI_signature(name, lp);
1126 } else {
1127 EISA_signature(name, gendev);
1128 }
1129
1130 if (*name == '\0') { /* Not found a board signature */
1131 return -ENXIO;
1132 }
1133
1134 dev->base_addr = iobase;
1135 printk ("%s: %s at 0x%04lx", dev_name(gendev), name, iobase);
1136
1137 status = get_hw_addr(dev);
1138 printk(", h/w address %pM\n", dev->dev_addr);
1139
1140 if (status != 0) {
1141 printk(" which has an Ethernet PROM CRC error.\n");
1142 return -ENXIO;
1143 } else {
1144 skb_queue_head_init(&lp->cache.queue);
1145 lp->cache.gepc = GEP_INIT;
1146 lp->asBit = GEP_SLNK;
1147 lp->asPolarity = GEP_SLNK;
1148 lp->asBitValid = ~0;
1149 lp->timeout = -1;
1150 lp->gendev = gendev;
1151 spin_lock_init(&lp->lock);
1152 init_timer(&lp->timer);
1153 lp->timer.function = (void (*)(unsigned long))de4x5_ast;
1154 lp->timer.data = (unsigned long)dev;
1155 de4x5_parse_params(dev);
1156
1157 /*
1158 ** Choose correct autosensing in case someone messed up
1159 */
1160 lp->autosense = lp->params.autosense;
1161 if (lp->chipset != DC21140) {
1162 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1163 lp->params.autosense = TP;
1164 }
1165 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1166 lp->params.autosense = BNC;
1167 }
1168 }
1169 lp->fdx = lp->params.fdx;
1170 sprintf(lp->adapter_name,"%s (%s)", name, dev_name(gendev));
1171
1172 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1173 #if defined(__alpha__) || defined(__powerpc__) || defined(CONFIG_SPARC) || \
1174 defined(DE4X5_DO_MEMCPY)
1175 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1176 #endif
1177 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1178 &lp->dma_rings, GFP_ATOMIC);
1179 if (lp->rx_ring == NULL) {
1180 return -ENOMEM;
1181 }
1182
1183 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1184
1185 /*
1186 ** Set up the RX descriptor ring (Intels)
1187 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1188 */
1189 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && \
1190 !defined(DE4X5_DO_MEMCPY)
1191 for (i=0; i<NUM_RX_DESC; i++) {
1192 lp->rx_ring[i].status = 0;
1193 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1194 lp->rx_ring[i].buf = 0;
1195 lp->rx_ring[i].next = 0;
1196 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1197 }
1198
1199 #else
1200 {
1201 dma_addr_t dma_rx_bufs;
1202
1203 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1204 * sizeof(struct de4x5_desc);
1205 dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN;
1206 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1207 + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1208 for (i=0; i<NUM_RX_DESC; i++) {
1209 lp->rx_ring[i].status = 0;
1210 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1211 lp->rx_ring[i].buf =
1212 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1213 lp->rx_ring[i].next = 0;
1214 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1215 }
1216
1217 }
1218 #endif
1219
1220 barrier();
1221
1222 lp->rxRingSize = NUM_RX_DESC;
1223 lp->txRingSize = NUM_TX_DESC;
1224
1225 /* Write the end of list marker to the descriptor lists */
1226 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1227 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1228
1229 /* Tell the adapter where the TX/RX rings are located. */
1230 outl(lp->dma_rings, DE4X5_RRBA);
1231 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1232 DE4X5_TRBA);
1233
1234 /* Initialise the IRQ mask and Enable/Disable */
1235 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1236 lp->irq_en = IMR_NIM | IMR_AIM;
1237
1238 /* Create a loopback packet frame for later media probing */
1239 create_packet(dev, lp->frame, sizeof(lp->frame));
1240
1241 /* Check if the RX overflow bug needs testing for */
1242 i = lp->cfrv & 0x000000fe;
1243 if ((lp->chipset == DC21140) && (i == 0x20)) {
1244 lp->rx_ovf = 1;
1245 }
1246
1247 /* Initialise the SROM pointers if possible */
1248 if (lp->useSROM) {
1249 lp->state = INITIALISED;
1250 if (srom_infoleaf_info(dev)) {
1251 dma_free_coherent (gendev, lp->dma_size,
1252 lp->rx_ring, lp->dma_rings);
1253 return -ENXIO;
1254 }
1255 srom_init(dev);
1256 }
1257
1258 lp->state = CLOSED;
1259
1260 /*
1261 ** Check for an MII interface
1262 */
1263 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1264 mii_get_phy(dev);
1265 }
1266
1267 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1268 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1269 }
1270
1271 if (de4x5_debug & DEBUG_VERSION) {
1272 printk(version);
1273 }
1274
1275 /* The DE4X5-specific entries in the device structure. */
1276 SET_NETDEV_DEV(dev, gendev);
1277 dev->netdev_ops = &de4x5_netdev_ops;
1278 dev->mem_start = 0;
1279
1280 /* Fill in the generic fields of the device structure. */
1281 if ((status = register_netdev (dev))) {
1282 dma_free_coherent (gendev, lp->dma_size,
1283 lp->rx_ring, lp->dma_rings);
1284 return status;
1285 }
1286
1287 /* Let the adapter sleep to save power */
1288 yawn(dev, SLEEP);
1289
1290 return status;
1291 }
1292
1293
1294 static int
1295 de4x5_open(struct net_device *dev)
1296 {
1297 struct de4x5_private *lp = netdev_priv(dev);
1298 u_long iobase = dev->base_addr;
1299 int i, status = 0;
1300 s32 omr;
1301
1302 /* Allocate the RX buffers */
1303 for (i=0; i<lp->rxRingSize; i++) {
1304 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1305 de4x5_free_rx_buffs(dev);
1306 return -EAGAIN;
1307 }
1308 }
1309
1310 /*
1311 ** Wake up the adapter
1312 */
1313 yawn(dev, WAKEUP);
1314
1315 /*
1316 ** Re-initialize the DE4X5...
1317 */
1318 status = de4x5_init(dev);
1319 spin_lock_init(&lp->lock);
1320 lp->state = OPEN;
1321 de4x5_dbg_open(dev);
1322
1323 if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED,
1324 lp->adapter_name, dev)) {
1325 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1326 if (request_irq(dev->irq, de4x5_interrupt, IRQF_DISABLED | IRQF_SHARED,
1327 lp->adapter_name, dev)) {
1328 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1329 disable_ast(dev);
1330 de4x5_free_rx_buffs(dev);
1331 de4x5_free_tx_buffs(dev);
1332 yawn(dev, SLEEP);
1333 lp->state = CLOSED;
1334 return -EAGAIN;
1335 } else {
1336 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1337 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1338 }
1339 }
1340
1341 lp->interrupt = UNMASK_INTERRUPTS;
1342 dev->trans_start = jiffies; /* prevent tx timeout */
1343
1344 START_DE4X5;
1345
1346 de4x5_setup_intr(dev);
1347
1348 if (de4x5_debug & DEBUG_OPEN) {
1349 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1350 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1351 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1352 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1353 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1354 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1355 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1356 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1357 }
1358
1359 return status;
1360 }
1361
1362 /*
1363 ** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1364 ** DC21140 requires using perfect filtering mode for that chip. Since I can't
1365 ** see why I'd want > 14 multicast addresses, I have changed all chips to use
1366 ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1367 ** to be data corruption problems if it is larger (UDP errors seen from a
1368 ** ttcp source).
1369 */
1370 static int
1371 de4x5_init(struct net_device *dev)
1372 {
1373 /* Lock out other processes whilst setting up the hardware */
1374 netif_stop_queue(dev);
1375
1376 de4x5_sw_reset(dev);
1377
1378 /* Autoconfigure the connected port */
1379 autoconf_media(dev);
1380
1381 return 0;
1382 }
1383
1384 static int
1385 de4x5_sw_reset(struct net_device *dev)
1386 {
1387 struct de4x5_private *lp = netdev_priv(dev);
1388 u_long iobase = dev->base_addr;
1389 int i, j, status = 0;
1390 s32 bmr, omr;
1391
1392 /* Select the MII or SRL port now and RESET the MAC */
1393 if (!lp->useSROM) {
1394 if (lp->phy[lp->active].id != 0) {
1395 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1396 } else {
1397 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1398 }
1399 de4x5_switch_mac_port(dev);
1400 }
1401
1402 /*
1403 ** Set the programmable burst length to 8 longwords for all the DC21140
1404 ** Fasternet chips and 4 longwords for all others: DMA errors result
1405 ** without these values. Cache align 16 long.
1406 */
1407 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1408 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1409 outl(bmr, DE4X5_BMR);
1410
1411 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1412 if (lp->chipset == DC21140) {
1413 omr |= (OMR_SDP | OMR_SB);
1414 }
1415 lp->setup_f = PERFECT;
1416 outl(lp->dma_rings, DE4X5_RRBA);
1417 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1418 DE4X5_TRBA);
1419
1420 lp->rx_new = lp->rx_old = 0;
1421 lp->tx_new = lp->tx_old = 0;
1422
1423 for (i = 0; i < lp->rxRingSize; i++) {
1424 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1425 }
1426
1427 for (i = 0; i < lp->txRingSize; i++) {
1428 lp->tx_ring[i].status = cpu_to_le32(0);
1429 }
1430
1431 barrier();
1432
1433 /* Build the setup frame depending on filtering mode */
1434 SetMulticastFilter(dev);
1435
1436 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1437 outl(omr|OMR_ST, DE4X5_OMR);
1438
1439 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1440
1441 for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */
1442 mdelay(1);
1443 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1444 }
1445 outl(omr, DE4X5_OMR); /* Stop everything! */
1446
1447 if (j == 0) {
1448 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1449 inl(DE4X5_STS));
1450 status = -EIO;
1451 }
1452
1453 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1454 lp->tx_old = lp->tx_new;
1455
1456 return status;
1457 }
1458
1459 /*
1460 ** Writes a socket buffer address to the next available transmit descriptor.
1461 */
1462 static netdev_tx_t
1463 de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1464 {
1465 struct de4x5_private *lp = netdev_priv(dev);
1466 u_long iobase = dev->base_addr;
1467 u_long flags = 0;
1468
1469 netif_stop_queue(dev);
1470 if (!lp->tx_enable) /* Cannot send for now */
1471 return NETDEV_TX_LOCKED;
1472
1473 /*
1474 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1475 ** interrupts are lost by delayed descriptor status updates relative to
1476 ** the irq assertion, especially with a busy PCI bus.
1477 */
1478 spin_lock_irqsave(&lp->lock, flags);
1479 de4x5_tx(dev);
1480 spin_unlock_irqrestore(&lp->lock, flags);
1481
1482 /* Test if cache is already locked - requeue skb if so */
1483 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1484 return NETDEV_TX_LOCKED;
1485
1486 /* Transmit descriptor ring full or stale skb */
1487 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1488 if (lp->interrupt) {
1489 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1490 } else {
1491 de4x5_put_cache(dev, skb);
1492 }
1493 if (de4x5_debug & DEBUG_TX) {
1494 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1495 }
1496 } else if (skb->len > 0) {
1497 /* If we already have stuff queued locally, use that first */
1498 if (!skb_queue_empty(&lp->cache.queue) && !lp->interrupt) {
1499 de4x5_put_cache(dev, skb);
1500 skb = de4x5_get_cache(dev);
1501 }
1502
1503 while (skb && !netif_queue_stopped(dev) &&
1504 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1505 spin_lock_irqsave(&lp->lock, flags);
1506 netif_stop_queue(dev);
1507 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1508 lp->stats.tx_bytes += skb->len;
1509 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1510
1511 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1512
1513 if (TX_BUFFS_AVAIL) {
1514 netif_start_queue(dev); /* Another pkt may be queued */
1515 }
1516 skb = de4x5_get_cache(dev);
1517 spin_unlock_irqrestore(&lp->lock, flags);
1518 }
1519 if (skb) de4x5_putb_cache(dev, skb);
1520 }
1521
1522 lp->cache.lock = 0;
1523
1524 return NETDEV_TX_OK;
1525 }
1526
1527 /*
1528 ** The DE4X5 interrupt handler.
1529 **
1530 ** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1531 ** so that the asserted interrupt always has some real data to work with -
1532 ** if these I/O accesses are ever changed to memory accesses, ensure the
1533 ** STS write is read immediately to complete the transaction if the adapter
1534 ** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1535 ** is high and descriptor status bits cannot be set before the associated
1536 ** interrupt is asserted and this routine entered.
1537 */
1538 static irqreturn_t
1539 de4x5_interrupt(int irq, void *dev_id)
1540 {
1541 struct net_device *dev = dev_id;
1542 struct de4x5_private *lp;
1543 s32 imr, omr, sts, limit;
1544 u_long iobase;
1545 unsigned int handled = 0;
1546
1547 lp = netdev_priv(dev);
1548 spin_lock(&lp->lock);
1549 iobase = dev->base_addr;
1550
1551 DISABLE_IRQs; /* Ensure non re-entrancy */
1552
1553 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1554 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1555
1556 synchronize_irq(dev->irq);
1557
1558 for (limit=0; limit<8; limit++) {
1559 sts = inl(DE4X5_STS); /* Read IRQ status */
1560 outl(sts, DE4X5_STS); /* Reset the board interrupts */
1561
1562 if (!(sts & lp->irq_mask)) break;/* All done */
1563 handled = 1;
1564
1565 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1566 de4x5_rx(dev);
1567
1568 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1569 de4x5_tx(dev);
1570
1571 if (sts & STS_LNF) { /* TP Link has failed */
1572 lp->irq_mask &= ~IMR_LFM;
1573 }
1574
1575 if (sts & STS_UNF) { /* Transmit underrun */
1576 de4x5_txur(dev);
1577 }
1578
1579 if (sts & STS_SE) { /* Bus Error */
1580 STOP_DE4X5;
1581 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1582 dev->name, sts);
1583 spin_unlock(&lp->lock);
1584 return IRQ_HANDLED;
1585 }
1586 }
1587
1588 /* Load the TX ring with any locally stored packets */
1589 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1590 while (!skb_queue_empty(&lp->cache.queue) && !netif_queue_stopped(dev) && lp->tx_enable) {
1591 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1592 }
1593 lp->cache.lock = 0;
1594 }
1595
1596 lp->interrupt = UNMASK_INTERRUPTS;
1597 ENABLE_IRQs;
1598 spin_unlock(&lp->lock);
1599
1600 return IRQ_RETVAL(handled);
1601 }
1602
1603 static int
1604 de4x5_rx(struct net_device *dev)
1605 {
1606 struct de4x5_private *lp = netdev_priv(dev);
1607 u_long iobase = dev->base_addr;
1608 int entry;
1609 s32 status;
1610
1611 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1612 entry=lp->rx_new) {
1613 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1614
1615 if (lp->rx_ovf) {
1616 if (inl(DE4X5_MFC) & MFC_FOCM) {
1617 de4x5_rx_ovfc(dev);
1618 break;
1619 }
1620 }
1621
1622 if (status & RD_FS) { /* Remember the start of frame */
1623 lp->rx_old = entry;
1624 }
1625
1626 if (status & RD_LS) { /* Valid frame status */
1627 if (lp->tx_enable) lp->linkOK++;
1628 if (status & RD_ES) { /* There was an error. */
1629 lp->stats.rx_errors++; /* Update the error stats. */
1630 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1631 if (status & RD_CE) lp->stats.rx_crc_errors++;
1632 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1633 if (status & RD_TL) lp->stats.rx_length_errors++;
1634 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1635 if (status & RD_CS) lp->pktStats.rx_collision++;
1636 if (status & RD_DB) lp->pktStats.rx_dribble++;
1637 if (status & RD_OF) lp->pktStats.rx_overflow++;
1638 } else { /* A valid frame received */
1639 struct sk_buff *skb;
1640 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1641 >> 16) - 4;
1642
1643 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1644 printk("%s: Insufficient memory; nuking packet.\n",
1645 dev->name);
1646 lp->stats.rx_dropped++;
1647 } else {
1648 de4x5_dbg_rx(skb, pkt_len);
1649
1650 /* Push up the protocol stack */
1651 skb->protocol=eth_type_trans(skb,dev);
1652 de4x5_local_stats(dev, skb->data, pkt_len);
1653 netif_rx(skb);
1654
1655 /* Update stats */
1656 lp->stats.rx_packets++;
1657 lp->stats.rx_bytes += pkt_len;
1658 }
1659 }
1660
1661 /* Change buffer ownership for this frame, back to the adapter */
1662 for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1663 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1664 barrier();
1665 }
1666 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1667 barrier();
1668 }
1669
1670 /*
1671 ** Update entry information
1672 */
1673 lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1674 }
1675
1676 return 0;
1677 }
1678
1679 static inline void
1680 de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1681 {
1682 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1683 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1684 DMA_TO_DEVICE);
1685 if ((u_long) lp->tx_skb[entry] > 1)
1686 dev_kfree_skb_irq(lp->tx_skb[entry]);
1687 lp->tx_skb[entry] = NULL;
1688 }
1689
1690 /*
1691 ** Buffer sent - check for TX buffer errors.
1692 */
1693 static int
1694 de4x5_tx(struct net_device *dev)
1695 {
1696 struct de4x5_private *lp = netdev_priv(dev);
1697 u_long iobase = dev->base_addr;
1698 int entry;
1699 s32 status;
1700
1701 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1702 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1703 if (status < 0) { /* Buffer not sent yet */
1704 break;
1705 } else if (status != 0x7fffffff) { /* Not setup frame */
1706 if (status & TD_ES) { /* An error happened */
1707 lp->stats.tx_errors++;
1708 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1709 if (status & TD_LC) lp->stats.tx_window_errors++;
1710 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1711 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1712 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1713
1714 if (TX_PKT_PENDING) {
1715 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1716 }
1717 } else { /* Packet sent */
1718 lp->stats.tx_packets++;
1719 if (lp->tx_enable) lp->linkOK++;
1720 }
1721 /* Update the collision counter */
1722 lp->stats.collisions += ((status & TD_EC) ? 16 :
1723 ((status & TD_CC) >> 3));
1724
1725 /* Free the buffer. */
1726 if (lp->tx_skb[entry] != NULL)
1727 de4x5_free_tx_buff(lp, entry);
1728 }
1729
1730 /* Update all the pointers */
1731 lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1732 }
1733
1734 /* Any resources available? */
1735 if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1736 if (lp->interrupt)
1737 netif_wake_queue(dev);
1738 else
1739 netif_start_queue(dev);
1740 }
1741
1742 return 0;
1743 }
1744
1745 static void
1746 de4x5_ast(struct net_device *dev)
1747 {
1748 struct de4x5_private *lp = netdev_priv(dev);
1749 int next_tick = DE4X5_AUTOSENSE_MS;
1750 int dt;
1751
1752 if (lp->useSROM)
1753 next_tick = srom_autoconf(dev);
1754 else if (lp->chipset == DC21140)
1755 next_tick = dc21140m_autoconf(dev);
1756 else if (lp->chipset == DC21041)
1757 next_tick = dc21041_autoconf(dev);
1758 else if (lp->chipset == DC21040)
1759 next_tick = dc21040_autoconf(dev);
1760 lp->linkOK = 0;
1761
1762 dt = (next_tick * HZ) / 1000;
1763
1764 if (!dt)
1765 dt = 1;
1766
1767 mod_timer(&lp->timer, jiffies + dt);
1768 }
1769
1770 static int
1771 de4x5_txur(struct net_device *dev)
1772 {
1773 struct de4x5_private *lp = netdev_priv(dev);
1774 u_long iobase = dev->base_addr;
1775 int omr;
1776
1777 omr = inl(DE4X5_OMR);
1778 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1779 omr &= ~(OMR_ST|OMR_SR);
1780 outl(omr, DE4X5_OMR);
1781 while (inl(DE4X5_STS) & STS_TS);
1782 if ((omr & OMR_TR) < OMR_TR) {
1783 omr += 0x4000;
1784 } else {
1785 omr |= OMR_SF;
1786 }
1787 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1788 }
1789
1790 return 0;
1791 }
1792
1793 static int
1794 de4x5_rx_ovfc(struct net_device *dev)
1795 {
1796 struct de4x5_private *lp = netdev_priv(dev);
1797 u_long iobase = dev->base_addr;
1798 int omr;
1799
1800 omr = inl(DE4X5_OMR);
1801 outl(omr & ~OMR_SR, DE4X5_OMR);
1802 while (inl(DE4X5_STS) & STS_RS);
1803
1804 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1805 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1806 lp->rx_new = (++lp->rx_new % lp->rxRingSize);
1807 }
1808
1809 outl(omr, DE4X5_OMR);
1810
1811 return 0;
1812 }
1813
1814 static int
1815 de4x5_close(struct net_device *dev)
1816 {
1817 struct de4x5_private *lp = netdev_priv(dev);
1818 u_long iobase = dev->base_addr;
1819 s32 imr, omr;
1820
1821 disable_ast(dev);
1822
1823 netif_stop_queue(dev);
1824
1825 if (de4x5_debug & DEBUG_CLOSE) {
1826 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1827 dev->name, inl(DE4X5_STS));
1828 }
1829
1830 /*
1831 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1832 */
1833 DISABLE_IRQs;
1834 STOP_DE4X5;
1835
1836 /* Free the associated irq */
1837 free_irq(dev->irq, dev);
1838 lp->state = CLOSED;
1839
1840 /* Free any socket buffers */
1841 de4x5_free_rx_buffs(dev);
1842 de4x5_free_tx_buffs(dev);
1843
1844 /* Put the adapter to sleep to save power */
1845 yawn(dev, SLEEP);
1846
1847 return 0;
1848 }
1849
1850 static struct net_device_stats *
1851 de4x5_get_stats(struct net_device *dev)
1852 {
1853 struct de4x5_private *lp = netdev_priv(dev);
1854 u_long iobase = dev->base_addr;
1855
1856 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1857
1858 return &lp->stats;
1859 }
1860
1861 static void
1862 de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1863 {
1864 struct de4x5_private *lp = netdev_priv(dev);
1865 int i;
1866
1867 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1868 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1869 lp->pktStats.bins[i]++;
1870 i = DE4X5_PKT_STAT_SZ;
1871 }
1872 }
1873 if (buf[0] & 0x01) { /* Multicast/Broadcast */
1874 if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1875 lp->pktStats.broadcast++;
1876 } else {
1877 lp->pktStats.multicast++;
1878 }
1879 } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1880 (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1881 lp->pktStats.unicast++;
1882 }
1883
1884 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1885 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1886 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1887 }
1888 }
1889
1890 /*
1891 ** Removes the TD_IC flag from previous descriptor to improve TX performance.
1892 ** If the flag is changed on a descriptor that is being read by the hardware,
1893 ** I assume PCI transaction ordering will mean you are either successful or
1894 ** just miss asserting the change to the hardware. Anyway you're messing with
1895 ** a descriptor you don't own, but this shouldn't kill the chip provided
1896 ** the descriptor register is read only to the hardware.
1897 */
1898 static void
1899 load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1900 {
1901 struct de4x5_private *lp = netdev_priv(dev);
1902 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1903 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1904
1905 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1906 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1907 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1908 lp->tx_skb[lp->tx_new] = skb;
1909 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1910 barrier();
1911
1912 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1913 barrier();
1914 }
1915
1916 /*
1917 ** Set or clear the multicast filter for this adaptor.
1918 */
1919 static void
1920 set_multicast_list(struct net_device *dev)
1921 {
1922 struct de4x5_private *lp = netdev_priv(dev);
1923 u_long iobase = dev->base_addr;
1924
1925 /* First, double check that the adapter is open */
1926 if (lp->state == OPEN) {
1927 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1928 u32 omr;
1929 omr = inl(DE4X5_OMR);
1930 omr |= OMR_PR;
1931 outl(omr, DE4X5_OMR);
1932 } else {
1933 SetMulticastFilter(dev);
1934 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1935 SETUP_FRAME_LEN, (struct sk_buff *)1);
1936
1937 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1938 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1939 dev->trans_start = jiffies; /* prevent tx timeout */
1940 }
1941 }
1942 }
1943
1944 /*
1945 ** Calculate the hash code and update the logical address filter
1946 ** from a list of ethernet multicast addresses.
1947 ** Little endian crc one liner from Matt Thomas, DEC.
1948 */
1949 static void
1950 SetMulticastFilter(struct net_device *dev)
1951 {
1952 struct de4x5_private *lp = netdev_priv(dev);
1953 struct netdev_hw_addr *ha;
1954 u_long iobase = dev->base_addr;
1955 int i, bit, byte;
1956 u16 hashcode;
1957 u32 omr, crc;
1958 char *pa;
1959 unsigned char *addrs;
1960
1961 omr = inl(DE4X5_OMR);
1962 omr &= ~(OMR_PR | OMR_PM);
1963 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
1964
1965 if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 14)) {
1966 omr |= OMR_PM; /* Pass all multicasts */
1967 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
1968 netdev_for_each_mc_addr(ha, dev) {
1969 addrs = ha->addr;
1970 if ((*addrs & 0x01) == 1) { /* multicast address? */
1971 crc = ether_crc_le(ETH_ALEN, addrs);
1972 hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
1973
1974 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
1975 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
1976
1977 byte <<= 1; /* calc offset into setup frame */
1978 if (byte & 0x02) {
1979 byte -= 1;
1980 }
1981 lp->setup_frame[byte] |= bit;
1982 }
1983 }
1984 } else { /* Perfect filtering */
1985 netdev_for_each_mc_addr(ha, dev) {
1986 addrs = ha->addr;
1987 for (i=0; i<ETH_ALEN; i++) {
1988 *(pa + (i&1)) = *addrs++;
1989 if (i & 0x01) pa += 4;
1990 }
1991 }
1992 }
1993 outl(omr, DE4X5_OMR);
1994 }
1995
1996 #ifdef CONFIG_EISA
1997
1998 static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
1999
2000 static int __init de4x5_eisa_probe (struct device *gendev)
2001 {
2002 struct eisa_device *edev;
2003 u_long iobase;
2004 u_char irq, regval;
2005 u_short vendor;
2006 u32 cfid;
2007 int status, device;
2008 struct net_device *dev;
2009 struct de4x5_private *lp;
2010
2011 edev = to_eisa_device (gendev);
2012 iobase = edev->base_addr;
2013
2014 if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5"))
2015 return -EBUSY;
2016
2017 if (!request_region (iobase + DE4X5_EISA_IO_PORTS,
2018 DE4X5_EISA_TOTAL_SIZE, "de4x5")) {
2019 status = -EBUSY;
2020 goto release_reg_1;
2021 }
2022
2023 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2024 status = -ENOMEM;
2025 goto release_reg_2;
2026 }
2027 lp = netdev_priv(dev);
2028
2029 cfid = (u32) inl(PCI_CFID);
2030 lp->cfrv = (u_short) inl(PCI_CFRV);
2031 device = (cfid >> 8) & 0x00ffff00;
2032 vendor = (u_short) cfid;
2033
2034 /* Read the EISA Configuration Registers */
2035 regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT);
2036 #ifdef CONFIG_ALPHA
2037 /* Looks like the Jensen firmware (rev 2.2) doesn't really
2038 * care about the EISA configuration, and thus doesn't
2039 * configure the PLX bridge properly. Oh well... Simply mimic
2040 * the EISA config file to sort it out. */
2041
2042 /* EISA REG1: Assert DecChip 21040 HW Reset */
2043 outb (ER1_IAM | 1, EISA_REG1);
2044 mdelay (1);
2045
2046 /* EISA REG1: Deassert DecChip 21040 HW Reset */
2047 outb (ER1_IAM, EISA_REG1);
2048 mdelay (1);
2049
2050 /* EISA REG3: R/W Burst Transfer Enable */
2051 outb (ER3_BWE | ER3_BRE, EISA_REG3);
2052
2053 /* 32_bit slave/master, Preempt Time=23 bclks, Unlatched Interrupt */
2054 outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0);
2055 #endif
2056 irq = de4x5_irq[(regval >> 1) & 0x03];
2057
2058 if (is_DC2114x) {
2059 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2060 }
2061 lp->chipset = device;
2062 lp->bus = EISA;
2063
2064 /* Write the PCI Configuration Registers */
2065 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2066 outl(0x00006000, PCI_CFLT);
2067 outl(iobase, PCI_CBIO);
2068
2069 DevicePresent(dev, EISA_APROM);
2070
2071 dev->irq = irq;
2072
2073 if (!(status = de4x5_hw_init (dev, iobase, gendev))) {
2074 return 0;
2075 }
2076
2077 free_netdev (dev);
2078 release_reg_2:
2079 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2080 release_reg_1:
2081 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2082
2083 return status;
2084 }
2085
2086 static int __devexit de4x5_eisa_remove (struct device *device)
2087 {
2088 struct net_device *dev;
2089 u_long iobase;
2090
2091 dev = dev_get_drvdata(device);
2092 iobase = dev->base_addr;
2093
2094 unregister_netdev (dev);
2095 free_netdev (dev);
2096 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2097 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2098
2099 return 0;
2100 }
2101
2102 static struct eisa_device_id de4x5_eisa_ids[] = {
2103 { "DEC4250", 0 }, /* 0 is the board name index... */
2104 { "" }
2105 };
2106 MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2107
2108 static struct eisa_driver de4x5_eisa_driver = {
2109 .id_table = de4x5_eisa_ids,
2110 .driver = {
2111 .name = "de4x5",
2112 .probe = de4x5_eisa_probe,
2113 .remove = __devexit_p (de4x5_eisa_remove),
2114 }
2115 };
2116 MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2117 #endif
2118
2119 #ifdef CONFIG_PCI
2120
2121 /*
2122 ** This function searches the current bus (which is >0) for a DECchip with an
2123 ** SROM, so that in multiport cards that have one SROM shared between multiple
2124 ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2125 ** For single port cards this is a time waster...
2126 */
2127 static void __devinit
2128 srom_search(struct net_device *dev, struct pci_dev *pdev)
2129 {
2130 u_char pb;
2131 u_short vendor, status;
2132 u_int irq = 0, device;
2133 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2134 int i, j;
2135 struct de4x5_private *lp = netdev_priv(dev);
2136 struct list_head *walk;
2137
2138 list_for_each(walk, &pdev->bus_list) {
2139 struct pci_dev *this_dev = pci_dev_b(walk);
2140
2141 /* Skip the pci_bus list entry */
2142 if (list_entry(walk, struct pci_bus, devices) == pdev->bus) continue;
2143
2144 vendor = this_dev->vendor;
2145 device = this_dev->device << 8;
2146 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2147
2148 /* Get the chip configuration revision register */
2149 pb = this_dev->bus->number;
2150
2151 /* Set the device number information */
2152 lp->device = PCI_SLOT(this_dev->devfn);
2153 lp->bus_num = pb;
2154
2155 /* Set the chipset information */
2156 if (is_DC2114x) {
2157 device = ((this_dev->revision & CFRV_RN) < DC2114x_BRK
2158 ? DC21142 : DC21143);
2159 }
2160 lp->chipset = device;
2161
2162 /* Get the board I/O address (64 bits on sparc64) */
2163 iobase = pci_resource_start(this_dev, 0);
2164
2165 /* Fetch the IRQ to be used */
2166 irq = this_dev->irq;
2167 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2168
2169 /* Check if I/O accesses are enabled */
2170 pci_read_config_word(this_dev, PCI_COMMAND, &status);
2171 if (!(status & PCI_COMMAND_IO)) continue;
2172
2173 /* Search for a valid SROM attached to this DECchip */
2174 DevicePresent(dev, DE4X5_APROM);
2175 for (j=0, i=0; i<ETH_ALEN; i++) {
2176 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2177 }
2178 if (j != 0 && j != 6 * 0xff) {
2179 last.chipset = device;
2180 last.bus = pb;
2181 last.irq = irq;
2182 for (i=0; i<ETH_ALEN; i++) {
2183 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2184 }
2185 return;
2186 }
2187 }
2188 }
2189
2190 /*
2191 ** PCI bus I/O device probe
2192 ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2193 ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2194 ** enabled by the user first in the set up utility. Hence we just check for
2195 ** enabled features and silently ignore the card if they're not.
2196 **
2197 ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2198 ** bit. Here, check for I/O accesses and then set BM. If you put the card in
2199 ** a non BM slot, you're on your own (and complain to the PC vendor that your
2200 ** PC doesn't conform to the PCI standard)!
2201 **
2202 ** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2203 ** kernels use the V0.535[n] drivers.
2204 */
2205
2206 static int __devinit de4x5_pci_probe (struct pci_dev *pdev,
2207 const struct pci_device_id *ent)
2208 {
2209 u_char pb, pbus = 0, dev_num, dnum = 0, timer;
2210 u_short vendor, status;
2211 u_int irq = 0, device;
2212 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2213 int error;
2214 struct net_device *dev;
2215 struct de4x5_private *lp;
2216
2217 dev_num = PCI_SLOT(pdev->devfn);
2218 pb = pdev->bus->number;
2219
2220 if (io) { /* probe a single PCI device */
2221 pbus = (u_short)(io >> 8);
2222 dnum = (u_short)(io & 0xff);
2223 if ((pbus != pb) || (dnum != dev_num))
2224 return -ENODEV;
2225 }
2226
2227 vendor = pdev->vendor;
2228 device = pdev->device << 8;
2229 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x))
2230 return -ENODEV;
2231
2232 /* Ok, the device seems to be for us. */
2233 if ((error = pci_enable_device (pdev)))
2234 return error;
2235
2236 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2237 error = -ENOMEM;
2238 goto disable_dev;
2239 }
2240
2241 lp = netdev_priv(dev);
2242 lp->bus = PCI;
2243 lp->bus_num = 0;
2244
2245 /* Search for an SROM on this bus */
2246 if (lp->bus_num != pb) {
2247 lp->bus_num = pb;
2248 srom_search(dev, pdev);
2249 }
2250
2251 /* Get the chip configuration revision register */
2252 lp->cfrv = pdev->revision;
2253
2254 /* Set the device number information */
2255 lp->device = dev_num;
2256 lp->bus_num = pb;
2257
2258 /* Set the chipset information */
2259 if (is_DC2114x) {
2260 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2261 }
2262 lp->chipset = device;
2263
2264 /* Get the board I/O address (64 bits on sparc64) */
2265 iobase = pci_resource_start(pdev, 0);
2266
2267 /* Fetch the IRQ to be used */
2268 irq = pdev->irq;
2269 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) {
2270 error = -ENODEV;
2271 goto free_dev;
2272 }
2273
2274 /* Check if I/O accesses and Bus Mastering are enabled */
2275 pci_read_config_word(pdev, PCI_COMMAND, &status);
2276 #ifdef __powerpc__
2277 if (!(status & PCI_COMMAND_IO)) {
2278 status |= PCI_COMMAND_IO;
2279 pci_write_config_word(pdev, PCI_COMMAND, status);
2280 pci_read_config_word(pdev, PCI_COMMAND, &status);
2281 }
2282 #endif /* __powerpc__ */
2283 if (!(status & PCI_COMMAND_IO)) {
2284 error = -ENODEV;
2285 goto free_dev;
2286 }
2287
2288 if (!(status & PCI_COMMAND_MASTER)) {
2289 status |= PCI_COMMAND_MASTER;
2290 pci_write_config_word(pdev, PCI_COMMAND, status);
2291 pci_read_config_word(pdev, PCI_COMMAND, &status);
2292 }
2293 if (!(status & PCI_COMMAND_MASTER)) {
2294 error = -ENODEV;
2295 goto free_dev;
2296 }
2297
2298 /* Check the latency timer for values >= 0x60 */
2299 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer);
2300 if (timer < 0x60) {
2301 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60);
2302 }
2303
2304 DevicePresent(dev, DE4X5_APROM);
2305
2306 if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) {
2307 error = -EBUSY;
2308 goto free_dev;
2309 }
2310
2311 dev->irq = irq;
2312
2313 if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) {
2314 goto release;
2315 }
2316
2317 return 0;
2318
2319 release:
2320 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2321 free_dev:
2322 free_netdev (dev);
2323 disable_dev:
2324 pci_disable_device (pdev);
2325 return error;
2326 }
2327
2328 static void __devexit de4x5_pci_remove (struct pci_dev *pdev)
2329 {
2330 struct net_device *dev;
2331 u_long iobase;
2332
2333 dev = dev_get_drvdata(&pdev->dev);
2334 iobase = dev->base_addr;
2335
2336 unregister_netdev (dev);
2337 free_netdev (dev);
2338 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2339 pci_disable_device (pdev);
2340 }
2341
2342 static struct pci_device_id de4x5_pci_tbl[] = {
2343 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
2344 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
2345 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
2346 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
2347 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
2348 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
2349 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
2350 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
2351 { },
2352 };
2353
2354 static struct pci_driver de4x5_pci_driver = {
2355 .name = "de4x5",
2356 .id_table = de4x5_pci_tbl,
2357 .probe = de4x5_pci_probe,
2358 .remove = __devexit_p (de4x5_pci_remove),
2359 };
2360
2361 #endif
2362
2363 /*
2364 ** Auto configure the media here rather than setting the port at compile
2365 ** time. This routine is called by de4x5_init() and when a loss of media is
2366 ** detected (excessive collisions, loss of carrier, no carrier or link fail
2367 ** [TP] or no recent receive activity) to check whether the user has been
2368 ** sneaky and changed the port on us.
2369 */
2370 static int
2371 autoconf_media(struct net_device *dev)
2372 {
2373 struct de4x5_private *lp = netdev_priv(dev);
2374 u_long iobase = dev->base_addr;
2375
2376 disable_ast(dev);
2377
2378 lp->c_media = AUTO; /* Bogus last media */
2379 inl(DE4X5_MFC); /* Zero the lost frames counter */
2380 lp->media = INIT;
2381 lp->tcount = 0;
2382
2383 de4x5_ast(dev);
2384
2385 return lp->media;
2386 }
2387
2388 /*
2389 ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2390 ** from BNC as the port has a jumper to set thick or thin wire. When set for
2391 ** BNC, the BNC port will indicate activity if it's not terminated correctly.
2392 ** The only way to test for that is to place a loopback packet onto the
2393 ** network and watch for errors. Since we're messing with the interrupt mask
2394 ** register, disable the board interrupts and do not allow any more packets to
2395 ** be queued to the hardware. Re-enable everything only when the media is
2396 ** found.
2397 ** I may have to "age out" locally queued packets so that the higher layer
2398 ** timeouts don't effectively duplicate packets on the network.
2399 */
2400 static int
2401 dc21040_autoconf(struct net_device *dev)
2402 {
2403 struct de4x5_private *lp = netdev_priv(dev);
2404 u_long iobase = dev->base_addr;
2405 int next_tick = DE4X5_AUTOSENSE_MS;
2406 s32 imr;
2407
2408 switch (lp->media) {
2409 case INIT:
2410 DISABLE_IRQs;
2411 lp->tx_enable = false;
2412 lp->timeout = -1;
2413 de4x5_save_skbs(dev);
2414 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2415 lp->media = TP;
2416 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2417 lp->media = BNC_AUI;
2418 } else if (lp->autosense == EXT_SIA) {
2419 lp->media = EXT_SIA;
2420 } else {
2421 lp->media = NC;
2422 }
2423 lp->local_state = 0;
2424 next_tick = dc21040_autoconf(dev);
2425 break;
2426
2427 case TP:
2428 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2429 TP_SUSPECT, test_tp);
2430 break;
2431
2432 case TP_SUSPECT:
2433 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2434 break;
2435
2436 case BNC:
2437 case AUI:
2438 case BNC_AUI:
2439 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2440 BNC_AUI_SUSPECT, ping_media);
2441 break;
2442
2443 case BNC_AUI_SUSPECT:
2444 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2445 break;
2446
2447 case EXT_SIA:
2448 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2449 NC, EXT_SIA_SUSPECT, ping_media);
2450 break;
2451
2452 case EXT_SIA_SUSPECT:
2453 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2454 break;
2455
2456 case NC:
2457 /* default to TP for all */
2458 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2459 if (lp->media != lp->c_media) {
2460 de4x5_dbg_media(dev);
2461 lp->c_media = lp->media;
2462 }
2463 lp->media = INIT;
2464 lp->tx_enable = false;
2465 break;
2466 }
2467
2468 return next_tick;
2469 }
2470
2471 static int
2472 dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2473 int next_state, int suspect_state,
2474 int (*fn)(struct net_device *, int))
2475 {
2476 struct de4x5_private *lp = netdev_priv(dev);
2477 int next_tick = DE4X5_AUTOSENSE_MS;
2478 int linkBad;
2479
2480 switch (lp->local_state) {
2481 case 0:
2482 reset_init_sia(dev, csr13, csr14, csr15);
2483 lp->local_state++;
2484 next_tick = 500;
2485 break;
2486
2487 case 1:
2488 if (!lp->tx_enable) {
2489 linkBad = fn(dev, timeout);
2490 if (linkBad < 0) {
2491 next_tick = linkBad & ~TIMER_CB;
2492 } else {
2493 if (linkBad && (lp->autosense == AUTO)) {
2494 lp->local_state = 0;
2495 lp->media = next_state;
2496 } else {
2497 de4x5_init_connection(dev);
2498 }
2499 }
2500 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2501 lp->media = suspect_state;
2502 next_tick = 3000;
2503 }
2504 break;
2505 }
2506
2507 return next_tick;
2508 }
2509
2510 static int
2511 de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2512 int (*fn)(struct net_device *, int),
2513 int (*asfn)(struct net_device *))
2514 {
2515 struct de4x5_private *lp = netdev_priv(dev);
2516 int next_tick = DE4X5_AUTOSENSE_MS;
2517 int linkBad;
2518
2519 switch (lp->local_state) {
2520 case 1:
2521 if (lp->linkOK) {
2522 lp->media = prev_state;
2523 } else {
2524 lp->local_state++;
2525 next_tick = asfn(dev);
2526 }
2527 break;
2528
2529 case 2:
2530 linkBad = fn(dev, timeout);
2531 if (linkBad < 0) {
2532 next_tick = linkBad & ~TIMER_CB;
2533 } else if (!linkBad) {
2534 lp->local_state--;
2535 lp->media = prev_state;
2536 } else {
2537 lp->media = INIT;
2538 lp->tcount++;
2539 }
2540 }
2541
2542 return next_tick;
2543 }
2544
2545 /*
2546 ** Autoconfigure the media when using the DC21041. AUI needs to be tested
2547 ** before BNC, because the BNC port will indicate activity if it's not
2548 ** terminated correctly. The only way to test for that is to place a loopback
2549 ** packet onto the network and watch for errors. Since we're messing with
2550 ** the interrupt mask register, disable the board interrupts and do not allow
2551 ** any more packets to be queued to the hardware. Re-enable everything only
2552 ** when the media is found.
2553 */
2554 static int
2555 dc21041_autoconf(struct net_device *dev)
2556 {
2557 struct de4x5_private *lp = netdev_priv(dev);
2558 u_long iobase = dev->base_addr;
2559 s32 sts, irqs, irq_mask, imr, omr;
2560 int next_tick = DE4X5_AUTOSENSE_MS;
2561
2562 switch (lp->media) {
2563 case INIT:
2564 DISABLE_IRQs;
2565 lp->tx_enable = false;
2566 lp->timeout = -1;
2567 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2568 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2569 lp->media = TP; /* On chip auto negotiation is broken */
2570 } else if (lp->autosense == TP) {
2571 lp->media = TP;
2572 } else if (lp->autosense == BNC) {
2573 lp->media = BNC;
2574 } else if (lp->autosense == AUI) {
2575 lp->media = AUI;
2576 } else {
2577 lp->media = NC;
2578 }
2579 lp->local_state = 0;
2580 next_tick = dc21041_autoconf(dev);
2581 break;
2582
2583 case TP_NW:
2584 if (lp->timeout < 0) {
2585 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2586 outl(omr | OMR_FDX, DE4X5_OMR);
2587 }
2588 irqs = STS_LNF | STS_LNP;
2589 irq_mask = IMR_LFM | IMR_LPM;
2590 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2591 if (sts < 0) {
2592 next_tick = sts & ~TIMER_CB;
2593 } else {
2594 if (sts & STS_LNP) {
2595 lp->media = ANS;
2596 } else {
2597 lp->media = AUI;
2598 }
2599 next_tick = dc21041_autoconf(dev);
2600 }
2601 break;
2602
2603 case ANS:
2604 if (!lp->tx_enable) {
2605 irqs = STS_LNP;
2606 irq_mask = IMR_LPM;
2607 sts = test_ans(dev, irqs, irq_mask, 3000);
2608 if (sts < 0) {
2609 next_tick = sts & ~TIMER_CB;
2610 } else {
2611 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2612 lp->media = TP;
2613 next_tick = dc21041_autoconf(dev);
2614 } else {
2615 lp->local_state = 1;
2616 de4x5_init_connection(dev);
2617 }
2618 }
2619 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2620 lp->media = ANS_SUSPECT;
2621 next_tick = 3000;
2622 }
2623 break;
2624
2625 case ANS_SUSPECT:
2626 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2627 break;
2628
2629 case TP:
2630 if (!lp->tx_enable) {
2631 if (lp->timeout < 0) {
2632 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2633 outl(omr & ~OMR_FDX, DE4X5_OMR);
2634 }
2635 irqs = STS_LNF | STS_LNP;
2636 irq_mask = IMR_LFM | IMR_LPM;
2637 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2638 if (sts < 0) {
2639 next_tick = sts & ~TIMER_CB;
2640 } else {
2641 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2642 if (inl(DE4X5_SISR) & SISR_NRA) {
2643 lp->media = AUI; /* Non selected port activity */
2644 } else {
2645 lp->media = BNC;
2646 }
2647 next_tick = dc21041_autoconf(dev);
2648 } else {
2649 lp->local_state = 1;
2650 de4x5_init_connection(dev);
2651 }
2652 }
2653 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2654 lp->media = TP_SUSPECT;
2655 next_tick = 3000;
2656 }
2657 break;
2658
2659 case TP_SUSPECT:
2660 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2661 break;
2662
2663 case AUI:
2664 if (!lp->tx_enable) {
2665 if (lp->timeout < 0) {
2666 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2667 outl(omr & ~OMR_FDX, DE4X5_OMR);
2668 }
2669 irqs = 0;
2670 irq_mask = 0;
2671 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2672 if (sts < 0) {
2673 next_tick = sts & ~TIMER_CB;
2674 } else {
2675 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2676 lp->media = BNC;
2677 next_tick = dc21041_autoconf(dev);
2678 } else {
2679 lp->local_state = 1;
2680 de4x5_init_connection(dev);
2681 }
2682 }
2683 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2684 lp->media = AUI_SUSPECT;
2685 next_tick = 3000;
2686 }
2687 break;
2688
2689 case AUI_SUSPECT:
2690 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2691 break;
2692
2693 case BNC:
2694 switch (lp->local_state) {
2695 case 0:
2696 if (lp->timeout < 0) {
2697 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2698 outl(omr & ~OMR_FDX, DE4X5_OMR);
2699 }
2700 irqs = 0;
2701 irq_mask = 0;
2702 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2703 if (sts < 0) {
2704 next_tick = sts & ~TIMER_CB;
2705 } else {
2706 lp->local_state++; /* Ensure media connected */
2707 next_tick = dc21041_autoconf(dev);
2708 }
2709 break;
2710
2711 case 1:
2712 if (!lp->tx_enable) {
2713 if ((sts = ping_media(dev, 3000)) < 0) {
2714 next_tick = sts & ~TIMER_CB;
2715 } else {
2716 if (sts) {
2717 lp->local_state = 0;
2718 lp->media = NC;
2719 } else {
2720 de4x5_init_connection(dev);
2721 }
2722 }
2723 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2724 lp->media = BNC_SUSPECT;
2725 next_tick = 3000;
2726 }
2727 break;
2728 }
2729 break;
2730
2731 case BNC_SUSPECT:
2732 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2733 break;
2734
2735 case NC:
2736 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2737 outl(omr | OMR_FDX, DE4X5_OMR);
2738 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2739 if (lp->media != lp->c_media) {
2740 de4x5_dbg_media(dev);
2741 lp->c_media = lp->media;
2742 }
2743 lp->media = INIT;
2744 lp->tx_enable = false;
2745 break;
2746 }
2747
2748 return next_tick;
2749 }
2750
2751 /*
2752 ** Some autonegotiation chips are broken in that they do not return the
2753 ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2754 ** register, except at the first power up negotiation.
2755 */
2756 static int
2757 dc21140m_autoconf(struct net_device *dev)
2758 {
2759 struct de4x5_private *lp = netdev_priv(dev);
2760 int ana, anlpa, cap, cr, slnk, sr;
2761 int next_tick = DE4X5_AUTOSENSE_MS;
2762 u_long imr, omr, iobase = dev->base_addr;
2763
2764 switch(lp->media) {
2765 case INIT:
2766 if (lp->timeout < 0) {
2767 DISABLE_IRQs;
2768 lp->tx_enable = false;
2769 lp->linkOK = 0;
2770 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2771 }
2772 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2773 next_tick &= ~TIMER_CB;
2774 } else {
2775 if (lp->useSROM) {
2776 if (srom_map_media(dev) < 0) {
2777 lp->tcount++;
2778 return next_tick;
2779 }
2780 srom_exec(dev, lp->phy[lp->active].gep);
2781 if (lp->infoblock_media == ANS) {
2782 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2783 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2784 }
2785 } else {
2786 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2787 SET_10Mb;
2788 if (lp->autosense == _100Mb) {
2789 lp->media = _100Mb;
2790 } else if (lp->autosense == _10Mb) {
2791 lp->media = _10Mb;
2792 } else if ((lp->autosense == AUTO) &&
2793 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2794 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2795 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2796 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2797 lp->media = ANS;
2798 } else if (lp->autosense == AUTO) {
2799 lp->media = SPD_DET;
2800 } else if (is_spd_100(dev) && is_100_up(dev)) {
2801 lp->media = _100Mb;
2802 } else {
2803 lp->media = NC;
2804 }
2805 }
2806 lp->local_state = 0;
2807 next_tick = dc21140m_autoconf(dev);
2808 }
2809 break;
2810
2811 case ANS:
2812 switch (lp->local_state) {
2813 case 0:
2814 if (lp->timeout < 0) {
2815 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2816 }
2817 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
2818 if (cr < 0) {
2819 next_tick = cr & ~TIMER_CB;
2820 } else {
2821 if (cr) {
2822 lp->local_state = 0;
2823 lp->media = SPD_DET;
2824 } else {
2825 lp->local_state++;
2826 }
2827 next_tick = dc21140m_autoconf(dev);
2828 }
2829 break;
2830
2831 case 1:
2832 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000)) < 0) {
2833 next_tick = sr & ~TIMER_CB;
2834 } else {
2835 lp->media = SPD_DET;
2836 lp->local_state = 0;
2837 if (sr) { /* Success! */
2838 lp->tmp = MII_SR_ASSC;
2839 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2840 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2841 if (!(anlpa & MII_ANLPA_RF) &&
2842 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2843 if (cap & MII_ANA_100M) {
2844 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
2845 lp->media = _100Mb;
2846 } else if (cap & MII_ANA_10M) {
2847 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
2848
2849 lp->media = _10Mb;
2850 }
2851 }
2852 } /* Auto Negotiation failed to finish */
2853 next_tick = dc21140m_autoconf(dev);
2854 } /* Auto Negotiation failed to start */
2855 break;
2856 }
2857 break;
2858
2859 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2860 if (lp->timeout < 0) {
2861 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2862 (~gep_rd(dev) & GEP_LNP));
2863 SET_100Mb_PDET;
2864 }
2865 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2866 next_tick = slnk & ~TIMER_CB;
2867 } else {
2868 if (is_spd_100(dev) && is_100_up(dev)) {
2869 lp->media = _100Mb;
2870 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2871 lp->media = _10Mb;
2872 } else {
2873 lp->media = NC;
2874 }
2875 next_tick = dc21140m_autoconf(dev);
2876 }
2877 break;
2878
2879 case _100Mb: /* Set 100Mb/s */
2880 next_tick = 3000;
2881 if (!lp->tx_enable) {
2882 SET_100Mb;
2883 de4x5_init_connection(dev);
2884 } else {
2885 if (!lp->linkOK && (lp->autosense == AUTO)) {
2886 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2887 lp->media = INIT;
2888 lp->tcount++;
2889 next_tick = DE4X5_AUTOSENSE_MS;
2890 }
2891 }
2892 }
2893 break;
2894
2895 case BNC:
2896 case AUI:
2897 case _10Mb: /* Set 10Mb/s */
2898 next_tick = 3000;
2899 if (!lp->tx_enable) {
2900 SET_10Mb;
2901 de4x5_init_connection(dev);
2902 } else {
2903 if (!lp->linkOK && (lp->autosense == AUTO)) {
2904 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2905 lp->media = INIT;
2906 lp->tcount++;
2907 next_tick = DE4X5_AUTOSENSE_MS;
2908 }
2909 }
2910 }
2911 break;
2912
2913 case NC:
2914 if (lp->media != lp->c_media) {
2915 de4x5_dbg_media(dev);
2916 lp->c_media = lp->media;
2917 }
2918 lp->media = INIT;
2919 lp->tx_enable = false;
2920 break;
2921 }
2922
2923 return next_tick;
2924 }
2925
2926 /*
2927 ** This routine may be merged into dc21140m_autoconf() sometime as I'm
2928 ** changing how I figure out the media - but trying to keep it backwards
2929 ** compatible with the de500-xa and de500-aa.
2930 ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2931 ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2932 ** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2933 ** active.
2934 ** When autonegotiation is working, the ANS part searches the SROM for
2935 ** the highest common speed (TP) link that both can run and if that can
2936 ** be full duplex. That infoblock is executed and then the link speed set.
2937 **
2938 ** Only _10Mb and _100Mb are tested here.
2939 */
2940 static int
2941 dc2114x_autoconf(struct net_device *dev)
2942 {
2943 struct de4x5_private *lp = netdev_priv(dev);
2944 u_long iobase = dev->base_addr;
2945 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2946 int next_tick = DE4X5_AUTOSENSE_MS;
2947
2948 switch (lp->media) {
2949 case INIT:
2950 if (lp->timeout < 0) {
2951 DISABLE_IRQs;
2952 lp->tx_enable = false;
2953 lp->linkOK = 0;
2954 lp->timeout = -1;
2955 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2956 if (lp->params.autosense & ~AUTO) {
2957 srom_map_media(dev); /* Fixed media requested */
2958 if (lp->media != lp->params.autosense) {
2959 lp->tcount++;
2960 lp->media = INIT;
2961 return next_tick;
2962 }
2963 lp->media = INIT;
2964 }
2965 }
2966 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2967 next_tick &= ~TIMER_CB;
2968 } else {
2969 if (lp->autosense == _100Mb) {
2970 lp->media = _100Mb;
2971 } else if (lp->autosense == _10Mb) {
2972 lp->media = _10Mb;
2973 } else if (lp->autosense == TP) {
2974 lp->media = TP;
2975 } else if (lp->autosense == BNC) {
2976 lp->media = BNC;
2977 } else if (lp->autosense == AUI) {
2978 lp->media = AUI;
2979 } else {
2980 lp->media = SPD_DET;
2981 if ((lp->infoblock_media == ANS) &&
2982 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2983 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2984 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2985 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2986 lp->media = ANS;
2987 }
2988 }
2989 lp->local_state = 0;
2990 next_tick = dc2114x_autoconf(dev);
2991 }
2992 break;
2993
2994 case ANS:
2995 switch (lp->local_state) {
2996 case 0:
2997 if (lp->timeout < 0) {
2998 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2999 }
3000 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
3001 if (cr < 0) {
3002 next_tick = cr & ~TIMER_CB;
3003 } else {
3004 if (cr) {
3005 lp->local_state = 0;
3006 lp->media = SPD_DET;
3007 } else {
3008 lp->local_state++;
3009 }
3010 next_tick = dc2114x_autoconf(dev);
3011 }
3012 break;
3013
3014 case 1:
3015 sr = test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000);
3016 if (sr < 0) {
3017 next_tick = sr & ~TIMER_CB;
3018 } else {
3019 lp->media = SPD_DET;
3020 lp->local_state = 0;
3021 if (sr) { /* Success! */
3022 lp->tmp = MII_SR_ASSC;
3023 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3024 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3025 if (!(anlpa & MII_ANLPA_RF) &&
3026 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3027 if (cap & MII_ANA_100M) {
3028 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
3029 lp->media = _100Mb;
3030 } else if (cap & MII_ANA_10M) {
3031 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
3032 lp->media = _10Mb;
3033 }
3034 }
3035 } /* Auto Negotiation failed to finish */
3036 next_tick = dc2114x_autoconf(dev);
3037 } /* Auto Negotiation failed to start */
3038 break;
3039 }
3040 break;
3041
3042 case AUI:
3043 if (!lp->tx_enable) {
3044 if (lp->timeout < 0) {
3045 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3046 outl(omr & ~OMR_FDX, DE4X5_OMR);
3047 }
3048 irqs = 0;
3049 irq_mask = 0;
3050 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3051 if (sts < 0) {
3052 next_tick = sts & ~TIMER_CB;
3053 } else {
3054 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3055 lp->media = BNC;
3056 next_tick = dc2114x_autoconf(dev);
3057 } else {
3058 lp->local_state = 1;
3059 de4x5_init_connection(dev);
3060 }
3061 }
3062 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3063 lp->media = AUI_SUSPECT;
3064 next_tick = 3000;
3065 }
3066 break;
3067
3068 case AUI_SUSPECT:
3069 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3070 break;
3071
3072 case BNC:
3073 switch (lp->local_state) {
3074 case 0:
3075 if (lp->timeout < 0) {
3076 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3077 outl(omr & ~OMR_FDX, DE4X5_OMR);
3078 }
3079 irqs = 0;
3080 irq_mask = 0;
3081 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3082 if (sts < 0) {
3083 next_tick = sts & ~TIMER_CB;
3084 } else {
3085 lp->local_state++; /* Ensure media connected */
3086 next_tick = dc2114x_autoconf(dev);
3087 }
3088 break;
3089
3090 case 1:
3091 if (!lp->tx_enable) {
3092 if ((sts = ping_media(dev, 3000)) < 0) {
3093 next_tick = sts & ~TIMER_CB;
3094 } else {
3095 if (sts) {
3096 lp->local_state = 0;
3097 lp->tcount++;
3098 lp->media = INIT;
3099 } else {
3100 de4x5_init_connection(dev);
3101 }
3102 }
3103 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3104 lp->media = BNC_SUSPECT;
3105 next_tick = 3000;
3106 }
3107 break;
3108 }
3109 break;
3110
3111 case BNC_SUSPECT:
3112 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3113 break;
3114
3115 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3116 if (srom_map_media(dev) < 0) {
3117 lp->tcount++;
3118 lp->media = INIT;
3119 return next_tick;
3120 }
3121 if (lp->media == _100Mb) {
3122 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3123 lp->media = SPD_DET;
3124 return (slnk & ~TIMER_CB);
3125 }
3126 } else {
3127 if (wait_for_link(dev) < 0) {
3128 lp->media = SPD_DET;
3129 return PDET_LINK_WAIT;
3130 }
3131 }
3132 if (lp->media == ANS) { /* Do MII parallel detection */
3133 if (is_spd_100(dev)) {
3134 lp->media = _100Mb;
3135 } else {
3136 lp->media = _10Mb;
3137 }
3138 next_tick = dc2114x_autoconf(dev);
3139 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3140 (((lp->media == _10Mb) || (lp->media == TP) ||
3141 (lp->media == BNC) || (lp->media == AUI)) &&
3142 is_10_up(dev))) {
3143 next_tick = dc2114x_autoconf(dev);
3144 } else {
3145 lp->tcount++;
3146 lp->media = INIT;
3147 }
3148 break;
3149
3150 case _10Mb:
3151 next_tick = 3000;
3152 if (!lp->tx_enable) {
3153 SET_10Mb;
3154 de4x5_init_connection(dev);
3155 } else {
3156 if (!lp->linkOK && (lp->autosense == AUTO)) {
3157 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3158 lp->media = INIT;
3159 lp->tcount++;
3160 next_tick = DE4X5_AUTOSENSE_MS;
3161 }
3162 }
3163 }
3164 break;
3165
3166 case _100Mb:
3167 next_tick = 3000;
3168 if (!lp->tx_enable) {
3169 SET_100Mb;
3170 de4x5_init_connection(dev);
3171 } else {
3172 if (!lp->linkOK && (lp->autosense == AUTO)) {
3173 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3174 lp->media = INIT;
3175 lp->tcount++;
3176 next_tick = DE4X5_AUTOSENSE_MS;
3177 }
3178 }
3179 }
3180 break;
3181
3182 default:
3183 lp->tcount++;
3184 printk("Huh?: media:%02x\n", lp->media);
3185 lp->media = INIT;
3186 break;
3187 }
3188
3189 return next_tick;
3190 }
3191
3192 static int
3193 srom_autoconf(struct net_device *dev)
3194 {
3195 struct de4x5_private *lp = netdev_priv(dev);
3196
3197 return lp->infoleaf_fn(dev);
3198 }
3199
3200 /*
3201 ** This mapping keeps the original media codes and FDX flag unchanged.
3202 ** While it isn't strictly necessary, it helps me for the moment...
3203 ** The early return avoids a media state / SROM media space clash.
3204 */
3205 static int
3206 srom_map_media(struct net_device *dev)
3207 {
3208 struct de4x5_private *lp = netdev_priv(dev);
3209
3210 lp->fdx = false;
3211 if (lp->infoblock_media == lp->media)
3212 return 0;
3213
3214 switch(lp->infoblock_media) {
3215 case SROM_10BASETF:
3216 if (!lp->params.fdx) return -1;
3217 lp->fdx = true;
3218 case SROM_10BASET:
3219 if (lp->params.fdx && !lp->fdx) return -1;
3220 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3221 lp->media = _10Mb;
3222 } else {
3223 lp->media = TP;
3224 }
3225 break;
3226
3227 case SROM_10BASE2:
3228 lp->media = BNC;
3229 break;
3230
3231 case SROM_10BASE5:
3232 lp->media = AUI;
3233 break;
3234
3235 case SROM_100BASETF:
3236 if (!lp->params.fdx) return -1;
3237 lp->fdx = true;
3238 case SROM_100BASET:
3239 if (lp->params.fdx && !lp->fdx) return -1;
3240 lp->media = _100Mb;
3241 break;
3242
3243 case SROM_100BASET4:
3244 lp->media = _100Mb;
3245 break;
3246
3247 case SROM_100BASEFF:
3248 if (!lp->params.fdx) return -1;
3249 lp->fdx = true;
3250 case SROM_100BASEF:
3251 if (lp->params.fdx && !lp->fdx) return -1;
3252 lp->media = _100Mb;
3253 break;
3254
3255 case ANS:
3256 lp->media = ANS;
3257 lp->fdx = lp->params.fdx;
3258 break;
3259
3260 default:
3261 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3262 lp->infoblock_media);
3263 return -1;
3264 break;
3265 }
3266
3267 return 0;
3268 }
3269
3270 static void
3271 de4x5_init_connection(struct net_device *dev)
3272 {
3273 struct de4x5_private *lp = netdev_priv(dev);
3274 u_long iobase = dev->base_addr;
3275 u_long flags = 0;
3276
3277 if (lp->media != lp->c_media) {
3278 de4x5_dbg_media(dev);
3279 lp->c_media = lp->media; /* Stop scrolling media messages */
3280 }
3281
3282 spin_lock_irqsave(&lp->lock, flags);
3283 de4x5_rst_desc_ring(dev);
3284 de4x5_setup_intr(dev);
3285 lp->tx_enable = true;
3286 spin_unlock_irqrestore(&lp->lock, flags);
3287 outl(POLL_DEMAND, DE4X5_TPD);
3288
3289 netif_wake_queue(dev);
3290 }
3291
3292 /*
3293 ** General PHY reset function. Some MII devices don't reset correctly
3294 ** since their MII address pins can float at voltages that are dependent
3295 ** on the signal pin use. Do a double reset to ensure a reset.
3296 */
3297 static int
3298 de4x5_reset_phy(struct net_device *dev)
3299 {
3300 struct de4x5_private *lp = netdev_priv(dev);
3301 u_long iobase = dev->base_addr;
3302 int next_tick = 0;
3303
3304 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3305 if (lp->timeout < 0) {
3306 if (lp->useSROM) {
3307 if (lp->phy[lp->active].rst) {
3308 srom_exec(dev, lp->phy[lp->active].rst);
3309 srom_exec(dev, lp->phy[lp->active].rst);
3310 } else if (lp->rst) { /* Type 5 infoblock reset */
3311 srom_exec(dev, lp->rst);
3312 srom_exec(dev, lp->rst);
3313 }
3314 } else {
3315 PHY_HARD_RESET;
3316 }
3317 if (lp->useMII) {
3318 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3319 }
3320 }
3321 if (lp->useMII) {
3322 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, false, 500);
3323 }
3324 } else if (lp->chipset == DC21140) {
3325 PHY_HARD_RESET;
3326 }
3327
3328 return next_tick;
3329 }
3330
3331 static int
3332 test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3333 {
3334 struct de4x5_private *lp = netdev_priv(dev);
3335 u_long iobase = dev->base_addr;
3336 s32 sts, csr12;
3337
3338 if (lp->timeout < 0) {
3339 lp->timeout = msec/100;
3340 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3341 reset_init_sia(dev, csr13, csr14, csr15);
3342 }
3343
3344 /* set up the interrupt mask */
3345 outl(irq_mask, DE4X5_IMR);
3346
3347 /* clear all pending interrupts */
3348 sts = inl(DE4X5_STS);
3349 outl(sts, DE4X5_STS);
3350
3351 /* clear csr12 NRA and SRA bits */
3352 if ((lp->chipset == DC21041) || lp->useSROM) {
3353 csr12 = inl(DE4X5_SISR);
3354 outl(csr12, DE4X5_SISR);
3355 }
3356 }
3357
3358 sts = inl(DE4X5_STS) & ~TIMER_CB;
3359
3360 if (!(sts & irqs) && --lp->timeout) {
3361 sts = 100 | TIMER_CB;
3362 } else {
3363 lp->timeout = -1;
3364 }
3365
3366 return sts;
3367 }
3368
3369 static int
3370 test_tp(struct net_device *dev, s32 msec)
3371 {
3372 struct de4x5_private *lp = netdev_priv(dev);
3373 u_long iobase = dev->base_addr;
3374 int sisr;
3375
3376 if (lp->timeout < 0) {
3377 lp->timeout = msec/100;
3378 }
3379
3380 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3381
3382 if (sisr && --lp->timeout) {
3383 sisr = 100 | TIMER_CB;
3384 } else {
3385 lp->timeout = -1;
3386 }
3387
3388 return sisr;
3389 }
3390
3391 /*
3392 ** Samples the 100Mb Link State Signal. The sample interval is important
3393 ** because too fast a rate can give erroneous results and confuse the
3394 ** speed sense algorithm.
3395 */
3396 #define SAMPLE_INTERVAL 500 /* ms */
3397 #define SAMPLE_DELAY 2000 /* ms */
3398 static int
3399 test_for_100Mb(struct net_device *dev, int msec)
3400 {
3401 struct de4x5_private *lp = netdev_priv(dev);
3402 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3403
3404 if (lp->timeout < 0) {
3405 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3406 if (msec > SAMPLE_DELAY) {
3407 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3408 gep = SAMPLE_DELAY | TIMER_CB;
3409 return gep;
3410 } else {
3411 lp->timeout = msec/SAMPLE_INTERVAL;
3412 }
3413 }
3414
3415 if (lp->phy[lp->active].id || lp->useSROM) {
3416 gep = is_100_up(dev) | is_spd_100(dev);
3417 } else {
3418 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3419 }
3420 if (!(gep & ret) && --lp->timeout) {
3421 gep = SAMPLE_INTERVAL | TIMER_CB;
3422 } else {
3423 lp->timeout = -1;
3424 }
3425
3426 return gep;
3427 }
3428
3429 static int
3430 wait_for_link(struct net_device *dev)
3431 {
3432 struct de4x5_private *lp = netdev_priv(dev);
3433
3434 if (lp->timeout < 0) {
3435 lp->timeout = 1;
3436 }
3437
3438 if (lp->timeout--) {
3439 return TIMER_CB;
3440 } else {
3441 lp->timeout = -1;
3442 }
3443
3444 return 0;
3445 }
3446
3447 /*
3448 **
3449 **
3450 */
3451 static int
3452 test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec)
3453 {
3454 struct de4x5_private *lp = netdev_priv(dev);
3455 int test;
3456 u_long iobase = dev->base_addr;
3457
3458 if (lp->timeout < 0) {
3459 lp->timeout = msec/100;
3460 }
3461
3462 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3463 test = (reg ^ (pol ? ~0 : 0)) & mask;
3464
3465 if (test && --lp->timeout) {
3466 reg = 100 | TIMER_CB;
3467 } else {
3468 lp->timeout = -1;
3469 }
3470
3471 return reg;
3472 }
3473
3474 static int
3475 is_spd_100(struct net_device *dev)
3476 {
3477 struct de4x5_private *lp = netdev_priv(dev);
3478 u_long iobase = dev->base_addr;
3479 int spd;
3480
3481 if (lp->useMII) {
3482 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3483 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3484 spd &= lp->phy[lp->active].spd.mask;
3485 } else if (!lp->useSROM) { /* de500-xa */
3486 spd = ((~gep_rd(dev)) & GEP_SLNK);
3487 } else {
3488 if ((lp->ibn == 2) || !lp->asBitValid)
3489 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3490
3491 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3492 (lp->linkOK & ~lp->asBitValid);
3493 }
3494
3495 return spd;
3496 }
3497
3498 static int
3499 is_100_up(struct net_device *dev)
3500 {
3501 struct de4x5_private *lp = netdev_priv(dev);
3502 u_long iobase = dev->base_addr;
3503
3504 if (lp->useMII) {
3505 /* Double read for sticky bits & temporary drops */
3506 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3507 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3508 } else if (!lp->useSROM) { /* de500-xa */
3509 return ((~gep_rd(dev)) & GEP_SLNK);
3510 } else {
3511 if ((lp->ibn == 2) || !lp->asBitValid)
3512 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3513
3514 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3515 (lp->linkOK & ~lp->asBitValid));
3516 }
3517 }
3518
3519 static int
3520 is_10_up(struct net_device *dev)
3521 {
3522 struct de4x5_private *lp = netdev_priv(dev);
3523 u_long iobase = dev->base_addr;
3524
3525 if (lp->useMII) {
3526 /* Double read for sticky bits & temporary drops */
3527 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3528 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3529 } else if (!lp->useSROM) { /* de500-xa */
3530 return ((~gep_rd(dev)) & GEP_LNP);
3531 } else {
3532 if ((lp->ibn == 2) || !lp->asBitValid)
3533 return (((lp->chipset & ~0x00ff) == DC2114x) ?
3534 (~inl(DE4X5_SISR)&SISR_LS10):
3535 0);
3536
3537 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3538 (lp->linkOK & ~lp->asBitValid));
3539 }
3540 }
3541
3542 static int
3543 is_anc_capable(struct net_device *dev)
3544 {
3545 struct de4x5_private *lp = netdev_priv(dev);
3546 u_long iobase = dev->base_addr;
3547
3548 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3549 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3550 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3551 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3552 } else {
3553 return 0;
3554 }
3555 }
3556
3557 /*
3558 ** Send a packet onto the media and watch for send errors that indicate the
3559 ** media is bad or unconnected.
3560 */
3561 static int
3562 ping_media(struct net_device *dev, int msec)
3563 {
3564 struct de4x5_private *lp = netdev_priv(dev);
3565 u_long iobase = dev->base_addr;
3566 int sisr;
3567
3568 if (lp->timeout < 0) {
3569 lp->timeout = msec/100;
3570
3571 lp->tmp = lp->tx_new; /* Remember the ring position */
3572 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3573 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
3574 outl(POLL_DEMAND, DE4X5_TPD);
3575 }
3576
3577 sisr = inl(DE4X5_SISR);
3578
3579 if ((!(sisr & SISR_NCR)) &&
3580 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3581 (--lp->timeout)) {
3582 sisr = 100 | TIMER_CB;
3583 } else {
3584 if ((!(sisr & SISR_NCR)) &&
3585 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3586 lp->timeout) {
3587 sisr = 0;
3588 } else {
3589 sisr = 1;
3590 }
3591 lp->timeout = -1;
3592 }
3593
3594 return sisr;
3595 }
3596
3597 /*
3598 ** This function does 2 things: on Intels it kmalloc's another buffer to
3599 ** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3600 ** into which the packet is copied.
3601 */
3602 static struct sk_buff *
3603 de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3604 {
3605 struct de4x5_private *lp = netdev_priv(dev);
3606 struct sk_buff *p;
3607
3608 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && \
3609 !defined(DE4X5_DO_MEMCPY)
3610 struct sk_buff *ret;
3611 u_long i=0, tmp;
3612
3613 p = dev_alloc_skb(IEEE802_3_SZ + DE4X5_ALIGN + 2);
3614 if (!p) return NULL;
3615
3616 tmp = virt_to_bus(p->data);
3617 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3618 skb_reserve(p, i);
3619 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3620
3621 ret = lp->rx_skb[index];
3622 lp->rx_skb[index] = p;
3623
3624 if ((u_long) ret > 1) {
3625 skb_put(ret, len);
3626 }
3627
3628 return ret;
3629
3630 #else
3631 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3632
3633 p = dev_alloc_skb(len + 2);
3634 if (!p) return NULL;
3635
3636 skb_reserve(p, 2); /* Align */
3637 if (index < lp->rx_old) { /* Wrapped buffer */
3638 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3639 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3640 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3641 } else { /* Linear buffer */
3642 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3643 }
3644
3645 return p;
3646 #endif
3647 }
3648
3649 static void
3650 de4x5_free_rx_buffs(struct net_device *dev)
3651 {
3652 struct de4x5_private *lp = netdev_priv(dev);
3653 int i;
3654
3655 for (i=0; i<lp->rxRingSize; i++) {
3656 if ((u_long) lp->rx_skb[i] > 1) {
3657 dev_kfree_skb(lp->rx_skb[i]);
3658 }
3659 lp->rx_ring[i].status = 0;
3660 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3661 }
3662 }
3663
3664 static void
3665 de4x5_free_tx_buffs(struct net_device *dev)
3666 {
3667 struct de4x5_private *lp = netdev_priv(dev);
3668 int i;
3669
3670 for (i=0; i<lp->txRingSize; i++) {
3671 if (lp->tx_skb[i])
3672 de4x5_free_tx_buff(lp, i);
3673 lp->tx_ring[i].status = 0;
3674 }
3675
3676 /* Unload the locally queued packets */
3677 __skb_queue_purge(&lp->cache.queue);
3678 }
3679
3680 /*
3681 ** When a user pulls a connection, the DECchip can end up in a
3682 ** 'running - waiting for end of transmission' state. This means that we
3683 ** have to perform a chip soft reset to ensure that we can synchronize
3684 ** the hardware and software and make any media probes using a loopback
3685 ** packet meaningful.
3686 */
3687 static void
3688 de4x5_save_skbs(struct net_device *dev)
3689 {
3690 struct de4x5_private *lp = netdev_priv(dev);
3691 u_long iobase = dev->base_addr;
3692 s32 omr;
3693
3694 if (!lp->cache.save_cnt) {
3695 STOP_DE4X5;
3696 de4x5_tx(dev); /* Flush any sent skb's */
3697 de4x5_free_tx_buffs(dev);
3698 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3699 de4x5_sw_reset(dev);
3700 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3701 lp->cache.save_cnt++;
3702 START_DE4X5;
3703 }
3704 }
3705
3706 static void
3707 de4x5_rst_desc_ring(struct net_device *dev)
3708 {
3709 struct de4x5_private *lp = netdev_priv(dev);
3710 u_long iobase = dev->base_addr;
3711 int i;
3712 s32 omr;
3713
3714 if (lp->cache.save_cnt) {
3715 STOP_DE4X5;
3716 outl(lp->dma_rings, DE4X5_RRBA);
3717 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3718 DE4X5_TRBA);
3719
3720 lp->rx_new = lp->rx_old = 0;
3721 lp->tx_new = lp->tx_old = 0;
3722
3723 for (i = 0; i < lp->rxRingSize; i++) {
3724 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3725 }
3726
3727 for (i = 0; i < lp->txRingSize; i++) {
3728 lp->tx_ring[i].status = cpu_to_le32(0);
3729 }
3730
3731 barrier();
3732 lp->cache.save_cnt--;
3733 START_DE4X5;
3734 }
3735 }
3736
3737 static void
3738 de4x5_cache_state(struct net_device *dev, int flag)
3739 {
3740 struct de4x5_private *lp = netdev_priv(dev);
3741 u_long iobase = dev->base_addr;
3742
3743 switch(flag) {
3744 case DE4X5_SAVE_STATE:
3745 lp->cache.csr0 = inl(DE4X5_BMR);
3746 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3747 lp->cache.csr7 = inl(DE4X5_IMR);
3748 break;
3749
3750 case DE4X5_RESTORE_STATE:
3751 outl(lp->cache.csr0, DE4X5_BMR);
3752 outl(lp->cache.csr6, DE4X5_OMR);
3753 outl(lp->cache.csr7, DE4X5_IMR);
3754 if (lp->chipset == DC21140) {
3755 gep_wr(lp->cache.gepc, dev);
3756 gep_wr(lp->cache.gep, dev);
3757 } else {
3758 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3759 lp->cache.csr15);
3760 }
3761 break;
3762 }
3763 }
3764
3765 static void
3766 de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3767 {
3768 struct de4x5_private *lp = netdev_priv(dev);
3769
3770 __skb_queue_tail(&lp->cache.queue, skb);
3771 }
3772
3773 static void
3774 de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3775 {
3776 struct de4x5_private *lp = netdev_priv(dev);
3777
3778 __skb_queue_head(&lp->cache.queue, skb);
3779 }
3780
3781 static struct sk_buff *
3782 de4x5_get_cache(struct net_device *dev)
3783 {
3784 struct de4x5_private *lp = netdev_priv(dev);
3785
3786 return __skb_dequeue(&lp->cache.queue);
3787 }
3788
3789 /*
3790 ** Check the Auto Negotiation State. Return OK when a link pass interrupt
3791 ** is received and the auto-negotiation status is NWAY OK.
3792 */
3793 static int
3794 test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3795 {
3796 struct de4x5_private *lp = netdev_priv(dev);
3797 u_long iobase = dev->base_addr;
3798 s32 sts, ans;
3799
3800 if (lp->timeout < 0) {
3801 lp->timeout = msec/100;
3802 outl(irq_mask, DE4X5_IMR);
3803
3804 /* clear all pending interrupts */
3805 sts = inl(DE4X5_STS);
3806 outl(sts, DE4X5_STS);
3807 }
3808
3809 ans = inl(DE4X5_SISR) & SISR_ANS;
3810 sts = inl(DE4X5_STS) & ~TIMER_CB;
3811
3812 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3813 sts = 100 | TIMER_CB;
3814 } else {
3815 lp->timeout = -1;
3816 }
3817
3818 return sts;
3819 }
3820
3821 static void
3822 de4x5_setup_intr(struct net_device *dev)
3823 {
3824 struct de4x5_private *lp = netdev_priv(dev);
3825 u_long iobase = dev->base_addr;
3826 s32 imr, sts;
3827
3828 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3829 imr = 0;
3830 UNMASK_IRQs;
3831 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3832 outl(sts, DE4X5_STS);
3833 ENABLE_IRQs;
3834 }
3835 }
3836
3837 /*
3838 **
3839 */
3840 static void
3841 reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3842 {
3843 struct de4x5_private *lp = netdev_priv(dev);
3844 u_long iobase = dev->base_addr;
3845
3846 RESET_SIA;
3847 if (lp->useSROM) {
3848 if (lp->ibn == 3) {
3849 srom_exec(dev, lp->phy[lp->active].rst);
3850 srom_exec(dev, lp->phy[lp->active].gep);
3851 outl(1, DE4X5_SICR);
3852 return;
3853 } else {
3854 csr15 = lp->cache.csr15;
3855 csr14 = lp->cache.csr14;
3856 csr13 = lp->cache.csr13;
3857 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3858 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3859 }
3860 } else {
3861 outl(csr15, DE4X5_SIGR);
3862 }
3863 outl(csr14, DE4X5_STRR);
3864 outl(csr13, DE4X5_SICR);
3865
3866 mdelay(10);
3867 }
3868
3869 /*
3870 ** Create a loopback ethernet packet
3871 */
3872 static void
3873 create_packet(struct net_device *dev, char *frame, int len)
3874 {
3875 int i;
3876 char *buf = frame;
3877
3878 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3879 *buf++ = dev->dev_addr[i];
3880 }
3881 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3882 *buf++ = dev->dev_addr[i];
3883 }
3884
3885 *buf++ = 0; /* Packet length (2 bytes) */
3886 *buf++ = 1;
3887 }
3888
3889 /*
3890 ** Look for a particular board name in the EISA configuration space
3891 */
3892 static int
3893 EISA_signature(char *name, struct device *device)
3894 {
3895 int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3896 struct eisa_device *edev;
3897
3898 *name = '\0';
3899 edev = to_eisa_device (device);
3900 i = edev->id.driver_data;
3901
3902 if (i >= 0 && i < siglen) {
3903 strcpy (name, de4x5_signatures[i]);
3904 status = 1;
3905 }
3906
3907 return status; /* return the device name string */
3908 }
3909
3910 /*
3911 ** Look for a particular board name in the PCI configuration space
3912 */
3913 static int
3914 PCI_signature(char *name, struct de4x5_private *lp)
3915 {
3916 int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3917
3918 if (lp->chipset == DC21040) {
3919 strcpy(name, "DE434/5");
3920 return status;
3921 } else { /* Search for a DEC name in the SROM */
3922 int tmp = *((char *)&lp->srom + 19) * 3;
3923 strncpy(name, (char *)&lp->srom + 26 + tmp, 8);
3924 }
3925 name[8] = '\0';
3926 for (i=0; i<siglen; i++) {
3927 if (strstr(name,de4x5_signatures[i])!=NULL) break;
3928 }
3929 if (i == siglen) {
3930 if (dec_only) {
3931 *name = '\0';
3932 } else { /* Use chip name to avoid confusion */
3933 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3934 ((lp->chipset == DC21041) ? "DC21041" :
3935 ((lp->chipset == DC21140) ? "DC21140" :
3936 ((lp->chipset == DC21142) ? "DC21142" :
3937 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
3938 )))))));
3939 }
3940 if (lp->chipset != DC21041) {
3941 lp->useSROM = true; /* card is not recognisably DEC */
3942 }
3943 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3944 lp->useSROM = true;
3945 }
3946
3947 return status;
3948 }
3949
3950 /*
3951 ** Set up the Ethernet PROM counter to the start of the Ethernet address on
3952 ** the DC21040, else read the SROM for the other chips.
3953 ** The SROM may not be present in a multi-MAC card, so first read the
3954 ** MAC address and check for a bad address. If there is a bad one then exit
3955 ** immediately with the prior srom contents intact (the h/w address will
3956 ** be fixed up later).
3957 */
3958 static void
3959 DevicePresent(struct net_device *dev, u_long aprom_addr)
3960 {
3961 int i, j=0;
3962 struct de4x5_private *lp = netdev_priv(dev);
3963
3964 if (lp->chipset == DC21040) {
3965 if (lp->bus == EISA) {
3966 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
3967 } else {
3968 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
3969 }
3970 } else { /* Read new srom */
3971 u_short tmp;
3972 __le16 *p = (__le16 *)((char *)&lp->srom + SROM_HWADD);
3973 for (i=0; i<(ETH_ALEN>>1); i++) {
3974 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
3975 j += tmp; /* for check for 0:0:0:0:0:0 or ff:ff:ff:ff:ff:ff */
3976 *p = cpu_to_le16(tmp);
3977 }
3978 if (j == 0 || j == 3 * 0xffff) {
3979 /* could get 0 only from all-0 and 3 * 0xffff only from all-1 */
3980 return;
3981 }
3982
3983 p = (__le16 *)&lp->srom;
3984 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
3985 tmp = srom_rd(aprom_addr, i);
3986 *p++ = cpu_to_le16(tmp);
3987 }
3988 de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
3989 }
3990 }
3991
3992 /*
3993 ** Since the write on the Enet PROM register doesn't seem to reset the PROM
3994 ** pointer correctly (at least on my DE425 EISA card), this routine should do
3995 ** it...from depca.c.
3996 */
3997 static void
3998 enet_addr_rst(u_long aprom_addr)
3999 {
4000 union {
4001 struct {
4002 u32 a;
4003 u32 b;
4004 } llsig;
4005 char Sig[sizeof(u32) << 1];
4006 } dev;
4007 short sigLength=0;
4008 s8 data;
4009 int i, j;
4010
4011 dev.llsig.a = ETH_PROM_SIG;
4012 dev.llsig.b = ETH_PROM_SIG;
4013 sigLength = sizeof(u32) << 1;
4014
4015 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4016 data = inb(aprom_addr);
4017 if (dev.Sig[j] == data) { /* track signature */
4018 j++;
4019 } else { /* lost signature; begin search again */
4020 if (data == dev.Sig[0]) { /* rare case.... */
4021 j=1;
4022 } else {
4023 j=0;
4024 }
4025 }
4026 }
4027 }
4028
4029 /*
4030 ** For the bad status case and no SROM, then add one to the previous
4031 ** address. However, need to add one backwards in case we have 0xff
4032 ** as one or more of the bytes. Only the last 3 bytes should be checked
4033 ** as the first three are invariant - assigned to an organisation.
4034 */
4035 static int
4036 get_hw_addr(struct net_device *dev)
4037 {
4038 u_long iobase = dev->base_addr;
4039 int broken, i, k, tmp, status = 0;
4040 u_short j,chksum;
4041 struct de4x5_private *lp = netdev_priv(dev);
4042
4043 broken = de4x5_bad_srom(lp);
4044
4045 for (i=0,k=0,j=0;j<3;j++) {
4046 k <<= 1;
4047 if (k > 0xffff) k-=0xffff;
4048
4049 if (lp->bus == PCI) {
4050 if (lp->chipset == DC21040) {
4051 while ((tmp = inl(DE4X5_APROM)) < 0);
4052 k += (u_char) tmp;
4053 dev->dev_addr[i++] = (u_char) tmp;
4054 while ((tmp = inl(DE4X5_APROM)) < 0);
4055 k += (u_short) (tmp << 8);
4056 dev->dev_addr[i++] = (u_char) tmp;
4057 } else if (!broken) {
4058 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4059 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4060 } else if ((broken == SMC) || (broken == ACCTON)) {
4061 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4062 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4063 }
4064 } else {
4065 k += (u_char) (tmp = inb(EISA_APROM));
4066 dev->dev_addr[i++] = (u_char) tmp;
4067 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4068 dev->dev_addr[i++] = (u_char) tmp;
4069 }
4070
4071 if (k > 0xffff) k-=0xffff;
4072 }
4073 if (k == 0xffff) k=0;
4074
4075 if (lp->bus == PCI) {
4076 if (lp->chipset == DC21040) {
4077 while ((tmp = inl(DE4X5_APROM)) < 0);
4078 chksum = (u_char) tmp;
4079 while ((tmp = inl(DE4X5_APROM)) < 0);
4080 chksum |= (u_short) (tmp << 8);
4081 if ((k != chksum) && (dec_only)) status = -1;
4082 }
4083 } else {
4084 chksum = (u_char) inb(EISA_APROM);
4085 chksum |= (u_short) (inb(EISA_APROM) << 8);
4086 if ((k != chksum) && (dec_only)) status = -1;
4087 }
4088
4089 /* If possible, try to fix a broken card - SMC only so far */
4090 srom_repair(dev, broken);
4091
4092 #ifdef CONFIG_PPC_PMAC
4093 /*
4094 ** If the address starts with 00 a0, we have to bit-reverse
4095 ** each byte of the address.
4096 */
4097 if ( machine_is(powermac) &&
4098 (dev->dev_addr[0] == 0) &&
4099 (dev->dev_addr[1] == 0xa0) )
4100 {
4101 for (i = 0; i < ETH_ALEN; ++i)
4102 {
4103 int x = dev->dev_addr[i];
4104 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4105 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4106 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4107 }
4108 }
4109 #endif /* CONFIG_PPC_PMAC */
4110
4111 /* Test for a bad enet address */
4112 status = test_bad_enet(dev, status);
4113
4114 return status;
4115 }
4116
4117 /*
4118 ** Test for enet addresses in the first 32 bytes. The built-in strncmp
4119 ** didn't seem to work here...?
4120 */
4121 static int
4122 de4x5_bad_srom(struct de4x5_private *lp)
4123 {
4124 int i, status = 0;
4125
4126 for (i = 0; i < ARRAY_SIZE(enet_det); i++) {
4127 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4128 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4129 if (i == 0) {
4130 status = SMC;
4131 } else if (i == 1) {
4132 status = ACCTON;
4133 }
4134 break;
4135 }
4136 }
4137
4138 return status;
4139 }
4140
4141 static int
4142 de4x5_strncmp(char *a, char *b, int n)
4143 {
4144 int ret=0;
4145
4146 for (;n && !ret; n--) {
4147 ret = *a++ - *b++;
4148 }
4149
4150 return ret;
4151 }
4152
4153 static void
4154 srom_repair(struct net_device *dev, int card)
4155 {
4156 struct de4x5_private *lp = netdev_priv(dev);
4157
4158 switch(card) {
4159 case SMC:
4160 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4161 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4162 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4163 lp->useSROM = true;
4164 break;
4165 }
4166 }
4167
4168 /*
4169 ** Assume that the irq's do not follow the PCI spec - this is seems
4170 ** to be true so far (2 for 2).
4171 */
4172 static int
4173 test_bad_enet(struct net_device *dev, int status)
4174 {
4175 struct de4x5_private *lp = netdev_priv(dev);
4176 int i, tmp;
4177
4178 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4179 if ((tmp == 0) || (tmp == 0x5fa)) {
4180 if ((lp->chipset == last.chipset) &&
4181 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4182 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4183 for (i=ETH_ALEN-1; i>2; --i) {
4184 dev->dev_addr[i] += 1;
4185 if (dev->dev_addr[i] != 0) break;
4186 }
4187 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4188 if (!an_exception(lp)) {
4189 dev->irq = last.irq;
4190 }
4191
4192 status = 0;
4193 }
4194 } else if (!status) {
4195 last.chipset = lp->chipset;
4196 last.bus = lp->bus_num;
4197 last.irq = dev->irq;
4198 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4199 }
4200
4201 return status;
4202 }
4203
4204 /*
4205 ** List of board exceptions with correctly wired IRQs
4206 */
4207 static int
4208 an_exception(struct de4x5_private *lp)
4209 {
4210 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4211 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4212 return -1;
4213 }
4214
4215 return 0;
4216 }
4217
4218 /*
4219 ** SROM Read
4220 */
4221 static short
4222 srom_rd(u_long addr, u_char offset)
4223 {
4224 sendto_srom(SROM_RD | SROM_SR, addr);
4225
4226 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4227 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4228 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4229
4230 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4231 }
4232
4233 static void
4234 srom_latch(u_int command, u_long addr)
4235 {
4236 sendto_srom(command, addr);
4237 sendto_srom(command | DT_CLK, addr);
4238 sendto_srom(command, addr);
4239 }
4240
4241 static void
4242 srom_command(u_int command, u_long addr)
4243 {
4244 srom_latch(command, addr);
4245 srom_latch(command, addr);
4246 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4247 }
4248
4249 static void
4250 srom_address(u_int command, u_long addr, u_char offset)
4251 {
4252 int i, a;
4253
4254 a = offset << 2;
4255 for (i=0; i<6; i++, a <<= 1) {
4256 srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4257 }
4258 udelay(1);
4259
4260 i = (getfrom_srom(addr) >> 3) & 0x01;
4261 }
4262
4263 static short
4264 srom_data(u_int command, u_long addr)
4265 {
4266 int i;
4267 short word = 0;
4268 s32 tmp;
4269
4270 for (i=0; i<16; i++) {
4271 sendto_srom(command | DT_CLK, addr);
4272 tmp = getfrom_srom(addr);
4273 sendto_srom(command, addr);
4274
4275 word = (word << 1) | ((tmp >> 3) & 0x01);
4276 }
4277
4278 sendto_srom(command & 0x0000ff00, addr);
4279
4280 return word;
4281 }
4282
4283 /*
4284 static void
4285 srom_busy(u_int command, u_long addr)
4286 {
4287 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4288
4289 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4290 mdelay(1);
4291 }
4292
4293 sendto_srom(command & 0x0000ff00, addr);
4294 }
4295 */
4296
4297 static void
4298 sendto_srom(u_int command, u_long addr)
4299 {
4300 outl(command, addr);
4301 udelay(1);
4302 }
4303
4304 static int
4305 getfrom_srom(u_long addr)
4306 {
4307 s32 tmp;
4308
4309 tmp = inl(addr);
4310 udelay(1);
4311
4312 return tmp;
4313 }
4314
4315 static int
4316 srom_infoleaf_info(struct net_device *dev)
4317 {
4318 struct de4x5_private *lp = netdev_priv(dev);
4319 int i, count;
4320 u_char *p;
4321
4322 /* Find the infoleaf decoder function that matches this chipset */
4323 for (i=0; i<INFOLEAF_SIZE; i++) {
4324 if (lp->chipset == infoleaf_array[i].chipset) break;
4325 }
4326 if (i == INFOLEAF_SIZE) {
4327 lp->useSROM = false;
4328 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4329 dev->name);
4330 return -ENXIO;
4331 }
4332
4333 lp->infoleaf_fn = infoleaf_array[i].fn;
4334
4335 /* Find the information offset that this function should use */
4336 count = *((u_char *)&lp->srom + 19);
4337 p = (u_char *)&lp->srom + 26;
4338
4339 if (count > 1) {
4340 for (i=count; i; --i, p+=3) {
4341 if (lp->device == *p) break;
4342 }
4343 if (i == 0) {
4344 lp->useSROM = false;
4345 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4346 dev->name, lp->device);
4347 return -ENXIO;
4348 }
4349 }
4350
4351 lp->infoleaf_offset = get_unaligned_le16(p + 1);
4352
4353 return 0;
4354 }
4355
4356 /*
4357 ** This routine loads any type 1 or 3 MII info into the mii device
4358 ** struct and executes any type 5 code to reset PHY devices for this
4359 ** controller.
4360 ** The info for the MII devices will be valid since the index used
4361 ** will follow the discovery process from MII address 1-31 then 0.
4362 */
4363 static void
4364 srom_init(struct net_device *dev)
4365 {
4366 struct de4x5_private *lp = netdev_priv(dev);
4367 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4368 u_char count;
4369
4370 p+=2;
4371 if (lp->chipset == DC21140) {
4372 lp->cache.gepc = (*p++ | GEP_CTRL);
4373 gep_wr(lp->cache.gepc, dev);
4374 }
4375
4376 /* Block count */
4377 count = *p++;
4378
4379 /* Jump the infoblocks to find types */
4380 for (;count; --count) {
4381 if (*p < 128) {
4382 p += COMPACT_LEN;
4383 } else if (*(p+1) == 5) {
4384 type5_infoblock(dev, 1, p);
4385 p += ((*p & BLOCK_LEN) + 1);
4386 } else if (*(p+1) == 4) {
4387 p += ((*p & BLOCK_LEN) + 1);
4388 } else if (*(p+1) == 3) {
4389 type3_infoblock(dev, 1, p);
4390 p += ((*p & BLOCK_LEN) + 1);
4391 } else if (*(p+1) == 2) {
4392 p += ((*p & BLOCK_LEN) + 1);
4393 } else if (*(p+1) == 1) {
4394 type1_infoblock(dev, 1, p);
4395 p += ((*p & BLOCK_LEN) + 1);
4396 } else {
4397 p += ((*p & BLOCK_LEN) + 1);
4398 }
4399 }
4400 }
4401
4402 /*
4403 ** A generic routine that writes GEP control, data and reset information
4404 ** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4405 */
4406 static void
4407 srom_exec(struct net_device *dev, u_char *p)
4408 {
4409 struct de4x5_private *lp = netdev_priv(dev);
4410 u_long iobase = dev->base_addr;
4411 u_char count = (p ? *p++ : 0);
4412 u_short *w = (u_short *)p;
4413
4414 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4415
4416 if (lp->chipset != DC21140) RESET_SIA;
4417
4418 while (count--) {
4419 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4420 *p++ : get_unaligned_le16(w++)), dev);
4421 mdelay(2); /* 2ms per action */
4422 }
4423
4424 if (lp->chipset != DC21140) {
4425 outl(lp->cache.csr14, DE4X5_STRR);
4426 outl(lp->cache.csr13, DE4X5_SICR);
4427 }
4428 }
4429
4430 /*
4431 ** Basically this function is a NOP since it will never be called,
4432 ** unless I implement the DC21041 SROM functions. There's no need
4433 ** since the existing code will be satisfactory for all boards.
4434 */
4435 static int
4436 dc21041_infoleaf(struct net_device *dev)
4437 {
4438 return DE4X5_AUTOSENSE_MS;
4439 }
4440
4441 static int
4442 dc21140_infoleaf(struct net_device *dev)
4443 {
4444 struct de4x5_private *lp = netdev_priv(dev);
4445 u_char count = 0;
4446 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4447 int next_tick = DE4X5_AUTOSENSE_MS;
4448
4449 /* Read the connection type */
4450 p+=2;
4451
4452 /* GEP control */
4453 lp->cache.gepc = (*p++ | GEP_CTRL);
4454
4455 /* Block count */
4456 count = *p++;
4457
4458 /* Recursively figure out the info blocks */
4459 if (*p < 128) {
4460 next_tick = dc_infoblock[COMPACT](dev, count, p);
4461 } else {
4462 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4463 }
4464
4465 if (lp->tcount == count) {
4466 lp->media = NC;
4467 if (lp->media != lp->c_media) {
4468 de4x5_dbg_media(dev);
4469 lp->c_media = lp->media;
4470 }
4471 lp->media = INIT;
4472 lp->tcount = 0;
4473 lp->tx_enable = false;
4474 }
4475
4476 return next_tick & ~TIMER_CB;
4477 }
4478
4479 static int
4480 dc21142_infoleaf(struct net_device *dev)
4481 {
4482 struct de4x5_private *lp = netdev_priv(dev);
4483 u_char count = 0;
4484 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4485 int next_tick = DE4X5_AUTOSENSE_MS;
4486
4487 /* Read the connection type */
4488 p+=2;
4489
4490 /* Block count */
4491 count = *p++;
4492
4493 /* Recursively figure out the info blocks */
4494 if (*p < 128) {
4495 next_tick = dc_infoblock[COMPACT](dev, count, p);
4496 } else {
4497 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4498 }
4499
4500 if (lp->tcount == count) {
4501 lp->media = NC;
4502 if (lp->media != lp->c_media) {
4503 de4x5_dbg_media(dev);
4504 lp->c_media = lp->media;
4505 }
4506 lp->media = INIT;
4507 lp->tcount = 0;
4508 lp->tx_enable = false;
4509 }
4510
4511 return next_tick & ~TIMER_CB;
4512 }
4513
4514 static int
4515 dc21143_infoleaf(struct net_device *dev)
4516 {
4517 struct de4x5_private *lp = netdev_priv(dev);
4518 u_char count = 0;
4519 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4520 int next_tick = DE4X5_AUTOSENSE_MS;
4521
4522 /* Read the connection type */
4523 p+=2;
4524
4525 /* Block count */
4526 count = *p++;
4527
4528 /* Recursively figure out the info blocks */
4529 if (*p < 128) {
4530 next_tick = dc_infoblock[COMPACT](dev, count, p);
4531 } else {
4532 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4533 }
4534 if (lp->tcount == count) {
4535 lp->media = NC;
4536 if (lp->media != lp->c_media) {
4537 de4x5_dbg_media(dev);
4538 lp->c_media = lp->media;
4539 }
4540 lp->media = INIT;
4541 lp->tcount = 0;
4542 lp->tx_enable = false;
4543 }
4544
4545 return next_tick & ~TIMER_CB;
4546 }
4547
4548 /*
4549 ** The compact infoblock is only designed for DC21140[A] chips, so
4550 ** we'll reuse the dc21140m_autoconf function. Non MII media only.
4551 */
4552 static int
4553 compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4554 {
4555 struct de4x5_private *lp = netdev_priv(dev);
4556 u_char flags, csr6;
4557
4558 /* Recursively figure out the info blocks */
4559 if (--count > lp->tcount) {
4560 if (*(p+COMPACT_LEN) < 128) {
4561 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4562 } else {
4563 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4564 }
4565 }
4566
4567 if ((lp->media == INIT) && (lp->timeout < 0)) {
4568 lp->ibn = COMPACT;
4569 lp->active = 0;
4570 gep_wr(lp->cache.gepc, dev);
4571 lp->infoblock_media = (*p++) & COMPACT_MC;
4572 lp->cache.gep = *p++;
4573 csr6 = *p++;
4574 flags = *p++;
4575
4576 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4577 lp->defMedium = (flags & 0x40) ? -1 : 0;
4578 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4579 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4580 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4581 lp->useMII = false;
4582
4583 de4x5_switch_mac_port(dev);
4584 }
4585
4586 return dc21140m_autoconf(dev);
4587 }
4588
4589 /*
4590 ** This block describes non MII media for the DC21140[A] only.
4591 */
4592 static int
4593 type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4594 {
4595 struct de4x5_private *lp = netdev_priv(dev);
4596 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4597
4598 /* Recursively figure out the info blocks */
4599 if (--count > lp->tcount) {
4600 if (*(p+len) < 128) {
4601 return dc_infoblock[COMPACT](dev, count, p+len);
4602 } else {
4603 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4604 }
4605 }
4606
4607 if ((lp->media == INIT) && (lp->timeout < 0)) {
4608 lp->ibn = 0;
4609 lp->active = 0;
4610 gep_wr(lp->cache.gepc, dev);
4611 p+=2;
4612 lp->infoblock_media = (*p++) & BLOCK0_MC;
4613 lp->cache.gep = *p++;
4614 csr6 = *p++;
4615 flags = *p++;
4616
4617 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4618 lp->defMedium = (flags & 0x40) ? -1 : 0;
4619 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4620 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4621 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4622 lp->useMII = false;
4623
4624 de4x5_switch_mac_port(dev);
4625 }
4626
4627 return dc21140m_autoconf(dev);
4628 }
4629
4630 /* These functions are under construction! */
4631
4632 static int
4633 type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4634 {
4635 struct de4x5_private *lp = netdev_priv(dev);
4636 u_char len = (*p & BLOCK_LEN)+1;
4637
4638 /* Recursively figure out the info blocks */
4639 if (--count > lp->tcount) {
4640 if (*(p+len) < 128) {
4641 return dc_infoblock[COMPACT](dev, count, p+len);
4642 } else {
4643 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4644 }
4645 }
4646
4647 p += 2;
4648 if (lp->state == INITIALISED) {
4649 lp->ibn = 1;
4650 lp->active = *p++;
4651 lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
4652 lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
4653 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4654 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4655 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4656 lp->phy[lp->active].ttm = get_unaligned_le16(p);
4657 return 0;
4658 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4659 lp->ibn = 1;
4660 lp->active = *p;
4661 lp->infoblock_csr6 = OMR_MII_100;
4662 lp->useMII = true;
4663 lp->infoblock_media = ANS;
4664
4665 de4x5_switch_mac_port(dev);
4666 }
4667
4668 return dc21140m_autoconf(dev);
4669 }
4670
4671 static int
4672 type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4673 {
4674 struct de4x5_private *lp = netdev_priv(dev);
4675 u_char len = (*p & BLOCK_LEN)+1;
4676
4677 /* Recursively figure out the info blocks */
4678 if (--count > lp->tcount) {
4679 if (*(p+len) < 128) {
4680 return dc_infoblock[COMPACT](dev, count, p+len);
4681 } else {
4682 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4683 }
4684 }
4685
4686 if ((lp->media == INIT) && (lp->timeout < 0)) {
4687 lp->ibn = 2;
4688 lp->active = 0;
4689 p += 2;
4690 lp->infoblock_media = (*p) & MEDIA_CODE;
4691
4692 if ((*p++) & EXT_FIELD) {
4693 lp->cache.csr13 = get_unaligned_le16(p); p += 2;
4694 lp->cache.csr14 = get_unaligned_le16(p); p += 2;
4695 lp->cache.csr15 = get_unaligned_le16(p); p += 2;
4696 } else {
4697 lp->cache.csr13 = CSR13;
4698 lp->cache.csr14 = CSR14;
4699 lp->cache.csr15 = CSR15;
4700 }
4701 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4702 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16);
4703 lp->infoblock_csr6 = OMR_SIA;
4704 lp->useMII = false;
4705
4706 de4x5_switch_mac_port(dev);
4707 }
4708
4709 return dc2114x_autoconf(dev);
4710 }
4711
4712 static int
4713 type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4714 {
4715 struct de4x5_private *lp = netdev_priv(dev);
4716 u_char len = (*p & BLOCK_LEN)+1;
4717
4718 /* Recursively figure out the info blocks */
4719 if (--count > lp->tcount) {
4720 if (*(p+len) < 128) {
4721 return dc_infoblock[COMPACT](dev, count, p+len);
4722 } else {
4723 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4724 }
4725 }
4726
4727 p += 2;
4728 if (lp->state == INITIALISED) {
4729 lp->ibn = 3;
4730 lp->active = *p++;
4731 if (MOTO_SROM_BUG) lp->active = 0;
4732 lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
4733 lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
4734 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4735 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4736 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4737 lp->phy[lp->active].ttm = get_unaligned_le16(p); p += 2;
4738 lp->phy[lp->active].mci = *p;
4739 return 0;
4740 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4741 lp->ibn = 3;
4742 lp->active = *p;
4743 if (MOTO_SROM_BUG) lp->active = 0;
4744 lp->infoblock_csr6 = OMR_MII_100;
4745 lp->useMII = true;
4746 lp->infoblock_media = ANS;
4747
4748 de4x5_switch_mac_port(dev);
4749 }
4750
4751 return dc2114x_autoconf(dev);
4752 }
4753
4754 static int
4755 type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4756 {
4757 struct de4x5_private *lp = netdev_priv(dev);
4758 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4759
4760 /* Recursively figure out the info blocks */
4761 if (--count > lp->tcount) {
4762 if (*(p+len) < 128) {
4763 return dc_infoblock[COMPACT](dev, count, p+len);
4764 } else {
4765 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4766 }
4767 }
4768
4769 if ((lp->media == INIT) && (lp->timeout < 0)) {
4770 lp->ibn = 4;
4771 lp->active = 0;
4772 p+=2;
4773 lp->infoblock_media = (*p++) & MEDIA_CODE;
4774 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4775 lp->cache.csr14 = CSR14;
4776 lp->cache.csr15 = CSR15;
4777 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4778 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4779 csr6 = *p++;
4780 flags = *p++;
4781
4782 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4783 lp->defMedium = (flags & 0x40) ? -1 : 0;
4784 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4785 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4786 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4787 lp->useMII = false;
4788
4789 de4x5_switch_mac_port(dev);
4790 }
4791
4792 return dc2114x_autoconf(dev);
4793 }
4794
4795 /*
4796 ** This block type provides information for resetting external devices
4797 ** (chips) through the General Purpose Register.
4798 */
4799 static int
4800 type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4801 {
4802 struct de4x5_private *lp = netdev_priv(dev);
4803 u_char len = (*p & BLOCK_LEN)+1;
4804
4805 /* Recursively figure out the info blocks */
4806 if (--count > lp->tcount) {
4807 if (*(p+len) < 128) {
4808 return dc_infoblock[COMPACT](dev, count, p+len);
4809 } else {
4810 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4811 }
4812 }
4813
4814 /* Must be initializing to run this code */
4815 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4816 p+=2;
4817 lp->rst = p;
4818 srom_exec(dev, lp->rst);
4819 }
4820
4821 return DE4X5_AUTOSENSE_MS;
4822 }
4823
4824 /*
4825 ** MII Read/Write
4826 */
4827
4828 static int
4829 mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4830 {
4831 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4832 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4833 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4834 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4835 mii_address(phyreg, ioaddr); /* PHY Register to read */
4836 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
4837
4838 return mii_rdata(ioaddr); /* Read data */
4839 }
4840
4841 static void
4842 mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4843 {
4844 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4845 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4846 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4847 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4848 mii_address(phyreg, ioaddr); /* PHY Register to write */
4849 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4850 data = mii_swap(data, 16); /* Swap data bit ordering */
4851 mii_wdata(data, 16, ioaddr); /* Write data */
4852 }
4853
4854 static int
4855 mii_rdata(u_long ioaddr)
4856 {
4857 int i;
4858 s32 tmp = 0;
4859
4860 for (i=0; i<16; i++) {
4861 tmp <<= 1;
4862 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4863 }
4864
4865 return tmp;
4866 }
4867
4868 static void
4869 mii_wdata(int data, int len, u_long ioaddr)
4870 {
4871 int i;
4872
4873 for (i=0; i<len; i++) {
4874 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4875 data >>= 1;
4876 }
4877 }
4878
4879 static void
4880 mii_address(u_char addr, u_long ioaddr)
4881 {
4882 int i;
4883
4884 addr = mii_swap(addr, 5);
4885 for (i=0; i<5; i++) {
4886 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4887 addr >>= 1;
4888 }
4889 }
4890
4891 static void
4892 mii_ta(u_long rw, u_long ioaddr)
4893 {
4894 if (rw == MII_STWR) {
4895 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4896 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
4897 } else {
4898 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
4899 }
4900 }
4901
4902 static int
4903 mii_swap(int data, int len)
4904 {
4905 int i, tmp = 0;
4906
4907 for (i=0; i<len; i++) {
4908 tmp <<= 1;
4909 tmp |= (data & 1);
4910 data >>= 1;
4911 }
4912
4913 return tmp;
4914 }
4915
4916 static void
4917 sendto_mii(u32 command, int data, u_long ioaddr)
4918 {
4919 u32 j;
4920
4921 j = (data & 1) << 17;
4922 outl(command | j, ioaddr);
4923 udelay(1);
4924 outl(command | MII_MDC | j, ioaddr);
4925 udelay(1);
4926 }
4927
4928 static int
4929 getfrom_mii(u32 command, u_long ioaddr)
4930 {
4931 outl(command, ioaddr);
4932 udelay(1);
4933 outl(command | MII_MDC, ioaddr);
4934 udelay(1);
4935
4936 return ((inl(ioaddr) >> 19) & 1);
4937 }
4938
4939 /*
4940 ** Here's 3 ways to calculate the OUI from the ID registers.
4941 */
4942 static int
4943 mii_get_oui(u_char phyaddr, u_long ioaddr)
4944 {
4945 /*
4946 union {
4947 u_short reg;
4948 u_char breg[2];
4949 } a;
4950 int i, r2, r3, ret=0;*/
4951 int r2, r3;
4952
4953 /* Read r2 and r3 */
4954 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
4955 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
4956 /* SEEQ and Cypress way * /
4957 / * Shuffle r2 and r3 * /
4958 a.reg=0;
4959 r3 = ((r3>>10)|(r2<<6))&0x0ff;
4960 r2 = ((r2>>2)&0x3fff);
4961
4962 / * Bit reverse r3 * /
4963 for (i=0;i<8;i++) {
4964 ret<<=1;
4965 ret |= (r3&1);
4966 r3>>=1;
4967 }
4968
4969 / * Bit reverse r2 * /
4970 for (i=0;i<16;i++) {
4971 a.reg<<=1;
4972 a.reg |= (r2&1);
4973 r2>>=1;
4974 }
4975
4976 / * Swap r2 bytes * /
4977 i=a.breg[0];
4978 a.breg[0]=a.breg[1];
4979 a.breg[1]=i;
4980
4981 return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */
4982 /* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */
4983 return r2; /* (I did it) My way */
4984 }
4985
4986 /*
4987 ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
4988 */
4989 static int
4990 mii_get_phy(struct net_device *dev)
4991 {
4992 struct de4x5_private *lp = netdev_priv(dev);
4993 u_long iobase = dev->base_addr;
4994 int i, j, k, n, limit=ARRAY_SIZE(phy_info);
4995 int id;
4996
4997 lp->active = 0;
4998 lp->useMII = true;
4999
5000 /* Search the MII address space for possible PHY devices */
5001 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
5002 lp->phy[lp->active].addr = i;
5003 if (i==0) n++; /* Count cycles */
5004 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
5005 id = mii_get_oui(i, DE4X5_MII);
5006 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
5007 for (j=0; j<limit; j++) { /* Search PHY table */
5008 if (id != phy_info[j].id) continue; /* ID match? */
5009 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
5010 if (k < DE4X5_MAX_PHY) {
5011 memcpy((char *)&lp->phy[k],
5012 (char *)&phy_info[j], sizeof(struct phy_table));
5013 lp->phy[k].addr = i;
5014 lp->mii_cnt++;
5015 lp->active++;
5016 } else {
5017 goto purgatory; /* Stop the search */
5018 }
5019 break;
5020 }
5021 if ((j == limit) && (i < DE4X5_MAX_MII)) {
5022 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
5023 lp->phy[k].addr = i;
5024 lp->phy[k].id = id;
5025 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5026 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5027 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5028 lp->mii_cnt++;
5029 lp->active++;
5030 printk("%s: Using generic MII device control. If the board doesn't operate,\nplease mail the following dump to the author:\n", dev->name);
5031 j = de4x5_debug;
5032 de4x5_debug |= DEBUG_MII;
5033 de4x5_dbg_mii(dev, k);
5034 de4x5_debug = j;
5035 printk("\n");
5036 }
5037 }
5038 purgatory:
5039 lp->active = 0;
5040 if (lp->phy[0].id) { /* Reset the PHY devices */
5041 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++) { /*For each PHY*/
5042 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5043 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5044
5045 de4x5_dbg_mii(dev, k);
5046 }
5047 }
5048 if (!lp->mii_cnt) lp->useMII = false;
5049
5050 return lp->mii_cnt;
5051 }
5052
5053 static char *
5054 build_setup_frame(struct net_device *dev, int mode)
5055 {
5056 struct de4x5_private *lp = netdev_priv(dev);
5057 int i;
5058 char *pa = lp->setup_frame;
5059
5060 /* Initialise the setup frame */
5061 if (mode == ALL) {
5062 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5063 }
5064
5065 if (lp->setup_f == HASH_PERF) {
5066 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5067 *(pa + i) = dev->dev_addr[i]; /* Host address */
5068 if (i & 0x01) pa += 2;
5069 }
5070 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5071 } else {
5072 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5073 *(pa + (i&1)) = dev->dev_addr[i];
5074 if (i & 0x01) pa += 4;
5075 }
5076 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5077 *(pa + (i&1)) = (char) 0xff;
5078 if (i & 0x01) pa += 4;
5079 }
5080 }
5081
5082 return pa; /* Points to the next entry */
5083 }
5084
5085 static void
5086 disable_ast(struct net_device *dev)
5087 {
5088 struct de4x5_private *lp = netdev_priv(dev);
5089 del_timer_sync(&lp->timer);
5090 }
5091
5092 static long
5093 de4x5_switch_mac_port(struct net_device *dev)
5094 {
5095 struct de4x5_private *lp = netdev_priv(dev);
5096 u_long iobase = dev->base_addr;
5097 s32 omr;
5098
5099 STOP_DE4X5;
5100
5101 /* Assert the OMR_PS bit in CSR6 */
5102 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5103 OMR_FDX));
5104 omr |= lp->infoblock_csr6;
5105 if (omr & OMR_PS) omr |= OMR_HBD;
5106 outl(omr, DE4X5_OMR);
5107
5108 /* Soft Reset */
5109 RESET_DE4X5;
5110
5111 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5112 if (lp->chipset == DC21140) {
5113 gep_wr(lp->cache.gepc, dev);
5114 gep_wr(lp->cache.gep, dev);
5115 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5116 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5117 }
5118
5119 /* Restore CSR6 */
5120 outl(omr, DE4X5_OMR);
5121
5122 /* Reset CSR8 */
5123 inl(DE4X5_MFC);
5124
5125 return omr;
5126 }
5127
5128 static void
5129 gep_wr(s32 data, struct net_device *dev)
5130 {
5131 struct de4x5_private *lp = netdev_priv(dev);
5132 u_long iobase = dev->base_addr;
5133
5134 if (lp->chipset == DC21140) {
5135 outl(data, DE4X5_GEP);
5136 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5137 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5138 }
5139 }
5140
5141 static int
5142 gep_rd(struct net_device *dev)
5143 {
5144 struct de4x5_private *lp = netdev_priv(dev);
5145 u_long iobase = dev->base_addr;
5146
5147 if (lp->chipset == DC21140) {
5148 return inl(DE4X5_GEP);
5149 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5150 return (inl(DE4X5_SIGR) & 0x000fffff);
5151 }
5152
5153 return 0;
5154 }
5155
5156 static void
5157 yawn(struct net_device *dev, int state)
5158 {
5159 struct de4x5_private *lp = netdev_priv(dev);
5160 u_long iobase = dev->base_addr;
5161
5162 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5163
5164 if(lp->bus == EISA) {
5165 switch(state) {
5166 case WAKEUP:
5167 outb(WAKEUP, PCI_CFPM);
5168 mdelay(10);
5169 break;
5170
5171 case SNOOZE:
5172 outb(SNOOZE, PCI_CFPM);
5173 break;
5174
5175 case SLEEP:
5176 outl(0, DE4X5_SICR);
5177 outb(SLEEP, PCI_CFPM);
5178 break;
5179 }
5180 } else {
5181 struct pci_dev *pdev = to_pci_dev (lp->gendev);
5182 switch(state) {
5183 case WAKEUP:
5184 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
5185 mdelay(10);
5186 break;
5187
5188 case SNOOZE:
5189 pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE);
5190 break;
5191
5192 case SLEEP:
5193 outl(0, DE4X5_SICR);
5194 pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP);
5195 break;
5196 }
5197 }
5198 }
5199
5200 static void
5201 de4x5_parse_params(struct net_device *dev)
5202 {
5203 struct de4x5_private *lp = netdev_priv(dev);
5204 char *p, *q, t;
5205
5206 lp->params.fdx = 0;
5207 lp->params.autosense = AUTO;
5208
5209 if (args == NULL) return;
5210
5211 if ((p = strstr(args, dev->name))) {
5212 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5213 t = *q;
5214 *q = '\0';
5215
5216 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5217
5218 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5219 if (strstr(p, "TP")) {
5220 lp->params.autosense = TP;
5221 } else if (strstr(p, "TP_NW")) {
5222 lp->params.autosense = TP_NW;
5223 } else if (strstr(p, "BNC")) {
5224 lp->params.autosense = BNC;
5225 } else if (strstr(p, "AUI")) {
5226 lp->params.autosense = AUI;
5227 } else if (strstr(p, "BNC_AUI")) {
5228 lp->params.autosense = BNC;
5229 } else if (strstr(p, "10Mb")) {
5230 lp->params.autosense = _10Mb;
5231 } else if (strstr(p, "100Mb")) {
5232 lp->params.autosense = _100Mb;
5233 } else if (strstr(p, "AUTO")) {
5234 lp->params.autosense = AUTO;
5235 }
5236 }
5237 *q = t;
5238 }
5239 }
5240
5241 static void
5242 de4x5_dbg_open(struct net_device *dev)
5243 {
5244 struct de4x5_private *lp = netdev_priv(dev);
5245 int i;
5246
5247 if (de4x5_debug & DEBUG_OPEN) {
5248 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5249 printk("\tphysical address: ");
5250 for (i=0;i<6;i++) {
5251 printk("%2.2x:",(short)dev->dev_addr[i]);
5252 }
5253 printk("\n");
5254 printk("Descriptor head addresses:\n");
5255 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5256 printk("Descriptor addresses:\nRX: ");
5257 for (i=0;i<lp->rxRingSize-1;i++){
5258 if (i < 3) {
5259 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5260 }
5261 }
5262 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5263 printk("TX: ");
5264 for (i=0;i<lp->txRingSize-1;i++){
5265 if (i < 3) {
5266 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5267 }
5268 }
5269 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5270 printk("Descriptor buffers:\nRX: ");
5271 for (i=0;i<lp->rxRingSize-1;i++){
5272 if (i < 3) {
5273 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5274 }
5275 }
5276 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5277 printk("TX: ");
5278 for (i=0;i<lp->txRingSize-1;i++){
5279 if (i < 3) {
5280 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5281 }
5282 }
5283 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5284 printk("Ring size:\nRX: %d\nTX: %d\n",
5285 (short)lp->rxRingSize,
5286 (short)lp->txRingSize);
5287 }
5288 }
5289
5290 static void
5291 de4x5_dbg_mii(struct net_device *dev, int k)
5292 {
5293 struct de4x5_private *lp = netdev_priv(dev);
5294 u_long iobase = dev->base_addr;
5295
5296 if (de4x5_debug & DEBUG_MII) {
5297 printk("\nMII device address: %d\n", lp->phy[k].addr);
5298 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5299 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5300 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5301 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5302 if (lp->phy[k].id != BROADCOM_T4) {
5303 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5304 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5305 }
5306 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5307 if (lp->phy[k].id != BROADCOM_T4) {
5308 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5309 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5310 } else {
5311 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5312 }
5313 }
5314 }
5315
5316 static void
5317 de4x5_dbg_media(struct net_device *dev)
5318 {
5319 struct de4x5_private *lp = netdev_priv(dev);
5320
5321 if (lp->media != lp->c_media) {
5322 if (de4x5_debug & DEBUG_MEDIA) {
5323 printk("%s: media is %s%s\n", dev->name,
5324 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5325 (lp->media == TP ? "TP" :
5326 (lp->media == ANS ? "TP/Nway" :
5327 (lp->media == BNC ? "BNC" :
5328 (lp->media == AUI ? "AUI" :
5329 (lp->media == BNC_AUI ? "BNC/AUI" :
5330 (lp->media == EXT_SIA ? "EXT SIA" :
5331 (lp->media == _100Mb ? "100Mb/s" :
5332 (lp->media == _10Mb ? "10Mb/s" :
5333 "???"
5334 ))))))))), (lp->fdx?" full duplex.":"."));
5335 }
5336 lp->c_media = lp->media;
5337 }
5338 }
5339
5340 static void
5341 de4x5_dbg_srom(struct de4x5_srom *p)
5342 {
5343 int i;
5344
5345 if (de4x5_debug & DEBUG_SROM) {
5346 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5347 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5348 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5349 printk("SROM version: %02x\n", (u_char)(p->version));
5350 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5351
5352 printk("Hardware Address: %pM\n", p->ieee_addr);
5353 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5354 for (i=0; i<64; i++) {
5355 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5356 }
5357 }
5358 }
5359
5360 static void
5361 de4x5_dbg_rx(struct sk_buff *skb, int len)
5362 {
5363 int i, j;
5364
5365 if (de4x5_debug & DEBUG_RX) {
5366 printk("R: %pM <- %pM len/SAP:%02x%02x [%d]\n",
5367 skb->data, &skb->data[6],
5368 (u_char)skb->data[12],
5369 (u_char)skb->data[13],
5370 len);
5371 for (j=0; len>0;j+=16, len-=16) {
5372 printk(" %03x: ",j);
5373 for (i=0; i<16 && i<len; i++) {
5374 printk("%02x ",(u_char)skb->data[i+j]);
5375 }
5376 printk("\n");
5377 }
5378 }
5379 }
5380
5381 /*
5382 ** Perform IOCTL call functions here. Some are privileged operations and the
5383 ** effective uid is checked in those cases. In the normal course of events
5384 ** this function is only used for my testing.
5385 */
5386 static int
5387 de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5388 {
5389 struct de4x5_private *lp = netdev_priv(dev);
5390 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru;
5391 u_long iobase = dev->base_addr;
5392 int i, j, status = 0;
5393 s32 omr;
5394 union {
5395 u8 addr[144];
5396 u16 sval[72];
5397 u32 lval[36];
5398 } tmp;
5399 u_long flags = 0;
5400
5401 switch(ioc->cmd) {
5402 case DE4X5_GET_HWADDR: /* Get the hardware address */
5403 ioc->len = ETH_ALEN;
5404 for (i=0; i<ETH_ALEN; i++) {
5405 tmp.addr[i] = dev->dev_addr[i];
5406 }
5407 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5408 break;
5409
5410 case DE4X5_SET_HWADDR: /* Set the hardware address */
5411 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5412 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5413 if (netif_queue_stopped(dev))
5414 return -EBUSY;
5415 netif_stop_queue(dev);
5416 for (i=0; i<ETH_ALEN; i++) {
5417 dev->dev_addr[i] = tmp.addr[i];
5418 }
5419 build_setup_frame(dev, PHYS_ADDR_ONLY);
5420 /* Set up the descriptor and give ownership to the card */
5421 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5422 SETUP_FRAME_LEN, (struct sk_buff *)1);
5423 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
5424 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5425 netif_wake_queue(dev); /* Unlock the TX ring */
5426 break;
5427
5428 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5429 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5430 printk("%s: Boo!\n", dev->name);
5431 break;
5432
5433 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5434 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5435 omr = inl(DE4X5_OMR);
5436 omr |= OMR_PM;
5437 outl(omr, DE4X5_OMR);
5438 break;
5439
5440 case DE4X5_GET_STATS: /* Get the driver statistics */
5441 {
5442 struct pkt_stats statbuf;
5443 ioc->len = sizeof(statbuf);
5444 spin_lock_irqsave(&lp->lock, flags);
5445 memcpy(&statbuf, &lp->pktStats, ioc->len);
5446 spin_unlock_irqrestore(&lp->lock, flags);
5447 if (copy_to_user(ioc->data, &statbuf, ioc->len))
5448 return -EFAULT;
5449 break;
5450 }
5451 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5452 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5453 spin_lock_irqsave(&lp->lock, flags);
5454 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5455 spin_unlock_irqrestore(&lp->lock, flags);
5456 break;
5457
5458 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5459 tmp.addr[0] = inl(DE4X5_OMR);
5460 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5461 break;
5462
5463 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5464 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5465 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5466 outl(tmp.addr[0], DE4X5_OMR);
5467 break;
5468
5469 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5470 j = 0;
5471 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5472 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5473 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5474 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5475 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5476 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5477 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5478 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5479 ioc->len = j;
5480 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5481 break;
5482
5483 #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5484 /*
5485 case DE4X5_DUMP:
5486 j = 0;
5487 tmp.addr[j++] = dev->irq;
5488 for (i=0; i<ETH_ALEN; i++) {
5489 tmp.addr[j++] = dev->dev_addr[i];
5490 }
5491 tmp.addr[j++] = lp->rxRingSize;
5492 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5493 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5494
5495 for (i=0;i<lp->rxRingSize-1;i++){
5496 if (i < 3) {
5497 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5498 }
5499 }
5500 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5501 for (i=0;i<lp->txRingSize-1;i++){
5502 if (i < 3) {
5503 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5504 }
5505 }
5506 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5507
5508 for (i=0;i<lp->rxRingSize-1;i++){
5509 if (i < 3) {
5510 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5511 }
5512 }
5513 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5514 for (i=0;i<lp->txRingSize-1;i++){
5515 if (i < 3) {
5516 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5517 }
5518 }
5519 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5520
5521 for (i=0;i<lp->rxRingSize;i++){
5522 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5523 }
5524 for (i=0;i<lp->txRingSize;i++){
5525 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5526 }
5527
5528 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5529 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5530 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5531 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5532 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5533 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5534 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5535 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5536 tmp.lval[j>>2] = lp->chipset; j+=4;
5537 if (lp->chipset == DC21140) {
5538 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5539 } else {
5540 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5541 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5542 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5543 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5544 }
5545 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5546 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5547 tmp.lval[j>>2] = lp->active; j+=4;
5548 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5549 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5550 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5551 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5552 if (lp->phy[lp->active].id != BROADCOM_T4) {
5553 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5554 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5555 }
5556 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5557 if (lp->phy[lp->active].id != BROADCOM_T4) {
5558 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5559 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5560 } else {
5561 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5562 }
5563 }
5564
5565 tmp.addr[j++] = lp->txRingSize;
5566 tmp.addr[j++] = netif_queue_stopped(dev);
5567
5568 ioc->len = j;
5569 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5570 break;
5571
5572 */
5573 default:
5574 return -EOPNOTSUPP;
5575 }
5576
5577 return status;
5578 }
5579
5580 static int __init de4x5_module_init (void)
5581 {
5582 int err = 0;
5583
5584 #ifdef CONFIG_PCI
5585 err = pci_register_driver(&de4x5_pci_driver);
5586 #endif
5587 #ifdef CONFIG_EISA
5588 err |= eisa_driver_register (&de4x5_eisa_driver);
5589 #endif
5590
5591 return err;
5592 }
5593
5594 static void __exit de4x5_module_exit (void)
5595 {
5596 #ifdef CONFIG_PCI
5597 pci_unregister_driver (&de4x5_pci_driver);
5598 #endif
5599 #ifdef CONFIG_EISA
5600 eisa_driver_unregister (&de4x5_eisa_driver);
5601 #endif
5602 }
5603
5604 module_init (de4x5_module_init);
5605 module_exit (de4x5_module_exit);
Tomato firmware and modifications.