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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / tlan.h
blobd13ff12d7500b95cff207a67ecf9f4c5118ab83b
1 #ifndef TLAN_H
2 #define TLAN_H
3 /********************************************************************
4 *
5 * Linux ThunderLAN Driver
6 *
7 * tlan.h
8 * by James Banks
9 *
10 * (C) 1997-1998 Caldera, Inc.
11 * (C) 1999-2001 Torben Mathiasen
12 *
13 * This software may be used and distributed according to the terms
14 * of the GNU General Public License, incorporated herein by reference.
15 *
16 *
17 * Dec 10, 1999 Torben Mathiasen <torben.mathiasen@compaq.com>
18 * New Maintainer
19 *
20 ********************************************************************/
21
22
23 #include <asm/io.h>
24 #include <asm/types.h>
25 #include <linux/netdevice.h>
26
27
28
29 /*****************************************************************
30 * TLan Definitions
31 *
32 ****************************************************************/
33
34 #define TLAN_MIN_FRAME_SIZE 64
35 #define TLAN_MAX_FRAME_SIZE 1600
36
37 #define TLAN_NUM_RX_LISTS 32
38 #define TLAN_NUM_TX_LISTS 64
39
40 #define TLAN_IGNORE 0
41 #define TLAN_RECORD 1
42
43 #define TLAN_DBG(lvl, format, args...) \
44 do { if (debug&lvl) printk(KERN_DEBUG "TLAN: " format, ##args ); } while(0)
45
46 #define TLAN_DEBUG_GNRL 0x0001
47 #define TLAN_DEBUG_TX 0x0002
48 #define TLAN_DEBUG_RX 0x0004
49 #define TLAN_DEBUG_LIST 0x0008
50 #define TLAN_DEBUG_PROBE 0x0010
51
52 #define TX_TIMEOUT (10*HZ) /* We need time for auto-neg */
53 #define MAX_TLAN_BOARDS 8 /* Max number of boards installed at a time */
54
55
56 /*****************************************************************
57 * Device Identification Definitions
58 *
59 ****************************************************************/
60
61 #define PCI_DEVICE_ID_NETELLIGENT_10_T2 0xB012
62 #define PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100 0xB030
63 #ifndef PCI_DEVICE_ID_OLICOM_OC2183
64 #define PCI_DEVICE_ID_OLICOM_OC2183 0x0013
65 #endif
66 #ifndef PCI_DEVICE_ID_OLICOM_OC2325
67 #define PCI_DEVICE_ID_OLICOM_OC2325 0x0012
68 #endif
69 #ifndef PCI_DEVICE_ID_OLICOM_OC2326
70 #define PCI_DEVICE_ID_OLICOM_OC2326 0x0014
71 #endif
72
73 typedef struct tlan_adapter_entry {
74 u16 vendorId;
75 u16 deviceId;
76 char *deviceLabel;
77 u32 flags;
78 u16 addrOfs;
79 } TLanAdapterEntry;
80
81 #define TLAN_ADAPTER_NONE 0x00000000
82 #define TLAN_ADAPTER_UNMANAGED_PHY 0x00000001
83 #define TLAN_ADAPTER_BIT_RATE_PHY 0x00000002
84 #define TLAN_ADAPTER_USE_INTERN_10 0x00000004
85 #define TLAN_ADAPTER_ACTIVITY_LED 0x00000008
86
87 #define TLAN_SPEED_DEFAULT 0
88 #define TLAN_SPEED_10 10
89 #define TLAN_SPEED_100 100
90
91 #define TLAN_DUPLEX_DEFAULT 0
92 #define TLAN_DUPLEX_HALF 1
93 #define TLAN_DUPLEX_FULL 2
94
95
96
97 /*****************************************************************
98 * EISA Definitions
99 *
100 ****************************************************************/
101
102 #define EISA_ID 0xc80 /* EISA ID Registers */
103 #define EISA_ID0 0xc80 /* EISA ID Register 0 */
104 #define EISA_ID1 0xc81 /* EISA ID Register 1 */
105 #define EISA_ID2 0xc82 /* EISA ID Register 2 */
106 #define EISA_ID3 0xc83 /* EISA ID Register 3 */
107 #define EISA_CR 0xc84 /* EISA Control Register */
108 #define EISA_REG0 0xc88 /* EISA Configuration Register 0 */
109 #define EISA_REG1 0xc89 /* EISA Configuration Register 1 */
110 #define EISA_REG2 0xc8a /* EISA Configuration Register 2 */
111 #define EISA_REG3 0xc8f /* EISA Configuration Register 3 */
112 #define EISA_APROM 0xc90 /* Ethernet Address PROM */
113
114
115
116 /*****************************************************************
117 * Rx/Tx List Definitions
118 *
119 ****************************************************************/
120
121 #define TLAN_BUFFERS_PER_LIST 10
122 #define TLAN_LAST_BUFFER 0x80000000
123 #define TLAN_CSTAT_UNUSED 0x8000
124 #define TLAN_CSTAT_FRM_CMP 0x4000
125 #define TLAN_CSTAT_READY 0x3000
126 #define TLAN_CSTAT_EOC 0x0800
127 #define TLAN_CSTAT_RX_ERROR 0x0400
128 #define TLAN_CSTAT_PASS_CRC 0x0200
129 #define TLAN_CSTAT_DP_PR 0x0100
130
131
132 typedef struct tlan_buffer_ref_tag {
133 u32 count;
134 u32 address;
135 } TLanBufferRef;
136
137
138 typedef struct tlan_list_tag {
139 u32 forward;
140 u16 cStat;
141 u16 frameSize;
142 TLanBufferRef buffer[TLAN_BUFFERS_PER_LIST];
143 } TLanList;
144
145
146 typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE];
147
148
149
150
151 /*****************************************************************
152 * PHY definitions
153 *
154 ****************************************************************/
155
156 #define TLAN_PHY_MAX_ADDR 0x1F
157 #define TLAN_PHY_NONE 0x20
158
159
160
161
162 /*****************************************************************
163 * TLAN Private Information Structure
164 *
165 ****************************************************************/
166
167 typedef struct tlan_private_tag {
168 struct net_device *nextDevice;
169 struct pci_dev *pciDev;
170 struct net_device *dev;
171 void *dmaStorage;
172 dma_addr_t dmaStorageDMA;
173 unsigned int dmaSize;
174 u8 *padBuffer;
175 TLanList *rxList;
176 dma_addr_t rxListDMA;
177 u8 *rxBuffer;
178 dma_addr_t rxBufferDMA;
179 u32 rxHead;
180 u32 rxTail;
181 u32 rxEocCount;
182 TLanList *txList;
183 dma_addr_t txListDMA;
184 u8 *txBuffer;
185 dma_addr_t txBufferDMA;
186 u32 txHead;
187 u32 txInProgress;
188 u32 txTail;
189 u32 txBusyCount;
190 u32 phyOnline;
191 u32 timerSetAt;
192 u32 timerType;
193 struct timer_list timer;
194 struct board *adapter;
195 u32 adapterRev;
196 u32 aui;
197 u32 debug;
198 u32 duplex;
199 u32 phy[2];
200 u32 phyNum;
201 u32 speed;
202 u8 tlanRev;
203 u8 tlanFullDuplex;
204 spinlock_t lock;
205 u8 link;
206 u8 is_eisa;
207 struct work_struct tlan_tqueue;
208 u8 neg_be_verbose;
209 } TLanPrivateInfo;
210
211
212
213
214 /*****************************************************************
215 * TLan Driver Timer Definitions
216 *
217 ****************************************************************/
218
219 #define TLAN_TIMER_LINK_BEAT 1
220 #define TLAN_TIMER_ACTIVITY 2
221 #define TLAN_TIMER_PHY_PDOWN 3
222 #define TLAN_TIMER_PHY_PUP 4
223 #define TLAN_TIMER_PHY_RESET 5
224 #define TLAN_TIMER_PHY_START_LINK 6
225 #define TLAN_TIMER_PHY_FINISH_AN 7
226 #define TLAN_TIMER_FINISH_RESET 8
227
228 #define TLAN_TIMER_ACT_DELAY (HZ/10)
229
230
231
232
233 /*****************************************************************
234 * TLan Driver Eeprom Definitions
235 *
236 ****************************************************************/
237
238 #define TLAN_EEPROM_ACK 0
239 #define TLAN_EEPROM_STOP 1
240
241
242
243
244 /*****************************************************************
245 * Host Register Offsets and Contents
246 *
247 ****************************************************************/
248
249 #define TLAN_HOST_CMD 0x00
250 #define TLAN_HC_GO 0x80000000
251 #define TLAN_HC_STOP 0x40000000
252 #define TLAN_HC_ACK 0x20000000
253 #define TLAN_HC_CS_MASK 0x1FE00000
254 #define TLAN_HC_EOC 0x00100000
255 #define TLAN_HC_RT 0x00080000
256 #define TLAN_HC_NES 0x00040000
257 #define TLAN_HC_AD_RST 0x00008000
258 #define TLAN_HC_LD_TMR 0x00004000
259 #define TLAN_HC_LD_THR 0x00002000
260 #define TLAN_HC_REQ_INT 0x00001000
261 #define TLAN_HC_INT_OFF 0x00000800
262 #define TLAN_HC_INT_ON 0x00000400
263 #define TLAN_HC_AC_MASK 0x000000FF
264 #define TLAN_CH_PARM 0x04
265 #define TLAN_DIO_ADR 0x08
266 #define TLAN_DA_ADR_INC 0x8000
267 #define TLAN_DA_RAM_ADR 0x4000
268 #define TLAN_HOST_INT 0x0A
269 #define TLAN_HI_IV_MASK 0x1FE0
270 #define TLAN_HI_IT_MASK 0x001C
271 #define TLAN_DIO_DATA 0x0C
272
273
274 /* ThunderLAN Internal Register DIO Offsets */
275
276 #define TLAN_NET_CMD 0x00
277 #define TLAN_NET_CMD_NRESET 0x80
278 #define TLAN_NET_CMD_NWRAP 0x40
279 #define TLAN_NET_CMD_CSF 0x20
280 #define TLAN_NET_CMD_CAF 0x10
281 #define TLAN_NET_CMD_NOBRX 0x08
282 #define TLAN_NET_CMD_DUPLEX 0x04
283 #define TLAN_NET_CMD_TRFRAM 0x02
284 #define TLAN_NET_CMD_TXPACE 0x01
285 #define TLAN_NET_SIO 0x01
286 #define TLAN_NET_SIO_MINTEN 0x80
287 #define TLAN_NET_SIO_ECLOK 0x40
288 #define TLAN_NET_SIO_ETXEN 0x20
289 #define TLAN_NET_SIO_EDATA 0x10
290 #define TLAN_NET_SIO_NMRST 0x08
291 #define TLAN_NET_SIO_MCLK 0x04
292 #define TLAN_NET_SIO_MTXEN 0x02
293 #define TLAN_NET_SIO_MDATA 0x01
294 #define TLAN_NET_STS 0x02
295 #define TLAN_NET_STS_MIRQ 0x80
296 #define TLAN_NET_STS_HBEAT 0x40
297 #define TLAN_NET_STS_TXSTOP 0x20
298 #define TLAN_NET_STS_RXSTOP 0x10
299 #define TLAN_NET_STS_RSRVD 0x0F
300 #define TLAN_NET_MASK 0x03
301 #define TLAN_NET_MASK_MASK7 0x80
302 #define TLAN_NET_MASK_MASK6 0x40
303 #define TLAN_NET_MASK_MASK5 0x20
304 #define TLAN_NET_MASK_MASK4 0x10
305 #define TLAN_NET_MASK_RSRVD 0x0F
306 #define TLAN_NET_CONFIG 0x04
307 #define TLAN_NET_CFG_RCLK 0x8000
308 #define TLAN_NET_CFG_TCLK 0x4000
309 #define TLAN_NET_CFG_BIT 0x2000
310 #define TLAN_NET_CFG_RXCRC 0x1000
311 #define TLAN_NET_CFG_PEF 0x0800
312 #define TLAN_NET_CFG_1FRAG 0x0400
313 #define TLAN_NET_CFG_1CHAN 0x0200
314 #define TLAN_NET_CFG_MTEST 0x0100
315 #define TLAN_NET_CFG_PHY_EN 0x0080
316 #define TLAN_NET_CFG_MSMASK 0x007F
317 #define TLAN_MAN_TEST 0x06
318 #define TLAN_DEF_VENDOR_ID 0x08
319 #define TLAN_DEF_DEVICE_ID 0x0A
320 #define TLAN_DEF_REVISION 0x0C
321 #define TLAN_DEF_SUBCLASS 0x0D
322 #define TLAN_DEF_MIN_LAT 0x0E
323 #define TLAN_DEF_MAX_LAT 0x0F
324 #define TLAN_AREG_0 0x10
325 #define TLAN_AREG_1 0x16
326 #define TLAN_AREG_2 0x1C
327 #define TLAN_AREG_3 0x22
328 #define TLAN_HASH_1 0x28
329 #define TLAN_HASH_2 0x2C
330 #define TLAN_GOOD_TX_FRMS 0x30
331 #define TLAN_TX_UNDERUNS 0x33
332 #define TLAN_GOOD_RX_FRMS 0x34
333 #define TLAN_RX_OVERRUNS 0x37
334 #define TLAN_DEFERRED_TX 0x38
335 #define TLAN_CRC_ERRORS 0x3A
336 #define TLAN_CODE_ERRORS 0x3B
337 #define TLAN_MULTICOL_FRMS 0x3C
338 #define TLAN_SINGLECOL_FRMS 0x3E
339 #define TLAN_EXCESSCOL_FRMS 0x40
340 #define TLAN_LATE_COLS 0x41
341 #define TLAN_CARRIER_LOSS 0x42
342 #define TLAN_ACOMMIT 0x43
343 #define TLAN_LED_REG 0x44
344 #define TLAN_LED_ACT 0x10
345 #define TLAN_LED_LINK 0x01
346 #define TLAN_BSIZE_REG 0x45
347 #define TLAN_MAX_RX 0x46
348 #define TLAN_INT_DIS 0x48
349 #define TLAN_ID_TX_EOC 0x04
350 #define TLAN_ID_RX_EOF 0x02
351 #define TLAN_ID_RX_EOC 0x01
352
353
354
355 /* ThunderLAN Interrupt Codes */
356
357 #define TLAN_INT_NUMBER_OF_INTS 8
358
359 #define TLAN_INT_NONE 0x0000
360 #define TLAN_INT_TX_EOF 0x0001
361 #define TLAN_INT_STAT_OVERFLOW 0x0002
362 #define TLAN_INT_RX_EOF 0x0003
363 #define TLAN_INT_DUMMY 0x0004
364 #define TLAN_INT_TX_EOC 0x0005
365 #define TLAN_INT_STATUS_CHECK 0x0006
366 #define TLAN_INT_RX_EOC 0x0007
367
368
369
370 /* ThunderLAN MII Registers */
371
372 /* Generic MII/PHY Registers */
373
374 #define MII_GEN_CTL 0x00
375 #define MII_GC_RESET 0x8000
376 #define MII_GC_LOOPBK 0x4000
377 #define MII_GC_SPEEDSEL 0x2000
378 #define MII_GC_AUTOENB 0x1000
379 #define MII_GC_PDOWN 0x0800
380 #define MII_GC_ISOLATE 0x0400
381 #define MII_GC_AUTORSRT 0x0200
382 #define MII_GC_DUPLEX 0x0100
383 #define MII_GC_COLTEST 0x0080
384 #define MII_GC_RESERVED 0x007F
385 #define MII_GEN_STS 0x01
386 #define MII_GS_100BT4 0x8000
387 #define MII_GS_100BTXFD 0x4000
388 #define MII_GS_100BTXHD 0x2000
389 #define MII_GS_10BTFD 0x1000
390 #define MII_GS_10BTHD 0x0800
391 #define MII_GS_RESERVED 0x07C0
392 #define MII_GS_AUTOCMPLT 0x0020
393 #define MII_GS_RFLT 0x0010
394 #define MII_GS_AUTONEG 0x0008
395 #define MII_GS_LINK 0x0004
396 #define MII_GS_JABBER 0x0002
397 #define MII_GS_EXTCAP 0x0001
398 #define MII_GEN_ID_HI 0x02
399 #define MII_GEN_ID_LO 0x03
400 #define MII_GIL_OUI 0xFC00
401 #define MII_GIL_MODEL 0x03F0
402 #define MII_GIL_REVISION 0x000F
403 #define MII_AN_ADV 0x04
404 #define MII_AN_LPA 0x05
405 #define MII_AN_EXP 0x06
406
407 /* ThunderLAN Specific MII/PHY Registers */
408
409 #define TLAN_TLPHY_ID 0x10
410 #define TLAN_TLPHY_CTL 0x11
411 #define TLAN_TC_IGLINK 0x8000
412 #define TLAN_TC_SWAPOL 0x4000
413 #define TLAN_TC_AUISEL 0x2000
414 #define TLAN_TC_SQEEN 0x1000
415 #define TLAN_TC_MTEST 0x0800
416 #define TLAN_TC_RESERVED 0x07F8
417 #define TLAN_TC_NFEW 0x0004
418 #define TLAN_TC_INTEN 0x0002
419 #define TLAN_TC_TINT 0x0001
420 #define TLAN_TLPHY_STS 0x12
421 #define TLAN_TS_MINT 0x8000
422 #define TLAN_TS_PHOK 0x4000
423 #define TLAN_TS_POLOK 0x2000
424 #define TLAN_TS_TPENERGY 0x1000
425 #define TLAN_TS_RESERVED 0x0FFF
426 #define TLAN_TLPHY_PAR 0x19
427 #define TLAN_PHY_CIM_STAT 0x0020
428 #define TLAN_PHY_SPEED_100 0x0040
429 #define TLAN_PHY_DUPLEX_FULL 0x0080
430 #define TLAN_PHY_AN_EN_STAT 0x0400
431
432 /* National Sem. & Level1 PHY id's */
433 #define NAT_SEM_ID1 0x2000
434 #define NAT_SEM_ID2 0x5C01
435 #define LEVEL1_ID1 0x7810
436 #define LEVEL1_ID2 0x0000
437
438 #define CIRC_INC( a, b ) if ( ++a >= b ) a = 0
439
440 /* Routines to access internal registers. */
441
442 static inline u8 TLan_DioRead8(u16 base_addr, u16 internal_addr)
443 {
444 outw(internal_addr, base_addr + TLAN_DIO_ADR);
445 return (inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3)));
446
447 } /* TLan_DioRead8 */
448
449
450
451
452 static inline u16 TLan_DioRead16(u16 base_addr, u16 internal_addr)
453 {
454 outw(internal_addr, base_addr + TLAN_DIO_ADR);
455 return (inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2)));
456
457 } /* TLan_DioRead16 */
458
459
460
461
462 static inline u32 TLan_DioRead32(u16 base_addr, u16 internal_addr)
463 {
464 outw(internal_addr, base_addr + TLAN_DIO_ADR);
465 return (inl(base_addr + TLAN_DIO_DATA));
466
467 } /* TLan_DioRead32 */
468
469
470
471
472 static inline void TLan_DioWrite8(u16 base_addr, u16 internal_addr, u8 data)
473 {
474 outw(internal_addr, base_addr + TLAN_DIO_ADR);
475 outb(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x3));
476
477 }
478
479
480
481
482 static inline void TLan_DioWrite16(u16 base_addr, u16 internal_addr, u16 data)
483 {
484 outw(internal_addr, base_addr + TLAN_DIO_ADR);
485 outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
486
487 }
488
489
490
491
492 static inline void TLan_DioWrite32(u16 base_addr, u16 internal_addr, u32 data)
493 {
494 outw(internal_addr, base_addr + TLAN_DIO_ADR);
495 outl(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
496
497 }
498
499 #define TLan_ClearBit( bit, port ) outb_p(inb_p(port) & ~bit, port)
500 #define TLan_GetBit( bit, port ) ((int) (inb_p(port) & bit))
501 #define TLan_SetBit( bit, port ) outb_p(inb_p(port) | bit, port)
502
503 /*
504 * given 6 bytes, view them as 8 6-bit numbers and return the XOR of those
505 * the code below is about seven times as fast as the original code
506 *
507 * The original code was:
508 *
509 * u32 xor( u32 a, u32 b ) { return ( ( a && ! b ) || ( ! a && b ) ); }
510 *
511 * #define XOR8( a, b, c, d, e, f, g, h ) \
512 * xor( a, xor( b, xor( c, xor( d, xor( e, xor( f, xor( g, h ) ) ) ) ) ) )
513 * #define DA( a, bit ) ( ( (u8) a[bit/8] ) & ( (u8) ( 1 << bit%8 ) ) )
514 *
515 * hash = XOR8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24),
516 * DA(a,30), DA(a,36), DA(a,42) );
517 * hash |= XOR8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25),
518 * DA(a,31), DA(a,37), DA(a,43) ) << 1;
519 * hash |= XOR8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26),
520 * DA(a,32), DA(a,38), DA(a,44) ) << 2;
521 * hash |= XOR8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27),
522 * DA(a,33), DA(a,39), DA(a,45) ) << 3;
523 * hash |= XOR8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28),
524 * DA(a,34), DA(a,40), DA(a,46) ) << 4;
525 * hash |= XOR8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29),
526 * DA(a,35), DA(a,41), DA(a,47) ) << 5;
527 *
528 */
529 static inline u32 TLan_HashFunc( const u8 *a )
530 {
531 u8 hash;
532
533 hash = (a[0]^a[3]); /* & 077 */
534 hash ^= ((a[0]^a[3])>>6); /* & 003 */
535 hash ^= ((a[1]^a[4])<<2); /* & 074 */
536 hash ^= ((a[1]^a[4])>>4); /* & 017 */
537 hash ^= ((a[2]^a[5])<<4); /* & 060 */
538 hash ^= ((a[2]^a[5])>>2); /* & 077 */
539
540 return (hash & 077);
541 }
542 #endif
Tomato firmware and modifications.