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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / sunhme.c
blob177bd5f49561185716cc323dc6c4f5c035a16d84
1 /* sunhme.c: Sparc HME/BigMac 10/100baseT half/full duplex auto switching,
2 * auto carrier detecting ethernet driver. Also known as the
3 * "Happy Meal Ethernet" found on SunSwift SBUS cards.
4 *
5 * Copyright (C) 1996, 1998, 1999, 2002, 2003,
6 * 2006, 2008 David S. Miller (davem@davemloft.net)
7 *
8 * Changes :
9 * 2000/11/11 Willy Tarreau <willy AT meta-x.org>
10 * - port to non-sparc architectures. Tested only on x86 and
11 * only currently works with QFE PCI cards.
12 * - ability to specify the MAC address at module load time by passing this
13 * argument : macaddr=0x00,0x10,0x20,0x30,0x40,0x50
14 */
15
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/fcntl.h>
20 #include <linux/interrupt.h>
21 #include <linux/ioport.h>
22 #include <linux/in.h>
23 #include <linux/slab.h>
24 #include <linux/string.h>
25 #include <linux/delay.h>
26 #include <linux/init.h>
27 #include <linux/ethtool.h>
28 #include <linux/mii.h>
29 #include <linux/crc32.h>
30 #include <linux/random.h>
31 #include <linux/errno.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/mm.h>
36 #include <linux/bitops.h>
37 #include <linux/dma-mapping.h>
38
39 #include <asm/system.h>
40 #include <asm/io.h>
41 #include <asm/dma.h>
42 #include <asm/byteorder.h>
43
44 #ifdef CONFIG_SPARC
45 #include <linux/of.h>
46 #include <linux/of_device.h>
47 #include <asm/idprom.h>
48 #include <asm/openprom.h>
49 #include <asm/oplib.h>
50 #include <asm/prom.h>
51 #include <asm/auxio.h>
52 #endif
53 #include <asm/uaccess.h>
54
55 #include <asm/pgtable.h>
56 #include <asm/irq.h>
57
58 #ifdef CONFIG_PCI
59 #include <linux/pci.h>
60 #endif
61
62 #include "sunhme.h"
63
64 #define DRV_NAME "sunhme"
65 #define DRV_VERSION "3.10"
66 #define DRV_RELDATE "August 26, 2008"
67 #define DRV_AUTHOR "David S. Miller (davem@davemloft.net)"
68
69 static char version[] =
70 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
71
72 MODULE_VERSION(DRV_VERSION);
73 MODULE_AUTHOR(DRV_AUTHOR);
74 MODULE_DESCRIPTION("Sun HappyMealEthernet(HME) 10/100baseT ethernet driver");
75 MODULE_LICENSE("GPL");
76
77 static int macaddr[6];
78
79 /* accept MAC address of the form macaddr=0x08,0x00,0x20,0x30,0x40,0x50 */
80 module_param_array(macaddr, int, NULL, 0);
81 MODULE_PARM_DESC(macaddr, "Happy Meal MAC address to set");
82
83 #ifdef CONFIG_SBUS
84 static struct quattro *qfe_sbus_list;
85 #endif
86
87 #ifdef CONFIG_PCI
88 static struct quattro *qfe_pci_list;
89 #endif
90
91 #undef HMEDEBUG
92 #undef SXDEBUG
93 #undef RXDEBUG
94 #undef TXDEBUG
95 #undef TXLOGGING
96
97 #ifdef TXLOGGING
98 struct hme_tx_logent {
99 unsigned int tstamp;
100 int tx_new, tx_old;
101 unsigned int action;
102 #define TXLOG_ACTION_IRQ 0x01
103 #define TXLOG_ACTION_TXMIT 0x02
104 #define TXLOG_ACTION_TBUSY 0x04
105 #define TXLOG_ACTION_NBUFS 0x08
106 unsigned int status;
107 };
108 #define TX_LOG_LEN 128
109 static struct hme_tx_logent tx_log[TX_LOG_LEN];
110 static int txlog_cur_entry;
111 static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
112 {
113 struct hme_tx_logent *tlp;
114 unsigned long flags;
115
116 local_irq_save(flags);
117 tlp = &tx_log[txlog_cur_entry];
118 tlp->tstamp = (unsigned int)jiffies;
119 tlp->tx_new = hp->tx_new;
120 tlp->tx_old = hp->tx_old;
121 tlp->action = a;
122 tlp->status = s;
123 txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1);
124 local_irq_restore(flags);
125 }
126 static __inline__ void tx_dump_log(void)
127 {
128 int i, this;
129
130 this = txlog_cur_entry;
131 for (i = 0; i < TX_LOG_LEN; i++) {
132 printk("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i,
133 tx_log[this].tstamp,
134 tx_log[this].tx_new, tx_log[this].tx_old,
135 tx_log[this].action, tx_log[this].status);
136 this = (this + 1) & (TX_LOG_LEN - 1);
137 }
138 }
139 static __inline__ void tx_dump_ring(struct happy_meal *hp)
140 {
141 struct hmeal_init_block *hb = hp->happy_block;
142 struct happy_meal_txd *tp = &hb->happy_meal_txd[0];
143 int i;
144
145 for (i = 0; i < TX_RING_SIZE; i+=4) {
146 printk("TXD[%d..%d]: [%08x:%08x] [%08x:%08x] [%08x:%08x] [%08x:%08x]\n",
147 i, i + 4,
148 le32_to_cpu(tp[i].tx_flags), le32_to_cpu(tp[i].tx_addr),
149 le32_to_cpu(tp[i + 1].tx_flags), le32_to_cpu(tp[i + 1].tx_addr),
150 le32_to_cpu(tp[i + 2].tx_flags), le32_to_cpu(tp[i + 2].tx_addr),
151 le32_to_cpu(tp[i + 3].tx_flags), le32_to_cpu(tp[i + 3].tx_addr));
152 }
153 }
154 #else
155 #define tx_add_log(hp, a, s) do { } while(0)
156 #define tx_dump_log() do { } while(0)
157 #define tx_dump_ring(hp) do { } while(0)
158 #endif
159
160 #ifdef HMEDEBUG
161 #define HMD(x) printk x
162 #else
163 #define HMD(x)
164 #endif
165
166 /* #define AUTO_SWITCH_DEBUG */
167
168 #ifdef AUTO_SWITCH_DEBUG
169 #define ASD(x) printk x
170 #else
171 #define ASD(x)
172 #endif
173
174 #define DEFAULT_IPG0 16 /* For lance-mode only */
175 #define DEFAULT_IPG1 8 /* For all modes */
176 #define DEFAULT_IPG2 4 /* For all modes */
177 #define DEFAULT_JAMSIZE 4 /* Toe jam */
178
179 /* NOTE: In the descriptor writes one _must_ write the address
180 * member _first_. The card must not be allowed to see
181 * the updated descriptor flags until the address is
182 * correct. I've added a write memory barrier between
183 * the two stores so that I can sleep well at night... -DaveM
184 */
185
186 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
187 static void sbus_hme_write32(void __iomem *reg, u32 val)
188 {
189 sbus_writel(val, reg);
190 }
191
192 static u32 sbus_hme_read32(void __iomem *reg)
193 {
194 return sbus_readl(reg);
195 }
196
197 static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
198 {
199 rxd->rx_addr = (__force hme32)addr;
200 wmb();
201 rxd->rx_flags = (__force hme32)flags;
202 }
203
204 static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
205 {
206 txd->tx_addr = (__force hme32)addr;
207 wmb();
208 txd->tx_flags = (__force hme32)flags;
209 }
210
211 static u32 sbus_hme_read_desc32(hme32 *p)
212 {
213 return (__force u32)*p;
214 }
215
216 static void pci_hme_write32(void __iomem *reg, u32 val)
217 {
218 writel(val, reg);
219 }
220
221 static u32 pci_hme_read32(void __iomem *reg)
222 {
223 return readl(reg);
224 }
225
226 static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
227 {
228 rxd->rx_addr = (__force hme32)cpu_to_le32(addr);
229 wmb();
230 rxd->rx_flags = (__force hme32)cpu_to_le32(flags);
231 }
232
233 static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
234 {
235 txd->tx_addr = (__force hme32)cpu_to_le32(addr);
236 wmb();
237 txd->tx_flags = (__force hme32)cpu_to_le32(flags);
238 }
239
240 static u32 pci_hme_read_desc32(hme32 *p)
241 {
242 return le32_to_cpup((__le32 *)p);
243 }
244
245 #define hme_write32(__hp, __reg, __val) \
246 ((__hp)->write32((__reg), (__val)))
247 #define hme_read32(__hp, __reg) \
248 ((__hp)->read32(__reg))
249 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
250 ((__hp)->write_rxd((__rxd), (__flags), (__addr)))
251 #define hme_write_txd(__hp, __txd, __flags, __addr) \
252 ((__hp)->write_txd((__txd), (__flags), (__addr)))
253 #define hme_read_desc32(__hp, __p) \
254 ((__hp)->read_desc32(__p))
255 #define hme_dma_map(__hp, __ptr, __size, __dir) \
256 ((__hp)->dma_map((__hp)->dma_dev, (__ptr), (__size), (__dir)))
257 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
258 ((__hp)->dma_unmap((__hp)->dma_dev, (__addr), (__size), (__dir)))
259 #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
260 ((__hp)->dma_sync_for_cpu((__hp)->dma_dev, (__addr), (__size), (__dir)))
261 #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
262 ((__hp)->dma_sync_for_device((__hp)->dma_dev, (__addr), (__size), (__dir)))
263 #else
264 #ifdef CONFIG_SBUS
265 /* SBUS only compilation */
266 #define hme_write32(__hp, __reg, __val) \
267 sbus_writel((__val), (__reg))
268 #define hme_read32(__hp, __reg) \
269 sbus_readl(__reg)
270 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
271 do { (__rxd)->rx_addr = (__force hme32)(u32)(__addr); \
272 wmb(); \
273 (__rxd)->rx_flags = (__force hme32)(u32)(__flags); \
274 } while(0)
275 #define hme_write_txd(__hp, __txd, __flags, __addr) \
276 do { (__txd)->tx_addr = (__force hme32)(u32)(__addr); \
277 wmb(); \
278 (__txd)->tx_flags = (__force hme32)(u32)(__flags); \
279 } while(0)
280 #define hme_read_desc32(__hp, __p) ((__force u32)(hme32)*(__p))
281 #define hme_dma_map(__hp, __ptr, __size, __dir) \
282 dma_map_single((__hp)->dma_dev, (__ptr), (__size), (__dir))
283 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
284 dma_unmap_single((__hp)->dma_dev, (__addr), (__size), (__dir))
285 #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
286 dma_dma_sync_single_for_cpu((__hp)->dma_dev, (__addr), (__size), (__dir))
287 #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
288 dma_dma_sync_single_for_device((__hp)->dma_dev, (__addr), (__size), (__dir))
289 #else
290 /* PCI only compilation */
291 #define hme_write32(__hp, __reg, __val) \
292 writel((__val), (__reg))
293 #define hme_read32(__hp, __reg) \
294 readl(__reg)
295 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
296 do { (__rxd)->rx_addr = (__force hme32)cpu_to_le32(__addr); \
297 wmb(); \
298 (__rxd)->rx_flags = (__force hme32)cpu_to_le32(__flags); \
299 } while(0)
300 #define hme_write_txd(__hp, __txd, __flags, __addr) \
301 do { (__txd)->tx_addr = (__force hme32)cpu_to_le32(__addr); \
302 wmb(); \
303 (__txd)->tx_flags = (__force hme32)cpu_to_le32(__flags); \
304 } while(0)
305 static inline u32 hme_read_desc32(struct happy_meal *hp, hme32 *p)
306 {
307 return le32_to_cpup((__le32 *)p);
308 }
309 #define hme_dma_map(__hp, __ptr, __size, __dir) \
310 pci_map_single((__hp)->dma_dev, (__ptr), (__size), (__dir))
311 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
312 pci_unmap_single((__hp)->dma_dev, (__addr), (__size), (__dir))
313 #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
314 pci_dma_sync_single_for_cpu((__hp)->dma_dev, (__addr), (__size), (__dir))
315 #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
316 pci_dma_sync_single_for_device((__hp)->dma_dev, (__addr), (__size), (__dir))
317 #endif
318 #endif
319
320
321 /* Oh yes, the MIF BitBang is mighty fun to program. BitBucket is more like it. */
322 static void BB_PUT_BIT(struct happy_meal *hp, void __iomem *tregs, int bit)
323 {
324 hme_write32(hp, tregs + TCVR_BBDATA, bit);
325 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
326 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
327 }
328
329
330 static u32 BB_GET_BIT2(struct happy_meal *hp, void __iomem *tregs, int internal)
331 {
332 u32 retval;
333
334 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
335 udelay(1);
336 retval = hme_read32(hp, tregs + TCVR_CFG);
337 if (internal)
338 retval &= TCV_CFG_MDIO0;
339 else
340 retval &= TCV_CFG_MDIO1;
341 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
342
343 return retval;
344 }
345
346 #define TCVR_FAILURE 0x80000000 /* Impossible MIF read value */
347
348 static int happy_meal_bb_read(struct happy_meal *hp,
349 void __iomem *tregs, int reg)
350 {
351 u32 tmp;
352 int retval = 0;
353 int i;
354
355 ASD(("happy_meal_bb_read: reg=%d ", reg));
356
357 /* Enable the MIF BitBang outputs. */
358 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
359
360 /* Force BitBang into the idle state. */
361 for (i = 0; i < 32; i++)
362 BB_PUT_BIT(hp, tregs, 1);
363
364 /* Give it the read sequence. */
365 BB_PUT_BIT(hp, tregs, 0);
366 BB_PUT_BIT(hp, tregs, 1);
367 BB_PUT_BIT(hp, tregs, 1);
368 BB_PUT_BIT(hp, tregs, 0);
369
370 /* Give it the PHY address. */
371 tmp = hp->paddr & 0xff;
372 for (i = 4; i >= 0; i--)
373 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
374
375 /* Tell it what register we want to read. */
376 tmp = (reg & 0xff);
377 for (i = 4; i >= 0; i--)
378 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
379
380 /* Close down the MIF BitBang outputs. */
381 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
382
383 /* Now read in the value. */
384 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
385 for (i = 15; i >= 0; i--)
386 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
387 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
388 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
389 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
390 ASD(("value=%x\n", retval));
391 return retval;
392 }
393
394 static void happy_meal_bb_write(struct happy_meal *hp,
395 void __iomem *tregs, int reg,
396 unsigned short value)
397 {
398 u32 tmp;
399 int i;
400
401 ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value));
402
403 /* Enable the MIF BitBang outputs. */
404 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
405
406 /* Force BitBang into the idle state. */
407 for (i = 0; i < 32; i++)
408 BB_PUT_BIT(hp, tregs, 1);
409
410 /* Give it write sequence. */
411 BB_PUT_BIT(hp, tregs, 0);
412 BB_PUT_BIT(hp, tregs, 1);
413 BB_PUT_BIT(hp, tregs, 0);
414 BB_PUT_BIT(hp, tregs, 1);
415
416 /* Give it the PHY address. */
417 tmp = (hp->paddr & 0xff);
418 for (i = 4; i >= 0; i--)
419 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
420
421 /* Tell it what register we will be writing. */
422 tmp = (reg & 0xff);
423 for (i = 4; i >= 0; i--)
424 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
425
426 /* Tell it to become ready for the bits. */
427 BB_PUT_BIT(hp, tregs, 1);
428 BB_PUT_BIT(hp, tregs, 0);
429
430 for (i = 15; i >= 0; i--)
431 BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
432
433 /* Close down the MIF BitBang outputs. */
434 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
435 }
436
437 #define TCVR_READ_TRIES 16
438
439 static int happy_meal_tcvr_read(struct happy_meal *hp,
440 void __iomem *tregs, int reg)
441 {
442 int tries = TCVR_READ_TRIES;
443 int retval;
444
445 ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg));
446 if (hp->tcvr_type == none) {
447 ASD(("no transceiver, value=TCVR_FAILURE\n"));
448 return TCVR_FAILURE;
449 }
450
451 if (!(hp->happy_flags & HFLAG_FENABLE)) {
452 ASD(("doing bit bang\n"));
453 return happy_meal_bb_read(hp, tregs, reg);
454 }
455
456 hme_write32(hp, tregs + TCVR_FRAME,
457 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
458 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
459 udelay(20);
460 if (!tries) {
461 printk(KERN_ERR "happy meal: Aieee, transceiver MIF read bolixed\n");
462 return TCVR_FAILURE;
463 }
464 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
465 ASD(("value=%04x\n", retval));
466 return retval;
467 }
468
469 #define TCVR_WRITE_TRIES 16
470
471 static void happy_meal_tcvr_write(struct happy_meal *hp,
472 void __iomem *tregs, int reg,
473 unsigned short value)
474 {
475 int tries = TCVR_WRITE_TRIES;
476
477 ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value));
478
479 /* Welcome to Sun Microsystems, can I take your order please? */
480 if (!(hp->happy_flags & HFLAG_FENABLE)) {
481 happy_meal_bb_write(hp, tregs, reg, value);
482 return;
483 }
484
485 /* Would you like fries with that? */
486 hme_write32(hp, tregs + TCVR_FRAME,
487 (FRAME_WRITE | (hp->paddr << 23) |
488 ((reg & 0xff) << 18) | (value & 0xffff)));
489 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
490 udelay(20);
491
492 /* Anything else? */
493 if (!tries)
494 printk(KERN_ERR "happy meal: Aieee, transceiver MIF write bolixed\n");
495
496 /* Fifty-two cents is your change, have a nice day. */
497 }
498
499 /* Auto negotiation. The scheme is very simple. We have a timer routine
500 * that keeps watching the auto negotiation process as it progresses.
501 * The DP83840 is first told to start doing it's thing, we set up the time
502 * and place the timer state machine in it's initial state.
503 *
504 * Here the timer peeks at the DP83840 status registers at each click to see
505 * if the auto negotiation has completed, we assume here that the DP83840 PHY
506 * will time out at some point and just tell us what (didn't) happen. For
507 * complete coverage we only allow so many of the ticks at this level to run,
508 * when this has expired we print a warning message and try another strategy.
509 * This "other" strategy is to force the interface into various speed/duplex
510 * configurations and we stop when we see a link-up condition before the
511 * maximum number of "peek" ticks have occurred.
512 *
513 * Once a valid link status has been detected we configure the BigMAC and
514 * the rest of the Happy Meal to speak the most efficient protocol we could
515 * get a clean link for. The priority for link configurations, highest first
516 * is:
517 * 100 Base-T Full Duplex
518 * 100 Base-T Half Duplex
519 * 10 Base-T Full Duplex
520 * 10 Base-T Half Duplex
521 *
522 * We start a new timer now, after a successful auto negotiation status has
523 * been detected. This timer just waits for the link-up bit to get set in
524 * the BMCR of the DP83840. When this occurs we print a kernel log message
525 * describing the link type in use and the fact that it is up.
526 *
527 * If a fatal error of some sort is signalled and detected in the interrupt
528 * service routine, and the chip is reset, or the link is ifconfig'd down
529 * and then back up, this entire process repeats itself all over again.
530 */
531 static int try_next_permutation(struct happy_meal *hp, void __iomem *tregs)
532 {
533 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
534
535 /* Downgrade from full to half duplex. Only possible
536 * via ethtool.
537 */
538 if (hp->sw_bmcr & BMCR_FULLDPLX) {
539 hp->sw_bmcr &= ~(BMCR_FULLDPLX);
540 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
541 return 0;
542 }
543
544 /* Downgrade from 100 to 10. */
545 if (hp->sw_bmcr & BMCR_SPEED100) {
546 hp->sw_bmcr &= ~(BMCR_SPEED100);
547 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
548 return 0;
549 }
550
551 /* We've tried everything. */
552 return -1;
553 }
554
555 static void display_link_mode(struct happy_meal *hp, void __iomem *tregs)
556 {
557 printk(KERN_INFO "%s: Link is up using ", hp->dev->name);
558 if (hp->tcvr_type == external)
559 printk("external ");
560 else
561 printk("internal ");
562 printk("transceiver at ");
563 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
564 if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) {
565 if (hp->sw_lpa & LPA_100FULL)
566 printk("100Mb/s, Full Duplex.\n");
567 else
568 printk("100Mb/s, Half Duplex.\n");
569 } else {
570 if (hp->sw_lpa & LPA_10FULL)
571 printk("10Mb/s, Full Duplex.\n");
572 else
573 printk("10Mb/s, Half Duplex.\n");
574 }
575 }
576
577 static void display_forced_link_mode(struct happy_meal *hp, void __iomem *tregs)
578 {
579 printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name);
580 if (hp->tcvr_type == external)
581 printk("external ");
582 else
583 printk("internal ");
584 printk("transceiver at ");
585 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
586 if (hp->sw_bmcr & BMCR_SPEED100)
587 printk("100Mb/s, ");
588 else
589 printk("10Mb/s, ");
590 if (hp->sw_bmcr & BMCR_FULLDPLX)
591 printk("Full Duplex.\n");
592 else
593 printk("Half Duplex.\n");
594 }
595
596 static int set_happy_link_modes(struct happy_meal *hp, void __iomem *tregs)
597 {
598 int full;
599
600 /* All we care about is making sure the bigmac tx_cfg has a
601 * proper duplex setting.
602 */
603 if (hp->timer_state == arbwait) {
604 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
605 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
606 goto no_response;
607 if (hp->sw_lpa & LPA_100FULL)
608 full = 1;
609 else if (hp->sw_lpa & LPA_100HALF)
610 full = 0;
611 else if (hp->sw_lpa & LPA_10FULL)
612 full = 1;
613 else
614 full = 0;
615 } else {
616 /* Forcing a link mode. */
617 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
618 if (hp->sw_bmcr & BMCR_FULLDPLX)
619 full = 1;
620 else
621 full = 0;
622 }
623
624 /* Before changing other bits in the tx_cfg register, and in
625 * general any of other the TX config registers too, you
626 * must:
627 * 1) Clear Enable
628 * 2) Poll with reads until that bit reads back as zero
629 * 3) Make TX configuration changes
630 * 4) Set Enable once more
631 */
632 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
633 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
634 ~(BIGMAC_TXCFG_ENABLE));
635 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
636 barrier();
637 if (full) {
638 hp->happy_flags |= HFLAG_FULL;
639 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
640 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
641 BIGMAC_TXCFG_FULLDPLX);
642 } else {
643 hp->happy_flags &= ~(HFLAG_FULL);
644 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
645 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
646 ~(BIGMAC_TXCFG_FULLDPLX));
647 }
648 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
649 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
650 BIGMAC_TXCFG_ENABLE);
651 return 0;
652 no_response:
653 return 1;
654 }
655
656 static int happy_meal_init(struct happy_meal *hp);
657
658 static int is_lucent_phy(struct happy_meal *hp)
659 {
660 void __iomem *tregs = hp->tcvregs;
661 unsigned short mr2, mr3;
662 int ret = 0;
663
664 mr2 = happy_meal_tcvr_read(hp, tregs, 2);
665 mr3 = happy_meal_tcvr_read(hp, tregs, 3);
666 if ((mr2 & 0xffff) == 0x0180 &&
667 ((mr3 & 0xffff) >> 10) == 0x1d)
668 ret = 1;
669
670 return ret;
671 }
672
673 static void happy_meal_timer(unsigned long data)
674 {
675 struct happy_meal *hp = (struct happy_meal *) data;
676 void __iomem *tregs = hp->tcvregs;
677 int restart_timer = 0;
678
679 spin_lock_irq(&hp->happy_lock);
680
681 hp->timer_ticks++;
682 switch(hp->timer_state) {
683 case arbwait:
684 /* Only allow for 5 ticks, thats 10 seconds and much too
685 * long to wait for arbitration to complete.
686 */
687 if (hp->timer_ticks >= 10) {
688 /* Enter force mode. */
689 do_force_mode:
690 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
691 printk(KERN_NOTICE "%s: Auto-Negotiation unsuccessful, trying force link mode\n",
692 hp->dev->name);
693 hp->sw_bmcr = BMCR_SPEED100;
694 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
695
696 if (!is_lucent_phy(hp)) {
697 /* OK, seems we need do disable the transceiver for the first
698 * tick to make sure we get an accurate link state at the
699 * second tick.
700 */
701 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
702 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
703 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
704 }
705 hp->timer_state = ltrywait;
706 hp->timer_ticks = 0;
707 restart_timer = 1;
708 } else {
709 /* Anything interesting happen? */
710 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
711 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
712 int ret;
713
714 /* Just what we've been waiting for... */
715 ret = set_happy_link_modes(hp, tregs);
716 if (ret) {
717 goto do_force_mode;
718 }
719
720 /* Success, at least so far, advance our state engine. */
721 hp->timer_state = lupwait;
722 restart_timer = 1;
723 } else {
724 restart_timer = 1;
725 }
726 }
727 break;
728
729 case lupwait:
730 /* Auto negotiation was successful and we are awaiting a
731 * link up status. I have decided to let this timer run
732 * forever until some sort of error is signalled, reporting
733 * a message to the user at 10 second intervals.
734 */
735 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
736 if (hp->sw_bmsr & BMSR_LSTATUS) {
737 /* Wheee, it's up, display the link mode in use and put
738 * the timer to sleep.
739 */
740 display_link_mode(hp, tregs);
741 hp->timer_state = asleep;
742 restart_timer = 0;
743 } else {
744 if (hp->timer_ticks >= 10) {
745 printk(KERN_NOTICE "%s: Auto negotiation successful, link still "
746 "not completely up.\n", hp->dev->name);
747 hp->timer_ticks = 0;
748 restart_timer = 1;
749 } else {
750 restart_timer = 1;
751 }
752 }
753 break;
754
755 case ltrywait:
756 /* Making the timeout here too long can make it take
757 * annoyingly long to attempt all of the link mode
758 * permutations, but then again this is essentially
759 * error recovery code for the most part.
760 */
761 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
762 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
763 if (hp->timer_ticks == 1) {
764 if (!is_lucent_phy(hp)) {
765 /* Re-enable transceiver, we'll re-enable the transceiver next
766 * tick, then check link state on the following tick.
767 */
768 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
769 happy_meal_tcvr_write(hp, tregs,
770 DP83840_CSCONFIG, hp->sw_csconfig);
771 }
772 restart_timer = 1;
773 break;
774 }
775 if (hp->timer_ticks == 2) {
776 if (!is_lucent_phy(hp)) {
777 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
778 happy_meal_tcvr_write(hp, tregs,
779 DP83840_CSCONFIG, hp->sw_csconfig);
780 }
781 restart_timer = 1;
782 break;
783 }
784 if (hp->sw_bmsr & BMSR_LSTATUS) {
785 /* Force mode selection success. */
786 display_forced_link_mode(hp, tregs);
787 set_happy_link_modes(hp, tregs);
788 hp->timer_state = asleep;
789 restart_timer = 0;
790 } else {
791 if (hp->timer_ticks >= 4) { /* 6 seconds or so... */
792 int ret;
793
794 ret = try_next_permutation(hp, tregs);
795 if (ret == -1) {
796 /* Aieee, tried them all, reset the
797 * chip and try all over again.
798 */
799
800 /* Let the user know... */
801 printk(KERN_NOTICE "%s: Link down, cable problem?\n",
802 hp->dev->name);
803
804 ret = happy_meal_init(hp);
805 if (ret) {
806 /* ho hum... */
807 printk(KERN_ERR "%s: Error, cannot re-init the "
808 "Happy Meal.\n", hp->dev->name);
809 }
810 goto out;
811 }
812 if (!is_lucent_phy(hp)) {
813 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
814 DP83840_CSCONFIG);
815 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
816 happy_meal_tcvr_write(hp, tregs,
817 DP83840_CSCONFIG, hp->sw_csconfig);
818 }
819 hp->timer_ticks = 0;
820 restart_timer = 1;
821 } else {
822 restart_timer = 1;
823 }
824 }
825 break;
826
827 case asleep:
828 default:
829 /* Can't happens.... */
830 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
831 hp->dev->name);
832 restart_timer = 0;
833 hp->timer_ticks = 0;
834 hp->timer_state = asleep; /* foo on you */
835 break;
836 }
837
838 if (restart_timer) {
839 hp->happy_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
840 add_timer(&hp->happy_timer);
841 }
842
843 out:
844 spin_unlock_irq(&hp->happy_lock);
845 }
846
847 #define TX_RESET_TRIES 32
848 #define RX_RESET_TRIES 32
849
850 /* hp->happy_lock must be held */
851 static void happy_meal_tx_reset(struct happy_meal *hp, void __iomem *bregs)
852 {
853 int tries = TX_RESET_TRIES;
854
855 HMD(("happy_meal_tx_reset: reset, "));
856
857 /* Would you like to try our SMCC Delux? */
858 hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
859 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
860 udelay(20);
861
862 /* Lettuce, tomato, buggy hardware (no extra charge)? */
863 if (!tries)
864 printk(KERN_ERR "happy meal: Transceiver BigMac ATTACK!");
865
866 /* Take care. */
867 HMD(("done\n"));
868 }
869
870 /* hp->happy_lock must be held */
871 static void happy_meal_rx_reset(struct happy_meal *hp, void __iomem *bregs)
872 {
873 int tries = RX_RESET_TRIES;
874
875 HMD(("happy_meal_rx_reset: reset, "));
876
877 /* We have a special on GNU/Viking hardware bugs today. */
878 hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
879 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
880 udelay(20);
881
882 /* Will that be all? */
883 if (!tries)
884 printk(KERN_ERR "happy meal: Receiver BigMac ATTACK!");
885
886 /* Don't forget your vik_1137125_wa. Have a nice day. */
887 HMD(("done\n"));
888 }
889
890 #define STOP_TRIES 16
891
892 /* hp->happy_lock must be held */
893 static void happy_meal_stop(struct happy_meal *hp, void __iomem *gregs)
894 {
895 int tries = STOP_TRIES;
896
897 HMD(("happy_meal_stop: reset, "));
898
899 /* We're consolidating our STB products, it's your lucky day. */
900 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
901 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
902 udelay(20);
903
904 /* Come back next week when we are "Sun Microelectronics". */
905 if (!tries)
906 printk(KERN_ERR "happy meal: Fry guys.");
907
908 /* Remember: "Different name, same old buggy as shit hardware." */
909 HMD(("done\n"));
910 }
911
912 /* hp->happy_lock must be held */
913 static void happy_meal_get_counters(struct happy_meal *hp, void __iomem *bregs)
914 {
915 struct net_device_stats *stats = &hp->net_stats;
916
917 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
918 hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
919
920 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
921 hme_write32(hp, bregs + BMAC_UNALECTR, 0);
922
923 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
924 hme_write32(hp, bregs + BMAC_GLECTR, 0);
925
926 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
927
928 stats->collisions +=
929 (hme_read32(hp, bregs + BMAC_EXCTR) +
930 hme_read32(hp, bregs + BMAC_LTCTR));
931 hme_write32(hp, bregs + BMAC_EXCTR, 0);
932 hme_write32(hp, bregs + BMAC_LTCTR, 0);
933 }
934
935 /* hp->happy_lock must be held */
936 static void happy_meal_poll_stop(struct happy_meal *hp, void __iomem *tregs)
937 {
938 ASD(("happy_meal_poll_stop: "));
939
940 /* If polling disabled or not polling already, nothing to do. */
941 if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) !=
942 (HFLAG_POLLENABLE | HFLAG_POLL)) {
943 HMD(("not polling, return\n"));
944 return;
945 }
946
947 /* Shut up the MIF. */
948 ASD(("were polling, mif ints off, "));
949 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
950
951 /* Turn off polling. */
952 ASD(("polling off, "));
953 hme_write32(hp, tregs + TCVR_CFG,
954 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE));
955
956 /* We are no longer polling. */
957 hp->happy_flags &= ~(HFLAG_POLL);
958
959 /* Let the bits set. */
960 udelay(200);
961 ASD(("done\n"));
962 }
963
964 /* Only Sun can take such nice parts and fuck up the programming interface
965 * like this. Good job guys...
966 */
967 #define TCVR_RESET_TRIES 16 /* It should reset quickly */
968 #define TCVR_UNISOLATE_TRIES 32 /* Dis-isolation can take longer. */
969
970 /* hp->happy_lock must be held */
971 static int happy_meal_tcvr_reset(struct happy_meal *hp, void __iomem *tregs)
972 {
973 u32 tconfig;
974 int result, tries = TCVR_RESET_TRIES;
975
976 tconfig = hme_read32(hp, tregs + TCVR_CFG);
977 ASD(("happy_meal_tcvr_reset: tcfg<%08lx> ", tconfig));
978 if (hp->tcvr_type == external) {
979 ASD(("external<"));
980 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
981 hp->tcvr_type = internal;
982 hp->paddr = TCV_PADDR_ITX;
983 ASD(("ISOLATE,"));
984 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
985 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
986 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
987 if (result == TCVR_FAILURE) {
988 ASD(("phyread_fail>\n"));
989 return -1;
990 }
991 ASD(("phyread_ok,PSELECT>"));
992 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
993 hp->tcvr_type = external;
994 hp->paddr = TCV_PADDR_ETX;
995 } else {
996 if (tconfig & TCV_CFG_MDIO1) {
997 ASD(("internal<PSELECT,"));
998 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
999 ASD(("ISOLATE,"));
1000 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1001 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1002 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1003 if (result == TCVR_FAILURE) {
1004 ASD(("phyread_fail>\n"));
1005 return -1;
1006 }
1007 ASD(("phyread_ok,~PSELECT>"));
1008 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
1009 hp->tcvr_type = internal;
1010 hp->paddr = TCV_PADDR_ITX;
1011 }
1012 }
1013
1014 ASD(("BMCR_RESET "));
1015 happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET);
1016
1017 while (--tries) {
1018 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1019 if (result == TCVR_FAILURE)
1020 return -1;
1021 hp->sw_bmcr = result;
1022 if (!(result & BMCR_RESET))
1023 break;
1024 udelay(20);
1025 }
1026 if (!tries) {
1027 ASD(("BMCR RESET FAILED!\n"));
1028 return -1;
1029 }
1030 ASD(("RESET_OK\n"));
1031
1032 /* Get fresh copies of the PHY registers. */
1033 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1034 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1035 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1036 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1037
1038 ASD(("UNISOLATE"));
1039 hp->sw_bmcr &= ~(BMCR_ISOLATE);
1040 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1041
1042 tries = TCVR_UNISOLATE_TRIES;
1043 while (--tries) {
1044 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1045 if (result == TCVR_FAILURE)
1046 return -1;
1047 if (!(result & BMCR_ISOLATE))
1048 break;
1049 udelay(20);
1050 }
1051 if (!tries) {
1052 ASD((" FAILED!\n"));
1053 return -1;
1054 }
1055 ASD((" SUCCESS and CSCONFIG_DFBYPASS\n"));
1056 if (!is_lucent_phy(hp)) {
1057 result = happy_meal_tcvr_read(hp, tregs,
1058 DP83840_CSCONFIG);
1059 happy_meal_tcvr_write(hp, tregs,
1060 DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS));
1061 }
1062 return 0;
1063 }
1064
1065 /* Figure out whether we have an internal or external transceiver.
1066 *
1067 * hp->happy_lock must be held
1068 */
1069 static void happy_meal_transceiver_check(struct happy_meal *hp, void __iomem *tregs)
1070 {
1071 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
1072
1073 ASD(("happy_meal_transceiver_check: tcfg=%08lx ", tconfig));
1074 if (hp->happy_flags & HFLAG_POLL) {
1075 /* If we are polling, we must stop to get the transceiver type. */
1076 ASD(("<polling> "));
1077 if (hp->tcvr_type == internal) {
1078 if (tconfig & TCV_CFG_MDIO1) {
1079 ASD(("<internal> <poll stop> "));
1080 happy_meal_poll_stop(hp, tregs);
1081 hp->paddr = TCV_PADDR_ETX;
1082 hp->tcvr_type = external;
1083 ASD(("<external>\n"));
1084 tconfig &= ~(TCV_CFG_PENABLE);
1085 tconfig |= TCV_CFG_PSELECT;
1086 hme_write32(hp, tregs + TCVR_CFG, tconfig);
1087 }
1088 } else {
1089 if (hp->tcvr_type == external) {
1090 ASD(("<external> "));
1091 if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) {
1092 ASD(("<poll stop> "));
1093 happy_meal_poll_stop(hp, tregs);
1094 hp->paddr = TCV_PADDR_ITX;
1095 hp->tcvr_type = internal;
1096 ASD(("<internal>\n"));
1097 hme_write32(hp, tregs + TCVR_CFG,
1098 hme_read32(hp, tregs + TCVR_CFG) &
1099 ~(TCV_CFG_PSELECT));
1100 }
1101 ASD(("\n"));
1102 } else {
1103 ASD(("<none>\n"));
1104 }
1105 }
1106 } else {
1107 u32 reread = hme_read32(hp, tregs + TCVR_CFG);
1108
1109 /* Else we can just work off of the MDIO bits. */
1110 ASD(("<not polling> "));
1111 if (reread & TCV_CFG_MDIO1) {
1112 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1113 hp->paddr = TCV_PADDR_ETX;
1114 hp->tcvr_type = external;
1115 ASD(("<external>\n"));
1116 } else {
1117 if (reread & TCV_CFG_MDIO0) {
1118 hme_write32(hp, tregs + TCVR_CFG,
1119 tconfig & ~(TCV_CFG_PSELECT));
1120 hp->paddr = TCV_PADDR_ITX;
1121 hp->tcvr_type = internal;
1122 ASD(("<internal>\n"));
1123 } else {
1124 printk(KERN_ERR "happy meal: Transceiver and a coke please.");
1125 hp->tcvr_type = none; /* Grrr... */
1126 ASD(("<none>\n"));
1127 }
1128 }
1129 }
1130 }
1131
1132 /* The receive ring buffers are a bit tricky to get right. Here goes...
1133 *
1134 * The buffers we dma into must be 64 byte aligned. So we use a special
1135 * alloc_skb() routine for the happy meal to allocate 64 bytes more than
1136 * we really need.
1137 *
1138 * We use skb_reserve() to align the data block we get in the skb. We
1139 * also program the etxregs->cfg register to use an offset of 2. This
1140 * imperical constant plus the ethernet header size will always leave
1141 * us with a nicely aligned ip header once we pass things up to the
1142 * protocol layers.
1143 *
1144 * The numbers work out to:
1145 *
1146 * Max ethernet frame size 1518
1147 * Ethernet header size 14
1148 * Happy Meal base offset 2
1149 *
1150 * Say a skb data area is at 0xf001b010, and its size alloced is
1151 * (ETH_FRAME_LEN + 64 + 2) = (1514 + 64 + 2) = 1580 bytes.
1152 *
1153 * First our alloc_skb() routine aligns the data base to a 64 byte
1154 * boundary. We now have 0xf001b040 as our skb data address. We
1155 * plug this into the receive descriptor address.
1156 *
1157 * Next, we skb_reserve() 2 bytes to account for the Happy Meal offset.
1158 * So now the data we will end up looking at starts at 0xf001b042. When
1159 * the packet arrives, we will check out the size received and subtract
1160 * this from the skb->length. Then we just pass the packet up to the
1161 * protocols as is, and allocate a new skb to replace this slot we have
1162 * just received from.
1163 *
1164 * The ethernet layer will strip the ether header from the front of the
1165 * skb we just sent to it, this leaves us with the ip header sitting
1166 * nicely aligned at 0xf001b050. Also, for tcp and udp packets the
1167 * Happy Meal has even checksummed the tcp/udp data for us. The 16
1168 * bit checksum is obtained from the low bits of the receive descriptor
1169 * flags, thus:
1170 *
1171 * skb->csum = rxd->rx_flags & 0xffff;
1172 * skb->ip_summed = CHECKSUM_COMPLETE;
1173 *
1174 * before sending off the skb to the protocols, and we are good as gold.
1175 */
1176 static void happy_meal_clean_rings(struct happy_meal *hp)
1177 {
1178 int i;
1179
1180 for (i = 0; i < RX_RING_SIZE; i++) {
1181 if (hp->rx_skbs[i] != NULL) {
1182 struct sk_buff *skb = hp->rx_skbs[i];
1183 struct happy_meal_rxd *rxd;
1184 u32 dma_addr;
1185
1186 rxd = &hp->happy_block->happy_meal_rxd[i];
1187 dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
1188 dma_unmap_single(hp->dma_dev, dma_addr,
1189 RX_BUF_ALLOC_SIZE, DMA_FROM_DEVICE);
1190 dev_kfree_skb_any(skb);
1191 hp->rx_skbs[i] = NULL;
1192 }
1193 }
1194
1195 for (i = 0; i < TX_RING_SIZE; i++) {
1196 if (hp->tx_skbs[i] != NULL) {
1197 struct sk_buff *skb = hp->tx_skbs[i];
1198 struct happy_meal_txd *txd;
1199 u32 dma_addr;
1200 int frag;
1201
1202 hp->tx_skbs[i] = NULL;
1203
1204 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1205 txd = &hp->happy_block->happy_meal_txd[i];
1206 dma_addr = hme_read_desc32(hp, &txd->tx_addr);
1207 if (!frag)
1208 dma_unmap_single(hp->dma_dev, dma_addr,
1209 (hme_read_desc32(hp, &txd->tx_flags)
1210 & TXFLAG_SIZE),
1211 DMA_TO_DEVICE);
1212 else
1213 dma_unmap_page(hp->dma_dev, dma_addr,
1214 (hme_read_desc32(hp, &txd->tx_flags)
1215 & TXFLAG_SIZE),
1216 DMA_TO_DEVICE);
1217
1218 if (frag != skb_shinfo(skb)->nr_frags)
1219 i++;
1220 }
1221
1222 dev_kfree_skb_any(skb);
1223 }
1224 }
1225 }
1226
1227 /* hp->happy_lock must be held */
1228 static void happy_meal_init_rings(struct happy_meal *hp)
1229 {
1230 struct hmeal_init_block *hb = hp->happy_block;
1231 struct net_device *dev = hp->dev;
1232 int i;
1233
1234 HMD(("happy_meal_init_rings: counters to zero, "));
1235 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
1236
1237 /* Free any skippy bufs left around in the rings. */
1238 HMD(("clean, "));
1239 happy_meal_clean_rings(hp);
1240
1241 /* Now get new skippy bufs for the receive ring. */
1242 HMD(("init rxring, "));
1243 for (i = 0; i < RX_RING_SIZE; i++) {
1244 struct sk_buff *skb;
1245
1246 skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
1247 if (!skb) {
1248 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1249 continue;
1250 }
1251 hp->rx_skbs[i] = skb;
1252 skb->dev = dev;
1253
1254 /* Because we reserve afterwards. */
1255 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET + 4));
1256 hme_write_rxd(hp, &hb->happy_meal_rxd[i],
1257 (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)),
1258 dma_map_single(hp->dma_dev, skb->data, RX_BUF_ALLOC_SIZE,
1259 DMA_FROM_DEVICE));
1260 skb_reserve(skb, RX_OFFSET);
1261 }
1262
1263 HMD(("init txring, "));
1264 for (i = 0; i < TX_RING_SIZE; i++)
1265 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
1266
1267 HMD(("done\n"));
1268 }
1269
1270 /* hp->happy_lock must be held */
1271 static void happy_meal_begin_auto_negotiation(struct happy_meal *hp,
1272 void __iomem *tregs,
1273 struct ethtool_cmd *ep)
1274 {
1275 int timeout;
1276
1277 /* Read all of the registers we are interested in now. */
1278 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1279 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1280 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1281 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1282
1283
1284 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1285 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1286 /* Advertise everything we can support. */
1287 if (hp->sw_bmsr & BMSR_10HALF)
1288 hp->sw_advertise |= (ADVERTISE_10HALF);
1289 else
1290 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1291
1292 if (hp->sw_bmsr & BMSR_10FULL)
1293 hp->sw_advertise |= (ADVERTISE_10FULL);
1294 else
1295 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1296 if (hp->sw_bmsr & BMSR_100HALF)
1297 hp->sw_advertise |= (ADVERTISE_100HALF);
1298 else
1299 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1300 if (hp->sw_bmsr & BMSR_100FULL)
1301 hp->sw_advertise |= (ADVERTISE_100FULL);
1302 else
1303 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1304 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1305
1306
1307 #ifdef AUTO_SWITCH_DEBUG
1308 ASD(("%s: Advertising [ ", hp->dev->name));
1309 if (hp->sw_advertise & ADVERTISE_10HALF)
1310 ASD(("10H "));
1311 if (hp->sw_advertise & ADVERTISE_10FULL)
1312 ASD(("10F "));
1313 if (hp->sw_advertise & ADVERTISE_100HALF)
1314 ASD(("100H "));
1315 if (hp->sw_advertise & ADVERTISE_100FULL)
1316 ASD(("100F "));
1317 #endif
1318
1319 /* Enable Auto-Negotiation, this is usually on already... */
1320 hp->sw_bmcr |= BMCR_ANENABLE;
1321 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1322
1323 /* Restart it to make sure it is going. */
1324 hp->sw_bmcr |= BMCR_ANRESTART;
1325 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1326
1327 /* BMCR_ANRESTART self clears when the process has begun. */
1328
1329 timeout = 64; /* More than enough. */
1330 while (--timeout) {
1331 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1332 if (!(hp->sw_bmcr & BMCR_ANRESTART))
1333 break; /* got it. */
1334 udelay(10);
1335 }
1336 if (!timeout) {
1337 printk(KERN_ERR "%s: Happy Meal would not start auto negotiation "
1338 "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr);
1339 printk(KERN_NOTICE "%s: Performing force link detection.\n",
1340 hp->dev->name);
1341 goto force_link;
1342 } else {
1343 hp->timer_state = arbwait;
1344 }
1345 } else {
1346 force_link:
1347 /* Force the link up, trying first a particular mode.
1348 * Either we are here at the request of ethtool or
1349 * because the Happy Meal would not start to autoneg.
1350 */
1351
1352 /* Disable auto-negotiation in BMCR, enable the duplex and
1353 * speed setting, init the timer state machine, and fire it off.
1354 */
1355 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1356 hp->sw_bmcr = BMCR_SPEED100;
1357 } else {
1358 if (ep->speed == SPEED_100)
1359 hp->sw_bmcr = BMCR_SPEED100;
1360 else
1361 hp->sw_bmcr = 0;
1362 if (ep->duplex == DUPLEX_FULL)
1363 hp->sw_bmcr |= BMCR_FULLDPLX;
1364 }
1365 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1366
1367 if (!is_lucent_phy(hp)) {
1368 /* OK, seems we need do disable the transceiver for the first
1369 * tick to make sure we get an accurate link state at the
1370 * second tick.
1371 */
1372 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
1373 DP83840_CSCONFIG);
1374 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
1375 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
1376 hp->sw_csconfig);
1377 }
1378 hp->timer_state = ltrywait;
1379 }
1380
1381 hp->timer_ticks = 0;
1382 hp->happy_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
1383 hp->happy_timer.data = (unsigned long) hp;
1384 hp->happy_timer.function = &happy_meal_timer;
1385 add_timer(&hp->happy_timer);
1386 }
1387
1388 /* hp->happy_lock must be held */
1389 static int happy_meal_init(struct happy_meal *hp)
1390 {
1391 void __iomem *gregs = hp->gregs;
1392 void __iomem *etxregs = hp->etxregs;
1393 void __iomem *erxregs = hp->erxregs;
1394 void __iomem *bregs = hp->bigmacregs;
1395 void __iomem *tregs = hp->tcvregs;
1396 u32 regtmp, rxcfg;
1397 unsigned char *e = &hp->dev->dev_addr[0];
1398
1399 /* If auto-negotiation timer is running, kill it. */
1400 del_timer(&hp->happy_timer);
1401
1402 HMD(("happy_meal_init: happy_flags[%08x] ",
1403 hp->happy_flags));
1404 if (!(hp->happy_flags & HFLAG_INIT)) {
1405 HMD(("set HFLAG_INIT, "));
1406 hp->happy_flags |= HFLAG_INIT;
1407 happy_meal_get_counters(hp, bregs);
1408 }
1409
1410 /* Stop polling. */
1411 HMD(("to happy_meal_poll_stop\n"));
1412 happy_meal_poll_stop(hp, tregs);
1413
1414 /* Stop transmitter and receiver. */
1415 HMD(("happy_meal_init: to happy_meal_stop\n"));
1416 happy_meal_stop(hp, gregs);
1417
1418 /* Alloc and reset the tx/rx descriptor chains. */
1419 HMD(("happy_meal_init: to happy_meal_init_rings\n"));
1420 happy_meal_init_rings(hp);
1421
1422 /* Shut up the MIF. */
1423 HMD(("happy_meal_init: Disable all MIF irqs (old[%08x]), ",
1424 hme_read32(hp, tregs + TCVR_IMASK)));
1425 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1426
1427 /* See if we can enable the MIF frame on this card to speak to the DP83840. */
1428 if (hp->happy_flags & HFLAG_FENABLE) {
1429 HMD(("use frame old[%08x], ",
1430 hme_read32(hp, tregs + TCVR_CFG)));
1431 hme_write32(hp, tregs + TCVR_CFG,
1432 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1433 } else {
1434 HMD(("use bitbang old[%08x], ",
1435 hme_read32(hp, tregs + TCVR_CFG)));
1436 hme_write32(hp, tregs + TCVR_CFG,
1437 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1438 }
1439
1440 /* Check the state of the transceiver. */
1441 HMD(("to happy_meal_transceiver_check\n"));
1442 happy_meal_transceiver_check(hp, tregs);
1443
1444 /* Put the Big Mac into a sane state. */
1445 HMD(("happy_meal_init: "));
1446 switch(hp->tcvr_type) {
1447 case none:
1448 /* Cannot operate if we don't know the transceiver type! */
1449 HMD(("AAIEEE no transceiver type, EAGAIN"));
1450 return -EAGAIN;
1451
1452 case internal:
1453 /* Using the MII buffers. */
1454 HMD(("internal, using MII, "));
1455 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1456 break;
1457
1458 case external:
1459 /* Not using the MII, disable it. */
1460 HMD(("external, disable MII, "));
1461 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1462 break;
1463 }
1464
1465 if (happy_meal_tcvr_reset(hp, tregs))
1466 return -EAGAIN;
1467
1468 /* Reset the Happy Meal Big Mac transceiver and the receiver. */
1469 HMD(("tx/rx reset, "));
1470 happy_meal_tx_reset(hp, bregs);
1471 happy_meal_rx_reset(hp, bregs);
1472
1473 /* Set jam size and inter-packet gaps to reasonable defaults. */
1474 HMD(("jsize/ipg1/ipg2, "));
1475 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
1476 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
1477 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
1478
1479 /* Load up the MAC address and random seed. */
1480 HMD(("rseed/macaddr, "));
1481
1482 /* The docs recommend to use the 10LSB of our MAC here. */
1483 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
1484
1485 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
1486 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
1487 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
1488
1489 HMD(("htable, "));
1490 if ((hp->dev->flags & IFF_ALLMULTI) ||
1491 (netdev_mc_count(hp->dev) > 64)) {
1492 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
1493 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
1494 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
1495 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
1496 } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
1497 u16 hash_table[4];
1498 struct netdev_hw_addr *ha;
1499 char *addrs;
1500 u32 crc;
1501
1502 memset(hash_table, 0, sizeof(hash_table));
1503 netdev_for_each_mc_addr(ha, hp->dev) {
1504 addrs = ha->addr;
1505
1506 if (!(*addrs & 1))
1507 continue;
1508
1509 crc = ether_crc_le(6, addrs);
1510 crc >>= 26;
1511 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1512 }
1513 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
1514 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
1515 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
1516 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
1517 } else {
1518 hme_write32(hp, bregs + BMAC_HTABLE3, 0);
1519 hme_write32(hp, bregs + BMAC_HTABLE2, 0);
1520 hme_write32(hp, bregs + BMAC_HTABLE1, 0);
1521 hme_write32(hp, bregs + BMAC_HTABLE0, 0);
1522 }
1523
1524 /* Set the RX and TX ring ptrs. */
1525 HMD(("ring ptrs rxr[%08x] txr[%08x]\n",
1526 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
1527 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
1528 hme_write32(hp, erxregs + ERX_RING,
1529 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
1530 hme_write32(hp, etxregs + ETX_RING,
1531 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
1532
1533 /* Parity issues in the ERX unit of some HME revisions can cause some
1534 * registers to not be written unless their parity is even. Detect such
1535 * lost writes and simply rewrite with a low bit set (which will be ignored
1536 * since the rxring needs to be 2K aligned).
1537 */
1538 if (hme_read32(hp, erxregs + ERX_RING) !=
1539 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)))
1540 hme_write32(hp, erxregs + ERX_RING,
1541 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))
1542 | 0x4);
1543
1544 /* Set the supported burst sizes. */
1545 HMD(("happy_meal_init: old[%08x] bursts<",
1546 hme_read32(hp, gregs + GREG_CFG)));
1547
1548 #ifndef CONFIG_SPARC
1549 /* It is always PCI and can handle 64byte bursts. */
1550 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64);
1551 #else
1552 if ((hp->happy_bursts & DMA_BURST64) &&
1553 ((hp->happy_flags & HFLAG_PCI) != 0
1554 #ifdef CONFIG_SBUS
1555 || sbus_can_burst64()
1556 #endif
1557 || 0)) {
1558 u32 gcfg = GREG_CFG_BURST64;
1559
1560 /* I have no idea if I should set the extended
1561 * transfer mode bit for Cheerio, so for now I
1562 * do not. -DaveM
1563 */
1564 #ifdef CONFIG_SBUS
1565 if ((hp->happy_flags & HFLAG_PCI) == 0) {
1566 struct platform_device *op = hp->happy_dev;
1567 if (sbus_can_dma_64bit()) {
1568 sbus_set_sbus64(&op->dev,
1569 hp->happy_bursts);
1570 gcfg |= GREG_CFG_64BIT;
1571 }
1572 }
1573 #endif
1574
1575 HMD(("64>"));
1576 hme_write32(hp, gregs + GREG_CFG, gcfg);
1577 } else if (hp->happy_bursts & DMA_BURST32) {
1578 HMD(("32>"));
1579 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
1580 } else if (hp->happy_bursts & DMA_BURST16) {
1581 HMD(("16>"));
1582 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
1583 } else {
1584 HMD(("XXX>"));
1585 hme_write32(hp, gregs + GREG_CFG, 0);
1586 }
1587 #endif /* CONFIG_SPARC */
1588
1589 /* Turn off interrupts we do not want to hear. */
1590 HMD((", enable global interrupts, "));
1591 hme_write32(hp, gregs + GREG_IMASK,
1592 (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP |
1593 GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR));
1594
1595 /* Set the transmit ring buffer size. */
1596 HMD(("tx rsize=%d oreg[%08x], ", (int)TX_RING_SIZE,
1597 hme_read32(hp, etxregs + ETX_RSIZE)));
1598 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
1599
1600 /* Enable transmitter DVMA. */
1601 HMD(("tx dma enable old[%08x], ",
1602 hme_read32(hp, etxregs + ETX_CFG)));
1603 hme_write32(hp, etxregs + ETX_CFG,
1604 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
1605
1606 /* This chip really rots, for the receiver sometimes when you
1607 * write to its control registers not all the bits get there
1608 * properly. I cannot think of a sane way to provide complete
1609 * coverage for this hardware bug yet.
1610 */
1611 HMD(("erx regs bug old[%08x]\n",
1612 hme_read32(hp, erxregs + ERX_CFG)));
1613 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1614 regtmp = hme_read32(hp, erxregs + ERX_CFG);
1615 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1616 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
1617 printk(KERN_ERR "happy meal: Eieee, rx config register gets greasy fries.\n");
1618 printk(KERN_ERR "happy meal: Trying to set %08x, reread gives %08x\n",
1619 ERX_CFG_DEFAULT(RX_OFFSET), regtmp);
1620 }
1621
1622 /* Enable Big Mac hash table filter. */
1623 HMD(("happy_meal_init: enable hash rx_cfg_old[%08x], ",
1624 hme_read32(hp, bregs + BMAC_RXCFG)));
1625 rxcfg = BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_REJME;
1626 if (hp->dev->flags & IFF_PROMISC)
1627 rxcfg |= BIGMAC_RXCFG_PMISC;
1628 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
1629
1630 /* Let the bits settle in the chip. */
1631 udelay(10);
1632
1633 /* Ok, configure the Big Mac transmitter. */
1634 HMD(("BIGMAC init, "));
1635 regtmp = 0;
1636 if (hp->happy_flags & HFLAG_FULL)
1637 regtmp |= BIGMAC_TXCFG_FULLDPLX;
1638
1639 /* Don't turn on the "don't give up" bit for now. It could cause hme
1640 * to deadlock with the PHY if a Jabber occurs.
1641 */
1642 hme_write32(hp, bregs + BMAC_TXCFG, regtmp /*| BIGMAC_TXCFG_DGIVEUP*/);
1643
1644 /* Give up after 16 TX attempts. */
1645 hme_write32(hp, bregs + BMAC_ALIMIT, 16);
1646
1647 /* Enable the output drivers no matter what. */
1648 regtmp = BIGMAC_XCFG_ODENABLE;
1649
1650 /* If card can do lance mode, enable it. */
1651 if (hp->happy_flags & HFLAG_LANCE)
1652 regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE;
1653
1654 /* Disable the MII buffers if using external transceiver. */
1655 if (hp->tcvr_type == external)
1656 regtmp |= BIGMAC_XCFG_MIIDISAB;
1657
1658 HMD(("XIF config old[%08x], ",
1659 hme_read32(hp, bregs + BMAC_XIFCFG)));
1660 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
1661
1662 /* Start things up. */
1663 HMD(("tx old[%08x] and rx [%08x] ON!\n",
1664 hme_read32(hp, bregs + BMAC_TXCFG),
1665 hme_read32(hp, bregs + BMAC_RXCFG)));
1666
1667 /* Set larger TX/RX size to allow for 802.1q */
1668 hme_write32(hp, bregs + BMAC_TXMAX, ETH_FRAME_LEN + 8);
1669 hme_write32(hp, bregs + BMAC_RXMAX, ETH_FRAME_LEN + 8);
1670
1671 hme_write32(hp, bregs + BMAC_TXCFG,
1672 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
1673 hme_write32(hp, bregs + BMAC_RXCFG,
1674 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
1675
1676 /* Get the autonegotiation started, and the watch timer ticking. */
1677 happy_meal_begin_auto_negotiation(hp, tregs, NULL);
1678
1679 /* Success. */
1680 return 0;
1681 }
1682
1683 /* hp->happy_lock must be held */
1684 static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
1685 {
1686 void __iomem *tregs = hp->tcvregs;
1687 void __iomem *bregs = hp->bigmacregs;
1688 void __iomem *gregs = hp->gregs;
1689
1690 happy_meal_stop(hp, gregs);
1691 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1692 if (hp->happy_flags & HFLAG_FENABLE)
1693 hme_write32(hp, tregs + TCVR_CFG,
1694 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1695 else
1696 hme_write32(hp, tregs + TCVR_CFG,
1697 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1698 happy_meal_transceiver_check(hp, tregs);
1699 switch(hp->tcvr_type) {
1700 case none:
1701 return;
1702 case internal:
1703 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1704 break;
1705 case external:
1706 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1707 break;
1708 }
1709 if (happy_meal_tcvr_reset(hp, tregs))
1710 return;
1711
1712 /* Latch PHY registers as of now. */
1713 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1714 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1715
1716 /* Advertise everything we can support. */
1717 if (hp->sw_bmsr & BMSR_10HALF)
1718 hp->sw_advertise |= (ADVERTISE_10HALF);
1719 else
1720 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1721
1722 if (hp->sw_bmsr & BMSR_10FULL)
1723 hp->sw_advertise |= (ADVERTISE_10FULL);
1724 else
1725 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1726 if (hp->sw_bmsr & BMSR_100HALF)
1727 hp->sw_advertise |= (ADVERTISE_100HALF);
1728 else
1729 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1730 if (hp->sw_bmsr & BMSR_100FULL)
1731 hp->sw_advertise |= (ADVERTISE_100FULL);
1732 else
1733 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1734
1735 /* Update the PHY advertisement register. */
1736 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1737 }
1738
1739 /* Once status is latched (by happy_meal_interrupt) it is cleared by
1740 * the hardware, so we cannot re-read it and get a correct value.
1741 *
1742 * hp->happy_lock must be held
1743 */
1744 static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
1745 {
1746 int reset = 0;
1747
1748 /* Only print messages for non-counter related interrupts. */
1749 if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND |
1750 GREG_STAT_MAXPKTERR | GREG_STAT_RXERR |
1751 GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR |
1752 GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR |
1753 GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR |
1754 GREG_STAT_SLVPERR))
1755 printk(KERN_ERR "%s: Error interrupt for happy meal, status = %08x\n",
1756 hp->dev->name, status);
1757
1758 if (status & GREG_STAT_RFIFOVF) {
1759 /* Receive FIFO overflow is harmless and the hardware will take
1760 care of it, just some packets are lost. Who cares. */
1761 printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name);
1762 }
1763
1764 if (status & GREG_STAT_STSTERR) {
1765 /* BigMAC SQE link test failed. */
1766 printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name);
1767 reset = 1;
1768 }
1769
1770 if (status & GREG_STAT_TFIFO_UND) {
1771 /* Transmit FIFO underrun, again DMA error likely. */
1772 printk(KERN_ERR "%s: Happy Meal transmitter FIFO underrun, DMA error.\n",
1773 hp->dev->name);
1774 reset = 1;
1775 }
1776
1777 if (status & GREG_STAT_MAXPKTERR) {
1778 /* Driver error, tried to transmit something larger
1779 * than ethernet max mtu.
1780 */
1781 printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name);
1782 reset = 1;
1783 }
1784
1785 if (status & GREG_STAT_NORXD) {
1786 /* This is harmless, it just means the system is
1787 * quite loaded and the incoming packet rate was
1788 * faster than the interrupt handler could keep up
1789 * with.
1790 */
1791 printk(KERN_INFO "%s: Happy Meal out of receive "
1792 "descriptors, packet dropped.\n",
1793 hp->dev->name);
1794 }
1795
1796 if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) {
1797 /* All sorts of DMA receive errors. */
1798 printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name);
1799 if (status & GREG_STAT_RXERR)
1800 printk("GenericError ");
1801 if (status & GREG_STAT_RXPERR)
1802 printk("ParityError ");
1803 if (status & GREG_STAT_RXTERR)
1804 printk("RxTagBotch ");
1805 printk("]\n");
1806 reset = 1;
1807 }
1808
1809 if (status & GREG_STAT_EOPERR) {
1810 /* Driver bug, didn't set EOP bit in tx descriptor given
1811 * to the happy meal.
1812 */
1813 printk(KERN_ERR "%s: EOP not set in happy meal transmit descriptor!\n",
1814 hp->dev->name);
1815 reset = 1;
1816 }
1817
1818 if (status & GREG_STAT_MIFIRQ) {
1819 /* MIF signalled an interrupt, were we polling it? */
1820 printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name);
1821 }
1822
1823 if (status &
1824 (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) {
1825 /* All sorts of transmit DMA errors. */
1826 printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name);
1827 if (status & GREG_STAT_TXEACK)
1828 printk("GenericError ");
1829 if (status & GREG_STAT_TXLERR)
1830 printk("LateError ");
1831 if (status & GREG_STAT_TXPERR)
1832 printk("ParityErro ");
1833 if (status & GREG_STAT_TXTERR)
1834 printk("TagBotch ");
1835 printk("]\n");
1836 reset = 1;
1837 }
1838
1839 if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) {
1840 /* Bus or parity error when cpu accessed happy meal registers
1841 * or it's internal FIFO's. Should never see this.
1842 */
1843 printk(KERN_ERR "%s: Happy Meal register access SBUS slave (%s) error.\n",
1844 hp->dev->name,
1845 (status & GREG_STAT_SLVPERR) ? "parity" : "generic");
1846 reset = 1;
1847 }
1848
1849 if (reset) {
1850 printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name);
1851 happy_meal_init(hp);
1852 return 1;
1853 }
1854 return 0;
1855 }
1856
1857 /* hp->happy_lock must be held */
1858 static void happy_meal_mif_interrupt(struct happy_meal *hp)
1859 {
1860 void __iomem *tregs = hp->tcvregs;
1861
1862 printk(KERN_INFO "%s: Link status change.\n", hp->dev->name);
1863 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1864 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
1865
1866 /* Use the fastest transmission protocol possible. */
1867 if (hp->sw_lpa & LPA_100FULL) {
1868 printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name);
1869 hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100);
1870 } else if (hp->sw_lpa & LPA_100HALF) {
1871 printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name);
1872 hp->sw_bmcr |= BMCR_SPEED100;
1873 } else if (hp->sw_lpa & LPA_10FULL) {
1874 printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name);
1875 hp->sw_bmcr |= BMCR_FULLDPLX;
1876 } else {
1877 printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name);
1878 }
1879 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1880
1881 /* Finally stop polling and shut up the MIF. */
1882 happy_meal_poll_stop(hp, tregs);
1883 }
1884
1885 #ifdef TXDEBUG
1886 #define TXD(x) printk x
1887 #else
1888 #define TXD(x)
1889 #endif
1890
1891 /* hp->happy_lock must be held */
1892 static void happy_meal_tx(struct happy_meal *hp)
1893 {
1894 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
1895 struct happy_meal_txd *this;
1896 struct net_device *dev = hp->dev;
1897 int elem;
1898
1899 elem = hp->tx_old;
1900 TXD(("TX<"));
1901 while (elem != hp->tx_new) {
1902 struct sk_buff *skb;
1903 u32 flags, dma_addr, dma_len;
1904 int frag;
1905
1906 TXD(("[%d]", elem));
1907 this = &txbase[elem];
1908 flags = hme_read_desc32(hp, &this->tx_flags);
1909 if (flags & TXFLAG_OWN)
1910 break;
1911 skb = hp->tx_skbs[elem];
1912 if (skb_shinfo(skb)->nr_frags) {
1913 int last;
1914
1915 last = elem + skb_shinfo(skb)->nr_frags;
1916 last &= (TX_RING_SIZE - 1);
1917 flags = hme_read_desc32(hp, &txbase[last].tx_flags);
1918 if (flags & TXFLAG_OWN)
1919 break;
1920 }
1921 hp->tx_skbs[elem] = NULL;
1922 hp->net_stats.tx_bytes += skb->len;
1923
1924 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1925 dma_addr = hme_read_desc32(hp, &this->tx_addr);
1926 dma_len = hme_read_desc32(hp, &this->tx_flags);
1927
1928 dma_len &= TXFLAG_SIZE;
1929 if (!frag)
1930 dma_unmap_single(hp->dma_dev, dma_addr, dma_len, DMA_TO_DEVICE);
1931 else
1932 dma_unmap_page(hp->dma_dev, dma_addr, dma_len, DMA_TO_DEVICE);
1933
1934 elem = NEXT_TX(elem);
1935 this = &txbase[elem];
1936 }
1937
1938 dev_kfree_skb_irq(skb);
1939 hp->net_stats.tx_packets++;
1940 }
1941 hp->tx_old = elem;
1942 TXD((">"));
1943
1944 if (netif_queue_stopped(dev) &&
1945 TX_BUFFS_AVAIL(hp) > (MAX_SKB_FRAGS + 1))
1946 netif_wake_queue(dev);
1947 }
1948
1949 #ifdef RXDEBUG
1950 #define RXD(x) printk x
1951 #else
1952 #define RXD(x)
1953 #endif
1954
1955 /* Originally I used to handle the allocation failure by just giving back just
1956 * that one ring buffer to the happy meal. Problem is that usually when that
1957 * condition is triggered, the happy meal expects you to do something reasonable
1958 * with all of the packets it has DMA'd in. So now I just drop the entire
1959 * ring when we cannot get a new skb and give them all back to the happy meal,
1960 * maybe things will be "happier" now.
1961 *
1962 * hp->happy_lock must be held
1963 */
1964 static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
1965 {
1966 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
1967 struct happy_meal_rxd *this;
1968 int elem = hp->rx_new, drops = 0;
1969 u32 flags;
1970
1971 RXD(("RX<"));
1972 this = &rxbase[elem];
1973 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
1974 struct sk_buff *skb;
1975 int len = flags >> 16;
1976 u16 csum = flags & RXFLAG_CSUM;
1977 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
1978
1979 RXD(("[%d ", elem));
1980
1981 /* Check for errors. */
1982 if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) {
1983 RXD(("ERR(%08x)]", flags));
1984 hp->net_stats.rx_errors++;
1985 if (len < ETH_ZLEN)
1986 hp->net_stats.rx_length_errors++;
1987 if (len & (RXFLAG_OVERFLOW >> 16)) {
1988 hp->net_stats.rx_over_errors++;
1989 hp->net_stats.rx_fifo_errors++;
1990 }
1991
1992 /* Return it to the Happy meal. */
1993 drop_it:
1994 hp->net_stats.rx_dropped++;
1995 hme_write_rxd(hp, this,
1996 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
1997 dma_addr);
1998 goto next;
1999 }
2000 skb = hp->rx_skbs[elem];
2001 if (len > RX_COPY_THRESHOLD) {
2002 struct sk_buff *new_skb;
2003
2004 /* Now refill the entry, if we can. */
2005 new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
2006 if (new_skb == NULL) {
2007 drops++;
2008 goto drop_it;
2009 }
2010 dma_unmap_single(hp->dma_dev, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROM_DEVICE);
2011 hp->rx_skbs[elem] = new_skb;
2012 new_skb->dev = dev;
2013 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET + 4));
2014 hme_write_rxd(hp, this,
2015 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2016 dma_map_single(hp->dma_dev, new_skb->data, RX_BUF_ALLOC_SIZE,
2017 DMA_FROM_DEVICE));
2018 skb_reserve(new_skb, RX_OFFSET);
2019
2020 /* Trim the original skb for the netif. */
2021 skb_trim(skb, len);
2022 } else {
2023 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
2024
2025 if (copy_skb == NULL) {
2026 drops++;
2027 goto drop_it;
2028 }
2029
2030 skb_reserve(copy_skb, 2);
2031 skb_put(copy_skb, len);
2032 dma_sync_single_for_cpu(hp->dma_dev, dma_addr, len, DMA_FROM_DEVICE);
2033 skb_copy_from_linear_data(skb, copy_skb->data, len);
2034 dma_sync_single_for_device(hp->dma_dev, dma_addr, len, DMA_FROM_DEVICE);
2035 /* Reuse original ring buffer. */
2036 hme_write_rxd(hp, this,
2037 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2038 dma_addr);
2039
2040 skb = copy_skb;
2041 }
2042
2043 /* This card is _fucking_ hot... */
2044 skb->csum = csum_unfold(~(__force __sum16)htons(csum));
2045 skb->ip_summed = CHECKSUM_COMPLETE;
2046
2047 RXD(("len=%d csum=%4x]", len, csum));
2048 skb->protocol = eth_type_trans(skb, dev);
2049 netif_rx(skb);
2050
2051 hp->net_stats.rx_packets++;
2052 hp->net_stats.rx_bytes += len;
2053 next:
2054 elem = NEXT_RX(elem);
2055 this = &rxbase[elem];
2056 }
2057 hp->rx_new = elem;
2058 if (drops)
2059 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name);
2060 RXD((">"));
2061 }
2062
2063 static irqreturn_t happy_meal_interrupt(int irq, void *dev_id)
2064 {
2065 struct net_device *dev = dev_id;
2066 struct happy_meal *hp = netdev_priv(dev);
2067 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2068
2069 HMD(("happy_meal_interrupt: status=%08x ", happy_status));
2070
2071 spin_lock(&hp->happy_lock);
2072
2073 if (happy_status & GREG_STAT_ERRORS) {
2074 HMD(("ERRORS "));
2075 if (happy_meal_is_not_so_happy(hp, /* un- */ happy_status))
2076 goto out;
2077 }
2078
2079 if (happy_status & GREG_STAT_MIFIRQ) {
2080 HMD(("MIFIRQ "));
2081 happy_meal_mif_interrupt(hp);
2082 }
2083
2084 if (happy_status & GREG_STAT_TXALL) {
2085 HMD(("TXALL "));
2086 happy_meal_tx(hp);
2087 }
2088
2089 if (happy_status & GREG_STAT_RXTOHOST) {
2090 HMD(("RXTOHOST "));
2091 happy_meal_rx(hp, dev);
2092 }
2093
2094 HMD(("done\n"));
2095 out:
2096 spin_unlock(&hp->happy_lock);
2097
2098 return IRQ_HANDLED;
2099 }
2100
2101 #ifdef CONFIG_SBUS
2102 static irqreturn_t quattro_sbus_interrupt(int irq, void *cookie)
2103 {
2104 struct quattro *qp = (struct quattro *) cookie;
2105 int i;
2106
2107 for (i = 0; i < 4; i++) {
2108 struct net_device *dev = qp->happy_meals[i];
2109 struct happy_meal *hp = netdev_priv(dev);
2110 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2111
2112 HMD(("quattro_interrupt: status=%08x ", happy_status));
2113
2114 if (!(happy_status & (GREG_STAT_ERRORS |
2115 GREG_STAT_MIFIRQ |
2116 GREG_STAT_TXALL |
2117 GREG_STAT_RXTOHOST)))
2118 continue;
2119
2120 spin_lock(&hp->happy_lock);
2121
2122 if (happy_status & GREG_STAT_ERRORS) {
2123 HMD(("ERRORS "));
2124 if (happy_meal_is_not_so_happy(hp, happy_status))
2125 goto next;
2126 }
2127
2128 if (happy_status & GREG_STAT_MIFIRQ) {
2129 HMD(("MIFIRQ "));
2130 happy_meal_mif_interrupt(hp);
2131 }
2132
2133 if (happy_status & GREG_STAT_TXALL) {
2134 HMD(("TXALL "));
2135 happy_meal_tx(hp);
2136 }
2137
2138 if (happy_status & GREG_STAT_RXTOHOST) {
2139 HMD(("RXTOHOST "));
2140 happy_meal_rx(hp, dev);
2141 }
2142
2143 next:
2144 spin_unlock(&hp->happy_lock);
2145 }
2146 HMD(("done\n"));
2147
2148 return IRQ_HANDLED;
2149 }
2150 #endif
2151
2152 static int happy_meal_open(struct net_device *dev)
2153 {
2154 struct happy_meal *hp = netdev_priv(dev);
2155 int res;
2156
2157 HMD(("happy_meal_open: "));
2158
2159 /* On SBUS Quattro QFE cards, all hme interrupts are concentrated
2160 * into a single source which we register handling at probe time.
2161 */
2162 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) {
2163 if (request_irq(dev->irq, happy_meal_interrupt,
2164 IRQF_SHARED, dev->name, (void *)dev)) {
2165 HMD(("EAGAIN\n"));
2166 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %d to go.\n",
2167 dev->irq);
2168
2169 return -EAGAIN;
2170 }
2171 }
2172
2173 HMD(("to happy_meal_init\n"));
2174
2175 spin_lock_irq(&hp->happy_lock);
2176 res = happy_meal_init(hp);
2177 spin_unlock_irq(&hp->happy_lock);
2178
2179 if (res && ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO))
2180 free_irq(dev->irq, dev);
2181 return res;
2182 }
2183
2184 static int happy_meal_close(struct net_device *dev)
2185 {
2186 struct happy_meal *hp = netdev_priv(dev);
2187
2188 spin_lock_irq(&hp->happy_lock);
2189 happy_meal_stop(hp, hp->gregs);
2190 happy_meal_clean_rings(hp);
2191
2192 /* If auto-negotiation timer is running, kill it. */
2193 del_timer(&hp->happy_timer);
2194
2195 spin_unlock_irq(&hp->happy_lock);
2196
2197 /* On Quattro QFE cards, all hme interrupts are concentrated
2198 * into a single source which we register handling at probe
2199 * time and never unregister.
2200 */
2201 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)
2202 free_irq(dev->irq, dev);
2203
2204 return 0;
2205 }
2206
2207 #ifdef SXDEBUG
2208 #define SXD(x) printk x
2209 #else
2210 #define SXD(x)
2211 #endif
2212
2213 static void happy_meal_tx_timeout(struct net_device *dev)
2214 {
2215 struct happy_meal *hp = netdev_priv(dev);
2216
2217 printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2218 tx_dump_log();
2219 printk (KERN_ERR "%s: Happy Status %08x TX[%08x:%08x]\n", dev->name,
2220 hme_read32(hp, hp->gregs + GREG_STAT),
2221 hme_read32(hp, hp->etxregs + ETX_CFG),
2222 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
2223
2224 spin_lock_irq(&hp->happy_lock);
2225 happy_meal_init(hp);
2226 spin_unlock_irq(&hp->happy_lock);
2227
2228 netif_wake_queue(dev);
2229 }
2230
2231 static netdev_tx_t happy_meal_start_xmit(struct sk_buff *skb,
2232 struct net_device *dev)
2233 {
2234 struct happy_meal *hp = netdev_priv(dev);
2235 int entry;
2236 u32 tx_flags;
2237
2238 tx_flags = TXFLAG_OWN;
2239 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2240 const u32 csum_start_off = skb_transport_offset(skb);
2241 const u32 csum_stuff_off = csum_start_off + skb->csum_offset;
2242
2243 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE |
2244 ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) |
2245 ((csum_stuff_off << 20) & TXFLAG_CSLOCATION));
2246 }
2247
2248 spin_lock_irq(&hp->happy_lock);
2249
2250 if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) {
2251 netif_stop_queue(dev);
2252 spin_unlock_irq(&hp->happy_lock);
2253 printk(KERN_ERR "%s: BUG! Tx Ring full when queue awake!\n",
2254 dev->name);
2255 return NETDEV_TX_BUSY;
2256 }
2257
2258 entry = hp->tx_new;
2259 SXD(("SX<l[%d]e[%d]>", len, entry));
2260 hp->tx_skbs[entry] = skb;
2261
2262 if (skb_shinfo(skb)->nr_frags == 0) {
2263 u32 mapping, len;
2264
2265 len = skb->len;
2266 mapping = dma_map_single(hp->dma_dev, skb->data, len, DMA_TO_DEVICE);
2267 tx_flags |= (TXFLAG_SOP | TXFLAG_EOP);
2268 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2269 (tx_flags | (len & TXFLAG_SIZE)),
2270 mapping);
2271 entry = NEXT_TX(entry);
2272 } else {
2273 u32 first_len, first_mapping;
2274 int frag, first_entry = entry;
2275
2276 /* We must give this initial chunk to the device last.
2277 * Otherwise we could race with the device.
2278 */
2279 first_len = skb_headlen(skb);
2280 first_mapping = dma_map_single(hp->dma_dev, skb->data, first_len,
2281 DMA_TO_DEVICE);
2282 entry = NEXT_TX(entry);
2283
2284 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
2285 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
2286 u32 len, mapping, this_txflags;
2287
2288 len = this_frag->size;
2289 mapping = dma_map_page(hp->dma_dev, this_frag->page,
2290 this_frag->page_offset, len,
2291 DMA_TO_DEVICE);
2292 this_txflags = tx_flags;
2293 if (frag == skb_shinfo(skb)->nr_frags - 1)
2294 this_txflags |= TXFLAG_EOP;
2295 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2296 (this_txflags | (len & TXFLAG_SIZE)),
2297 mapping);
2298 entry = NEXT_TX(entry);
2299 }
2300 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry],
2301 (tx_flags | TXFLAG_SOP | (first_len & TXFLAG_SIZE)),
2302 first_mapping);
2303 }
2304
2305 hp->tx_new = entry;
2306
2307 if (TX_BUFFS_AVAIL(hp) <= (MAX_SKB_FRAGS + 1))
2308 netif_stop_queue(dev);
2309
2310 /* Get it going. */
2311 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
2312
2313 spin_unlock_irq(&hp->happy_lock);
2314
2315 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
2316 return NETDEV_TX_OK;
2317 }
2318
2319 static struct net_device_stats *happy_meal_get_stats(struct net_device *dev)
2320 {
2321 struct happy_meal *hp = netdev_priv(dev);
2322
2323 spin_lock_irq(&hp->happy_lock);
2324 happy_meal_get_counters(hp, hp->bigmacregs);
2325 spin_unlock_irq(&hp->happy_lock);
2326
2327 return &hp->net_stats;
2328 }
2329
2330 static void happy_meal_set_multicast(struct net_device *dev)
2331 {
2332 struct happy_meal *hp = netdev_priv(dev);
2333 void __iomem *bregs = hp->bigmacregs;
2334 struct netdev_hw_addr *ha;
2335 char *addrs;
2336 u32 crc;
2337
2338 spin_lock_irq(&hp->happy_lock);
2339
2340 if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 64)) {
2341 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
2342 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
2343 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
2344 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
2345 } else if (dev->flags & IFF_PROMISC) {
2346 hme_write32(hp, bregs + BMAC_RXCFG,
2347 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
2348 } else {
2349 u16 hash_table[4];
2350
2351 memset(hash_table, 0, sizeof(hash_table));
2352 netdev_for_each_mc_addr(ha, dev) {
2353 addrs = ha->addr;
2354
2355 if (!(*addrs & 1))
2356 continue;
2357
2358 crc = ether_crc_le(6, addrs);
2359 crc >>= 26;
2360 hash_table[crc >> 4] |= 1 << (crc & 0xf);
2361 }
2362 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
2363 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
2364 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
2365 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
2366 }
2367
2368 spin_unlock_irq(&hp->happy_lock);
2369 }
2370
2371 /* Ethtool support... */
2372 static int hme_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2373 {
2374 struct happy_meal *hp = netdev_priv(dev);
2375
2376 cmd->supported =
2377 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2378 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2379 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
2380
2381 cmd->port = PORT_TP;
2382 cmd->transceiver = XCVR_INTERNAL;
2383 cmd->phy_address = 0;
2384
2385 /* Record PHY settings. */
2386 spin_lock_irq(&hp->happy_lock);
2387 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2388 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA);
2389 spin_unlock_irq(&hp->happy_lock);
2390
2391 if (hp->sw_bmcr & BMCR_ANENABLE) {
2392 cmd->autoneg = AUTONEG_ENABLE;
2393 cmd->speed =
2394 (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
2395 SPEED_100 : SPEED_10;
2396 if (cmd->speed == SPEED_100)
2397 cmd->duplex =
2398 (hp->sw_lpa & (LPA_100FULL)) ?
2399 DUPLEX_FULL : DUPLEX_HALF;
2400 else
2401 cmd->duplex =
2402 (hp->sw_lpa & (LPA_10FULL)) ?
2403 DUPLEX_FULL : DUPLEX_HALF;
2404 } else {
2405 cmd->autoneg = AUTONEG_DISABLE;
2406 cmd->speed =
2407 (hp->sw_bmcr & BMCR_SPEED100) ?
2408 SPEED_100 : SPEED_10;
2409 cmd->duplex =
2410 (hp->sw_bmcr & BMCR_FULLDPLX) ?
2411 DUPLEX_FULL : DUPLEX_HALF;
2412 }
2413 return 0;
2414 }
2415
2416 static int hme_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2417 {
2418 struct happy_meal *hp = netdev_priv(dev);
2419
2420 /* Verify the settings we care about. */
2421 if (cmd->autoneg != AUTONEG_ENABLE &&
2422 cmd->autoneg != AUTONEG_DISABLE)
2423 return -EINVAL;
2424 if (cmd->autoneg == AUTONEG_DISABLE &&
2425 ((cmd->speed != SPEED_100 &&
2426 cmd->speed != SPEED_10) ||
2427 (cmd->duplex != DUPLEX_HALF &&
2428 cmd->duplex != DUPLEX_FULL)))
2429 return -EINVAL;
2430
2431 /* Ok, do it to it. */
2432 spin_lock_irq(&hp->happy_lock);
2433 del_timer(&hp->happy_timer);
2434 happy_meal_begin_auto_negotiation(hp, hp->tcvregs, cmd);
2435 spin_unlock_irq(&hp->happy_lock);
2436
2437 return 0;
2438 }
2439
2440 static void hme_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2441 {
2442 struct happy_meal *hp = netdev_priv(dev);
2443
2444 strcpy(info->driver, "sunhme");
2445 strcpy(info->version, "2.02");
2446 if (hp->happy_flags & HFLAG_PCI) {
2447 struct pci_dev *pdev = hp->happy_dev;
2448 strcpy(info->bus_info, pci_name(pdev));
2449 }
2450 #ifdef CONFIG_SBUS
2451 else {
2452 const struct linux_prom_registers *regs;
2453 struct platform_device *op = hp->happy_dev;
2454 regs = of_get_property(op->dev.of_node, "regs", NULL);
2455 if (regs)
2456 sprintf(info->bus_info, "SBUS:%d",
2457 regs->which_io);
2458 }
2459 #endif
2460 }
2461
2462 static u32 hme_get_link(struct net_device *dev)
2463 {
2464 struct happy_meal *hp = netdev_priv(dev);
2465
2466 spin_lock_irq(&hp->happy_lock);
2467 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2468 spin_unlock_irq(&hp->happy_lock);
2469
2470 return (hp->sw_bmsr & BMSR_LSTATUS);
2471 }
2472
2473 static const struct ethtool_ops hme_ethtool_ops = {
2474 .get_settings = hme_get_settings,
2475 .set_settings = hme_set_settings,
2476 .get_drvinfo = hme_get_drvinfo,
2477 .get_link = hme_get_link,
2478 };
2479
2480 static int hme_version_printed;
2481
2482 #ifdef CONFIG_SBUS
2483 /* Given a happy meal sbus device, find it's quattro parent.
2484 * If none exist, allocate and return a new one.
2485 *
2486 * Return NULL on failure.
2487 */
2488 static struct quattro * __devinit quattro_sbus_find(struct platform_device *child)
2489 {
2490 struct device *parent = child->dev.parent;
2491 struct platform_device *op;
2492 struct quattro *qp;
2493
2494 op = to_platform_device(parent);
2495 qp = dev_get_drvdata(&op->dev);
2496 if (qp)
2497 return qp;
2498
2499 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2500 if (qp != NULL) {
2501 int i;
2502
2503 for (i = 0; i < 4; i++)
2504 qp->happy_meals[i] = NULL;
2505
2506 qp->quattro_dev = child;
2507 qp->next = qfe_sbus_list;
2508 qfe_sbus_list = qp;
2509
2510 dev_set_drvdata(&op->dev, qp);
2511 }
2512 return qp;
2513 }
2514
2515 /* After all quattro cards have been probed, we call these functions
2516 * to register the IRQ handlers for the cards that have been
2517 * successfully probed and skip the cards that failed to initialize
2518 */
2519 static int __init quattro_sbus_register_irqs(void)
2520 {
2521 struct quattro *qp;
2522
2523 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2524 struct platform_device *op = qp->quattro_dev;
2525 int err, qfe_slot, skip = 0;
2526
2527 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++) {
2528 if (!qp->happy_meals[qfe_slot])
2529 skip = 1;
2530 }
2531 if (skip)
2532 continue;
2533
2534 err = request_irq(op->archdata.irqs[0],
2535 quattro_sbus_interrupt,
2536 IRQF_SHARED, "Quattro",
2537 qp);
2538 if (err != 0) {
2539 printk(KERN_ERR "Quattro HME: IRQ registration "
2540 "error %d.\n", err);
2541 return err;
2542 }
2543 }
2544
2545 return 0;
2546 }
2547
2548 static void quattro_sbus_free_irqs(void)
2549 {
2550 struct quattro *qp;
2551
2552 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2553 struct platform_device *op = qp->quattro_dev;
2554 int qfe_slot, skip = 0;
2555
2556 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++) {
2557 if (!qp->happy_meals[qfe_slot])
2558 skip = 1;
2559 }
2560 if (skip)
2561 continue;
2562
2563 free_irq(op->archdata.irqs[0], qp);
2564 }
2565 }
2566 #endif /* CONFIG_SBUS */
2567
2568 #ifdef CONFIG_PCI
2569 static struct quattro * __devinit quattro_pci_find(struct pci_dev *pdev)
2570 {
2571 struct pci_dev *bdev = pdev->bus->self;
2572 struct quattro *qp;
2573
2574 if (!bdev) return NULL;
2575 for (qp = qfe_pci_list; qp != NULL; qp = qp->next) {
2576 struct pci_dev *qpdev = qp->quattro_dev;
2577
2578 if (qpdev == bdev)
2579 return qp;
2580 }
2581 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2582 if (qp != NULL) {
2583 int i;
2584
2585 for (i = 0; i < 4; i++)
2586 qp->happy_meals[i] = NULL;
2587
2588 qp->quattro_dev = bdev;
2589 qp->next = qfe_pci_list;
2590 qfe_pci_list = qp;
2591
2592 /* No range tricks necessary on PCI. */
2593 qp->nranges = 0;
2594 }
2595 return qp;
2596 }
2597 #endif /* CONFIG_PCI */
2598
2599 static const struct net_device_ops hme_netdev_ops = {
2600 .ndo_open = happy_meal_open,
2601 .ndo_stop = happy_meal_close,
2602 .ndo_start_xmit = happy_meal_start_xmit,
2603 .ndo_tx_timeout = happy_meal_tx_timeout,
2604 .ndo_get_stats = happy_meal_get_stats,
2605 .ndo_set_multicast_list = happy_meal_set_multicast,
2606 .ndo_change_mtu = eth_change_mtu,
2607 .ndo_set_mac_address = eth_mac_addr,
2608 .ndo_validate_addr = eth_validate_addr,
2609 };
2610
2611 #ifdef CONFIG_SBUS
2612 static int __devinit happy_meal_sbus_probe_one(struct platform_device *op, int is_qfe)
2613 {
2614 struct device_node *dp = op->dev.of_node, *sbus_dp;
2615 struct quattro *qp = NULL;
2616 struct happy_meal *hp;
2617 struct net_device *dev;
2618 int i, qfe_slot = -1;
2619 int err = -ENODEV;
2620
2621 sbus_dp = op->dev.parent->of_node;
2622
2623 /* We can match PCI devices too, do not accept those here. */
2624 if (strcmp(sbus_dp->name, "sbus"))
2625 return err;
2626
2627 if (is_qfe) {
2628 qp = quattro_sbus_find(op);
2629 if (qp == NULL)
2630 goto err_out;
2631 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2632 if (qp->happy_meals[qfe_slot] == NULL)
2633 break;
2634 if (qfe_slot == 4)
2635 goto err_out;
2636 }
2637
2638 err = -ENOMEM;
2639 dev = alloc_etherdev(sizeof(struct happy_meal));
2640 if (!dev)
2641 goto err_out;
2642 SET_NETDEV_DEV(dev, &op->dev);
2643
2644 if (hme_version_printed++ == 0)
2645 printk(KERN_INFO "%s", version);
2646
2647 /* If user did not specify a MAC address specifically, use
2648 * the Quattro local-mac-address property...
2649 */
2650 for (i = 0; i < 6; i++) {
2651 if (macaddr[i] != 0)
2652 break;
2653 }
2654 if (i < 6) { /* a mac address was given */
2655 for (i = 0; i < 6; i++)
2656 dev->dev_addr[i] = macaddr[i];
2657 macaddr[5]++;
2658 } else {
2659 const unsigned char *addr;
2660 int len;
2661
2662 addr = of_get_property(dp, "local-mac-address", &len);
2663
2664 if (qfe_slot != -1 && addr && len == 6)
2665 memcpy(dev->dev_addr, addr, 6);
2666 else
2667 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2668 }
2669
2670 hp = netdev_priv(dev);
2671
2672 hp->happy_dev = op;
2673 hp->dma_dev = &op->dev;
2674
2675 spin_lock_init(&hp->happy_lock);
2676
2677 err = -ENODEV;
2678 if (qp != NULL) {
2679 hp->qfe_parent = qp;
2680 hp->qfe_ent = qfe_slot;
2681 qp->happy_meals[qfe_slot] = dev;
2682 }
2683
2684 hp->gregs = of_ioremap(&op->resource[0], 0,
2685 GREG_REG_SIZE, "HME Global Regs");
2686 if (!hp->gregs) {
2687 printk(KERN_ERR "happymeal: Cannot map global registers.\n");
2688 goto err_out_free_netdev;
2689 }
2690
2691 hp->etxregs = of_ioremap(&op->resource[1], 0,
2692 ETX_REG_SIZE, "HME TX Regs");
2693 if (!hp->etxregs) {
2694 printk(KERN_ERR "happymeal: Cannot map MAC TX registers.\n");
2695 goto err_out_iounmap;
2696 }
2697
2698 hp->erxregs = of_ioremap(&op->resource[2], 0,
2699 ERX_REG_SIZE, "HME RX Regs");
2700 if (!hp->erxregs) {
2701 printk(KERN_ERR "happymeal: Cannot map MAC RX registers.\n");
2702 goto err_out_iounmap;
2703 }
2704
2705 hp->bigmacregs = of_ioremap(&op->resource[3], 0,
2706 BMAC_REG_SIZE, "HME BIGMAC Regs");
2707 if (!hp->bigmacregs) {
2708 printk(KERN_ERR "happymeal: Cannot map BIGMAC registers.\n");
2709 goto err_out_iounmap;
2710 }
2711
2712 hp->tcvregs = of_ioremap(&op->resource[4], 0,
2713 TCVR_REG_SIZE, "HME Tranceiver Regs");
2714 if (!hp->tcvregs) {
2715 printk(KERN_ERR "happymeal: Cannot map TCVR registers.\n");
2716 goto err_out_iounmap;
2717 }
2718
2719 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
2720 if (hp->hm_revision == 0xff)
2721 hp->hm_revision = 0xa0;
2722
2723 /* Now enable the feature flags we can. */
2724 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2725 hp->happy_flags = HFLAG_20_21;
2726 else if (hp->hm_revision != 0xa0)
2727 hp->happy_flags = HFLAG_NOT_A0;
2728
2729 if (qp != NULL)
2730 hp->happy_flags |= HFLAG_QUATTRO;
2731
2732 /* Get the supported DVMA burst sizes from our Happy SBUS. */
2733 hp->happy_bursts = of_getintprop_default(sbus_dp,
2734 "burst-sizes", 0x00);
2735
2736 hp->happy_block = dma_alloc_coherent(hp->dma_dev,
2737 PAGE_SIZE,
2738 &hp->hblock_dvma,
2739 GFP_ATOMIC);
2740 err = -ENOMEM;
2741 if (!hp->happy_block) {
2742 printk(KERN_ERR "happymeal: Cannot allocate descriptors.\n");
2743 goto err_out_iounmap;
2744 }
2745
2746 /* Force check of the link first time we are brought up. */
2747 hp->linkcheck = 0;
2748
2749 /* Force timer state to 'asleep' with count of zero. */
2750 hp->timer_state = asleep;
2751 hp->timer_ticks = 0;
2752
2753 init_timer(&hp->happy_timer);
2754
2755 hp->dev = dev;
2756 dev->netdev_ops = &hme_netdev_ops;
2757 dev->watchdog_timeo = 5*HZ;
2758 dev->ethtool_ops = &hme_ethtool_ops;
2759
2760 /* Happy Meal can do it all... */
2761 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
2762
2763 dev->irq = op->archdata.irqs[0];
2764
2765 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
2766 /* Hook up SBUS register/descriptor accessors. */
2767 hp->read_desc32 = sbus_hme_read_desc32;
2768 hp->write_txd = sbus_hme_write_txd;
2769 hp->write_rxd = sbus_hme_write_rxd;
2770 hp->read32 = sbus_hme_read32;
2771 hp->write32 = sbus_hme_write32;
2772 #endif
2773
2774 /* Grrr, Happy Meal comes up by default not advertising
2775 * full duplex 100baseT capabilities, fix this.
2776 */
2777 spin_lock_irq(&hp->happy_lock);
2778 happy_meal_set_initial_advertisement(hp);
2779 spin_unlock_irq(&hp->happy_lock);
2780
2781 if (register_netdev(hp->dev)) {
2782 printk(KERN_ERR "happymeal: Cannot register net device, "
2783 "aborting.\n");
2784 goto err_out_free_coherent;
2785 }
2786
2787 dev_set_drvdata(&op->dev, hp);
2788
2789 if (qfe_slot != -1)
2790 printk(KERN_INFO "%s: Quattro HME slot %d (SBUS) 10/100baseT Ethernet ",
2791 dev->name, qfe_slot);
2792 else
2793 printk(KERN_INFO "%s: HAPPY MEAL (SBUS) 10/100baseT Ethernet ",
2794 dev->name);
2795
2796 printk("%pM\n", dev->dev_addr);
2797
2798 return 0;
2799
2800 err_out_free_coherent:
2801 dma_free_coherent(hp->dma_dev,
2802 PAGE_SIZE,
2803 hp->happy_block,
2804 hp->hblock_dvma);
2805
2806 err_out_iounmap:
2807 if (hp->gregs)
2808 of_iounmap(&op->resource[0], hp->gregs, GREG_REG_SIZE);
2809 if (hp->etxregs)
2810 of_iounmap(&op->resource[1], hp->etxregs, ETX_REG_SIZE);
2811 if (hp->erxregs)
2812 of_iounmap(&op->resource[2], hp->erxregs, ERX_REG_SIZE);
2813 if (hp->bigmacregs)
2814 of_iounmap(&op->resource[3], hp->bigmacregs, BMAC_REG_SIZE);
2815 if (hp->tcvregs)
2816 of_iounmap(&op->resource[4], hp->tcvregs, TCVR_REG_SIZE);
2817
2818 if (qp)
2819 qp->happy_meals[qfe_slot] = NULL;
2820
2821 err_out_free_netdev:
2822 free_netdev(dev);
2823
2824 err_out:
2825 return err;
2826 }
2827 #endif
2828
2829 #ifdef CONFIG_PCI
2830 #ifndef CONFIG_SPARC
2831 static int is_quattro_p(struct pci_dev *pdev)
2832 {
2833 struct pci_dev *busdev = pdev->bus->self;
2834 struct list_head *tmp;
2835 int n_hmes;
2836
2837 if (busdev == NULL ||
2838 busdev->vendor != PCI_VENDOR_ID_DEC ||
2839 busdev->device != PCI_DEVICE_ID_DEC_21153)
2840 return 0;
2841
2842 n_hmes = 0;
2843 tmp = pdev->bus->devices.next;
2844 while (tmp != &pdev->bus->devices) {
2845 struct pci_dev *this_pdev = pci_dev_b(tmp);
2846
2847 if (this_pdev->vendor == PCI_VENDOR_ID_SUN &&
2848 this_pdev->device == PCI_DEVICE_ID_SUN_HAPPYMEAL)
2849 n_hmes++;
2850
2851 tmp = tmp->next;
2852 }
2853
2854 if (n_hmes != 4)
2855 return 0;
2856
2857 return 1;
2858 }
2859
2860 /* Fetch MAC address from vital product data of PCI ROM. */
2861 static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, int index, unsigned char *dev_addr)
2862 {
2863 int this_offset;
2864
2865 for (this_offset = 0x20; this_offset < len; this_offset++) {
2866 void __iomem *p = rom_base + this_offset;
2867
2868 if (readb(p + 0) != 0x90 ||
2869 readb(p + 1) != 0x00 ||
2870 readb(p + 2) != 0x09 ||
2871 readb(p + 3) != 0x4e ||
2872 readb(p + 4) != 0x41 ||
2873 readb(p + 5) != 0x06)
2874 continue;
2875
2876 this_offset += 6;
2877 p += 6;
2878
2879 if (index == 0) {
2880 int i;
2881
2882 for (i = 0; i < 6; i++)
2883 dev_addr[i] = readb(p + i);
2884 return 1;
2885 }
2886 index--;
2887 }
2888 return 0;
2889 }
2890
2891 static void get_hme_mac_nonsparc(struct pci_dev *pdev, unsigned char *dev_addr)
2892 {
2893 size_t size;
2894 void __iomem *p = pci_map_rom(pdev, &size);
2895
2896 if (p) {
2897 int index = 0;
2898 int found;
2899
2900 if (is_quattro_p(pdev))
2901 index = PCI_SLOT(pdev->devfn);
2902
2903 found = readb(p) == 0x55 &&
2904 readb(p + 1) == 0xaa &&
2905 find_eth_addr_in_vpd(p, (64 * 1024), index, dev_addr);
2906 pci_unmap_rom(pdev, p);
2907 if (found)
2908 return;
2909 }
2910
2911 /* Sun MAC prefix then 3 random bytes. */
2912 dev_addr[0] = 0x08;
2913 dev_addr[1] = 0x00;
2914 dev_addr[2] = 0x20;
2915 get_random_bytes(&dev_addr[3], 3);
2916 }
2917 #endif /* !(CONFIG_SPARC) */
2918
2919 static int __devinit happy_meal_pci_probe(struct pci_dev *pdev,
2920 const struct pci_device_id *ent)
2921 {
2922 struct quattro *qp = NULL;
2923 #ifdef CONFIG_SPARC
2924 struct device_node *dp;
2925 #endif
2926 struct happy_meal *hp;
2927 struct net_device *dev;
2928 void __iomem *hpreg_base;
2929 unsigned long hpreg_res;
2930 int i, qfe_slot = -1;
2931 char prom_name[64];
2932 int err;
2933
2934 /* Now make sure pci_dev cookie is there. */
2935 #ifdef CONFIG_SPARC
2936 dp = pci_device_to_OF_node(pdev);
2937 strcpy(prom_name, dp->name);
2938 #else
2939 if (is_quattro_p(pdev))
2940 strcpy(prom_name, "SUNW,qfe");
2941 else
2942 strcpy(prom_name, "SUNW,hme");
2943 #endif
2944
2945 err = -ENODEV;
2946
2947 if (pci_enable_device(pdev))
2948 goto err_out;
2949 pci_set_master(pdev);
2950
2951 if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
2952 qp = quattro_pci_find(pdev);
2953 if (qp == NULL)
2954 goto err_out;
2955 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2956 if (qp->happy_meals[qfe_slot] == NULL)
2957 break;
2958 if (qfe_slot == 4)
2959 goto err_out;
2960 }
2961
2962 dev = alloc_etherdev(sizeof(struct happy_meal));
2963 err = -ENOMEM;
2964 if (!dev)
2965 goto err_out;
2966 SET_NETDEV_DEV(dev, &pdev->dev);
2967
2968 if (hme_version_printed++ == 0)
2969 printk(KERN_INFO "%s", version);
2970
2971 dev->base_addr = (long) pdev;
2972
2973 hp = netdev_priv(dev);
2974
2975 hp->happy_dev = pdev;
2976 hp->dma_dev = &pdev->dev;
2977
2978 spin_lock_init(&hp->happy_lock);
2979
2980 if (qp != NULL) {
2981 hp->qfe_parent = qp;
2982 hp->qfe_ent = qfe_slot;
2983 qp->happy_meals[qfe_slot] = dev;
2984 }
2985
2986 hpreg_res = pci_resource_start(pdev, 0);
2987 err = -ENODEV;
2988 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
2989 printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n");
2990 goto err_out_clear_quattro;
2991 }
2992 if (pci_request_regions(pdev, DRV_NAME)) {
2993 printk(KERN_ERR "happymeal(PCI): Cannot obtain PCI resources, "
2994 "aborting.\n");
2995 goto err_out_clear_quattro;
2996 }
2997
2998 if ((hpreg_base = ioremap(hpreg_res, 0x8000)) == NULL) {
2999 printk(KERN_ERR "happymeal(PCI): Unable to remap card memory.\n");
3000 goto err_out_free_res;
3001 }
3002
3003 for (i = 0; i < 6; i++) {
3004 if (macaddr[i] != 0)
3005 break;
3006 }
3007 if (i < 6) { /* a mac address was given */
3008 for (i = 0; i < 6; i++)
3009 dev->dev_addr[i] = macaddr[i];
3010 macaddr[5]++;
3011 } else {
3012 #ifdef CONFIG_SPARC
3013 const unsigned char *addr;
3014 int len;
3015
3016 if (qfe_slot != -1 &&
3017 (addr = of_get_property(dp, "local-mac-address", &len))
3018 != NULL &&
3019 len == 6) {
3020 memcpy(dev->dev_addr, addr, 6);
3021 } else {
3022 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
3023 }
3024 #else
3025 get_hme_mac_nonsparc(pdev, &dev->dev_addr[0]);
3026 #endif
3027 }
3028
3029 /* Layout registers. */
3030 hp->gregs = (hpreg_base + 0x0000UL);
3031 hp->etxregs = (hpreg_base + 0x2000UL);
3032 hp->erxregs = (hpreg_base + 0x4000UL);
3033 hp->bigmacregs = (hpreg_base + 0x6000UL);
3034 hp->tcvregs = (hpreg_base + 0x7000UL);
3035
3036 #ifdef CONFIG_SPARC
3037 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
3038 if (hp->hm_revision == 0xff)
3039 hp->hm_revision = 0xc0 | (pdev->revision & 0x0f);
3040 #else
3041 /* works with this on non-sparc hosts */
3042 hp->hm_revision = 0x20;
3043 #endif
3044
3045 /* Now enable the feature flags we can. */
3046 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
3047 hp->happy_flags = HFLAG_20_21;
3048 else if (hp->hm_revision != 0xa0 && hp->hm_revision != 0xc0)
3049 hp->happy_flags = HFLAG_NOT_A0;
3050
3051 if (qp != NULL)
3052 hp->happy_flags |= HFLAG_QUATTRO;
3053
3054 /* And of course, indicate this is PCI. */
3055 hp->happy_flags |= HFLAG_PCI;
3056
3057 #ifdef CONFIG_SPARC
3058 /* Assume PCI happy meals can handle all burst sizes. */
3059 hp->happy_bursts = DMA_BURSTBITS;
3060 #endif
3061
3062 hp->happy_block = (struct hmeal_init_block *)
3063 dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &hp->hblock_dvma, GFP_KERNEL);
3064
3065 err = -ENODEV;
3066 if (!hp->happy_block) {
3067 printk(KERN_ERR "happymeal(PCI): Cannot get hme init block.\n");
3068 goto err_out_iounmap;
3069 }
3070
3071 hp->linkcheck = 0;
3072 hp->timer_state = asleep;
3073 hp->timer_ticks = 0;
3074
3075 init_timer(&hp->happy_timer);
3076
3077 hp->dev = dev;
3078 dev->netdev_ops = &hme_netdev_ops;
3079 dev->watchdog_timeo = 5*HZ;
3080 dev->ethtool_ops = &hme_ethtool_ops;
3081 dev->irq = pdev->irq;
3082 dev->dma = 0;
3083
3084 /* Happy Meal can do it all... */
3085 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
3086
3087 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
3088 /* Hook up PCI register/descriptor accessors. */
3089 hp->read_desc32 = pci_hme_read_desc32;
3090 hp->write_txd = pci_hme_write_txd;
3091 hp->write_rxd = pci_hme_write_rxd;
3092 hp->read32 = pci_hme_read32;
3093 hp->write32 = pci_hme_write32;
3094 #endif
3095
3096 /* Grrr, Happy Meal comes up by default not advertising
3097 * full duplex 100baseT capabilities, fix this.
3098 */
3099 spin_lock_irq(&hp->happy_lock);
3100 happy_meal_set_initial_advertisement(hp);
3101 spin_unlock_irq(&hp->happy_lock);
3102
3103 if (register_netdev(hp->dev)) {
3104 printk(KERN_ERR "happymeal(PCI): Cannot register net device, "
3105 "aborting.\n");
3106 goto err_out_iounmap;
3107 }
3108
3109 dev_set_drvdata(&pdev->dev, hp);
3110
3111 if (!qfe_slot) {
3112 struct pci_dev *qpdev = qp->quattro_dev;
3113
3114 prom_name[0] = 0;
3115 if (!strncmp(dev->name, "eth", 3)) {
3116 int i = simple_strtoul(dev->name + 3, NULL, 10);
3117 sprintf(prom_name, "-%d", i + 3);
3118 }
3119 printk(KERN_INFO "%s%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet ", dev->name, prom_name);
3120 if (qpdev->vendor == PCI_VENDOR_ID_DEC &&
3121 qpdev->device == PCI_DEVICE_ID_DEC_21153)
3122 printk("DEC 21153 PCI Bridge\n");
3123 else
3124 printk("unknown bridge %04x.%04x\n",
3125 qpdev->vendor, qpdev->device);
3126 }
3127
3128 if (qfe_slot != -1)
3129 printk(KERN_INFO "%s: Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet ",
3130 dev->name, qfe_slot);
3131 else
3132 printk(KERN_INFO "%s: HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet ",
3133 dev->name);
3134
3135 printk("%pM\n", dev->dev_addr);
3136
3137 return 0;
3138
3139 err_out_iounmap:
3140 iounmap(hp->gregs);
3141
3142 err_out_free_res:
3143 pci_release_regions(pdev);
3144
3145 err_out_clear_quattro:
3146 if (qp != NULL)
3147 qp->happy_meals[qfe_slot] = NULL;
3148
3149 free_netdev(dev);
3150
3151 err_out:
3152 return err;
3153 }
3154
3155 static void __devexit happy_meal_pci_remove(struct pci_dev *pdev)
3156 {
3157 struct happy_meal *hp = dev_get_drvdata(&pdev->dev);
3158 struct net_device *net_dev = hp->dev;
3159
3160 unregister_netdev(net_dev);
3161
3162 dma_free_coherent(hp->dma_dev, PAGE_SIZE,
3163 hp->happy_block, hp->hblock_dvma);
3164 iounmap(hp->gregs);
3165 pci_release_regions(hp->happy_dev);
3166
3167 free_netdev(net_dev);
3168
3169 dev_set_drvdata(&pdev->dev, NULL);
3170 }
3171
3172 static DEFINE_PCI_DEVICE_TABLE(happymeal_pci_ids) = {
3173 { PCI_DEVICE(PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_HAPPYMEAL) },
3174 { } /* Terminating entry */
3175 };
3176
3177 MODULE_DEVICE_TABLE(pci, happymeal_pci_ids);
3178
3179 static struct pci_driver hme_pci_driver = {
3180 .name = "hme",
3181 .id_table = happymeal_pci_ids,
3182 .probe = happy_meal_pci_probe,
3183 .remove = __devexit_p(happy_meal_pci_remove),
3184 };
3185
3186 static int __init happy_meal_pci_init(void)
3187 {
3188 return pci_register_driver(&hme_pci_driver);
3189 }
3190
3191 static void happy_meal_pci_exit(void)
3192 {
3193 pci_unregister_driver(&hme_pci_driver);
3194
3195 while (qfe_pci_list) {
3196 struct quattro *qfe = qfe_pci_list;
3197 struct quattro *next = qfe->next;
3198
3199 kfree(qfe);
3200
3201 qfe_pci_list = next;
3202 }
3203 }
3204
3205 #endif
3206
3207 #ifdef CONFIG_SBUS
3208 static int __devinit hme_sbus_probe(struct platform_device *op, const struct of_device_id *match)
3209 {
3210 struct device_node *dp = op->dev.of_node;
3211 const char *model = of_get_property(dp, "model", NULL);
3212 int is_qfe = (match->data != NULL);
3213
3214 if (!is_qfe && model && !strcmp(model, "SUNW,sbus-qfe"))
3215 is_qfe = 1;
3216
3217 return happy_meal_sbus_probe_one(op, is_qfe);
3218 }
3219
3220 static int __devexit hme_sbus_remove(struct platform_device *op)
3221 {
3222 struct happy_meal *hp = dev_get_drvdata(&op->dev);
3223 struct net_device *net_dev = hp->dev;
3224
3225 unregister_netdev(net_dev);
3226
3227
3228 of_iounmap(&op->resource[0], hp->gregs, GREG_REG_SIZE);
3229 of_iounmap(&op->resource[1], hp->etxregs, ETX_REG_SIZE);
3230 of_iounmap(&op->resource[2], hp->erxregs, ERX_REG_SIZE);
3231 of_iounmap(&op->resource[3], hp->bigmacregs, BMAC_REG_SIZE);
3232 of_iounmap(&op->resource[4], hp->tcvregs, TCVR_REG_SIZE);
3233 dma_free_coherent(hp->dma_dev,
3234 PAGE_SIZE,
3235 hp->happy_block,
3236 hp->hblock_dvma);
3237
3238 free_netdev(net_dev);
3239
3240 dev_set_drvdata(&op->dev, NULL);
3241
3242 return 0;
3243 }
3244
3245 static const struct of_device_id hme_sbus_match[] = {
3246 {
3247 .name = "SUNW,hme",
3248 },
3249 {
3250 .name = "SUNW,qfe",
3251 .data = (void *) 1,
3252 },
3253 {
3254 .name = "qfe",
3255 .data = (void *) 1,
3256 },
3257 {},
3258 };
3259
3260 MODULE_DEVICE_TABLE(of, hme_sbus_match);
3261
3262 static struct of_platform_driver hme_sbus_driver = {
3263 .driver = {
3264 .name = "hme",
3265 .owner = THIS_MODULE,
3266 .of_match_table = hme_sbus_match,
3267 },
3268 .probe = hme_sbus_probe,
3269 .remove = __devexit_p(hme_sbus_remove),
3270 };
3271
3272 static int __init happy_meal_sbus_init(void)
3273 {
3274 int err;
3275
3276 err = of_register_platform_driver(&hme_sbus_driver);
3277 if (!err)
3278 err = quattro_sbus_register_irqs();
3279
3280 return err;
3281 }
3282
3283 static void happy_meal_sbus_exit(void)
3284 {
3285 of_unregister_platform_driver(&hme_sbus_driver);
3286 quattro_sbus_free_irqs();
3287
3288 while (qfe_sbus_list) {
3289 struct quattro *qfe = qfe_sbus_list;
3290 struct quattro *next = qfe->next;
3291
3292 kfree(qfe);
3293
3294 qfe_sbus_list = next;
3295 }
3296 }
3297 #endif
3298
3299 static int __init happy_meal_probe(void)
3300 {
3301 int err = 0;
3302
3303 #ifdef CONFIG_SBUS
3304 err = happy_meal_sbus_init();
3305 #endif
3306 #ifdef CONFIG_PCI
3307 if (!err) {
3308 err = happy_meal_pci_init();
3309 #ifdef CONFIG_SBUS
3310 if (err)
3311 happy_meal_sbus_exit();
3312 #endif
3313 }
3314 #endif
3315
3316 return err;
3317 }
3318
3319
3320 static void __exit happy_meal_exit(void)
3321 {
3322 #ifdef CONFIG_SBUS
3323 happy_meal_sbus_exit();
3324 #endif
3325 #ifdef CONFIG_PCI
3326 happy_meal_pci_exit();
3327 #endif
3328 }
3329
3330 module_init(happy_meal_probe);
3331 module_exit(happy_meal_exit);
Tomato firmware and modifications.