release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/stmmac/dwmac100_core.c

   1 /*******************************************************************************
   2   This is the driver for the MAC 10/100 on-chip Ethernet controller
   3   currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
   4
   5   DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
   6   this code.
   7
   8   This only implements the mac core functions for this chip.
   9
  10   Copyright (C) 2007-2009  STMicroelectronics Ltd
  11
  12   This program is free software; you can redistribute it and/or modify it
  13   under the terms and conditions of the GNU General Public License,
  14   version 2, as published by the Free Software Foundation.
  15
  16   This program is distributed in the hope it will be useful, but WITHOUT
  17   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19   more details.
  20
  21   You should have received a copy of the GNU General Public License along with
  22   this program; if not, write to the Free Software Foundation, Inc.,
  23   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  24
  25   The full GNU General Public License is included in this distribution in
  26   the file called "COPYING".
  27
  28   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  29 *******************************************************************************/
  30
  31 #include <linux/crc32.h>
  32 #include "dwmac100.h"
  33
  34 static void dwmac100_core_init(unsigned long ioaddr)
  35 {
  36         u32 value = readl(ioaddr + MAC_CONTROL);
  37
  38         writel((value | MAC_CORE_INIT), ioaddr + MAC_CONTROL);
  39
  40 #ifdef STMMAC_VLAN_TAG_USED
  41         writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
  42 #endif
  43 }
  44
  45 static void dwmac100_dump_mac_regs(unsigned long ioaddr)
  46 {
  47         pr_info("\t----------------------------------------------\n"
  48                 "\t  DWMAC 100 CSR (base addr = 0x%8x)\n"
  49                 "\t----------------------------------------------\n",
  50                 (unsigned int)ioaddr);
  51         pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,
  52                 readl(ioaddr + MAC_CONTROL));
  53         pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,
  54                 readl(ioaddr + MAC_ADDR_HIGH));
  55         pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW,
  56                 readl(ioaddr + MAC_ADDR_LOW));
  57         pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n",
  58                 MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));
  59         pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n",
  60                 MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));
  61         pr_info("\tflow control (offset 0x%x): 0x%08x\n",
  62                 MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));
  63         pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1,
  64                 readl(ioaddr + MAC_VLAN1));
  65         pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,
  66                 readl(ioaddr + MAC_VLAN2));
  67         pr_info("\n\tMAC management counter registers\n");
  68         pr_info("\t MMC crtl (offset 0x%x): 0x%08x\n",
  69                 MMC_CONTROL, readl(ioaddr + MMC_CONTROL));
  70         pr_info("\t MMC High Interrupt (offset 0x%x): 0x%08x\n",
  71                 MMC_HIGH_INTR, readl(ioaddr + MMC_HIGH_INTR));
  72         pr_info("\t MMC Low Interrupt (offset 0x%x): 0x%08x\n",
  73                 MMC_LOW_INTR, readl(ioaddr + MMC_LOW_INTR));
  74         pr_info("\t MMC High Interrupt Mask (offset 0x%x): 0x%08x\n",
  75                 MMC_HIGH_INTR_MASK, readl(ioaddr + MMC_HIGH_INTR_MASK));
  76         pr_info("\t MMC Low Interrupt Mask (offset 0x%x): 0x%08x\n",
  77                 MMC_LOW_INTR_MASK, readl(ioaddr + MMC_LOW_INTR_MASK));
  78 }
  79
  80 static void dwmac100_irq_status(unsigned long ioaddr)
  81 {
  82         return;
  83 }
  84
  85 static void dwmac100_set_umac_addr(unsigned long ioaddr, unsigned char *addr,
  86                                    unsigned int reg_n)
  87 {
  88         stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
  89 }
  90
  91 static void dwmac100_get_umac_addr(unsigned long ioaddr, unsigned char *addr,
  92                                    unsigned int reg_n)
  93 {
  94         stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
  95 }
  96
  97 static void dwmac100_set_filter(struct net_device *dev)
  98 {
  99         unsigned long ioaddr = dev->base_addr;
 100         u32 value = readl(ioaddr + MAC_CONTROL);
 101
 102         if (dev->flags & IFF_PROMISC) {
 103                 value |= MAC_CONTROL_PR;
 104                 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO |
 105                            MAC_CONTROL_HP);
 106         } else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
 107                    || (dev->flags & IFF_ALLMULTI)) {
 108                 value |= MAC_CONTROL_PM;
 109                 value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO);
 110                 writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
 111                 writel(0xffffffff, ioaddr + MAC_HASH_LOW);
 112         } else if (netdev_mc_empty(dev)) {      /* no multicast */
 113                 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF |
 114                            MAC_CONTROL_HO | MAC_CONTROL_HP);
 115         } else {
 116                 u32 mc_filter[2];
 117                 struct netdev_hw_addr *ha;
 118
 119                 /* Perfect filter mode for physical address and Hash
 120                    filter for multicast */
 121                 value |= MAC_CONTROL_HP;
 122                 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR |
 123                            MAC_CONTROL_IF | MAC_CONTROL_HO);
 124
 125                 memset(mc_filter, 0, sizeof(mc_filter));
 126                 netdev_for_each_mc_addr(ha, dev) {
 127                         /* The upper 6 bits of the calculated CRC are used to
 128                          * index the contens of the hash table */
 129                         int bit_nr =
 130                             ether_crc(ETH_ALEN, ha->addr) >> 26;
 131                         /* The most significant bit determines the register to
 132                          * use (H/L) while the other 5 bits determine the bit
 133                          * within the register. */
 134                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
 135                 }
 136                 writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
 137                 writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
 138         }
 139
 140         writel(value, ioaddr + MAC_CONTROL);
 141
 142         CHIP_DBG(KERN_INFO "%s: CTRL reg: 0x%08x Hash regs: "
 143             "HI 0x%08x, LO 0x%08x\n",
 144             __func__, readl(ioaddr + MAC_CONTROL),
 145             readl(ioaddr + MAC_HASH_HIGH), readl(ioaddr + MAC_HASH_LOW));
 146 }
 147
 148 static void dwmac100_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
 149                                unsigned int fc, unsigned int pause_time)
 150 {
 151         unsigned int flow = MAC_FLOW_CTRL_ENABLE;
 152
 153         if (duplex)
 154                 flow |= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
 155         writel(flow, ioaddr + MAC_FLOW_CTRL);
 156 }
 157
 158 /* No PMT module supported for this Ethernet Controller.
 159  * Tested on ST platforms only.
 160  */
 161 static void dwmac100_pmt(unsigned long ioaddr, unsigned long mode)
 162 {
 163         return;
 164 }
 165
 166 struct stmmac_ops dwmac100_ops = {
 167         .core_init = dwmac100_core_init,
 168         .dump_regs = dwmac100_dump_mac_regs,
 169         .host_irq_status = dwmac100_irq_status,
 170         .set_filter = dwmac100_set_filter,
 171         .flow_ctrl = dwmac100_flow_ctrl,
 172         .pmt = dwmac100_pmt,
 173         .set_umac_addr = dwmac100_set_umac_addr,
 174         .get_umac_addr = dwmac100_get_umac_addr,
 175 };
 176
 177 struct mac_device_info *dwmac100_setup(unsigned long ioaddr)
 178 {
 179         struct mac_device_info *mac;
 180
 181         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 182         if (!mac)
 183                 return NULL;
 184
 185         pr_info("\tDWMAC100\n");
 186
 187         mac->mac = &dwmac100_ops;
 188         mac->dma = &dwmac100_dma_ops;
 189
 190         mac->pmt = PMT_NOT_SUPPORTED;
 191         mac->link.port = MAC_CONTROL_PS;
 192         mac->link.duplex = MAC_CONTROL_F;
 193         mac->link.speed = 0;
 194         mac->mii.addr = MAC_MII_ADDR;
 195         mac->mii.data = MAC_MII_DATA;
 196
 197         return mac;
 198 }