2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/pci.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/mii.h>
31 #include <linux/crc32.h>
32 #include <linux/delay.h>
33 #include <linux/spinlock.h>
36 #include <linux/ipv6.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/if_vlan.h>
40 #include <linux/slab.h>
41 #include <net/ip6_checksum.h>
44 static int force_pseudohp
= -1;
45 static int no_pseudohp
= -1;
46 static int no_extplug
= -1;
47 module_param(force_pseudohp
, int, 0);
48 MODULE_PARM_DESC(force_pseudohp
,
49 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
50 module_param(no_pseudohp
, int, 0);
51 MODULE_PARM_DESC(no_pseudohp
, "Disable pseudo hot-plug feature.");
52 module_param(no_extplug
, int, 0);
53 MODULE_PARM_DESC(no_extplug
,
54 "Do not use external plug signal for pseudo hot-plug.");
57 jme_mdio_read(struct net_device
*netdev
, int phy
, int reg
)
59 struct jme_adapter
*jme
= netdev_priv(netdev
);
60 int i
, val
, again
= (reg
== MII_BMSR
) ? 1 : 0;
63 jwrite32(jme
, JME_SMI
, SMI_OP_REQ
|
68 for (i
= JME_PHY_TIMEOUT
* 50 ; i
> 0 ; --i
) {
70 val
= jread32(jme
, JME_SMI
);
71 if ((val
& SMI_OP_REQ
) == 0)
76 jeprintk(jme
->pdev
, "phy(%d) read timeout : %d\n", phy
, reg
);
83 return (val
& SMI_DATA_MASK
) >> SMI_DATA_SHIFT
;
87 jme_mdio_write(struct net_device
*netdev
,
88 int phy
, int reg
, int val
)
90 struct jme_adapter
*jme
= netdev_priv(netdev
);
93 jwrite32(jme
, JME_SMI
, SMI_OP_WRITE
| SMI_OP_REQ
|
94 ((val
<< SMI_DATA_SHIFT
) & SMI_DATA_MASK
) |
95 smi_phy_addr(phy
) | smi_reg_addr(reg
));
98 for (i
= JME_PHY_TIMEOUT
* 50 ; i
> 0 ; --i
) {
100 if ((jread32(jme
, JME_SMI
) & SMI_OP_REQ
) == 0)
105 jeprintk(jme
->pdev
, "phy(%d) write timeout : %d\n", phy
, reg
);
109 jme_reset_phy_processor(struct jme_adapter
*jme
)
113 jme_mdio_write(jme
->dev
,
115 MII_ADVERTISE
, ADVERTISE_ALL
|
116 ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
118 if (jme
->pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
)
119 jme_mdio_write(jme
->dev
,
122 ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
124 val
= jme_mdio_read(jme
->dev
,
128 jme_mdio_write(jme
->dev
,
130 MII_BMCR
, val
| BMCR_RESET
);
134 jme_setup_wakeup_frame(struct jme_adapter
*jme
,
135 u32
*mask
, u32 crc
, int fnr
)
142 jwrite32(jme
, JME_WFOI
, WFOI_CRC_SEL
| (fnr
& WFOI_FRAME_SEL
));
144 jwrite32(jme
, JME_WFODP
, crc
);
150 for (i
= 0 ; i
< WAKEUP_FRAME_MASK_DWNR
; ++i
) {
151 jwrite32(jme
, JME_WFOI
,
152 ((i
<< WFOI_MASK_SHIFT
) & WFOI_MASK_SEL
) |
153 (fnr
& WFOI_FRAME_SEL
));
155 jwrite32(jme
, JME_WFODP
, mask
[i
]);
161 jme_reset_mac_processor(struct jme_adapter
*jme
)
163 u32 mask
[WAKEUP_FRAME_MASK_DWNR
] = {0, 0, 0, 0};
164 u32 crc
= 0xCDCDCDCD;
168 jwrite32(jme
, JME_GHC
, jme
->reg_ghc
| GHC_SWRST
);
170 jwrite32(jme
, JME_GHC
, jme
->reg_ghc
);
172 jwrite32(jme
, JME_RXDBA_LO
, 0x00000000);
173 jwrite32(jme
, JME_RXDBA_HI
, 0x00000000);
174 jwrite32(jme
, JME_RXQDC
, 0x00000000);
175 jwrite32(jme
, JME_RXNDA
, 0x00000000);
176 jwrite32(jme
, JME_TXDBA_LO
, 0x00000000);
177 jwrite32(jme
, JME_TXDBA_HI
, 0x00000000);
178 jwrite32(jme
, JME_TXQDC
, 0x00000000);
179 jwrite32(jme
, JME_TXNDA
, 0x00000000);
181 jwrite32(jme
, JME_RXMCHT_LO
, 0x00000000);
182 jwrite32(jme
, JME_RXMCHT_HI
, 0x00000000);
183 for (i
= 0 ; i
< WAKEUP_FRAME_NR
; ++i
)
184 jme_setup_wakeup_frame(jme
, mask
, crc
, i
);
186 gpreg0
= GPREG0_DEFAULT
| GPREG0_LNKINTPOLL
;
188 gpreg0
= GPREG0_DEFAULT
;
189 jwrite32(jme
, JME_GPREG0
, gpreg0
);
190 jwrite32(jme
, JME_GPREG1
, GPREG1_DEFAULT
);
194 jme_reset_ghc_speed(struct jme_adapter
*jme
)
196 jme
->reg_ghc
&= ~(GHC_SPEED_1000M
| GHC_DPX
);
197 jwrite32(jme
, JME_GHC
, jme
->reg_ghc
);
201 jme_clear_pm(struct jme_adapter
*jme
)
203 jwrite32(jme
, JME_PMCS
, 0xFFFF0000 | jme
->reg_pmcs
);
204 pci_set_power_state(jme
->pdev
, PCI_D0
);
205 pci_enable_wake(jme
->pdev
, PCI_D0
, false);
209 jme_reload_eeprom(struct jme_adapter
*jme
)
214 val
= jread32(jme
, JME_SMBCSR
);
216 if (val
& SMBCSR_EEPROMD
) {
218 jwrite32(jme
, JME_SMBCSR
, val
);
219 val
|= SMBCSR_RELOAD
;
220 jwrite32(jme
, JME_SMBCSR
, val
);
223 for (i
= JME_EEPROM_RELOAD_TIMEOUT
; i
> 0; --i
) {
225 if ((jread32(jme
, JME_SMBCSR
) & SMBCSR_RELOAD
) == 0)
230 jeprintk(jme
->pdev
, "eeprom reload timeout\n");
239 jme_load_macaddr(struct net_device
*netdev
)
241 struct jme_adapter
*jme
= netdev_priv(netdev
);
242 unsigned char macaddr
[6];
245 spin_lock_bh(&jme
->macaddr_lock
);
246 val
= jread32(jme
, JME_RXUMA_LO
);
247 macaddr
[0] = (val
>> 0) & 0xFF;
248 macaddr
[1] = (val
>> 8) & 0xFF;
249 macaddr
[2] = (val
>> 16) & 0xFF;
250 macaddr
[3] = (val
>> 24) & 0xFF;
251 val
= jread32(jme
, JME_RXUMA_HI
);
252 macaddr
[4] = (val
>> 0) & 0xFF;
253 macaddr
[5] = (val
>> 8) & 0xFF;
254 memcpy(netdev
->dev_addr
, macaddr
, 6);
255 spin_unlock_bh(&jme
->macaddr_lock
);
259 jme_set_rx_pcc(struct jme_adapter
*jme
, int p
)
263 jwrite32(jme
, JME_PCCRX0
,
264 ((PCC_OFF_TO
<< PCCRXTO_SHIFT
) & PCCRXTO_MASK
) |
265 ((PCC_OFF_CNT
<< PCCRX_SHIFT
) & PCCRX_MASK
));
268 jwrite32(jme
, JME_PCCRX0
,
269 ((PCC_P1_TO
<< PCCRXTO_SHIFT
) & PCCRXTO_MASK
) |
270 ((PCC_P1_CNT
<< PCCRX_SHIFT
) & PCCRX_MASK
));
273 jwrite32(jme
, JME_PCCRX0
,
274 ((PCC_P2_TO
<< PCCRXTO_SHIFT
) & PCCRXTO_MASK
) |
275 ((PCC_P2_CNT
<< PCCRX_SHIFT
) & PCCRX_MASK
));
278 jwrite32(jme
, JME_PCCRX0
,
279 ((PCC_P3_TO
<< PCCRXTO_SHIFT
) & PCCRXTO_MASK
) |
280 ((PCC_P3_CNT
<< PCCRX_SHIFT
) & PCCRX_MASK
));
287 if (!(test_bit(JME_FLAG_POLL
, &jme
->flags
)))
288 netif_info(jme
, rx_status
, jme
->dev
, "Switched to PCC_P%d\n", p
);
292 jme_start_irq(struct jme_adapter
*jme
)
294 register struct dynpcc_info
*dpi
= &(jme
->dpi
);
296 jme_set_rx_pcc(jme
, PCC_P1
);
298 dpi
->attempt
= PCC_P1
;
301 jwrite32(jme
, JME_PCCTX
,
302 ((PCC_TX_TO
<< PCCTXTO_SHIFT
) & PCCTXTO_MASK
) |
303 ((PCC_TX_CNT
<< PCCTX_SHIFT
) & PCCTX_MASK
) |
310 jwrite32(jme
, JME_IENS
, INTR_ENABLE
);
314 jme_stop_irq(struct jme_adapter
*jme
)
319 jwrite32f(jme
, JME_IENC
, INTR_ENABLE
);
323 jme_linkstat_from_phy(struct jme_adapter
*jme
)
327 phylink
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, 17);
328 bmsr
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMSR
);
329 if (bmsr
& BMSR_ANCOMP
)
330 phylink
|= PHY_LINK_AUTONEG_COMPLETE
;
336 jme_set_phyfifoa(struct jme_adapter
*jme
)
338 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, 27, 0x0004);
342 jme_set_phyfifob(struct jme_adapter
*jme
)
344 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, 27, 0x0000);
348 jme_check_link(struct net_device
*netdev
, int testonly
)
350 struct jme_adapter
*jme
= netdev_priv(netdev
);
351 u32 phylink
, ghc
, cnt
= JME_SPDRSV_TIMEOUT
, bmcr
, gpreg1
;
358 phylink
= jme_linkstat_from_phy(jme
);
360 phylink
= jread32(jme
, JME_PHY_LINK
);
362 if (phylink
& PHY_LINK_UP
) {
363 if (!(phylink
& PHY_LINK_AUTONEG_COMPLETE
)) {
365 * If we did not enable AN
366 * Speed/Duplex Info should be obtained from SMI
368 phylink
= PHY_LINK_UP
;
370 bmcr
= jme_mdio_read(jme
->dev
,
374 phylink
|= ((bmcr
& BMCR_SPEED1000
) &&
375 (bmcr
& BMCR_SPEED100
) == 0) ?
376 PHY_LINK_SPEED_1000M
:
377 (bmcr
& BMCR_SPEED100
) ?
378 PHY_LINK_SPEED_100M
:
381 phylink
|= (bmcr
& BMCR_FULLDPLX
) ?
384 strcat(linkmsg
, "Forced: ");
387 * Keep polling for speed/duplex resolve complete
389 while (!(phylink
& PHY_LINK_SPEEDDPU_RESOLVED
) &&
395 phylink
= jme_linkstat_from_phy(jme
);
397 phylink
= jread32(jme
, JME_PHY_LINK
);
401 "Waiting speed resolve timeout.\n");
403 strcat(linkmsg
, "ANed: ");
406 if (jme
->phylink
== phylink
) {
413 jme
->phylink
= phylink
;
415 ghc
= jme
->reg_ghc
& ~(GHC_SPEED
| GHC_DPX
|
416 GHC_TO_CLK_PCIE
| GHC_TXMAC_CLK_PCIE
|
417 GHC_TO_CLK_GPHY
| GHC_TXMAC_CLK_GPHY
);
418 switch (phylink
& PHY_LINK_SPEED_MASK
) {
419 case PHY_LINK_SPEED_10M
:
420 ghc
|= GHC_SPEED_10M
|
421 GHC_TO_CLK_PCIE
| GHC_TXMAC_CLK_PCIE
;
422 strcat(linkmsg
, "10 Mbps, ");
424 case PHY_LINK_SPEED_100M
:
425 ghc
|= GHC_SPEED_100M
|
426 GHC_TO_CLK_PCIE
| GHC_TXMAC_CLK_PCIE
;
427 strcat(linkmsg
, "100 Mbps, ");
429 case PHY_LINK_SPEED_1000M
:
430 ghc
|= GHC_SPEED_1000M
|
431 GHC_TO_CLK_GPHY
| GHC_TXMAC_CLK_GPHY
;
432 strcat(linkmsg
, "1000 Mbps, ");
438 if (phylink
& PHY_LINK_DUPLEX
) {
439 jwrite32(jme
, JME_TXMCS
, TXMCS_DEFAULT
);
442 jwrite32(jme
, JME_TXMCS
, TXMCS_DEFAULT
|
446 jwrite32(jme
, JME_TXTRHD
, TXTRHD_TXPEN
|
447 ((0x2000 << TXTRHD_TXP_SHIFT
) & TXTRHD_TXP
) |
449 ((8 << TXTRHD_TXRL_SHIFT
) & TXTRHD_TXRL
));
452 gpreg1
= GPREG1_DEFAULT
;
453 if (is_buggy250(jme
->pdev
->device
, jme
->chiprev
)) {
454 if (!(phylink
& PHY_LINK_DUPLEX
))
455 gpreg1
|= GPREG1_HALFMODEPATCH
;
456 switch (phylink
& PHY_LINK_SPEED_MASK
) {
457 case PHY_LINK_SPEED_10M
:
458 jme_set_phyfifoa(jme
);
459 gpreg1
|= GPREG1_RSSPATCH
;
461 case PHY_LINK_SPEED_100M
:
462 jme_set_phyfifob(jme
);
463 gpreg1
|= GPREG1_RSSPATCH
;
465 case PHY_LINK_SPEED_1000M
:
466 jme_set_phyfifoa(jme
);
473 jwrite32(jme
, JME_GPREG1
, gpreg1
);
474 jwrite32(jme
, JME_GHC
, ghc
);
477 strcat(linkmsg
, (phylink
& PHY_LINK_DUPLEX
) ?
480 strcat(linkmsg
, (phylink
& PHY_LINK_MDI_STAT
) ?
483 netif_info(jme
, link
, jme
->dev
, "Link is up at %s.\n", linkmsg
);
484 netif_carrier_on(netdev
);
489 netif_info(jme
, link
, jme
->dev
, "Link is down.\n");
491 netif_carrier_off(netdev
);
499 jme_setup_tx_resources(struct jme_adapter
*jme
)
501 struct jme_ring
*txring
= &(jme
->txring
[0]);
503 txring
->alloc
= dma_alloc_coherent(&(jme
->pdev
->dev
),
504 TX_RING_ALLOC_SIZE(jme
->tx_ring_size
),
514 txring
->desc
= (void *)ALIGN((unsigned long)(txring
->alloc
),
516 txring
->dma
= ALIGN(txring
->dmaalloc
, RING_DESC_ALIGN
);
517 txring
->next_to_use
= 0;
518 atomic_set(&txring
->next_to_clean
, 0);
519 atomic_set(&txring
->nr_free
, jme
->tx_ring_size
);
521 txring
->bufinf
= kmalloc(sizeof(struct jme_buffer_info
) *
522 jme
->tx_ring_size
, GFP_ATOMIC
);
523 if (unlikely(!(txring
->bufinf
)))
524 goto err_free_txring
;
527 * Initialize Transmit Descriptors
529 memset(txring
->alloc
, 0, TX_RING_ALLOC_SIZE(jme
->tx_ring_size
));
530 memset(txring
->bufinf
, 0,
531 sizeof(struct jme_buffer_info
) * jme
->tx_ring_size
);
536 dma_free_coherent(&(jme
->pdev
->dev
),
537 TX_RING_ALLOC_SIZE(jme
->tx_ring_size
),
543 txring
->dmaalloc
= 0;
545 txring
->bufinf
= NULL
;
551 jme_free_tx_resources(struct jme_adapter
*jme
)
554 struct jme_ring
*txring
= &(jme
->txring
[0]);
555 struct jme_buffer_info
*txbi
;
558 if (txring
->bufinf
) {
559 for (i
= 0 ; i
< jme
->tx_ring_size
; ++i
) {
560 txbi
= txring
->bufinf
+ i
;
562 dev_kfree_skb(txbi
->skb
);
568 txbi
->start_xmit
= 0;
570 kfree(txring
->bufinf
);
573 dma_free_coherent(&(jme
->pdev
->dev
),
574 TX_RING_ALLOC_SIZE(jme
->tx_ring_size
),
578 txring
->alloc
= NULL
;
580 txring
->dmaalloc
= 0;
582 txring
->bufinf
= NULL
;
584 txring
->next_to_use
= 0;
585 atomic_set(&txring
->next_to_clean
, 0);
586 atomic_set(&txring
->nr_free
, 0);
590 jme_enable_tx_engine(struct jme_adapter
*jme
)
595 jwrite32(jme
, JME_TXCS
, TXCS_DEFAULT
| TXCS_SELECT_QUEUE0
);
599 * Setup TX Queue 0 DMA Bass Address
601 jwrite32(jme
, JME_TXDBA_LO
, (__u64
)jme
->txring
[0].dma
& 0xFFFFFFFFUL
);
602 jwrite32(jme
, JME_TXDBA_HI
, (__u64
)(jme
->txring
[0].dma
) >> 32);
603 jwrite32(jme
, JME_TXNDA
, (__u64
)jme
->txring
[0].dma
& 0xFFFFFFFFUL
);
606 * Setup TX Descptor Count
608 jwrite32(jme
, JME_TXQDC
, jme
->tx_ring_size
);
614 jwrite32(jme
, JME_TXCS
, jme
->reg_txcs
|
621 jme_restart_tx_engine(struct jme_adapter
*jme
)
626 jwrite32(jme
, JME_TXCS
, jme
->reg_txcs
|
632 jme_disable_tx_engine(struct jme_adapter
*jme
)
640 jwrite32(jme
, JME_TXCS
, jme
->reg_txcs
| TXCS_SELECT_QUEUE0
);
643 val
= jread32(jme
, JME_TXCS
);
644 for (i
= JME_TX_DISABLE_TIMEOUT
; (val
& TXCS_ENABLE
) && i
> 0 ; --i
) {
646 val
= jread32(jme
, JME_TXCS
);
651 jeprintk(jme
->pdev
, "Disable TX engine timeout.\n");
655 jme_set_clean_rxdesc(struct jme_adapter
*jme
, int i
)
657 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
658 register struct rxdesc
*rxdesc
= rxring
->desc
;
659 struct jme_buffer_info
*rxbi
= rxring
->bufinf
;
665 rxdesc
->desc1
.bufaddrh
= cpu_to_le32((__u64
)rxbi
->mapping
>> 32);
666 rxdesc
->desc1
.bufaddrl
= cpu_to_le32(
667 (__u64
)rxbi
->mapping
& 0xFFFFFFFFUL
);
668 rxdesc
->desc1
.datalen
= cpu_to_le16(rxbi
->len
);
669 if (jme
->dev
->features
& NETIF_F_HIGHDMA
)
670 rxdesc
->desc1
.flags
= RXFLAG_64BIT
;
672 rxdesc
->desc1
.flags
|= RXFLAG_OWN
| RXFLAG_INT
;
676 jme_make_new_rx_buf(struct jme_adapter
*jme
, int i
)
678 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
679 struct jme_buffer_info
*rxbi
= rxring
->bufinf
+ i
;
682 skb
= netdev_alloc_skb(jme
->dev
,
683 jme
->dev
->mtu
+ RX_EXTRA_LEN
);
688 rxbi
->len
= skb_tailroom(skb
);
689 rxbi
->mapping
= pci_map_page(jme
->pdev
,
690 virt_to_page(skb
->data
),
691 offset_in_page(skb
->data
),
699 jme_free_rx_buf(struct jme_adapter
*jme
, int i
)
701 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
702 struct jme_buffer_info
*rxbi
= rxring
->bufinf
;
706 pci_unmap_page(jme
->pdev
,
710 dev_kfree_skb(rxbi
->skb
);
718 jme_free_rx_resources(struct jme_adapter
*jme
)
721 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
724 if (rxring
->bufinf
) {
725 for (i
= 0 ; i
< jme
->rx_ring_size
; ++i
)
726 jme_free_rx_buf(jme
, i
);
727 kfree(rxring
->bufinf
);
730 dma_free_coherent(&(jme
->pdev
->dev
),
731 RX_RING_ALLOC_SIZE(jme
->rx_ring_size
),
734 rxring
->alloc
= NULL
;
736 rxring
->dmaalloc
= 0;
738 rxring
->bufinf
= NULL
;
740 rxring
->next_to_use
= 0;
741 atomic_set(&rxring
->next_to_clean
, 0);
745 jme_setup_rx_resources(struct jme_adapter
*jme
)
748 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
750 rxring
->alloc
= dma_alloc_coherent(&(jme
->pdev
->dev
),
751 RX_RING_ALLOC_SIZE(jme
->rx_ring_size
),
760 rxring
->desc
= (void *)ALIGN((unsigned long)(rxring
->alloc
),
762 rxring
->dma
= ALIGN(rxring
->dmaalloc
, RING_DESC_ALIGN
);
763 rxring
->next_to_use
= 0;
764 atomic_set(&rxring
->next_to_clean
, 0);
766 rxring
->bufinf
= kmalloc(sizeof(struct jme_buffer_info
) *
767 jme
->rx_ring_size
, GFP_ATOMIC
);
768 if (unlikely(!(rxring
->bufinf
)))
769 goto err_free_rxring
;
772 * Initiallize Receive Descriptors
774 memset(rxring
->bufinf
, 0,
775 sizeof(struct jme_buffer_info
) * jme
->rx_ring_size
);
776 for (i
= 0 ; i
< jme
->rx_ring_size
; ++i
) {
777 if (unlikely(jme_make_new_rx_buf(jme
, i
))) {
778 jme_free_rx_resources(jme
);
782 jme_set_clean_rxdesc(jme
, i
);
788 dma_free_coherent(&(jme
->pdev
->dev
),
789 RX_RING_ALLOC_SIZE(jme
->rx_ring_size
),
794 rxring
->dmaalloc
= 0;
796 rxring
->bufinf
= NULL
;
802 jme_enable_rx_engine(struct jme_adapter
*jme
)
807 jwrite32(jme
, JME_RXCS
, jme
->reg_rxcs
|
812 * Setup RX DMA Bass Address
814 jwrite32(jme
, JME_RXDBA_LO
, (__u64
)(jme
->rxring
[0].dma
) & 0xFFFFFFFFUL
);
815 jwrite32(jme
, JME_RXDBA_HI
, (__u64
)(jme
->rxring
[0].dma
) >> 32);
816 jwrite32(jme
, JME_RXNDA
, (__u64
)(jme
->rxring
[0].dma
) & 0xFFFFFFFFUL
);
819 * Setup RX Descriptor Count
821 jwrite32(jme
, JME_RXQDC
, jme
->rx_ring_size
);
824 * Setup Unicast Filter
826 jme_set_multi(jme
->dev
);
832 jwrite32(jme
, JME_RXCS
, jme
->reg_rxcs
|
839 jme_restart_rx_engine(struct jme_adapter
*jme
)
844 jwrite32(jme
, JME_RXCS
, jme
->reg_rxcs
|
851 jme_disable_rx_engine(struct jme_adapter
*jme
)
859 jwrite32(jme
, JME_RXCS
, jme
->reg_rxcs
);
862 val
= jread32(jme
, JME_RXCS
);
863 for (i
= JME_RX_DISABLE_TIMEOUT
; (val
& RXCS_ENABLE
) && i
> 0 ; --i
) {
865 val
= jread32(jme
, JME_RXCS
);
870 jeprintk(jme
->pdev
, "Disable RX engine timeout.\n");
875 jme_rxsum_ok(struct jme_adapter
*jme
, u16 flags
)
877 if (!(flags
& (RXWBFLAG_TCPON
| RXWBFLAG_UDPON
| RXWBFLAG_IPV4
)))
880 if (unlikely((flags
& (RXWBFLAG_MF
| RXWBFLAG_TCPON
| RXWBFLAG_TCPCS
))
881 == RXWBFLAG_TCPON
)) {
882 if (flags
& RXWBFLAG_IPV4
)
883 netif_err(jme
, rx_err
, jme
->dev
, "TCP Checksum error\n");
887 if (unlikely((flags
& (RXWBFLAG_MF
| RXWBFLAG_UDPON
| RXWBFLAG_UDPCS
))
888 == RXWBFLAG_UDPON
)) {
889 if (flags
& RXWBFLAG_IPV4
)
890 netif_err(jme
, rx_err
, jme
->dev
, "UDP Checksum error.\n");
894 if (unlikely((flags
& (RXWBFLAG_IPV4
| RXWBFLAG_IPCS
))
896 netif_err(jme
, rx_err
, jme
->dev
, "IPv4 Checksum error.\n");
904 jme_alloc_and_feed_skb(struct jme_adapter
*jme
, int idx
)
906 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
907 struct rxdesc
*rxdesc
= rxring
->desc
;
908 struct jme_buffer_info
*rxbi
= rxring
->bufinf
;
916 pci_dma_sync_single_for_cpu(jme
->pdev
,
921 if (unlikely(jme_make_new_rx_buf(jme
, idx
))) {
922 pci_dma_sync_single_for_device(jme
->pdev
,
927 ++(NET_STAT(jme
).rx_dropped
);
929 framesize
= le16_to_cpu(rxdesc
->descwb
.framesize
)
932 skb_reserve(skb
, RX_PREPAD_SIZE
);
933 skb_put(skb
, framesize
);
934 skb
->protocol
= eth_type_trans(skb
, jme
->dev
);
936 if (jme_rxsum_ok(jme
, le16_to_cpu(rxdesc
->descwb
.flags
)))
937 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
939 skb
->ip_summed
= CHECKSUM_NONE
;
941 if (rxdesc
->descwb
.flags
& cpu_to_le16(RXWBFLAG_TAGON
)) {
943 jme
->jme_vlan_rx(skb
, jme
->vlgrp
,
944 le16_to_cpu(rxdesc
->descwb
.vlan
));
945 NET_STAT(jme
).rx_bytes
+= 4;
953 if ((rxdesc
->descwb
.flags
& cpu_to_le16(RXWBFLAG_DEST
)) ==
954 cpu_to_le16(RXWBFLAG_DEST_MUL
))
955 ++(NET_STAT(jme
).multicast
);
957 NET_STAT(jme
).rx_bytes
+= framesize
;
958 ++(NET_STAT(jme
).rx_packets
);
961 jme_set_clean_rxdesc(jme
, idx
);
966 jme_process_receive(struct jme_adapter
*jme
, int limit
)
968 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
969 struct rxdesc
*rxdesc
= rxring
->desc
;
970 int i
, j
, ccnt
, desccnt
, mask
= jme
->rx_ring_mask
;
972 if (unlikely(!atomic_dec_and_test(&jme
->rx_cleaning
)))
975 if (unlikely(atomic_read(&jme
->link_changing
) != 1))
978 if (unlikely(!netif_carrier_ok(jme
->dev
)))
981 i
= atomic_read(&rxring
->next_to_clean
);
983 rxdesc
= rxring
->desc
;
986 if ((rxdesc
->descwb
.flags
& cpu_to_le16(RXWBFLAG_OWN
)) ||
987 !(rxdesc
->descwb
.desccnt
& RXWBDCNT_WBCPL
))
991 desccnt
= rxdesc
->descwb
.desccnt
& RXWBDCNT_DCNT
;
993 if (unlikely(desccnt
> 1 ||
994 rxdesc
->descwb
.errstat
& RXWBERR_ALLERR
)) {
996 if (rxdesc
->descwb
.errstat
& RXWBERR_CRCERR
)
997 ++(NET_STAT(jme
).rx_crc_errors
);
998 else if (rxdesc
->descwb
.errstat
& RXWBERR_OVERUN
)
999 ++(NET_STAT(jme
).rx_fifo_errors
);
1001 ++(NET_STAT(jme
).rx_errors
);
1004 limit
-= desccnt
- 1;
1006 for (j
= i
, ccnt
= desccnt
; ccnt
-- ; ) {
1007 jme_set_clean_rxdesc(jme
, j
);
1008 j
= (j
+ 1) & (mask
);
1012 jme_alloc_and_feed_skb(jme
, i
);
1015 i
= (i
+ desccnt
) & (mask
);
1019 atomic_set(&rxring
->next_to_clean
, i
);
1022 atomic_inc(&jme
->rx_cleaning
);
1024 return limit
> 0 ? limit
: 0;
1029 jme_attempt_pcc(struct dynpcc_info
*dpi
, int atmp
)
1031 if (likely(atmp
== dpi
->cur
)) {
1036 if (dpi
->attempt
== atmp
) {
1039 dpi
->attempt
= atmp
;
1046 jme_dynamic_pcc(struct jme_adapter
*jme
)
1048 register struct dynpcc_info
*dpi
= &(jme
->dpi
);
1050 if ((NET_STAT(jme
).rx_bytes
- dpi
->last_bytes
) > PCC_P3_THRESHOLD
)
1051 jme_attempt_pcc(dpi
, PCC_P3
);
1052 else if ((NET_STAT(jme
).rx_packets
- dpi
->last_pkts
) > PCC_P2_THRESHOLD
||
1053 dpi
->intr_cnt
> PCC_INTR_THRESHOLD
)
1054 jme_attempt_pcc(dpi
, PCC_P2
);
1056 jme_attempt_pcc(dpi
, PCC_P1
);
1058 if (unlikely(dpi
->attempt
!= dpi
->cur
&& dpi
->cnt
> 5)) {
1059 if (dpi
->attempt
< dpi
->cur
)
1060 tasklet_schedule(&jme
->rxclean_task
);
1061 jme_set_rx_pcc(jme
, dpi
->attempt
);
1062 dpi
->cur
= dpi
->attempt
;
1068 jme_start_pcc_timer(struct jme_adapter
*jme
)
1070 struct dynpcc_info
*dpi
= &(jme
->dpi
);
1071 dpi
->last_bytes
= NET_STAT(jme
).rx_bytes
;
1072 dpi
->last_pkts
= NET_STAT(jme
).rx_packets
;
1074 jwrite32(jme
, JME_TMCSR
,
1075 TMCSR_EN
| ((0xFFFFFF - PCC_INTERVAL_US
) & TMCSR_CNT
));
1079 jme_stop_pcc_timer(struct jme_adapter
*jme
)
1081 jwrite32(jme
, JME_TMCSR
, 0);
1085 jme_shutdown_nic(struct jme_adapter
*jme
)
1089 phylink
= jme_linkstat_from_phy(jme
);
1091 if (!(phylink
& PHY_LINK_UP
)) {
1093 * Disable all interrupt before issue timer
1096 jwrite32(jme
, JME_TIMER2
, TMCSR_EN
| 0xFFFFFE);
1101 jme_pcc_tasklet(unsigned long arg
)
1103 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1104 struct net_device
*netdev
= jme
->dev
;
1106 if (unlikely(test_bit(JME_FLAG_SHUTDOWN
, &jme
->flags
))) {
1107 jme_shutdown_nic(jme
);
1111 if (unlikely(!netif_carrier_ok(netdev
) ||
1112 (atomic_read(&jme
->link_changing
) != 1)
1114 jme_stop_pcc_timer(jme
);
1118 if (!(test_bit(JME_FLAG_POLL
, &jme
->flags
)))
1119 jme_dynamic_pcc(jme
);
1121 jme_start_pcc_timer(jme
);
1125 jme_polling_mode(struct jme_adapter
*jme
)
1127 jme_set_rx_pcc(jme
, PCC_OFF
);
1131 jme_interrupt_mode(struct jme_adapter
*jme
)
1133 jme_set_rx_pcc(jme
, PCC_P1
);
1137 jme_pseudo_hotplug_enabled(struct jme_adapter
*jme
)
1140 apmc
= jread32(jme
, JME_APMC
);
1141 return apmc
& JME_APMC_PSEUDO_HP_EN
;
1145 jme_start_shutdown_timer(struct jme_adapter
*jme
)
1149 apmc
= jread32(jme
, JME_APMC
) | JME_APMC_PCIE_SD_EN
;
1150 apmc
&= ~JME_APMC_EPIEN_CTRL
;
1152 jwrite32f(jme
, JME_APMC
, apmc
| JME_APMC_EPIEN_CTRL_EN
);
1155 jwrite32f(jme
, JME_APMC
, apmc
);
1157 jwrite32f(jme
, JME_TIMER2
, 0);
1158 set_bit(JME_FLAG_SHUTDOWN
, &jme
->flags
);
1159 jwrite32(jme
, JME_TMCSR
,
1160 TMCSR_EN
| ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY
) & TMCSR_CNT
));
1164 jme_stop_shutdown_timer(struct jme_adapter
*jme
)
1168 jwrite32f(jme
, JME_TMCSR
, 0);
1169 jwrite32f(jme
, JME_TIMER2
, 0);
1170 clear_bit(JME_FLAG_SHUTDOWN
, &jme
->flags
);
1172 apmc
= jread32(jme
, JME_APMC
);
1173 apmc
&= ~(JME_APMC_PCIE_SD_EN
| JME_APMC_EPIEN_CTRL
);
1174 jwrite32f(jme
, JME_APMC
, apmc
| JME_APMC_EPIEN_CTRL_DIS
);
1176 jwrite32f(jme
, JME_APMC
, apmc
);
1180 jme_link_change_tasklet(unsigned long arg
)
1182 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1183 struct net_device
*netdev
= jme
->dev
;
1186 while (!atomic_dec_and_test(&jme
->link_changing
)) {
1187 atomic_inc(&jme
->link_changing
);
1188 netif_info(jme
, intr
, jme
->dev
, "Get link change lock failed.\n");
1189 while (atomic_read(&jme
->link_changing
) != 1)
1190 netif_info(jme
, intr
, jme
->dev
, "Waiting link change lock.\n");
1193 if (jme_check_link(netdev
, 1) && jme
->old_mtu
== netdev
->mtu
)
1196 jme
->old_mtu
= netdev
->mtu
;
1197 netif_stop_queue(netdev
);
1198 if (jme_pseudo_hotplug_enabled(jme
))
1199 jme_stop_shutdown_timer(jme
);
1201 jme_stop_pcc_timer(jme
);
1202 tasklet_disable(&jme
->txclean_task
);
1203 tasklet_disable(&jme
->rxclean_task
);
1204 tasklet_disable(&jme
->rxempty_task
);
1206 if (netif_carrier_ok(netdev
)) {
1207 jme_reset_ghc_speed(jme
);
1208 jme_disable_rx_engine(jme
);
1209 jme_disable_tx_engine(jme
);
1210 jme_reset_mac_processor(jme
);
1211 jme_free_rx_resources(jme
);
1212 jme_free_tx_resources(jme
);
1214 if (test_bit(JME_FLAG_POLL
, &jme
->flags
))
1215 jme_polling_mode(jme
);
1217 netif_carrier_off(netdev
);
1220 jme_check_link(netdev
, 0);
1221 if (netif_carrier_ok(netdev
)) {
1222 rc
= jme_setup_rx_resources(jme
);
1224 jeprintk(jme
->pdev
, "Allocating resources for RX error"
1225 ", Device STOPPED!\n");
1226 goto out_enable_tasklet
;
1229 rc
= jme_setup_tx_resources(jme
);
1231 jeprintk(jme
->pdev
, "Allocating resources for TX error"
1232 ", Device STOPPED!\n");
1233 goto err_out_free_rx_resources
;
1236 jme_enable_rx_engine(jme
);
1237 jme_enable_tx_engine(jme
);
1239 netif_start_queue(netdev
);
1241 if (test_bit(JME_FLAG_POLL
, &jme
->flags
))
1242 jme_interrupt_mode(jme
);
1244 jme_start_pcc_timer(jme
);
1245 } else if (jme_pseudo_hotplug_enabled(jme
)) {
1246 jme_start_shutdown_timer(jme
);
1249 goto out_enable_tasklet
;
1251 err_out_free_rx_resources
:
1252 jme_free_rx_resources(jme
);
1254 tasklet_enable(&jme
->txclean_task
);
1255 tasklet_hi_enable(&jme
->rxclean_task
);
1256 tasklet_hi_enable(&jme
->rxempty_task
);
1258 atomic_inc(&jme
->link_changing
);
1262 jme_rx_clean_tasklet(unsigned long arg
)
1264 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1265 struct dynpcc_info
*dpi
= &(jme
->dpi
);
1267 jme_process_receive(jme
, jme
->rx_ring_size
);
1273 jme_poll(JME_NAPI_HOLDER(holder
), JME_NAPI_WEIGHT(budget
))
1275 struct jme_adapter
*jme
= jme_napi_priv(holder
);
1278 rest
= jme_process_receive(jme
, JME_NAPI_WEIGHT_VAL(budget
));
1280 while (atomic_read(&jme
->rx_empty
) > 0) {
1281 atomic_dec(&jme
->rx_empty
);
1282 ++(NET_STAT(jme
).rx_dropped
);
1283 jme_restart_rx_engine(jme
);
1285 atomic_inc(&jme
->rx_empty
);
1288 JME_RX_COMPLETE(netdev
, holder
);
1289 jme_interrupt_mode(jme
);
1292 JME_NAPI_WEIGHT_SET(budget
, rest
);
1293 return JME_NAPI_WEIGHT_VAL(budget
) - rest
;
1297 jme_rx_empty_tasklet(unsigned long arg
)
1299 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1301 if (unlikely(atomic_read(&jme
->link_changing
) != 1))
1304 if (unlikely(!netif_carrier_ok(jme
->dev
)))
1307 netif_info(jme
, rx_status
, jme
->dev
, "RX Queue Full!\n");
1309 jme_rx_clean_tasklet(arg
);
1311 while (atomic_read(&jme
->rx_empty
) > 0) {
1312 atomic_dec(&jme
->rx_empty
);
1313 ++(NET_STAT(jme
).rx_dropped
);
1314 jme_restart_rx_engine(jme
);
1316 atomic_inc(&jme
->rx_empty
);
1320 jme_wake_queue_if_stopped(struct jme_adapter
*jme
)
1322 struct jme_ring
*txring
= &(jme
->txring
[0]);
1325 if (unlikely(netif_queue_stopped(jme
->dev
) &&
1326 atomic_read(&txring
->nr_free
) >= (jme
->tx_wake_threshold
))) {
1327 netif_info(jme
, tx_done
, jme
->dev
, "TX Queue Waked.\n");
1328 netif_wake_queue(jme
->dev
);
1334 jme_tx_clean_tasklet(unsigned long arg
)
1336 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1337 struct jme_ring
*txring
= &(jme
->txring
[0]);
1338 struct txdesc
*txdesc
= txring
->desc
;
1339 struct jme_buffer_info
*txbi
= txring
->bufinf
, *ctxbi
, *ttxbi
;
1340 int i
, j
, cnt
= 0, max
, err
, mask
;
1342 tx_dbg(jme
, "Into txclean.\n");
1344 if (unlikely(!atomic_dec_and_test(&jme
->tx_cleaning
)))
1347 if (unlikely(atomic_read(&jme
->link_changing
) != 1))
1350 if (unlikely(!netif_carrier_ok(jme
->dev
)))
1353 max
= jme
->tx_ring_size
- atomic_read(&txring
->nr_free
);
1354 mask
= jme
->tx_ring_mask
;
1356 for (i
= atomic_read(&txring
->next_to_clean
) ; cnt
< max
; ) {
1360 if (likely(ctxbi
->skb
&&
1361 !(txdesc
[i
].descwb
.flags
& TXWBFLAG_OWN
))) {
1363 tx_dbg(jme
, "txclean: %d+%d@%lu\n",
1364 i
, ctxbi
->nr_desc
, jiffies
);
1366 err
= txdesc
[i
].descwb
.flags
& TXWBFLAG_ALLERR
;
1368 for (j
= 1 ; j
< ctxbi
->nr_desc
; ++j
) {
1369 ttxbi
= txbi
+ ((i
+ j
) & (mask
));
1370 txdesc
[(i
+ j
) & (mask
)].dw
[0] = 0;
1372 pci_unmap_page(jme
->pdev
,
1381 dev_kfree_skb(ctxbi
->skb
);
1383 cnt
+= ctxbi
->nr_desc
;
1385 if (unlikely(err
)) {
1386 ++(NET_STAT(jme
).tx_carrier_errors
);
1388 ++(NET_STAT(jme
).tx_packets
);
1389 NET_STAT(jme
).tx_bytes
+= ctxbi
->len
;
1394 ctxbi
->start_xmit
= 0;
1400 i
= (i
+ ctxbi
->nr_desc
) & mask
;
1405 tx_dbg(jme
, "txclean: done %d@%lu.\n", i
, jiffies
);
1406 atomic_set(&txring
->next_to_clean
, i
);
1407 atomic_add(cnt
, &txring
->nr_free
);
1409 jme_wake_queue_if_stopped(jme
);
1412 atomic_inc(&jme
->tx_cleaning
);
1416 jme_intr_msi(struct jme_adapter
*jme
, u32 intrstat
)
1421 jwrite32f(jme
, JME_IENC
, INTR_ENABLE
);
1423 if (intrstat
& (INTR_LINKCH
| INTR_SWINTR
)) {
1425 * Link change event is critical
1426 * all other events are ignored
1428 jwrite32(jme
, JME_IEVE
, intrstat
);
1429 tasklet_schedule(&jme
->linkch_task
);
1433 if (intrstat
& INTR_TMINTR
) {
1434 jwrite32(jme
, JME_IEVE
, INTR_TMINTR
);
1435 tasklet_schedule(&jme
->pcc_task
);
1438 if (intrstat
& (INTR_PCCTXTO
| INTR_PCCTX
)) {
1439 jwrite32(jme
, JME_IEVE
, INTR_PCCTXTO
| INTR_PCCTX
| INTR_TX0
);
1440 tasklet_schedule(&jme
->txclean_task
);
1443 if ((intrstat
& (INTR_PCCRX0TO
| INTR_PCCRX0
| INTR_RX0EMP
))) {
1444 jwrite32(jme
, JME_IEVE
, (intrstat
& (INTR_PCCRX0TO
|
1450 if (test_bit(JME_FLAG_POLL
, &jme
->flags
)) {
1451 if (intrstat
& INTR_RX0EMP
)
1452 atomic_inc(&jme
->rx_empty
);
1454 if ((intrstat
& (INTR_PCCRX0TO
| INTR_PCCRX0
| INTR_RX0EMP
))) {
1455 if (likely(JME_RX_SCHEDULE_PREP(jme
))) {
1456 jme_polling_mode(jme
);
1457 JME_RX_SCHEDULE(jme
);
1461 if (intrstat
& INTR_RX0EMP
) {
1462 atomic_inc(&jme
->rx_empty
);
1463 tasklet_hi_schedule(&jme
->rxempty_task
);
1464 } else if (intrstat
& (INTR_PCCRX0TO
| INTR_PCCRX0
)) {
1465 tasklet_hi_schedule(&jme
->rxclean_task
);
1471 * Re-enable interrupt
1473 jwrite32f(jme
, JME_IENS
, INTR_ENABLE
);
1477 jme_intr(int irq
, void *dev_id
)
1479 struct net_device
*netdev
= dev_id
;
1480 struct jme_adapter
*jme
= netdev_priv(netdev
);
1483 intrstat
= jread32(jme
, JME_IEVE
);
1486 * Check if it's really an interrupt for us
1488 if (unlikely((intrstat
& INTR_ENABLE
) == 0))
1492 * Check if the device still exist
1494 if (unlikely(intrstat
== ~((typeof(intrstat
))0)))
1497 jme_intr_msi(jme
, intrstat
);
1503 jme_msi(int irq
, void *dev_id
)
1505 struct net_device
*netdev
= dev_id
;
1506 struct jme_adapter
*jme
= netdev_priv(netdev
);
1509 intrstat
= jread32(jme
, JME_IEVE
);
1511 jme_intr_msi(jme
, intrstat
);
1517 jme_reset_link(struct jme_adapter
*jme
)
1519 jwrite32(jme
, JME_TMCSR
, TMCSR_SWIT
);
1523 jme_restart_an(struct jme_adapter
*jme
)
1527 spin_lock_bh(&jme
->phy_lock
);
1528 bmcr
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
);
1529 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
1530 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
, bmcr
);
1531 spin_unlock_bh(&jme
->phy_lock
);
1535 jme_request_irq(struct jme_adapter
*jme
)
1538 struct net_device
*netdev
= jme
->dev
;
1539 irq_handler_t handler
= jme_intr
;
1540 int irq_flags
= IRQF_SHARED
;
1542 if (!pci_enable_msi(jme
->pdev
)) {
1543 set_bit(JME_FLAG_MSI
, &jme
->flags
);
1548 rc
= request_irq(jme
->pdev
->irq
, handler
, irq_flags
, netdev
->name
,
1552 "Unable to request %s interrupt (return: %d)\n",
1553 test_bit(JME_FLAG_MSI
, &jme
->flags
) ? "MSI" : "INTx",
1556 if (test_bit(JME_FLAG_MSI
, &jme
->flags
)) {
1557 pci_disable_msi(jme
->pdev
);
1558 clear_bit(JME_FLAG_MSI
, &jme
->flags
);
1561 netdev
->irq
= jme
->pdev
->irq
;
1568 jme_free_irq(struct jme_adapter
*jme
)
1570 free_irq(jme
->pdev
->irq
, jme
->dev
);
1571 if (test_bit(JME_FLAG_MSI
, &jme
->flags
)) {
1572 pci_disable_msi(jme
->pdev
);
1573 clear_bit(JME_FLAG_MSI
, &jme
->flags
);
1574 jme
->dev
->irq
= jme
->pdev
->irq
;
1579 jme_phy_on(struct jme_adapter
*jme
)
1583 bmcr
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
);
1584 bmcr
&= ~BMCR_PDOWN
;
1585 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
, bmcr
);
1589 jme_open(struct net_device
*netdev
)
1591 struct jme_adapter
*jme
= netdev_priv(netdev
);
1595 JME_NAPI_ENABLE(jme
);
1597 tasklet_enable(&jme
->linkch_task
);
1598 tasklet_enable(&jme
->txclean_task
);
1599 tasklet_hi_enable(&jme
->rxclean_task
);
1600 tasklet_hi_enable(&jme
->rxempty_task
);
1602 rc
= jme_request_irq(jme
);
1608 if (test_bit(JME_FLAG_SSET
, &jme
->flags
)) {
1610 jme_set_settings(netdev
, &jme
->old_ecmd
);
1612 jme_reset_phy_processor(jme
);
1615 jme_reset_link(jme
);
1620 netif_stop_queue(netdev
);
1621 netif_carrier_off(netdev
);
1627 jme_set_100m_half(struct jme_adapter
*jme
)
1631 bmcr
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
);
1632 tmp
= bmcr
& ~(BMCR_ANENABLE
| BMCR_SPEED100
|
1633 BMCR_SPEED1000
| BMCR_FULLDPLX
);
1634 tmp
|= BMCR_SPEED100
;
1637 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
, tmp
);
1640 jwrite32(jme
, JME_GHC
, GHC_SPEED_100M
| GHC_LINK_POLL
);
1642 jwrite32(jme
, JME_GHC
, GHC_SPEED_100M
);
1645 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1647 jme_wait_link(struct jme_adapter
*jme
)
1649 u32 phylink
, to
= JME_WAIT_LINK_TIME
;
1652 phylink
= jme_linkstat_from_phy(jme
);
1653 while (!(phylink
& PHY_LINK_UP
) && (to
-= 10) > 0) {
1655 phylink
= jme_linkstat_from_phy(jme
);
1661 jme_phy_off(struct jme_adapter
*jme
)
1663 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
, BMCR_PDOWN
);
1667 jme_close(struct net_device
*netdev
)
1669 struct jme_adapter
*jme
= netdev_priv(netdev
);
1671 netif_stop_queue(netdev
);
1672 netif_carrier_off(netdev
);
1677 JME_NAPI_DISABLE(jme
);
1679 tasklet_disable(&jme
->linkch_task
);
1680 tasklet_disable(&jme
->txclean_task
);
1681 tasklet_disable(&jme
->rxclean_task
);
1682 tasklet_disable(&jme
->rxempty_task
);
1684 jme_reset_ghc_speed(jme
);
1685 jme_disable_rx_engine(jme
);
1686 jme_disable_tx_engine(jme
);
1687 jme_reset_mac_processor(jme
);
1688 jme_free_rx_resources(jme
);
1689 jme_free_tx_resources(jme
);
1697 jme_alloc_txdesc(struct jme_adapter
*jme
,
1698 struct sk_buff
*skb
)
1700 struct jme_ring
*txring
= &(jme
->txring
[0]);
1701 int idx
, nr_alloc
, mask
= jme
->tx_ring_mask
;
1703 idx
= txring
->next_to_use
;
1704 nr_alloc
= skb_shinfo(skb
)->nr_frags
+ 2;
1706 if (unlikely(atomic_read(&txring
->nr_free
) < nr_alloc
))
1709 atomic_sub(nr_alloc
, &txring
->nr_free
);
1711 txring
->next_to_use
= (txring
->next_to_use
+ nr_alloc
) & mask
;
1717 jme_fill_tx_map(struct pci_dev
*pdev
,
1718 struct txdesc
*txdesc
,
1719 struct jme_buffer_info
*txbi
,
1727 dmaaddr
= pci_map_page(pdev
,
1733 pci_dma_sync_single_for_device(pdev
,
1740 txdesc
->desc2
.flags
= TXFLAG_OWN
;
1741 txdesc
->desc2
.flags
|= (hidma
) ? TXFLAG_64BIT
: 0;
1742 txdesc
->desc2
.datalen
= cpu_to_le16(len
);
1743 txdesc
->desc2
.bufaddrh
= cpu_to_le32((__u64
)dmaaddr
>> 32);
1744 txdesc
->desc2
.bufaddrl
= cpu_to_le32(
1745 (__u64
)dmaaddr
& 0xFFFFFFFFUL
);
1747 txbi
->mapping
= dmaaddr
;
1752 jme_map_tx_skb(struct jme_adapter
*jme
, struct sk_buff
*skb
, int idx
)
1754 struct jme_ring
*txring
= &(jme
->txring
[0]);
1755 struct txdesc
*txdesc
= txring
->desc
, *ctxdesc
;
1756 struct jme_buffer_info
*txbi
= txring
->bufinf
, *ctxbi
;
1757 u8 hidma
= jme
->dev
->features
& NETIF_F_HIGHDMA
;
1758 int i
, nr_frags
= skb_shinfo(skb
)->nr_frags
;
1759 int mask
= jme
->tx_ring_mask
;
1760 struct skb_frag_struct
*frag
;
1763 for (i
= 0 ; i
< nr_frags
; ++i
) {
1764 frag
= &skb_shinfo(skb
)->frags
[i
];
1765 ctxdesc
= txdesc
+ ((idx
+ i
+ 2) & (mask
));
1766 ctxbi
= txbi
+ ((idx
+ i
+ 2) & (mask
));
1768 jme_fill_tx_map(jme
->pdev
, ctxdesc
, ctxbi
, frag
->page
,
1769 frag
->page_offset
, frag
->size
, hidma
);
1772 len
= skb_is_nonlinear(skb
) ? skb_headlen(skb
) : skb
->len
;
1773 ctxdesc
= txdesc
+ ((idx
+ 1) & (mask
));
1774 ctxbi
= txbi
+ ((idx
+ 1) & (mask
));
1775 jme_fill_tx_map(jme
->pdev
, ctxdesc
, ctxbi
, virt_to_page(skb
->data
),
1776 offset_in_page(skb
->data
), len
, hidma
);
1781 jme_expand_header(struct jme_adapter
*jme
, struct sk_buff
*skb
)
1783 if (unlikely(skb_shinfo(skb
)->gso_size
&&
1784 skb_header_cloned(skb
) &&
1785 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
))) {
1794 jme_tx_tso(struct sk_buff
*skb
, __le16
*mss
, u8
*flags
)
1796 *mss
= cpu_to_le16(skb_shinfo(skb
)->gso_size
<< TXDESC_MSS_SHIFT
);
1798 *flags
|= TXFLAG_LSEN
;
1800 if (skb
->protocol
== htons(ETH_P_IP
)) {
1801 struct iphdr
*iph
= ip_hdr(skb
);
1804 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
1809 struct ipv6hdr
*ip6h
= ipv6_hdr(skb
);
1811 tcp_hdr(skb
)->check
= ~csum_ipv6_magic(&ip6h
->saddr
,
1824 jme_tx_csum(struct jme_adapter
*jme
, struct sk_buff
*skb
, u8
*flags
)
1826 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1829 switch (skb
->protocol
) {
1830 case htons(ETH_P_IP
):
1831 ip_proto
= ip_hdr(skb
)->protocol
;
1833 case htons(ETH_P_IPV6
):
1834 ip_proto
= ipv6_hdr(skb
)->nexthdr
;
1843 *flags
|= TXFLAG_TCPCS
;
1846 *flags
|= TXFLAG_UDPCS
;
1849 netif_err(jme
, tx_err
, jme
->dev
, "Error upper layer protocol.\n");
1856 jme_tx_vlan(struct sk_buff
*skb
, __le16
*vlan
, u8
*flags
)
1858 if (vlan_tx_tag_present(skb
)) {
1859 *flags
|= TXFLAG_TAGON
;
1860 *vlan
= cpu_to_le16(vlan_tx_tag_get(skb
));
1865 jme_fill_tx_desc(struct jme_adapter
*jme
, struct sk_buff
*skb
, int idx
)
1867 struct jme_ring
*txring
= &(jme
->txring
[0]);
1868 struct txdesc
*txdesc
;
1869 struct jme_buffer_info
*txbi
;
1872 txdesc
= (struct txdesc
*)txring
->desc
+ idx
;
1873 txbi
= txring
->bufinf
+ idx
;
1879 txdesc
->desc1
.pktsize
= cpu_to_le16(skb
->len
);
1881 * Set OWN bit at final.
1882 * When kernel transmit faster than NIC.
1883 * And NIC trying to send this descriptor before we tell
1884 * it to start sending this TX queue.
1885 * Other fields are already filled correctly.
1888 flags
= TXFLAG_OWN
| TXFLAG_INT
;
1890 * Set checksum flags while not tso
1892 if (jme_tx_tso(skb
, &txdesc
->desc1
.mss
, &flags
))
1893 jme_tx_csum(jme
, skb
, &flags
);
1894 jme_tx_vlan(skb
, &txdesc
->desc1
.vlan
, &flags
);
1895 jme_map_tx_skb(jme
, skb
, idx
);
1896 txdesc
->desc1
.flags
= flags
;
1898 * Set tx buffer info after telling NIC to send
1899 * For better tx_clean timing
1902 txbi
->nr_desc
= skb_shinfo(skb
)->nr_frags
+ 2;
1904 txbi
->len
= skb
->len
;
1905 txbi
->start_xmit
= jiffies
;
1906 if (!txbi
->start_xmit
)
1907 txbi
->start_xmit
= (0UL-1);
1913 jme_stop_queue_if_full(struct jme_adapter
*jme
)
1915 struct jme_ring
*txring
= &(jme
->txring
[0]);
1916 struct jme_buffer_info
*txbi
= txring
->bufinf
;
1917 int idx
= atomic_read(&txring
->next_to_clean
);
1922 if (unlikely(atomic_read(&txring
->nr_free
) < (MAX_SKB_FRAGS
+2))) {
1923 netif_stop_queue(jme
->dev
);
1924 netif_info(jme
, tx_queued
, jme
->dev
, "TX Queue Paused.\n");
1926 if (atomic_read(&txring
->nr_free
)
1927 >= (jme
->tx_wake_threshold
)) {
1928 netif_wake_queue(jme
->dev
);
1929 netif_info(jme
, tx_queued
, jme
->dev
, "TX Queue Fast Waked.\n");
1933 if (unlikely(txbi
->start_xmit
&&
1934 (jiffies
- txbi
->start_xmit
) >= TX_TIMEOUT
&&
1936 netif_stop_queue(jme
->dev
);
1937 netif_info(jme
, tx_queued
, jme
->dev
, "TX Queue Stopped %d@%lu.\n", idx
, jiffies
);
1942 * This function is already protected by netif_tx_lock()
1946 jme_start_xmit(struct sk_buff
*skb
, struct net_device
*netdev
)
1948 struct jme_adapter
*jme
= netdev_priv(netdev
);
1951 if (unlikely(jme_expand_header(jme
, skb
))) {
1952 ++(NET_STAT(jme
).tx_dropped
);
1953 return NETDEV_TX_OK
;
1956 idx
= jme_alloc_txdesc(jme
, skb
);
1958 if (unlikely(idx
< 0)) {
1959 netif_stop_queue(netdev
);
1960 netif_err(jme
, tx_err
, jme
->dev
, "BUG! Tx ring full when queue awake!\n");
1962 return NETDEV_TX_BUSY
;
1965 jme_fill_tx_desc(jme
, skb
, idx
);
1967 jwrite32(jme
, JME_TXCS
, jme
->reg_txcs
|
1968 TXCS_SELECT_QUEUE0
|
1972 tx_dbg(jme
, "xmit: %d+%d@%lu\n", idx
,
1973 skb_shinfo(skb
)->nr_frags
+ 2,
1975 jme_stop_queue_if_full(jme
);
1977 return NETDEV_TX_OK
;
1981 jme_set_macaddr(struct net_device
*netdev
, void *p
)
1983 struct jme_adapter
*jme
= netdev_priv(netdev
);
1984 struct sockaddr
*addr
= p
;
1987 if (netif_running(netdev
))
1990 spin_lock_bh(&jme
->macaddr_lock
);
1991 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
1993 val
= (addr
->sa_data
[3] & 0xff) << 24 |
1994 (addr
->sa_data
[2] & 0xff) << 16 |
1995 (addr
->sa_data
[1] & 0xff) << 8 |
1996 (addr
->sa_data
[0] & 0xff);
1997 jwrite32(jme
, JME_RXUMA_LO
, val
);
1998 val
= (addr
->sa_data
[5] & 0xff) << 8 |
1999 (addr
->sa_data
[4] & 0xff);
2000 jwrite32(jme
, JME_RXUMA_HI
, val
);
2001 spin_unlock_bh(&jme
->macaddr_lock
);
2007 jme_set_multi(struct net_device
*netdev
)
2009 struct jme_adapter
*jme
= netdev_priv(netdev
);
2010 u32 mc_hash
[2] = {};
2012 spin_lock_bh(&jme
->rxmcs_lock
);
2014 jme
->reg_rxmcs
|= RXMCS_BRDFRAME
| RXMCS_UNIFRAME
;
2016 if (netdev
->flags
& IFF_PROMISC
) {
2017 jme
->reg_rxmcs
|= RXMCS_ALLFRAME
;
2018 } else if (netdev
->flags
& IFF_ALLMULTI
) {
2019 jme
->reg_rxmcs
|= RXMCS_ALLMULFRAME
;
2020 } else if (netdev
->flags
& IFF_MULTICAST
) {
2021 struct netdev_hw_addr
*ha
;
2024 jme
->reg_rxmcs
|= RXMCS_MULFRAME
| RXMCS_MULFILTERED
;
2025 netdev_for_each_mc_addr(ha
, netdev
) {
2026 bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) & 0x3F;
2027 mc_hash
[bit_nr
>> 5] |= 1 << (bit_nr
& 0x1F);
2030 jwrite32(jme
, JME_RXMCHT_LO
, mc_hash
[0]);
2031 jwrite32(jme
, JME_RXMCHT_HI
, mc_hash
[1]);
2035 jwrite32(jme
, JME_RXMCS
, jme
->reg_rxmcs
);
2037 spin_unlock_bh(&jme
->rxmcs_lock
);
2041 jme_change_mtu(struct net_device
*netdev
, int new_mtu
)
2043 struct jme_adapter
*jme
= netdev_priv(netdev
);
2045 if (new_mtu
== jme
->old_mtu
)
2048 if (((new_mtu
+ ETH_HLEN
) > MAX_ETHERNET_JUMBO_PACKET_SIZE
) ||
2049 ((new_mtu
) < IPV6_MIN_MTU
))
2052 if (new_mtu
> 4000) {
2053 jme
->reg_rxcs
&= ~RXCS_FIFOTHNP
;
2054 jme
->reg_rxcs
|= RXCS_FIFOTHNP_64QW
;
2055 jme_restart_rx_engine(jme
);
2057 jme
->reg_rxcs
&= ~RXCS_FIFOTHNP
;
2058 jme
->reg_rxcs
|= RXCS_FIFOTHNP_128QW
;
2059 jme_restart_rx_engine(jme
);
2062 if (new_mtu
> 1900) {
2063 netdev
->features
&= ~(NETIF_F_HW_CSUM
|
2067 if (test_bit(JME_FLAG_TXCSUM
, &jme
->flags
))
2068 netdev
->features
|= NETIF_F_HW_CSUM
;
2069 if (test_bit(JME_FLAG_TSO
, &jme
->flags
))
2070 netdev
->features
|= NETIF_F_TSO
| NETIF_F_TSO6
;
2073 netdev
->mtu
= new_mtu
;
2074 jme_reset_link(jme
);
2080 jme_tx_timeout(struct net_device
*netdev
)
2082 struct jme_adapter
*jme
= netdev_priv(netdev
);
2085 jme_reset_phy_processor(jme
);
2086 if (test_bit(JME_FLAG_SSET
, &jme
->flags
))
2087 jme_set_settings(netdev
, &jme
->old_ecmd
);
2090 * Force to Reset the link again
2092 jme_reset_link(jme
);
2095 static inline void jme_pause_rx(struct jme_adapter
*jme
)
2097 atomic_dec(&jme
->link_changing
);
2099 jme_set_rx_pcc(jme
, PCC_OFF
);
2100 if (test_bit(JME_FLAG_POLL
, &jme
->flags
)) {
2101 JME_NAPI_DISABLE(jme
);
2103 tasklet_disable(&jme
->rxclean_task
);
2104 tasklet_disable(&jme
->rxempty_task
);
2108 static inline void jme_resume_rx(struct jme_adapter
*jme
)
2110 struct dynpcc_info
*dpi
= &(jme
->dpi
);
2112 if (test_bit(JME_FLAG_POLL
, &jme
->flags
)) {
2113 JME_NAPI_ENABLE(jme
);
2115 tasklet_hi_enable(&jme
->rxclean_task
);
2116 tasklet_hi_enable(&jme
->rxempty_task
);
2119 dpi
->attempt
= PCC_P1
;
2121 jme_set_rx_pcc(jme
, PCC_P1
);
2123 atomic_inc(&jme
->link_changing
);
2127 jme_vlan_rx_register(struct net_device
*netdev
, struct vlan_group
*grp
)
2129 struct jme_adapter
*jme
= netdev_priv(netdev
);
2137 jme_get_drvinfo(struct net_device
*netdev
,
2138 struct ethtool_drvinfo
*info
)
2140 struct jme_adapter
*jme
= netdev_priv(netdev
);
2142 strcpy(info
->driver
, DRV_NAME
);
2143 strcpy(info
->version
, DRV_VERSION
);
2144 strcpy(info
->bus_info
, pci_name(jme
->pdev
));
2148 jme_get_regs_len(struct net_device
*netdev
)
2154 mmapio_memcpy(struct jme_adapter
*jme
, u32
*p
, u32 reg
, int len
)
2158 for (i
= 0 ; i
< len
; i
+= 4)
2159 p
[i
>> 2] = jread32(jme
, reg
+ i
);
2163 mdio_memcpy(struct jme_adapter
*jme
, u32
*p
, int reg_nr
)
2166 u16
*p16
= (u16
*)p
;
2168 for (i
= 0 ; i
< reg_nr
; ++i
)
2169 p16
[i
] = jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, i
);
2173 jme_get_regs(struct net_device
*netdev
, struct ethtool_regs
*regs
, void *p
)
2175 struct jme_adapter
*jme
= netdev_priv(netdev
);
2176 u32
*p32
= (u32
*)p
;
2178 memset(p
, 0xFF, JME_REG_LEN
);
2181 mmapio_memcpy(jme
, p32
, JME_MAC
, JME_MAC_LEN
);
2184 mmapio_memcpy(jme
, p32
, JME_PHY
, JME_PHY_LEN
);
2187 mmapio_memcpy(jme
, p32
, JME_MISC
, JME_MISC_LEN
);
2190 mmapio_memcpy(jme
, p32
, JME_RSS
, JME_RSS_LEN
);
2193 mdio_memcpy(jme
, p32
, JME_PHY_REG_NR
);
2197 jme_get_coalesce(struct net_device
*netdev
, struct ethtool_coalesce
*ecmd
)
2199 struct jme_adapter
*jme
= netdev_priv(netdev
);
2201 ecmd
->tx_coalesce_usecs
= PCC_TX_TO
;
2202 ecmd
->tx_max_coalesced_frames
= PCC_TX_CNT
;
2204 if (test_bit(JME_FLAG_POLL
, &jme
->flags
)) {
2205 ecmd
->use_adaptive_rx_coalesce
= false;
2206 ecmd
->rx_coalesce_usecs
= 0;
2207 ecmd
->rx_max_coalesced_frames
= 0;
2211 ecmd
->use_adaptive_rx_coalesce
= true;
2213 switch (jme
->dpi
.cur
) {
2215 ecmd
->rx_coalesce_usecs
= PCC_P1_TO
;
2216 ecmd
->rx_max_coalesced_frames
= PCC_P1_CNT
;
2219 ecmd
->rx_coalesce_usecs
= PCC_P2_TO
;
2220 ecmd
->rx_max_coalesced_frames
= PCC_P2_CNT
;
2223 ecmd
->rx_coalesce_usecs
= PCC_P3_TO
;
2224 ecmd
->rx_max_coalesced_frames
= PCC_P3_CNT
;
2234 jme_set_coalesce(struct net_device
*netdev
, struct ethtool_coalesce
*ecmd
)
2236 struct jme_adapter
*jme
= netdev_priv(netdev
);
2237 struct dynpcc_info
*dpi
= &(jme
->dpi
);
2239 if (netif_running(netdev
))
2242 if (ecmd
->use_adaptive_rx_coalesce
&&
2243 test_bit(JME_FLAG_POLL
, &jme
->flags
)) {
2244 clear_bit(JME_FLAG_POLL
, &jme
->flags
);
2245 jme
->jme_rx
= netif_rx
;
2246 jme
->jme_vlan_rx
= vlan_hwaccel_rx
;
2248 dpi
->attempt
= PCC_P1
;
2250 jme_set_rx_pcc(jme
, PCC_P1
);
2251 jme_interrupt_mode(jme
);
2252 } else if (!(ecmd
->use_adaptive_rx_coalesce
) &&
2253 !(test_bit(JME_FLAG_POLL
, &jme
->flags
))) {
2254 set_bit(JME_FLAG_POLL
, &jme
->flags
);
2255 jme
->jme_rx
= netif_receive_skb
;
2256 jme
->jme_vlan_rx
= vlan_hwaccel_receive_skb
;
2257 jme_interrupt_mode(jme
);
2264 jme_get_pauseparam(struct net_device
*netdev
,
2265 struct ethtool_pauseparam
*ecmd
)
2267 struct jme_adapter
*jme
= netdev_priv(netdev
);
2270 ecmd
->tx_pause
= (jme
->reg_txpfc
& TXPFC_PF_EN
) != 0;
2271 ecmd
->rx_pause
= (jme
->reg_rxmcs
& RXMCS_FLOWCTRL
) != 0;
2273 spin_lock_bh(&jme
->phy_lock
);
2274 val
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_ADVERTISE
);
2275 spin_unlock_bh(&jme
->phy_lock
);
2278 (val
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
)) != 0;
2282 jme_set_pauseparam(struct net_device
*netdev
,
2283 struct ethtool_pauseparam
*ecmd
)
2285 struct jme_adapter
*jme
= netdev_priv(netdev
);
2288 if (((jme
->reg_txpfc
& TXPFC_PF_EN
) != 0) ^
2289 (ecmd
->tx_pause
!= 0)) {
2292 jme
->reg_txpfc
|= TXPFC_PF_EN
;
2294 jme
->reg_txpfc
&= ~TXPFC_PF_EN
;
2296 jwrite32(jme
, JME_TXPFC
, jme
->reg_txpfc
);
2299 spin_lock_bh(&jme
->rxmcs_lock
);
2300 if (((jme
->reg_rxmcs
& RXMCS_FLOWCTRL
) != 0) ^
2301 (ecmd
->rx_pause
!= 0)) {
2304 jme
->reg_rxmcs
|= RXMCS_FLOWCTRL
;
2306 jme
->reg_rxmcs
&= ~RXMCS_FLOWCTRL
;
2308 jwrite32(jme
, JME_RXMCS
, jme
->reg_rxmcs
);
2310 spin_unlock_bh(&jme
->rxmcs_lock
);
2312 spin_lock_bh(&jme
->phy_lock
);
2313 val
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_ADVERTISE
);
2314 if (((val
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
)) != 0) ^
2315 (ecmd
->autoneg
!= 0)) {
2318 val
|= (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
2320 val
&= ~(ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
2322 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
,
2323 MII_ADVERTISE
, val
);
2325 spin_unlock_bh(&jme
->phy_lock
);
2331 jme_get_wol(struct net_device
*netdev
,
2332 struct ethtool_wolinfo
*wol
)
2334 struct jme_adapter
*jme
= netdev_priv(netdev
);
2336 wol
->supported
= WAKE_MAGIC
| WAKE_PHY
;
2340 if (jme
->reg_pmcs
& (PMCS_LFEN
| PMCS_LREN
))
2341 wol
->wolopts
|= WAKE_PHY
;
2343 if (jme
->reg_pmcs
& PMCS_MFEN
)
2344 wol
->wolopts
|= WAKE_MAGIC
;
2349 jme_set_wol(struct net_device
*netdev
,
2350 struct ethtool_wolinfo
*wol
)
2352 struct jme_adapter
*jme
= netdev_priv(netdev
);
2354 if (wol
->wolopts
& (WAKE_MAGICSECURE
|
2363 if (wol
->wolopts
& WAKE_PHY
)
2364 jme
->reg_pmcs
|= PMCS_LFEN
| PMCS_LREN
;
2366 if (wol
->wolopts
& WAKE_MAGIC
)
2367 jme
->reg_pmcs
|= PMCS_MFEN
;
2369 jwrite32(jme
, JME_PMCS
, jme
->reg_pmcs
);
2375 jme_get_settings(struct net_device
*netdev
,
2376 struct ethtool_cmd
*ecmd
)
2378 struct jme_adapter
*jme
= netdev_priv(netdev
);
2381 spin_lock_bh(&jme
->phy_lock
);
2382 rc
= mii_ethtool_gset(&(jme
->mii_if
), ecmd
);
2383 spin_unlock_bh(&jme
->phy_lock
);
2388 jme_set_settings(struct net_device
*netdev
,
2389 struct ethtool_cmd
*ecmd
)
2391 struct jme_adapter
*jme
= netdev_priv(netdev
);
2394 if (ecmd
->speed
== SPEED_1000
&& ecmd
->autoneg
!= AUTONEG_ENABLE
)
2397 if (jme
->mii_if
.force_media
&&
2398 ecmd
->autoneg
!= AUTONEG_ENABLE
&&
2399 (jme
->mii_if
.full_duplex
!= ecmd
->duplex
))
2402 spin_lock_bh(&jme
->phy_lock
);
2403 rc
= mii_ethtool_sset(&(jme
->mii_if
), ecmd
);
2404 spin_unlock_bh(&jme
->phy_lock
);
2407 jme_reset_link(jme
);
2410 set_bit(JME_FLAG_SSET
, &jme
->flags
);
2411 jme
->old_ecmd
= *ecmd
;
2418 jme_get_link(struct net_device
*netdev
)
2420 struct jme_adapter
*jme
= netdev_priv(netdev
);
2421 return jread32(jme
, JME_PHY_LINK
) & PHY_LINK_UP
;
2425 jme_get_msglevel(struct net_device
*netdev
)
2427 struct jme_adapter
*jme
= netdev_priv(netdev
);
2428 return jme
->msg_enable
;
2432 jme_set_msglevel(struct net_device
*netdev
, u32 value
)
2434 struct jme_adapter
*jme
= netdev_priv(netdev
);
2435 jme
->msg_enable
= value
;
2439 jme_get_rx_csum(struct net_device
*netdev
)
2441 struct jme_adapter
*jme
= netdev_priv(netdev
);
2442 return jme
->reg_rxmcs
& RXMCS_CHECKSUM
;
2446 jme_set_rx_csum(struct net_device
*netdev
, u32 on
)
2448 struct jme_adapter
*jme
= netdev_priv(netdev
);
2450 spin_lock_bh(&jme
->rxmcs_lock
);
2452 jme
->reg_rxmcs
|= RXMCS_CHECKSUM
;
2454 jme
->reg_rxmcs
&= ~RXMCS_CHECKSUM
;
2455 jwrite32(jme
, JME_RXMCS
, jme
->reg_rxmcs
);
2456 spin_unlock_bh(&jme
->rxmcs_lock
);
2462 jme_set_tx_csum(struct net_device
*netdev
, u32 on
)
2464 struct jme_adapter
*jme
= netdev_priv(netdev
);
2467 set_bit(JME_FLAG_TXCSUM
, &jme
->flags
);
2468 if (netdev
->mtu
<= 1900)
2469 netdev
->features
|= NETIF_F_HW_CSUM
;
2471 clear_bit(JME_FLAG_TXCSUM
, &jme
->flags
);
2472 netdev
->features
&= ~NETIF_F_HW_CSUM
;
2479 jme_set_tso(struct net_device
*netdev
, u32 on
)
2481 struct jme_adapter
*jme
= netdev_priv(netdev
);
2484 set_bit(JME_FLAG_TSO
, &jme
->flags
);
2485 if (netdev
->mtu
<= 1900)
2486 netdev
->features
|= NETIF_F_TSO
| NETIF_F_TSO6
;
2488 clear_bit(JME_FLAG_TSO
, &jme
->flags
);
2489 netdev
->features
&= ~(NETIF_F_TSO
| NETIF_F_TSO6
);
2496 jme_nway_reset(struct net_device
*netdev
)
2498 struct jme_adapter
*jme
= netdev_priv(netdev
);
2499 jme_restart_an(jme
);
2504 jme_smb_read(struct jme_adapter
*jme
, unsigned int addr
)
2509 val
= jread32(jme
, JME_SMBCSR
);
2510 to
= JME_SMB_BUSY_TIMEOUT
;
2511 while ((val
& SMBCSR_BUSY
) && --to
) {
2513 val
= jread32(jme
, JME_SMBCSR
);
2516 netif_err(jme
, hw
, jme
->dev
, "SMB Bus Busy.\n");
2520 jwrite32(jme
, JME_SMBINTF
,
2521 ((addr
<< SMBINTF_HWADDR_SHIFT
) & SMBINTF_HWADDR
) |
2522 SMBINTF_HWRWN_READ
|
2525 val
= jread32(jme
, JME_SMBINTF
);
2526 to
= JME_SMB_BUSY_TIMEOUT
;
2527 while ((val
& SMBINTF_HWCMD
) && --to
) {
2529 val
= jread32(jme
, JME_SMBINTF
);
2532 netif_err(jme
, hw
, jme
->dev
, "SMB Bus Busy.\n");
2536 return (val
& SMBINTF_HWDATR
) >> SMBINTF_HWDATR_SHIFT
;
2540 jme_smb_write(struct jme_adapter
*jme
, unsigned int addr
, u8 data
)
2545 val
= jread32(jme
, JME_SMBCSR
);
2546 to
= JME_SMB_BUSY_TIMEOUT
;
2547 while ((val
& SMBCSR_BUSY
) && --to
) {
2549 val
= jread32(jme
, JME_SMBCSR
);
2552 netif_err(jme
, hw
, jme
->dev
, "SMB Bus Busy.\n");
2556 jwrite32(jme
, JME_SMBINTF
,
2557 ((data
<< SMBINTF_HWDATW_SHIFT
) & SMBINTF_HWDATW
) |
2558 ((addr
<< SMBINTF_HWADDR_SHIFT
) & SMBINTF_HWADDR
) |
2559 SMBINTF_HWRWN_WRITE
|
2562 val
= jread32(jme
, JME_SMBINTF
);
2563 to
= JME_SMB_BUSY_TIMEOUT
;
2564 while ((val
& SMBINTF_HWCMD
) && --to
) {
2566 val
= jread32(jme
, JME_SMBINTF
);
2569 netif_err(jme
, hw
, jme
->dev
, "SMB Bus Busy.\n");
2577 jme_get_eeprom_len(struct net_device
*netdev
)
2579 struct jme_adapter
*jme
= netdev_priv(netdev
);
2581 val
= jread32(jme
, JME_SMBCSR
);
2582 return (val
& SMBCSR_EEPROMD
) ? JME_SMB_LEN
: 0;
2586 jme_get_eeprom(struct net_device
*netdev
,
2587 struct ethtool_eeprom
*eeprom
, u8
*data
)
2589 struct jme_adapter
*jme
= netdev_priv(netdev
);
2590 int i
, offset
= eeprom
->offset
, len
= eeprom
->len
;
2593 * ethtool will check the boundary for us
2595 eeprom
->magic
= JME_EEPROM_MAGIC
;
2596 for (i
= 0 ; i
< len
; ++i
)
2597 data
[i
] = jme_smb_read(jme
, i
+ offset
);
2603 jme_set_eeprom(struct net_device
*netdev
,
2604 struct ethtool_eeprom
*eeprom
, u8
*data
)
2606 struct jme_adapter
*jme
= netdev_priv(netdev
);
2607 int i
, offset
= eeprom
->offset
, len
= eeprom
->len
;
2609 if (eeprom
->magic
!= JME_EEPROM_MAGIC
)
2613 * ethtool will check the boundary for us
2615 for (i
= 0 ; i
< len
; ++i
)
2616 jme_smb_write(jme
, i
+ offset
, data
[i
]);
2621 static const struct ethtool_ops jme_ethtool_ops
= {
2622 .get_drvinfo
= jme_get_drvinfo
,
2623 .get_regs_len
= jme_get_regs_len
,
2624 .get_regs
= jme_get_regs
,
2625 .get_coalesce
= jme_get_coalesce
,
2626 .set_coalesce
= jme_set_coalesce
,
2627 .get_pauseparam
= jme_get_pauseparam
,
2628 .set_pauseparam
= jme_set_pauseparam
,
2629 .get_wol
= jme_get_wol
,
2630 .set_wol
= jme_set_wol
,
2631 .get_settings
= jme_get_settings
,
2632 .set_settings
= jme_set_settings
,
2633 .get_link
= jme_get_link
,
2634 .get_msglevel
= jme_get_msglevel
,
2635 .set_msglevel
= jme_set_msglevel
,
2636 .get_rx_csum
= jme_get_rx_csum
,
2637 .set_rx_csum
= jme_set_rx_csum
,
2638 .set_tx_csum
= jme_set_tx_csum
,
2639 .set_tso
= jme_set_tso
,
2640 .set_sg
= ethtool_op_set_sg
,
2641 .nway_reset
= jme_nway_reset
,
2642 .get_eeprom_len
= jme_get_eeprom_len
,
2643 .get_eeprom
= jme_get_eeprom
,
2644 .set_eeprom
= jme_set_eeprom
,
2648 jme_pci_dma64(struct pci_dev
*pdev
)
2650 if (pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
&&
2651 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)))
2652 if (!pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64)))
2655 if (pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
&&
2656 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(40)))
2657 if (!pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(40)))
2660 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(32)))
2661 if (!pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32)))
2668 jme_phy_init(struct jme_adapter
*jme
)
2672 reg26
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, 26);
2673 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, 26, reg26
| 0x1000);
2677 jme_check_hw_ver(struct jme_adapter
*jme
)
2681 chipmode
= jread32(jme
, JME_CHIPMODE
);
2683 jme
->fpgaver
= (chipmode
& CM_FPGAVER_MASK
) >> CM_FPGAVER_SHIFT
;
2684 jme
->chiprev
= (chipmode
& CM_CHIPREV_MASK
) >> CM_CHIPREV_SHIFT
;
2687 static const struct net_device_ops jme_netdev_ops
= {
2688 .ndo_open
= jme_open
,
2689 .ndo_stop
= jme_close
,
2690 .ndo_validate_addr
= eth_validate_addr
,
2691 .ndo_start_xmit
= jme_start_xmit
,
2692 .ndo_set_mac_address
= jme_set_macaddr
,
2693 .ndo_set_multicast_list
= jme_set_multi
,
2694 .ndo_change_mtu
= jme_change_mtu
,
2695 .ndo_tx_timeout
= jme_tx_timeout
,
2696 .ndo_vlan_rx_register
= jme_vlan_rx_register
,
2699 static int __devinit
2700 jme_init_one(struct pci_dev
*pdev
,
2701 const struct pci_device_id
*ent
)
2703 int rc
= 0, using_dac
, i
;
2704 struct net_device
*netdev
;
2705 struct jme_adapter
*jme
;
2710 * set up PCI device basics
2712 rc
= pci_enable_device(pdev
);
2714 jeprintk(pdev
, "Cannot enable PCI device.\n");
2718 using_dac
= jme_pci_dma64(pdev
);
2719 if (using_dac
< 0) {
2720 jeprintk(pdev
, "Cannot set PCI DMA Mask.\n");
2722 goto err_out_disable_pdev
;
2725 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
2726 jeprintk(pdev
, "No PCI resource region found.\n");
2728 goto err_out_disable_pdev
;
2731 rc
= pci_request_regions(pdev
, DRV_NAME
);
2733 jeprintk(pdev
, "Cannot obtain PCI resource region.\n");
2734 goto err_out_disable_pdev
;
2737 pci_set_master(pdev
);
2740 * alloc and init net device
2742 netdev
= alloc_etherdev(sizeof(*jme
));
2744 jeprintk(pdev
, "Cannot allocate netdev structure.\n");
2746 goto err_out_release_regions
;
2748 netdev
->netdev_ops
= &jme_netdev_ops
;
2749 netdev
->ethtool_ops
= &jme_ethtool_ops
;
2750 netdev
->watchdog_timeo
= TX_TIMEOUT
;
2751 netdev
->features
= NETIF_F_HW_CSUM
|
2755 NETIF_F_HW_VLAN_TX
|
2758 netdev
->features
|= NETIF_F_HIGHDMA
;
2760 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
2761 pci_set_drvdata(pdev
, netdev
);
2766 jme
= netdev_priv(netdev
);
2769 jme
->jme_rx
= netif_rx
;
2770 jme
->jme_vlan_rx
= vlan_hwaccel_rx
;
2771 jme
->old_mtu
= netdev
->mtu
= 1500;
2773 jme
->tx_ring_size
= 1 << 10;
2774 jme
->tx_ring_mask
= jme
->tx_ring_size
- 1;
2775 jme
->tx_wake_threshold
= 1 << 9;
2776 jme
->rx_ring_size
= 1 << 9;
2777 jme
->rx_ring_mask
= jme
->rx_ring_size
- 1;
2778 jme
->msg_enable
= JME_DEF_MSG_ENABLE
;
2779 jme
->regs
= ioremap(pci_resource_start(pdev
, 0),
2780 pci_resource_len(pdev
, 0));
2782 jeprintk(pdev
, "Mapping PCI resource region error.\n");
2784 goto err_out_free_netdev
;
2788 apmc
= jread32(jme
, JME_APMC
) & ~JME_APMC_PSEUDO_HP_EN
;
2789 jwrite32(jme
, JME_APMC
, apmc
);
2790 } else if (force_pseudohp
) {
2791 apmc
= jread32(jme
, JME_APMC
) | JME_APMC_PSEUDO_HP_EN
;
2792 jwrite32(jme
, JME_APMC
, apmc
);
2795 NETIF_NAPI_SET(netdev
, &jme
->napi
, jme_poll
, jme
->rx_ring_size
>> 2)
2797 spin_lock_init(&jme
->phy_lock
);
2798 spin_lock_init(&jme
->macaddr_lock
);
2799 spin_lock_init(&jme
->rxmcs_lock
);
2801 atomic_set(&jme
->link_changing
, 1);
2802 atomic_set(&jme
->rx_cleaning
, 1);
2803 atomic_set(&jme
->tx_cleaning
, 1);
2804 atomic_set(&jme
->rx_empty
, 1);
2806 tasklet_init(&jme
->pcc_task
,
2808 (unsigned long) jme
);
2809 tasklet_init(&jme
->linkch_task
,
2810 jme_link_change_tasklet
,
2811 (unsigned long) jme
);
2812 tasklet_init(&jme
->txclean_task
,
2813 jme_tx_clean_tasklet
,
2814 (unsigned long) jme
);
2815 tasklet_init(&jme
->rxclean_task
,
2816 jme_rx_clean_tasklet
,
2817 (unsigned long) jme
);
2818 tasklet_init(&jme
->rxempty_task
,
2819 jme_rx_empty_tasklet
,
2820 (unsigned long) jme
);
2821 tasklet_disable_nosync(&jme
->linkch_task
);
2822 tasklet_disable_nosync(&jme
->txclean_task
);
2823 tasklet_disable_nosync(&jme
->rxclean_task
);
2824 tasklet_disable_nosync(&jme
->rxempty_task
);
2825 jme
->dpi
.cur
= PCC_P1
;
2828 jme
->reg_rxcs
= RXCS_DEFAULT
;
2829 jme
->reg_rxmcs
= RXMCS_DEFAULT
;
2831 jme
->reg_pmcs
= PMCS_MFEN
;
2832 set_bit(JME_FLAG_TXCSUM
, &jme
->flags
);
2833 set_bit(JME_FLAG_TSO
, &jme
->flags
);
2836 * Get Max Read Req Size from PCI Config Space
2838 pci_read_config_byte(pdev
, PCI_DCSR_MRRS
, &jme
->mrrs
);
2839 jme
->mrrs
&= PCI_DCSR_MRRS_MASK
;
2840 switch (jme
->mrrs
) {
2842 jme
->reg_txcs
= TXCS_DEFAULT
| TXCS_DMASIZE_128B
;
2845 jme
->reg_txcs
= TXCS_DEFAULT
| TXCS_DMASIZE_256B
;
2848 jme
->reg_txcs
= TXCS_DEFAULT
| TXCS_DMASIZE_512B
;
2853 * Must check before reset_mac_processor
2855 jme_check_hw_ver(jme
);
2856 jme
->mii_if
.dev
= netdev
;
2858 jme
->mii_if
.phy_id
= 0;
2859 for (i
= 1 ; i
< 32 ; ++i
) {
2860 bmcr
= jme_mdio_read(netdev
, i
, MII_BMCR
);
2861 bmsr
= jme_mdio_read(netdev
, i
, MII_BMSR
);
2862 if (bmcr
!= 0xFFFFU
&& (bmcr
!= 0 || bmsr
!= 0)) {
2863 jme
->mii_if
.phy_id
= i
;
2868 if (!jme
->mii_if
.phy_id
) {
2870 jeprintk(pdev
, "Can not find phy_id.\n");
2874 jme
->reg_ghc
|= GHC_LINK_POLL
;
2876 jme
->mii_if
.phy_id
= 1;
2878 if (pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
)
2879 jme
->mii_if
.supports_gmii
= true;
2881 jme
->mii_if
.supports_gmii
= false;
2882 jme
->mii_if
.mdio_read
= jme_mdio_read
;
2883 jme
->mii_if
.mdio_write
= jme_mdio_write
;
2886 jme_set_phyfifoa(jme
);
2887 pci_read_config_byte(pdev
, PCI_REVISION_ID
, &jme
->rev
);
2893 * Reset MAC processor and reload EEPROM for MAC Address
2895 jme_reset_mac_processor(jme
);
2896 rc
= jme_reload_eeprom(jme
);
2899 "Reload eeprom for reading MAC Address error.\n");
2902 jme_load_macaddr(netdev
);
2905 * Tell stack that we are not ready to work until open()
2907 netif_carrier_off(netdev
);
2908 netif_stop_queue(netdev
);
2913 rc
= register_netdev(netdev
);
2915 jeprintk(pdev
, "Cannot register net device.\n");
2919 netif_info(jme
, probe
, jme
->dev
, "%s%s ver:%x rev:%x macaddr:%pM\n",
2920 (jme
->pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
) ?
2921 "JMC250 Gigabit Ethernet" :
2922 (jme
->pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC260
) ?
2923 "JMC260 Fast Ethernet" : "Unknown",
2924 (jme
->fpgaver
!= 0) ? " (FPGA)" : "",
2925 (jme
->fpgaver
!= 0) ? jme
->fpgaver
: jme
->chiprev
,
2926 jme
->rev
, netdev
->dev_addr
);
2932 err_out_free_netdev
:
2933 pci_set_drvdata(pdev
, NULL
);
2934 free_netdev(netdev
);
2935 err_out_release_regions
:
2936 pci_release_regions(pdev
);
2937 err_out_disable_pdev
:
2938 pci_disable_device(pdev
);
2943 static void __devexit
2944 jme_remove_one(struct pci_dev
*pdev
)
2946 struct net_device
*netdev
= pci_get_drvdata(pdev
);
2947 struct jme_adapter
*jme
= netdev_priv(netdev
);
2949 unregister_netdev(netdev
);
2951 pci_set_drvdata(pdev
, NULL
);
2952 free_netdev(netdev
);
2953 pci_release_regions(pdev
);
2954 pci_disable_device(pdev
);
2960 jme_suspend(struct pci_dev
*pdev
, pm_message_t state
)
2962 struct net_device
*netdev
= pci_get_drvdata(pdev
);
2963 struct jme_adapter
*jme
= netdev_priv(netdev
);
2965 atomic_dec(&jme
->link_changing
);
2967 netif_device_detach(netdev
);
2968 netif_stop_queue(netdev
);
2971 tasklet_disable(&jme
->txclean_task
);
2972 tasklet_disable(&jme
->rxclean_task
);
2973 tasklet_disable(&jme
->rxempty_task
);
2975 if (netif_carrier_ok(netdev
)) {
2976 if (test_bit(JME_FLAG_POLL
, &jme
->flags
))
2977 jme_polling_mode(jme
);
2979 jme_stop_pcc_timer(jme
);
2980 jme_reset_ghc_speed(jme
);
2981 jme_disable_rx_engine(jme
);
2982 jme_disable_tx_engine(jme
);
2983 jme_reset_mac_processor(jme
);
2984 jme_free_rx_resources(jme
);
2985 jme_free_tx_resources(jme
);
2986 netif_carrier_off(netdev
);
2990 tasklet_enable(&jme
->txclean_task
);
2991 tasklet_hi_enable(&jme
->rxclean_task
);
2992 tasklet_hi_enable(&jme
->rxempty_task
);
2994 pci_save_state(pdev
);
2995 if (jme
->reg_pmcs
) {
2996 jme_set_100m_half(jme
);
2998 if (jme
->reg_pmcs
& (PMCS_LFEN
| PMCS_LREN
))
3001 jwrite32(jme
, JME_PMCS
, jme
->reg_pmcs
);
3003 pci_enable_wake(pdev
, PCI_D3cold
, true);
3007 pci_set_power_state(pdev
, PCI_D3cold
);
3013 jme_resume(struct pci_dev
*pdev
)
3015 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3016 struct jme_adapter
*jme
= netdev_priv(netdev
);
3019 pci_restore_state(pdev
);
3021 if (test_bit(JME_FLAG_SSET
, &jme
->flags
)) {
3023 jme_set_settings(netdev
, &jme
->old_ecmd
);
3025 jme_reset_phy_processor(jme
);
3029 netif_device_attach(netdev
);
3031 atomic_inc(&jme
->link_changing
);
3033 jme_reset_link(jme
);
3039 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl
) = {
3040 { PCI_VDEVICE(JMICRON
, PCI_DEVICE_ID_JMICRON_JMC250
) },
3041 { PCI_VDEVICE(JMICRON
, PCI_DEVICE_ID_JMICRON_JMC260
) },
3045 static struct pci_driver jme_driver
= {
3047 .id_table
= jme_pci_tbl
,
3048 .probe
= jme_init_one
,
3049 .remove
= __devexit_p(jme_remove_one
),
3051 .suspend
= jme_suspend
,
3052 .resume
= jme_resume
,
3053 #endif /* CONFIG_PM */
3057 jme_init_module(void)
3059 printk(KERN_INFO PFX
"JMicron JMC2XX ethernet "
3060 "driver version %s\n", DRV_VERSION
);
3061 return pci_register_driver(&jme_driver
);
3065 jme_cleanup_module(void)
3067 pci_unregister_driver(&jme_driver
);
3070 module_init(jme_init_module
);
3071 module_exit(jme_cleanup_module
);
3073 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3074 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3075 MODULE_LICENSE("GPL");
3076 MODULE_VERSION(DRV_VERSION
);
3077 MODULE_DEVICE_TABLE(pci
, jme_pci_tbl
);