release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/can/flexcan.c

   1 /*
   2  * flexcan.c - FLEXCAN CAN controller driver
   3  *
   4  * Copyright (c) 2005-2006 Varma Electronics Oy
   5  * Copyright (c) 2009 Sascha Hauer, Pengutronix
   6  * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
   7  *
   8  * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
   9  *
  10  * LICENCE:
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation version 2.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  */
  21
  22 #include <linux/netdevice.h>
  23 #include <linux/can.h>
  24 #include <linux/can/dev.h>
  25 #include <linux/can/error.h>
  26 #include <linux/can/platform/flexcan.h>
  27 #include <linux/clk.h>
  28 #include <linux/delay.h>
  29 #include <linux/if_arp.h>
  30 #include <linux/if_ether.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/io.h>
  33 #include <linux/kernel.h>
  34 #include <linux/list.h>
  35 #include <linux/module.h>
  36 #include <linux/platform_device.h>
  37
  38 #include <mach/clock.h>
  39
  40 #define DRV_NAME                        "flexcan"
  41
  42 /* 8 for RX fifo and 2 error handling */
  43 #define FLEXCAN_NAPI_WEIGHT             (8 + 2)
  44
  45 /* FLEXCAN module configuration register (CANMCR) bits */
  46 #define FLEXCAN_MCR_MDIS                BIT(31)
  47 #define FLEXCAN_MCR_FRZ                 BIT(30)
  48 #define FLEXCAN_MCR_FEN                 BIT(29)
  49 #define FLEXCAN_MCR_HALT                BIT(28)
  50 #define FLEXCAN_MCR_NOT_RDY             BIT(27)
  51 #define FLEXCAN_MCR_WAK_MSK             BIT(26)
  52 #define FLEXCAN_MCR_SOFTRST             BIT(25)
  53 #define FLEXCAN_MCR_FRZ_ACK             BIT(24)
  54 #define FLEXCAN_MCR_SUPV                BIT(23)
  55 #define FLEXCAN_MCR_SLF_WAK             BIT(22)
  56 #define FLEXCAN_MCR_WRN_EN              BIT(21)
  57 #define FLEXCAN_MCR_LPM_ACK             BIT(20)
  58 #define FLEXCAN_MCR_WAK_SRC             BIT(19)
  59 #define FLEXCAN_MCR_DOZE                BIT(18)
  60 #define FLEXCAN_MCR_SRX_DIS             BIT(17)
  61 #define FLEXCAN_MCR_BCC                 BIT(16)
  62 #define FLEXCAN_MCR_LPRIO_EN            BIT(13)
  63 #define FLEXCAN_MCR_AEN                 BIT(12)
  64 #define FLEXCAN_MCR_MAXMB(x)            ((x) & 0xf)
  65 #define FLEXCAN_MCR_IDAM_A              (0 << 8)
  66 #define FLEXCAN_MCR_IDAM_B              (1 << 8)
  67 #define FLEXCAN_MCR_IDAM_C              (2 << 8)
  68 #define FLEXCAN_MCR_IDAM_D              (3 << 8)
  69
  70 /* FLEXCAN control register (CANCTRL) bits */
  71 #define FLEXCAN_CTRL_PRESDIV(x)         (((x) & 0xff) << 24)
  72 #define FLEXCAN_CTRL_RJW(x)             (((x) & 0x03) << 22)
  73 #define FLEXCAN_CTRL_PSEG1(x)           (((x) & 0x07) << 19)
  74 #define FLEXCAN_CTRL_PSEG2(x)           (((x) & 0x07) << 16)
  75 #define FLEXCAN_CTRL_BOFF_MSK           BIT(15)
  76 #define FLEXCAN_CTRL_ERR_MSK            BIT(14)
  77 #define FLEXCAN_CTRL_CLK_SRC            BIT(13)
  78 #define FLEXCAN_CTRL_LPB                BIT(12)
  79 #define FLEXCAN_CTRL_TWRN_MSK           BIT(11)
  80 #define FLEXCAN_CTRL_RWRN_MSK           BIT(10)
  81 #define FLEXCAN_CTRL_SMP                BIT(7)
  82 #define FLEXCAN_CTRL_BOFF_REC           BIT(6)
  83 #define FLEXCAN_CTRL_TSYN               BIT(5)
  84 #define FLEXCAN_CTRL_LBUF               BIT(4)
  85 #define FLEXCAN_CTRL_LOM                BIT(3)
  86 #define FLEXCAN_CTRL_PROPSEG(x)         ((x) & 0x07)
  87 #define FLEXCAN_CTRL_ERR_BUS            (FLEXCAN_CTRL_ERR_MSK)
  88 #define FLEXCAN_CTRL_ERR_STATE \
  89         (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
  90          FLEXCAN_CTRL_BOFF_MSK)
  91 #define FLEXCAN_CTRL_ERR_ALL \
  92         (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
  93
  94 /* FLEXCAN error and status register (ESR) bits */
  95 #define FLEXCAN_ESR_TWRN_INT            BIT(17)
  96 #define FLEXCAN_ESR_RWRN_INT            BIT(16)
  97 #define FLEXCAN_ESR_BIT1_ERR            BIT(15)
  98 #define FLEXCAN_ESR_BIT0_ERR            BIT(14)
  99 #define FLEXCAN_ESR_ACK_ERR             BIT(13)
 100 #define FLEXCAN_ESR_CRC_ERR             BIT(12)
 101 #define FLEXCAN_ESR_FRM_ERR             BIT(11)
 102 #define FLEXCAN_ESR_STF_ERR             BIT(10)
 103 #define FLEXCAN_ESR_TX_WRN              BIT(9)
 104 #define FLEXCAN_ESR_RX_WRN              BIT(8)
 105 #define FLEXCAN_ESR_IDLE                BIT(7)
 106 #define FLEXCAN_ESR_TXRX                BIT(6)
 107 #define FLEXCAN_EST_FLT_CONF_SHIFT      (4)
 108 #define FLEXCAN_ESR_FLT_CONF_MASK       (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
 109 #define FLEXCAN_ESR_FLT_CONF_ACTIVE     (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
 110 #define FLEXCAN_ESR_FLT_CONF_PASSIVE    (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
 111 #define FLEXCAN_ESR_BOFF_INT            BIT(2)
 112 #define FLEXCAN_ESR_ERR_INT             BIT(1)
 113 #define FLEXCAN_ESR_WAK_INT             BIT(0)
 114 #define FLEXCAN_ESR_ERR_BUS \
 115         (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
 116          FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
 117          FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
 118 #define FLEXCAN_ESR_ERR_STATE \
 119         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
 120 #define FLEXCAN_ESR_ERR_ALL \
 121         (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
 122
 123 /* FLEXCAN interrupt flag register (IFLAG) bits */
 124 #define FLEXCAN_TX_BUF_ID               8
 125 #define FLEXCAN_IFLAG_BUF(x)            BIT(x)
 126 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW  BIT(7)
 127 #define FLEXCAN_IFLAG_RX_FIFO_WARN      BIT(6)
 128 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
 129 #define FLEXCAN_IFLAG_DEFAULT \
 130         (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
 131          FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
 132
 133 /* FLEXCAN message buffers */
 134 #define FLEXCAN_MB_CNT_CODE(x)          (((x) & 0xf) << 24)
 135 #define FLEXCAN_MB_CNT_SRR              BIT(22)
 136 #define FLEXCAN_MB_CNT_IDE              BIT(21)
 137 #define FLEXCAN_MB_CNT_RTR              BIT(20)
 138 #define FLEXCAN_MB_CNT_LENGTH(x)        (((x) & 0xf) << 16)
 139 #define FLEXCAN_MB_CNT_TIMESTAMP(x)     ((x) & 0xffff)
 140
 141 #define FLEXCAN_MB_CODE_MASK            (0xf0ffffff)
 142
 143 /* Structure of the message buffer */
 144 struct flexcan_mb {
 145         u32 can_ctrl;
 146         u32 can_id;
 147         u32 data[2];
 148 };
 149
 150 /* Structure of the hardware registers */
 151 struct flexcan_regs {
 152         u32 mcr;                /* 0x00 */
 153         u32 ctrl;               /* 0x04 */
 154         u32 timer;              /* 0x08 */
 155         u32 _reserved1;         /* 0x0c */
 156         u32 rxgmask;            /* 0x10 */
 157         u32 rx14mask;           /* 0x14 */
 158         u32 rx15mask;           /* 0x18 */
 159         u32 ecr;                /* 0x1c */
 160         u32 esr;                /* 0x20 */
 161         u32 imask2;             /* 0x24 */
 162         u32 imask1;             /* 0x28 */
 163         u32 iflag2;             /* 0x2c */
 164         u32 iflag1;             /* 0x30 */
 165         u32 _reserved2[19];
 166         struct flexcan_mb cantxfg[64];
 167 };
 168
 169 struct flexcan_priv {
 170         struct can_priv can;
 171         struct net_device *dev;
 172         struct napi_struct napi;
 173
 174         void __iomem *base;
 175         u32 reg_esr;
 176         u32 reg_ctrl_default;
 177
 178         struct clk *clk;
 179         struct flexcan_platform_data *pdata;
 180 };
 181
 182 static struct can_bittiming_const flexcan_bittiming_const = {
 183         .name = DRV_NAME,
 184         .tseg1_min = 4,
 185         .tseg1_max = 16,
 186         .tseg2_min = 2,
 187         .tseg2_max = 8,
 188         .sjw_max = 4,
 189         .brp_min = 1,
 190         .brp_max = 256,
 191         .brp_inc = 1,
 192 };
 193
 194 /*
 195  * Swtich transceiver on or off
 196  */
 197 static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on)
 198 {
 199         if (priv->pdata && priv->pdata->transceiver_switch)
 200                 priv->pdata->transceiver_switch(on);
 201 }
 202
 203 static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
 204                                               u32 reg_esr)
 205 {
 206         return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
 207                 (reg_esr & FLEXCAN_ESR_ERR_BUS);
 208 }
 209
 210 static inline void flexcan_chip_enable(struct flexcan_priv *priv)
 211 {
 212         struct flexcan_regs __iomem *regs = priv->base;
 213         u32 reg;
 214
 215         reg = readl(&regs->mcr);
 216         reg &= ~FLEXCAN_MCR_MDIS;
 217         writel(reg, &regs->mcr);
 218
 219         udelay(10);
 220 }
 221
 222 static inline void flexcan_chip_disable(struct flexcan_priv *priv)
 223 {
 224         struct flexcan_regs __iomem *regs = priv->base;
 225         u32 reg;
 226
 227         reg = readl(&regs->mcr);
 228         reg |= FLEXCAN_MCR_MDIS;
 229         writel(reg, &regs->mcr);
 230 }
 231
 232 static int flexcan_get_berr_counter(const struct net_device *dev,
 233                                     struct can_berr_counter *bec)
 234 {
 235         const struct flexcan_priv *priv = netdev_priv(dev);
 236         struct flexcan_regs __iomem *regs = priv->base;
 237         u32 reg = readl(&regs->ecr);
 238
 239         bec->txerr = (reg >> 0) & 0xff;
 240         bec->rxerr = (reg >> 8) & 0xff;
 241
 242         return 0;
 243 }
 244
 245 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 246 {
 247         const struct flexcan_priv *priv = netdev_priv(dev);
 248         struct net_device_stats *stats = &dev->stats;
 249         struct flexcan_regs __iomem *regs = priv->base;
 250         struct can_frame *cf = (struct can_frame *)skb->data;
 251         u32 can_id;
 252         u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
 253
 254         if (can_dropped_invalid_skb(dev, skb))
 255                 return NETDEV_TX_OK;
 256
 257         netif_stop_queue(dev);
 258
 259         if (cf->can_id & CAN_EFF_FLAG) {
 260                 can_id = cf->can_id & CAN_EFF_MASK;
 261                 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
 262         } else {
 263                 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
 264         }
 265
 266         if (cf->can_id & CAN_RTR_FLAG)
 267                 ctrl |= FLEXCAN_MB_CNT_RTR;
 268
 269         if (cf->can_dlc > 0) {
 270                 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
 271                 writel(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
 272         }
 273         if (cf->can_dlc > 3) {
 274                 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
 275                 writel(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
 276         }
 277
 278         writel(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
 279         writel(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
 280
 281         kfree_skb(skb);
 282
 283         /* tx_packets is incremented in flexcan_irq */
 284         stats->tx_bytes += cf->can_dlc;
 285
 286         return NETDEV_TX_OK;
 287 }
 288
 289 static void do_bus_err(struct net_device *dev,
 290                        struct can_frame *cf, u32 reg_esr)
 291 {
 292         struct flexcan_priv *priv = netdev_priv(dev);
 293         int rx_errors = 0, tx_errors = 0;
 294
 295         cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 296
 297         if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
 298                 dev_dbg(dev->dev.parent, "BIT1_ERR irq\n");
 299                 cf->data[2] |= CAN_ERR_PROT_BIT1;
 300                 tx_errors = 1;
 301         }
 302         if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
 303                 dev_dbg(dev->dev.parent, "BIT0_ERR irq\n");
 304                 cf->data[2] |= CAN_ERR_PROT_BIT0;
 305                 tx_errors = 1;
 306         }
 307         if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
 308                 dev_dbg(dev->dev.parent, "ACK_ERR irq\n");
 309                 cf->can_id |= CAN_ERR_ACK;
 310                 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
 311                 tx_errors = 1;
 312         }
 313         if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
 314                 dev_dbg(dev->dev.parent, "CRC_ERR irq\n");
 315                 cf->data[2] |= CAN_ERR_PROT_BIT;
 316                 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
 317                 rx_errors = 1;
 318         }
 319         if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
 320                 dev_dbg(dev->dev.parent, "FRM_ERR irq\n");
 321                 cf->data[2] |= CAN_ERR_PROT_FORM;
 322                 rx_errors = 1;
 323         }
 324         if (reg_esr & FLEXCAN_ESR_STF_ERR) {
 325                 dev_dbg(dev->dev.parent, "STF_ERR irq\n");
 326                 cf->data[2] |= CAN_ERR_PROT_STUFF;
 327                 rx_errors = 1;
 328         }
 329
 330         priv->can.can_stats.bus_error++;
 331         if (rx_errors)
 332                 dev->stats.rx_errors++;
 333         if (tx_errors)
 334                 dev->stats.tx_errors++;
 335 }
 336
 337 static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
 338 {
 339         struct sk_buff *skb;
 340         struct can_frame *cf;
 341
 342         skb = alloc_can_err_skb(dev, &cf);
 343         if (unlikely(!skb))
 344                 return 0;
 345
 346         do_bus_err(dev, cf, reg_esr);
 347         netif_receive_skb(skb);
 348
 349         dev->stats.rx_packets++;
 350         dev->stats.rx_bytes += cf->can_dlc;
 351
 352         return 1;
 353 }
 354
 355 static void do_state(struct net_device *dev,
 356                      struct can_frame *cf, enum can_state new_state)
 357 {
 358         struct flexcan_priv *priv = netdev_priv(dev);
 359         struct can_berr_counter bec;
 360
 361         flexcan_get_berr_counter(dev, &bec);
 362
 363         switch (priv->can.state) {
 364         case CAN_STATE_ERROR_ACTIVE:
 365                 /*
 366                  * from: ERROR_ACTIVE
 367                  * to  : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
 368                  * =>  : there was a warning int
 369                  */
 370                 if (new_state >= CAN_STATE_ERROR_WARNING &&
 371                     new_state <= CAN_STATE_BUS_OFF) {
 372                         dev_dbg(dev->dev.parent, "Error Warning IRQ\n");
 373                         priv->can.can_stats.error_warning++;
 374
 375                         cf->can_id |= CAN_ERR_CRTL;
 376                         cf->data[1] = (bec.txerr > bec.rxerr) ?
 377                                 CAN_ERR_CRTL_TX_WARNING :
 378                                 CAN_ERR_CRTL_RX_WARNING;
 379                 }
 380         case CAN_STATE_ERROR_WARNING:   /* fallthrough */
 381                 /*
 382                  * from: ERROR_ACTIVE, ERROR_WARNING
 383                  * to  : ERROR_PASSIVE, BUS_OFF
 384                  * =>  : error passive int
 385                  */
 386                 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
 387                     new_state <= CAN_STATE_BUS_OFF) {
 388                         dev_dbg(dev->dev.parent, "Error Passive IRQ\n");
 389                         priv->can.can_stats.error_passive++;
 390
 391                         cf->can_id |= CAN_ERR_CRTL;
 392                         cf->data[1] = (bec.txerr > bec.rxerr) ?
 393                                 CAN_ERR_CRTL_TX_PASSIVE :
 394                                 CAN_ERR_CRTL_RX_PASSIVE;
 395                 }
 396                 break;
 397         case CAN_STATE_BUS_OFF:
 398                 dev_err(dev->dev.parent,
 399                         "BUG! hardware recovered automatically from BUS_OFF\n");
 400                 break;
 401         default:
 402                 break;
 403         }
 404
 405         /* process state changes depending on the new state */
 406         switch (new_state) {
 407         case CAN_STATE_ERROR_ACTIVE:
 408                 dev_dbg(dev->dev.parent, "Error Active\n");
 409                 cf->can_id |= CAN_ERR_PROT;
 410                 cf->data[2] = CAN_ERR_PROT_ACTIVE;
 411                 break;
 412         case CAN_STATE_BUS_OFF:
 413                 cf->can_id |= CAN_ERR_BUSOFF;
 414                 can_bus_off(dev);
 415                 break;
 416         default:
 417                 break;
 418         }
 419 }
 420
 421 static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
 422 {
 423         struct flexcan_priv *priv = netdev_priv(dev);
 424         struct sk_buff *skb;
 425         struct can_frame *cf;
 426         enum can_state new_state;
 427         int flt;
 428
 429         flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
 430         if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
 431                 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN |
 432                                         FLEXCAN_ESR_RX_WRN))))
 433                         new_state = CAN_STATE_ERROR_ACTIVE;
 434                 else
 435                         new_state = CAN_STATE_ERROR_WARNING;
 436         } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE))
 437                 new_state = CAN_STATE_ERROR_PASSIVE;
 438         else
 439                 new_state = CAN_STATE_BUS_OFF;
 440
 441         /* state hasn't changed */
 442         if (likely(new_state == priv->can.state))
 443                 return 0;
 444
 445         skb = alloc_can_err_skb(dev, &cf);
 446         if (unlikely(!skb))
 447                 return 0;
 448
 449         do_state(dev, cf, new_state);
 450         priv->can.state = new_state;
 451         netif_receive_skb(skb);
 452
 453         dev->stats.rx_packets++;
 454         dev->stats.rx_bytes += cf->can_dlc;
 455
 456         return 1;
 457 }
 458
 459 static void flexcan_read_fifo(const struct net_device *dev,
 460                               struct can_frame *cf)
 461 {
 462         const struct flexcan_priv *priv = netdev_priv(dev);
 463         struct flexcan_regs __iomem *regs = priv->base;
 464         struct flexcan_mb __iomem *mb = &regs->cantxfg[0];
 465         u32 reg_ctrl, reg_id;
 466
 467         reg_ctrl = readl(&mb->can_ctrl);
 468         reg_id = readl(&mb->can_id);
 469         if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
 470                 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
 471         else
 472                 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
 473
 474         if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
 475                 cf->can_id |= CAN_RTR_FLAG;
 476         cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
 477
 478         *(__be32 *)(cf->data + 0) = cpu_to_be32(readl(&mb->data[0]));
 479         *(__be32 *)(cf->data + 4) = cpu_to_be32(readl(&mb->data[1]));
 480
 481         /* mark as read */
 482         writel(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
 483         readl(&regs->timer);
 484 }
 485
 486 static int flexcan_read_frame(struct net_device *dev)
 487 {
 488         struct net_device_stats *stats = &dev->stats;
 489         struct can_frame *cf;
 490         struct sk_buff *skb;
 491
 492         skb = alloc_can_skb(dev, &cf);
 493         if (unlikely(!skb)) {
 494                 stats->rx_dropped++;
 495                 return 0;
 496         }
 497
 498         flexcan_read_fifo(dev, cf);
 499         netif_receive_skb(skb);
 500
 501         stats->rx_packets++;
 502         stats->rx_bytes += cf->can_dlc;
 503
 504         return 1;
 505 }
 506
 507 static int flexcan_poll(struct napi_struct *napi, int quota)
 508 {
 509         struct net_device *dev = napi->dev;
 510         const struct flexcan_priv *priv = netdev_priv(dev);
 511         struct flexcan_regs __iomem *regs = priv->base;
 512         u32 reg_iflag1, reg_esr;
 513         int work_done = 0;
 514
 515         /*
 516          * The error bits are cleared on read,
 517          * use saved value from irq handler.
 518          */
 519         reg_esr = readl(&regs->esr) | priv->reg_esr;
 520
 521         /* handle state changes */
 522         work_done += flexcan_poll_state(dev, reg_esr);
 523
 524         /* handle RX-FIFO */
 525         reg_iflag1 = readl(&regs->iflag1);
 526         while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
 527                work_done < quota) {
 528                 work_done += flexcan_read_frame(dev);
 529                 reg_iflag1 = readl(&regs->iflag1);
 530         }
 531
 532         /* report bus errors */
 533         if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
 534                 work_done += flexcan_poll_bus_err(dev, reg_esr);
 535
 536         if (work_done < quota) {
 537                 napi_complete(napi);
 538                 /* enable IRQs */
 539                 writel(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
 540                 writel(priv->reg_ctrl_default, &regs->ctrl);
 541         }
 542
 543         return work_done;
 544 }
 545
 546 static irqreturn_t flexcan_irq(int irq, void *dev_id)
 547 {
 548         struct net_device *dev = dev_id;
 549         struct net_device_stats *stats = &dev->stats;
 550         struct flexcan_priv *priv = netdev_priv(dev);
 551         struct flexcan_regs __iomem *regs = priv->base;
 552         u32 reg_iflag1, reg_esr;
 553
 554         reg_iflag1 = readl(&regs->iflag1);
 555         reg_esr = readl(&regs->esr);
 556         writel(FLEXCAN_ESR_ERR_INT, &regs->esr);        /* ACK err IRQ */
 557
 558         /*
 559          * schedule NAPI in case of:
 560          * - rx IRQ
 561          * - state change IRQ
 562          * - bus error IRQ and bus error reporting is activated
 563          */
 564         if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
 565             (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
 566             flexcan_has_and_handle_berr(priv, reg_esr)) {
 567                 /*
 568                  * The error bits are cleared on read,
 569                  * save them for later use.
 570                  */
 571                 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
 572                 writel(FLEXCAN_IFLAG_DEFAULT & ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE,
 573                        &regs->imask1);
 574                 writel(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
 575                        &regs->ctrl);
 576                 napi_schedule(&priv->napi);
 577         }
 578
 579         /* FIFO overflow */
 580         if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
 581                 writel(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
 582                 dev->stats.rx_over_errors++;
 583                 dev->stats.rx_errors++;
 584         }
 585
 586         /* transmission complete interrupt */
 587         if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
 588                 /* tx_bytes is incremented in flexcan_start_xmit */
 589                 stats->tx_packets++;
 590                 writel((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
 591                 netif_wake_queue(dev);
 592         }
 593
 594         return IRQ_HANDLED;
 595 }
 596
 597 static void flexcan_set_bittiming(struct net_device *dev)
 598 {
 599         const struct flexcan_priv *priv = netdev_priv(dev);
 600         const struct can_bittiming *bt = &priv->can.bittiming;
 601         struct flexcan_regs __iomem *regs = priv->base;
 602         u32 reg;
 603
 604         reg = readl(&regs->ctrl);
 605         reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
 606                  FLEXCAN_CTRL_RJW(0x3) |
 607                  FLEXCAN_CTRL_PSEG1(0x7) |
 608                  FLEXCAN_CTRL_PSEG2(0x7) |
 609                  FLEXCAN_CTRL_PROPSEG(0x7) |
 610                  FLEXCAN_CTRL_LPB |
 611                  FLEXCAN_CTRL_SMP |
 612                  FLEXCAN_CTRL_LOM);
 613
 614         reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
 615                 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
 616                 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
 617                 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
 618                 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
 619
 620         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
 621                 reg |= FLEXCAN_CTRL_LPB;
 622         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
 623                 reg |= FLEXCAN_CTRL_LOM;
 624         if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
 625                 reg |= FLEXCAN_CTRL_SMP;
 626
 627         dev_info(dev->dev.parent, "writing ctrl=0x%08x\n", reg);
 628         writel(reg, &regs->ctrl);
 629
 630         /* print chip status */
 631         dev_dbg(dev->dev.parent, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
 632                 readl(&regs->mcr), readl(&regs->ctrl));
 633 }
 634
 635 /*
 636  * flexcan_chip_start
 637  *
 638  * this functions is entered with clocks enabled
 639  *
 640  */
 641 static int flexcan_chip_start(struct net_device *dev)
 642 {
 643         struct flexcan_priv *priv = netdev_priv(dev);
 644         struct flexcan_regs __iomem *regs = priv->base;
 645         unsigned int i;
 646         int err;
 647         u32 reg_mcr, reg_ctrl;
 648
 649         /* enable module */
 650         flexcan_chip_enable(priv);
 651
 652         /* soft reset */
 653         writel(FLEXCAN_MCR_SOFTRST, &regs->mcr);
 654         udelay(10);
 655
 656         reg_mcr = readl(&regs->mcr);
 657         if (reg_mcr & FLEXCAN_MCR_SOFTRST) {
 658                 dev_err(dev->dev.parent,
 659                         "Failed to softreset can module (mcr=0x%08x)\n",
 660                         reg_mcr);
 661                 err = -ENODEV;
 662                 goto out;
 663         }
 664
 665         flexcan_set_bittiming(dev);
 666
 667         /*
 668          * MCR
 669          *
 670          * enable freeze
 671          * enable fifo
 672          * halt now
 673          * only supervisor access
 674          * enable warning int
 675          * choose format C
 676          *
 677          */
 678         reg_mcr = readl(&regs->mcr);
 679         reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
 680                 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
 681                 FLEXCAN_MCR_IDAM_C;
 682         dev_dbg(dev->dev.parent, "%s: writing mcr=0x%08x", __func__, reg_mcr);
 683         writel(reg_mcr, &regs->mcr);
 684
 685         /*
 686          * CTRL
 687          *
 688          * disable timer sync feature
 689          *
 690          * disable auto busoff recovery
 691          * transmit lowest buffer first
 692          *
 693          * enable tx and rx warning interrupt
 694          * enable bus off interrupt
 695          * (== FLEXCAN_CTRL_ERR_STATE)
 696          *
 697          * _note_: we enable the "error interrupt"
 698          * (FLEXCAN_CTRL_ERR_MSK), too. Otherwise we don't get any
 699          * warning or bus passive interrupts.
 700          */
 701         reg_ctrl = readl(&regs->ctrl);
 702         reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
 703         reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
 704                 FLEXCAN_CTRL_ERR_STATE | FLEXCAN_CTRL_ERR_MSK;
 705
 706         /* save for later use */
 707         priv->reg_ctrl_default = reg_ctrl;
 708         dev_dbg(dev->dev.parent, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
 709         writel(reg_ctrl, &regs->ctrl);
 710
 711         for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) {
 712                 writel(0, &regs->cantxfg[i].can_ctrl);
 713                 writel(0, &regs->cantxfg[i].can_id);
 714                 writel(0, &regs->cantxfg[i].data[0]);
 715                 writel(0, &regs->cantxfg[i].data[1]);
 716
 717                 /* put MB into rx queue */
 718                 writel(FLEXCAN_MB_CNT_CODE(0x4), &regs->cantxfg[i].can_ctrl);
 719         }
 720
 721         /* acceptance mask/acceptance code (accept everything) */
 722         writel(0x0, &regs->rxgmask);
 723         writel(0x0, &regs->rx14mask);
 724         writel(0x0, &regs->rx15mask);
 725
 726         flexcan_transceiver_switch(priv, 1);
 727
 728         /* synchronize with the can bus */
 729         reg_mcr = readl(&regs->mcr);
 730         reg_mcr &= ~FLEXCAN_MCR_HALT;
 731         writel(reg_mcr, &regs->mcr);
 732
 733         priv->can.state = CAN_STATE_ERROR_ACTIVE;
 734
 735         /* enable FIFO interrupts */
 736         writel(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
 737
 738         /* print chip status */
 739         dev_dbg(dev->dev.parent, "%s: reading mcr=0x%08x ctrl=0x%08x\n",
 740                 __func__, readl(&regs->mcr), readl(&regs->ctrl));
 741
 742         return 0;
 743
 744  out:
 745         flexcan_chip_disable(priv);
 746         return err;
 747 }
 748
 749 /*
 750  * flexcan_chip_stop
 751  *
 752  * this functions is entered with clocks enabled
 753  *
 754  */
 755 static void flexcan_chip_stop(struct net_device *dev)
 756 {
 757         struct flexcan_priv *priv = netdev_priv(dev);
 758         struct flexcan_regs __iomem *regs = priv->base;
 759         u32 reg;
 760
 761         /* Disable all interrupts */
 762         writel(0, &regs->imask1);
 763
 764         /* Disable + halt module */
 765         reg = readl(&regs->mcr);
 766         reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT;
 767         writel(reg, &regs->mcr);
 768
 769         flexcan_transceiver_switch(priv, 0);
 770         priv->can.state = CAN_STATE_STOPPED;
 771
 772         return;
 773 }
 774
 775 static int flexcan_open(struct net_device *dev)
 776 {
 777         struct flexcan_priv *priv = netdev_priv(dev);
 778         int err;
 779
 780         clk_enable(priv->clk);
 781
 782         err = open_candev(dev);
 783         if (err)
 784                 goto out;
 785
 786         err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
 787         if (err)
 788                 goto out_close;
 789
 790         /* start chip and queuing */
 791         err = flexcan_chip_start(dev);
 792         if (err)
 793                 goto out_close;
 794         napi_enable(&priv->napi);
 795         netif_start_queue(dev);
 796
 797         return 0;
 798
 799  out_close:
 800         close_candev(dev);
 801  out:
 802         clk_disable(priv->clk);
 803
 804         return err;
 805 }
 806
 807 static int flexcan_close(struct net_device *dev)
 808 {
 809         struct flexcan_priv *priv = netdev_priv(dev);
 810
 811         netif_stop_queue(dev);
 812         napi_disable(&priv->napi);
 813         flexcan_chip_stop(dev);
 814
 815         free_irq(dev->irq, dev);
 816         clk_disable(priv->clk);
 817
 818         close_candev(dev);
 819
 820         return 0;
 821 }
 822
 823 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
 824 {
 825         int err;
 826
 827         switch (mode) {
 828         case CAN_MODE_START:
 829                 err = flexcan_chip_start(dev);
 830                 if (err)
 831                         return err;
 832
 833                 netif_wake_queue(dev);
 834                 break;
 835
 836         default:
 837                 return -EOPNOTSUPP;
 838         }
 839
 840         return 0;
 841 }
 842
 843 static const struct net_device_ops flexcan_netdev_ops = {
 844         .ndo_open       = flexcan_open,
 845         .ndo_stop       = flexcan_close,
 846         .ndo_start_xmit = flexcan_start_xmit,
 847 };
 848
 849 static int __devinit register_flexcandev(struct net_device *dev)
 850 {
 851         struct flexcan_priv *priv = netdev_priv(dev);
 852         struct flexcan_regs __iomem *regs = priv->base;
 853         u32 reg, err;
 854
 855         clk_enable(priv->clk);
 856
 857         /* select "bus clock", chip must be disabled */
 858         flexcan_chip_disable(priv);
 859         reg = readl(&regs->ctrl);
 860         reg |= FLEXCAN_CTRL_CLK_SRC;
 861         writel(reg, &regs->ctrl);
 862
 863         flexcan_chip_enable(priv);
 864
 865         /* set freeze, halt and activate FIFO, restrict register access */
 866         reg = readl(&regs->mcr);
 867         reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
 868                 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
 869         writel(reg, &regs->mcr);
 870
 871         /*
 872          * Currently we only support newer versions of this core
 873          * featuring a RX FIFO. Older cores found on some Coldfire
 874          * derivates are not yet supported.
 875          */
 876         reg = readl(&regs->mcr);
 877         if (!(reg & FLEXCAN_MCR_FEN)) {
 878                 dev_err(dev->dev.parent,
 879                         "Could not enable RX FIFO, unsupported core\n");
 880                 err = -ENODEV;
 881                 goto out;
 882         }
 883
 884         err = register_candev(dev);
 885
 886  out:
 887         /* disable core and turn off clocks */
 888         flexcan_chip_disable(priv);
 889         clk_disable(priv->clk);
 890
 891         return err;
 892 }
 893
 894 static void __devexit unregister_flexcandev(struct net_device *dev)
 895 {
 896         unregister_candev(dev);
 897 }
 898
 899 static int __devinit flexcan_probe(struct platform_device *pdev)
 900 {
 901         struct net_device *dev;
 902         struct flexcan_priv *priv;
 903         struct resource *mem;
 904         struct clk *clk;
 905         void __iomem *base;
 906         resource_size_t mem_size;
 907         int err, irq;
 908
 909         clk = clk_get(&pdev->dev, NULL);
 910         if (IS_ERR(clk)) {
 911                 dev_err(&pdev->dev, "no clock defined\n");
 912                 err = PTR_ERR(clk);
 913                 goto failed_clock;
 914         }
 915
 916         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 917         irq = platform_get_irq(pdev, 0);
 918         if (!mem || irq <= 0) {
 919                 err = -ENODEV;
 920                 goto failed_get;
 921         }
 922
 923         mem_size = resource_size(mem);
 924         if (!request_mem_region(mem->start, mem_size, pdev->name)) {
 925                 err = -EBUSY;
 926                 goto failed_req;
 927         }
 928
 929         base = ioremap(mem->start, mem_size);
 930         if (!base) {
 931                 err = -ENOMEM;
 932                 goto failed_map;
 933         }
 934
 935         dev = alloc_candev(sizeof(struct flexcan_priv), 0);
 936         if (!dev) {
 937                 err = -ENOMEM;
 938                 goto failed_alloc;
 939         }
 940
 941         dev->netdev_ops = &flexcan_netdev_ops;
 942         dev->irq = irq;
 943         dev->flags |= IFF_ECHO; /* we support local echo in hardware */
 944
 945         priv = netdev_priv(dev);
 946         priv->can.clock.freq = clk_get_rate(clk);
 947         priv->can.bittiming_const = &flexcan_bittiming_const;
 948         priv->can.do_set_mode = flexcan_set_mode;
 949         priv->can.do_get_berr_counter = flexcan_get_berr_counter;
 950         priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
 951                 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
 952                 CAN_CTRLMODE_BERR_REPORTING;
 953         priv->base = base;
 954         priv->dev = dev;
 955         priv->clk = clk;
 956         priv->pdata = pdev->dev.platform_data;
 957
 958         netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
 959
 960         dev_set_drvdata(&pdev->dev, dev);
 961         SET_NETDEV_DEV(dev, &pdev->dev);
 962
 963         err = register_flexcandev(dev);
 964         if (err) {
 965                 dev_err(&pdev->dev, "registering netdev failed\n");
 966                 goto failed_register;
 967         }
 968
 969         dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
 970                  priv->base, dev->irq);
 971
 972         return 0;
 973
 974  failed_register:
 975         free_candev(dev);
 976  failed_alloc:
 977         iounmap(base);
 978  failed_map:
 979         release_mem_region(mem->start, mem_size);
 980  failed_req:
 981         clk_put(clk);
 982  failed_get:
 983  failed_clock:
 984         return err;
 985 }
 986
 987 static int __devexit flexcan_remove(struct platform_device *pdev)
 988 {
 989         struct net_device *dev = platform_get_drvdata(pdev);
 990         struct flexcan_priv *priv = netdev_priv(dev);
 991         struct resource *mem;
 992
 993         unregister_flexcandev(dev);
 994         platform_set_drvdata(pdev, NULL);
 995         free_candev(dev);
 996         iounmap(priv->base);
 997
 998         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 999         release_mem_region(mem->start, resource_size(mem));
1000
1001         clk_put(priv->clk);
1002
1003         return 0;
1004 }
1005
1006 static struct platform_driver flexcan_driver = {
1007         .driver.name = DRV_NAME,
1008         .probe = flexcan_probe,
1009         .remove = __devexit_p(flexcan_remove),
1010 };
1011
1012 static int __init flexcan_init(void)
1013 {
1014         pr_info("%s netdevice driver\n", DRV_NAME);
1015         return platform_driver_register(&flexcan_driver);
1016 }
1017
1018 static void __exit flexcan_exit(void)
1019 {
1020         platform_driver_unregister(&flexcan_driver);
1021         pr_info("%s: driver removed\n", DRV_NAME);
1022 }
1023
1024 module_init(flexcan_init);
1025 module_exit(flexcan_exit);
1026
1027 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1028               "Marc Kleine-Budde <kernel@pengutronix.de>");
1029 MODULE_LICENSE("GPL v2");
1030 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");