2 * at91_can.c - CAN network driver for AT91 SoC CAN controller
4 * (C) 2007 by Hans J. Koch <hjk@linutronix.de>
5 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
7 * This software may be distributed under the terms of the GNU General
8 * Public License ("GPL") version 2 as distributed in the 'COPYING'
9 * file from the main directory of the linux kernel source.
11 * Send feedback to <socketcan-users@lists.berlios.de>
14 * Your platform definition file should specify something like:
16 * static struct at91_can_data ek_can_data = {
17 * transceiver_switch = sam9263ek_transceiver_switch,
20 * at91_add_device_can(&ek_can_data);
24 #include <linux/clk.h>
25 #include <linux/errno.h>
26 #include <linux/if_arp.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/platform_device.h>
33 #include <linux/skbuff.h>
34 #include <linux/spinlock.h>
35 #include <linux/string.h>
36 #include <linux/types.h>
38 #include <linux/can/dev.h>
39 #include <linux/can/error.h>
41 #include <mach/board.h>
43 #define DRV_NAME "at91_can"
44 #define AT91_NAPI_WEIGHT 12
50 #define AT91_MB_RX_NUM 12
51 #define AT91_MB_TX_SHIFT 2
53 #define AT91_MB_RX_FIRST 0
54 #define AT91_MB_RX_LAST (AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1)
56 #define AT91_MB_RX_MASK(i) ((1 << (i)) - 1)
57 #define AT91_MB_RX_SPLIT 8
58 #define AT91_MB_RX_LOW_LAST (AT91_MB_RX_SPLIT - 1)
59 #define AT91_MB_RX_LOW_MASK (AT91_MB_RX_MASK(AT91_MB_RX_SPLIT))
61 #define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT)
62 #define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1)
63 #define AT91_MB_TX_LAST (AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1)
65 #define AT91_NEXT_PRIO_SHIFT (AT91_MB_TX_SHIFT)
66 #define AT91_NEXT_PRIO_MASK (0xf << AT91_MB_TX_SHIFT)
67 #define AT91_NEXT_MB_MASK (AT91_MB_TX_NUM - 1)
68 #define AT91_NEXT_MASK ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK)
70 /* Common registers */
85 /* Mailbox registers (0 <= i <= 15) */
86 #define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20))
87 #define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20))
88 #define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20))
89 #define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20))
90 #define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20))
91 #define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20))
92 #define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20))
93 #define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20))
96 #define AT91_MR_CANEN BIT(0)
97 #define AT91_MR_LPM BIT(1)
98 #define AT91_MR_ABM BIT(2)
99 #define AT91_MR_OVL BIT(3)
100 #define AT91_MR_TEOF BIT(4)
101 #define AT91_MR_TTM BIT(5)
102 #define AT91_MR_TIMFRZ BIT(6)
103 #define AT91_MR_DRPT BIT(7)
105 #define AT91_SR_RBSY BIT(29)
107 #define AT91_MMR_PRIO_SHIFT (16)
109 #define AT91_MID_MIDE BIT(29)
111 #define AT91_MSR_MRTR BIT(20)
112 #define AT91_MSR_MABT BIT(22)
113 #define AT91_MSR_MRDY BIT(23)
114 #define AT91_MSR_MMI BIT(24)
116 #define AT91_MCR_MRTR BIT(20)
117 #define AT91_MCR_MTCR BIT(23)
121 AT91_MB_MODE_DISABLED
= 0,
123 AT91_MB_MODE_RX_OVRWR
= 2,
125 AT91_MB_MODE_CONSUMER
= 4,
126 AT91_MB_MODE_PRODUCER
= 5,
129 /* Interrupt mask bits */
130 #define AT91_IRQ_MB_RX ((1 << (AT91_MB_RX_LAST + 1)) \
131 - (1 << AT91_MB_RX_FIRST))
132 #define AT91_IRQ_MB_TX ((1 << (AT91_MB_TX_LAST + 1)) \
133 - (1 << AT91_MB_TX_FIRST))
134 #define AT91_IRQ_MB_ALL (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX)
136 #define AT91_IRQ_ERRA (1 << 16)
137 #define AT91_IRQ_WARN (1 << 17)
138 #define AT91_IRQ_ERRP (1 << 18)
139 #define AT91_IRQ_BOFF (1 << 19)
140 #define AT91_IRQ_SLEEP (1 << 20)
141 #define AT91_IRQ_WAKEUP (1 << 21)
142 #define AT91_IRQ_TOVF (1 << 22)
143 #define AT91_IRQ_TSTP (1 << 23)
144 #define AT91_IRQ_CERR (1 << 24)
145 #define AT91_IRQ_SERR (1 << 25)
146 #define AT91_IRQ_AERR (1 << 26)
147 #define AT91_IRQ_FERR (1 << 27)
148 #define AT91_IRQ_BERR (1 << 28)
150 #define AT91_IRQ_ERR_ALL (0x1fff0000)
151 #define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \
152 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
153 #define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \
154 AT91_IRQ_ERRP | AT91_IRQ_BOFF)
156 #define AT91_IRQ_ALL (0x1fffffff)
159 struct can_priv can
; /* must be the first member! */
160 struct net_device
*dev
;
161 struct napi_struct napi
;
163 void __iomem
*reg_base
;
166 unsigned int tx_next
;
167 unsigned int tx_echo
;
168 unsigned int rx_next
;
171 struct at91_can_data
*pdata
;
174 static struct can_bittiming_const at91_bittiming_const
= {
185 static inline int get_tx_next_mb(const struct at91_priv
*priv
)
187 return (priv
->tx_next
& AT91_NEXT_MB_MASK
) + AT91_MB_TX_FIRST
;
190 static inline int get_tx_next_prio(const struct at91_priv
*priv
)
192 return (priv
->tx_next
>> AT91_NEXT_PRIO_SHIFT
) & 0xf;
195 static inline int get_tx_echo_mb(const struct at91_priv
*priv
)
197 return (priv
->tx_echo
& AT91_NEXT_MB_MASK
) + AT91_MB_TX_FIRST
;
200 static inline u32
at91_read(const struct at91_priv
*priv
, enum at91_reg reg
)
202 return readl(priv
->reg_base
+ reg
);
205 static inline void at91_write(const struct at91_priv
*priv
, enum at91_reg reg
,
208 writel(value
, priv
->reg_base
+ reg
);
211 static inline void set_mb_mode_prio(const struct at91_priv
*priv
,
212 unsigned int mb
, enum at91_mb_mode mode
, int prio
)
214 at91_write(priv
, AT91_MMR(mb
), (mode
<< 24) | (prio
<< 16));
217 static inline void set_mb_mode(const struct at91_priv
*priv
, unsigned int mb
,
218 enum at91_mb_mode mode
)
220 set_mb_mode_prio(priv
, mb
, mode
, 0);
224 * Swtich transceiver on or off
226 static void at91_transceiver_switch(const struct at91_priv
*priv
, int on
)
228 if (priv
->pdata
&& priv
->pdata
->transceiver_switch
)
229 priv
->pdata
->transceiver_switch(on
);
232 static void at91_setup_mailboxes(struct net_device
*dev
)
234 struct at91_priv
*priv
= netdev_priv(dev
);
238 * The first 12 mailboxes are used as a reception FIFO. The
239 * last mailbox is configured with overwrite option. The
240 * overwrite flag indicates a FIFO overflow.
242 for (i
= AT91_MB_RX_FIRST
; i
< AT91_MB_RX_LAST
; i
++)
243 set_mb_mode(priv
, i
, AT91_MB_MODE_RX
);
244 set_mb_mode(priv
, AT91_MB_RX_LAST
, AT91_MB_MODE_RX_OVRWR
);
246 /* The last 4 mailboxes are used for transmitting. */
247 for (i
= AT91_MB_TX_FIRST
; i
<= AT91_MB_TX_LAST
; i
++)
248 set_mb_mode_prio(priv
, i
, AT91_MB_MODE_TX
, 0);
250 /* Reset tx and rx helper pointers */
251 priv
->tx_next
= priv
->tx_echo
= priv
->rx_next
= 0;
254 static int at91_set_bittiming(struct net_device
*dev
)
256 const struct at91_priv
*priv
= netdev_priv(dev
);
257 const struct can_bittiming
*bt
= &priv
->can
.bittiming
;
260 reg_br
= ((priv
->can
.ctrlmode
& CAN_CTRLMODE_3_SAMPLES
) << 24) |
261 ((bt
->brp
- 1) << 16) | ((bt
->sjw
- 1) << 12) |
262 ((bt
->prop_seg
- 1) << 8) | ((bt
->phase_seg1
- 1) << 4) |
263 ((bt
->phase_seg2
- 1) << 0);
265 dev_info(dev
->dev
.parent
, "writing AT91_BR: 0x%08x\n", reg_br
);
267 at91_write(priv
, AT91_BR
, reg_br
);
272 static void at91_chip_start(struct net_device
*dev
)
274 struct at91_priv
*priv
= netdev_priv(dev
);
277 /* disable interrupts */
278 at91_write(priv
, AT91_IDR
, AT91_IRQ_ALL
);
281 reg_mr
= at91_read(priv
, AT91_MR
);
282 at91_write(priv
, AT91_MR
, reg_mr
& ~AT91_MR_CANEN
);
284 at91_setup_mailboxes(dev
);
285 at91_transceiver_switch(priv
, 1);
288 at91_write(priv
, AT91_MR
, AT91_MR_CANEN
);
290 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
292 /* Enable interrupts */
293 reg_ier
= AT91_IRQ_MB_RX
| AT91_IRQ_ERRP
| AT91_IRQ_ERR_FRAME
;
294 at91_write(priv
, AT91_IDR
, AT91_IRQ_ALL
);
295 at91_write(priv
, AT91_IER
, reg_ier
);
298 static void at91_chip_stop(struct net_device
*dev
, enum can_state state
)
300 struct at91_priv
*priv
= netdev_priv(dev
);
303 /* disable interrupts */
304 at91_write(priv
, AT91_IDR
, AT91_IRQ_ALL
);
306 reg_mr
= at91_read(priv
, AT91_MR
);
307 at91_write(priv
, AT91_MR
, reg_mr
& ~AT91_MR_CANEN
);
309 at91_transceiver_switch(priv
, 0);
310 priv
->can
.state
= state
;
314 * theory of operation:
316 * According to the datasheet priority 0 is the highest priority, 15
317 * is the lowest. If two mailboxes have the same priority level the
318 * message of the mailbox with the lowest number is sent first.
320 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then
321 * the next mailbox with prio 0, and so on, until all mailboxes are
322 * used. Then we start from the beginning with mailbox
323 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1
324 * prio 1. When we reach the last mailbox with prio 15, we have to
325 * stop sending, waiting for all messages to be delivered, then start
326 * again with mailbox AT91_MB_TX_FIRST prio 0.
328 * We use the priv->tx_next as counter for the next transmission
329 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
330 * encode the mailbox number, the upper 4 bits the mailbox priority:
332 * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) ||
333 * (mb - AT91_MB_TX_FIRST);
336 static netdev_tx_t
at91_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
338 struct at91_priv
*priv
= netdev_priv(dev
);
339 struct net_device_stats
*stats
= &dev
->stats
;
340 struct can_frame
*cf
= (struct can_frame
*)skb
->data
;
341 unsigned int mb
, prio
;
342 u32 reg_mid
, reg_mcr
;
344 if (can_dropped_invalid_skb(dev
, skb
))
347 mb
= get_tx_next_mb(priv
);
348 prio
= get_tx_next_prio(priv
);
350 if (unlikely(!(at91_read(priv
, AT91_MSR(mb
)) & AT91_MSR_MRDY
))) {
351 netif_stop_queue(dev
);
353 dev_err(dev
->dev
.parent
,
354 "BUG! TX buffer full when queue awake!\n");
355 return NETDEV_TX_BUSY
;
358 if (cf
->can_id
& CAN_EFF_FLAG
)
359 reg_mid
= (cf
->can_id
& CAN_EFF_MASK
) | AT91_MID_MIDE
;
361 reg_mid
= (cf
->can_id
& CAN_SFF_MASK
) << 18;
363 reg_mcr
= ((cf
->can_id
& CAN_RTR_FLAG
) ? AT91_MCR_MRTR
: 0) |
364 (cf
->can_dlc
<< 16) | AT91_MCR_MTCR
;
366 /* disable MB while writing ID (see datasheet) */
367 set_mb_mode(priv
, mb
, AT91_MB_MODE_DISABLED
);
368 at91_write(priv
, AT91_MID(mb
), reg_mid
);
369 set_mb_mode_prio(priv
, mb
, AT91_MB_MODE_TX
, prio
);
371 at91_write(priv
, AT91_MDL(mb
), *(u32
*)(cf
->data
+ 0));
372 at91_write(priv
, AT91_MDH(mb
), *(u32
*)(cf
->data
+ 4));
374 /* This triggers transmission */
375 at91_write(priv
, AT91_MCR(mb
), reg_mcr
);
377 stats
->tx_bytes
+= cf
->can_dlc
;
379 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */
380 can_put_echo_skb(skb
, dev
, mb
- AT91_MB_TX_FIRST
);
383 * we have to stop the queue and deliver all messages in case
384 * of a prio+mb counter wrap around. This is the case if
385 * tx_next buffer prio and mailbox equals 0.
387 * also stop the queue if next buffer is still in use
391 if (!(at91_read(priv
, AT91_MSR(get_tx_next_mb(priv
))) &
393 (priv
->tx_next
& AT91_NEXT_MASK
) == 0)
394 netif_stop_queue(dev
);
396 /* Enable interrupt for this mailbox */
397 at91_write(priv
, AT91_IER
, 1 << mb
);
403 * at91_activate_rx_low - activate lower rx mailboxes
406 * Reenables the lower mailboxes for reception of new CAN messages
408 static inline void at91_activate_rx_low(const struct at91_priv
*priv
)
410 u32 mask
= AT91_MB_RX_LOW_MASK
;
411 at91_write(priv
, AT91_TCR
, mask
);
415 * at91_activate_rx_mb - reactive single rx mailbox
417 * @mb: mailbox to reactivate
419 * Reenables given mailbox for reception of new CAN messages
421 static inline void at91_activate_rx_mb(const struct at91_priv
*priv
,
425 at91_write(priv
, AT91_TCR
, mask
);
429 * at91_rx_overflow_err - send error frame due to rx overflow
432 static void at91_rx_overflow_err(struct net_device
*dev
)
434 struct net_device_stats
*stats
= &dev
->stats
;
436 struct can_frame
*cf
;
438 dev_dbg(dev
->dev
.parent
, "RX buffer overflow\n");
439 stats
->rx_over_errors
++;
442 skb
= alloc_can_err_skb(dev
, &cf
);
446 cf
->can_id
|= CAN_ERR_CRTL
;
447 cf
->data
[1] = CAN_ERR_CRTL_RX_OVERFLOW
;
448 netif_receive_skb(skb
);
451 stats
->rx_bytes
+= cf
->can_dlc
;
455 * at91_read_mb - read CAN msg from mailbox (lowlevel impl)
457 * @mb: mailbox number to read from
458 * @cf: can frame where to store message
460 * Reads a CAN message from the given mailbox and stores data into
461 * given can frame. "mb" and "cf" must be valid.
463 static void at91_read_mb(struct net_device
*dev
, unsigned int mb
,
464 struct can_frame
*cf
)
466 const struct at91_priv
*priv
= netdev_priv(dev
);
467 u32 reg_msr
, reg_mid
;
469 reg_mid
= at91_read(priv
, AT91_MID(mb
));
470 if (reg_mid
& AT91_MID_MIDE
)
471 cf
->can_id
= ((reg_mid
>> 0) & CAN_EFF_MASK
) | CAN_EFF_FLAG
;
473 cf
->can_id
= (reg_mid
>> 18) & CAN_SFF_MASK
;
475 reg_msr
= at91_read(priv
, AT91_MSR(mb
));
476 if (reg_msr
& AT91_MSR_MRTR
)
477 cf
->can_id
|= CAN_RTR_FLAG
;
478 cf
->can_dlc
= get_can_dlc((reg_msr
>> 16) & 0xf);
480 *(u32
*)(cf
->data
+ 0) = at91_read(priv
, AT91_MDL(mb
));
481 *(u32
*)(cf
->data
+ 4) = at91_read(priv
, AT91_MDH(mb
));
483 if (unlikely(mb
== AT91_MB_RX_LAST
&& reg_msr
& AT91_MSR_MMI
))
484 at91_rx_overflow_err(dev
);
488 * at91_read_msg - read CAN message from mailbox
490 * @mb: mail box to read from
492 * Reads a CAN message from given mailbox, and put into linux network
493 * RX queue, does all housekeeping chores (stats, ...)
495 static void at91_read_msg(struct net_device
*dev
, unsigned int mb
)
497 struct net_device_stats
*stats
= &dev
->stats
;
498 struct can_frame
*cf
;
501 skb
= alloc_can_skb(dev
, &cf
);
502 if (unlikely(!skb
)) {
507 at91_read_mb(dev
, mb
, cf
);
508 netif_receive_skb(skb
);
511 stats
->rx_bytes
+= cf
->can_dlc
;
514 static int at91_poll_rx(struct net_device
*dev
, int quota
)
516 struct at91_priv
*priv
= netdev_priv(dev
);
517 u32 reg_sr
= at91_read(priv
, AT91_SR
);
518 const unsigned long *addr
= (unsigned long *)®_sr
;
522 if (priv
->rx_next
> AT91_MB_RX_LOW_LAST
&&
523 reg_sr
& AT91_MB_RX_LOW_MASK
)
524 dev_info(dev
->dev
.parent
,
525 "order of incoming frames cannot be guaranteed\n");
528 for (mb
= find_next_bit(addr
, AT91_MB_RX_NUM
, priv
->rx_next
);
529 mb
< AT91_MB_RX_NUM
&& quota
> 0;
530 reg_sr
= at91_read(priv
, AT91_SR
),
531 mb
= find_next_bit(addr
, AT91_MB_RX_NUM
, ++priv
->rx_next
)) {
532 at91_read_msg(dev
, mb
);
534 /* reactivate mailboxes */
535 if (mb
== AT91_MB_RX_LOW_LAST
)
536 /* all lower mailboxed, if just finished it */
537 at91_activate_rx_low(priv
);
538 else if (mb
> AT91_MB_RX_LOW_LAST
)
539 /* only the mailbox we read */
540 at91_activate_rx_mb(priv
, mb
);
546 /* upper group completed, look again in lower */
547 if (priv
->rx_next
> AT91_MB_RX_LOW_LAST
&&
548 quota
> 0 && mb
>= AT91_MB_RX_NUM
) {
556 static void at91_poll_err_frame(struct net_device
*dev
,
557 struct can_frame
*cf
, u32 reg_sr
)
559 struct at91_priv
*priv
= netdev_priv(dev
);
562 if (reg_sr
& AT91_IRQ_CERR
) {
563 dev_dbg(dev
->dev
.parent
, "CERR irq\n");
564 dev
->stats
.rx_errors
++;
565 priv
->can
.can_stats
.bus_error
++;
566 cf
->can_id
|= CAN_ERR_PROT
| CAN_ERR_BUSERROR
;
570 if (reg_sr
& AT91_IRQ_SERR
) {
571 dev_dbg(dev
->dev
.parent
, "SERR irq\n");
572 dev
->stats
.rx_errors
++;
573 priv
->can
.can_stats
.bus_error
++;
574 cf
->can_id
|= CAN_ERR_PROT
| CAN_ERR_BUSERROR
;
575 cf
->data
[2] |= CAN_ERR_PROT_STUFF
;
578 /* Acknowledgement Error */
579 if (reg_sr
& AT91_IRQ_AERR
) {
580 dev_dbg(dev
->dev
.parent
, "AERR irq\n");
581 dev
->stats
.tx_errors
++;
582 cf
->can_id
|= CAN_ERR_ACK
;
586 if (reg_sr
& AT91_IRQ_FERR
) {
587 dev_dbg(dev
->dev
.parent
, "FERR irq\n");
588 dev
->stats
.rx_errors
++;
589 priv
->can
.can_stats
.bus_error
++;
590 cf
->can_id
|= CAN_ERR_PROT
| CAN_ERR_BUSERROR
;
591 cf
->data
[2] |= CAN_ERR_PROT_FORM
;
595 if (reg_sr
& AT91_IRQ_BERR
) {
596 dev_dbg(dev
->dev
.parent
, "BERR irq\n");
597 dev
->stats
.tx_errors
++;
598 priv
->can
.can_stats
.bus_error
++;
599 cf
->can_id
|= CAN_ERR_PROT
| CAN_ERR_BUSERROR
;
600 cf
->data
[2] |= CAN_ERR_PROT_BIT
;
604 static int at91_poll_err(struct net_device
*dev
, int quota
, u32 reg_sr
)
607 struct can_frame
*cf
;
612 skb
= alloc_can_err_skb(dev
, &cf
);
616 at91_poll_err_frame(dev
, cf
, reg_sr
);
617 netif_receive_skb(skb
);
619 dev
->stats
.rx_packets
++;
620 dev
->stats
.rx_bytes
+= cf
->can_dlc
;
625 static int at91_poll(struct napi_struct
*napi
, int quota
)
627 struct net_device
*dev
= napi
->dev
;
628 const struct at91_priv
*priv
= netdev_priv(dev
);
629 u32 reg_sr
= at91_read(priv
, AT91_SR
);
632 if (reg_sr
& AT91_IRQ_MB_RX
)
633 work_done
+= at91_poll_rx(dev
, quota
- work_done
);
636 * The error bits are clear on read,
637 * so use saved value from irq handler.
639 reg_sr
|= priv
->reg_sr
;
640 if (reg_sr
& AT91_IRQ_ERR_FRAME
)
641 work_done
+= at91_poll_err(dev
, quota
- work_done
, reg_sr
);
643 if (work_done
< quota
) {
644 /* enable IRQs for frame errors and all mailboxes >= rx_next */
645 u32 reg_ier
= AT91_IRQ_ERR_FRAME
;
646 reg_ier
|= AT91_IRQ_MB_RX
& ~AT91_MB_RX_MASK(priv
->rx_next
);
649 at91_write(priv
, AT91_IER
, reg_ier
);
656 * theory of operation:
658 * priv->tx_echo holds the number of the oldest can_frame put for
659 * transmission into the hardware, but not yet ACKed by the CAN tx
662 * We iterate from priv->tx_echo to priv->tx_next and check if the
663 * packet has been transmitted, echo it back to the CAN framework. If
664 * we discover a not yet transmitted package, stop looking for more.
667 static void at91_irq_tx(struct net_device
*dev
, u32 reg_sr
)
669 struct at91_priv
*priv
= netdev_priv(dev
);
673 /* masking of reg_sr not needed, already done by at91_irq */
675 for (/* nix */; (priv
->tx_next
- priv
->tx_echo
) > 0; priv
->tx_echo
++) {
676 mb
= get_tx_echo_mb(priv
);
678 /* no event in mailbox? */
679 if (!(reg_sr
& (1 << mb
)))
682 /* Disable irq for this TX mailbox */
683 at91_write(priv
, AT91_IDR
, 1 << mb
);
686 * only echo if mailbox signals us a transfer
687 * complete (MSR_MRDY). Otherwise it's a tansfer
688 * abort. "can_bus_off()" takes care about the skbs
689 * parked in the echo queue.
691 reg_msr
= at91_read(priv
, AT91_MSR(mb
));
692 if (likely(reg_msr
& AT91_MSR_MRDY
&&
693 ~reg_msr
& AT91_MSR_MABT
)) {
694 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */
695 can_get_echo_skb(dev
, mb
- AT91_MB_TX_FIRST
);
696 dev
->stats
.tx_packets
++;
701 * restart queue if we don't have a wrap around but restart if
702 * we get a TX int for the last can frame directly before a
705 if ((priv
->tx_next
& AT91_NEXT_MASK
) != 0 ||
706 (priv
->tx_echo
& AT91_NEXT_MASK
) == 0)
707 netif_wake_queue(dev
);
710 static void at91_irq_err_state(struct net_device
*dev
,
711 struct can_frame
*cf
, enum can_state new_state
)
713 struct at91_priv
*priv
= netdev_priv(dev
);
714 u32 reg_idr
, reg_ier
, reg_ecr
;
717 reg_ecr
= at91_read(priv
, AT91_ECR
);
718 rec
= reg_ecr
& 0xff;
721 switch (priv
->can
.state
) {
722 case CAN_STATE_ERROR_ACTIVE
:
725 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
726 * => : there was a warning int
728 if (new_state
>= CAN_STATE_ERROR_WARNING
&&
729 new_state
<= CAN_STATE_BUS_OFF
) {
730 dev_dbg(dev
->dev
.parent
, "Error Warning IRQ\n");
731 priv
->can
.can_stats
.error_warning
++;
733 cf
->can_id
|= CAN_ERR_CRTL
;
734 cf
->data
[1] = (tec
> rec
) ?
735 CAN_ERR_CRTL_TX_WARNING
:
736 CAN_ERR_CRTL_RX_WARNING
;
738 case CAN_STATE_ERROR_WARNING
: /* fallthrough */
740 * from: ERROR_ACTIVE, ERROR_WARNING
741 * to : ERROR_PASSIVE, BUS_OFF
742 * => : error passive int
744 if (new_state
>= CAN_STATE_ERROR_PASSIVE
&&
745 new_state
<= CAN_STATE_BUS_OFF
) {
746 dev_dbg(dev
->dev
.parent
, "Error Passive IRQ\n");
747 priv
->can
.can_stats
.error_passive
++;
749 cf
->can_id
|= CAN_ERR_CRTL
;
750 cf
->data
[1] = (tec
> rec
) ?
751 CAN_ERR_CRTL_TX_PASSIVE
:
752 CAN_ERR_CRTL_RX_PASSIVE
;
755 case CAN_STATE_BUS_OFF
:
758 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE
760 if (new_state
<= CAN_STATE_ERROR_PASSIVE
) {
761 cf
->can_id
|= CAN_ERR_RESTARTED
;
763 dev_dbg(dev
->dev
.parent
, "restarted\n");
764 priv
->can
.can_stats
.restarts
++;
766 netif_carrier_on(dev
);
767 netif_wake_queue(dev
);
775 /* process state changes depending on the new state */
777 case CAN_STATE_ERROR_ACTIVE
:
779 * actually we want to enable AT91_IRQ_WARN here, but
780 * it screws up the system under certain
781 * circumstances. so just enable AT91_IRQ_ERRP, thus
784 dev_dbg(dev
->dev
.parent
, "Error Active\n");
785 cf
->can_id
|= CAN_ERR_PROT
;
786 cf
->data
[2] = CAN_ERR_PROT_ACTIVE
;
787 case CAN_STATE_ERROR_WARNING
: /* fallthrough */
788 reg_idr
= AT91_IRQ_ERRA
| AT91_IRQ_WARN
| AT91_IRQ_BOFF
;
789 reg_ier
= AT91_IRQ_ERRP
;
791 case CAN_STATE_ERROR_PASSIVE
:
792 reg_idr
= AT91_IRQ_ERRA
| AT91_IRQ_WARN
| AT91_IRQ_ERRP
;
793 reg_ier
= AT91_IRQ_BOFF
;
795 case CAN_STATE_BUS_OFF
:
796 reg_idr
= AT91_IRQ_ERRA
| AT91_IRQ_ERRP
|
797 AT91_IRQ_WARN
| AT91_IRQ_BOFF
;
800 cf
->can_id
|= CAN_ERR_BUSOFF
;
802 dev_dbg(dev
->dev
.parent
, "bus-off\n");
803 netif_carrier_off(dev
);
804 priv
->can
.can_stats
.bus_off
++;
806 /* turn off chip, if restart is disabled */
807 if (!priv
->can
.restart_ms
) {
808 at91_chip_stop(dev
, CAN_STATE_BUS_OFF
);
816 at91_write(priv
, AT91_IDR
, reg_idr
);
817 at91_write(priv
, AT91_IER
, reg_ier
);
820 static void at91_irq_err(struct net_device
*dev
)
822 struct at91_priv
*priv
= netdev_priv(dev
);
824 struct can_frame
*cf
;
825 enum can_state new_state
;
828 reg_sr
= at91_read(priv
, AT91_SR
);
830 /* we need to look at the unmasked reg_sr */
831 if (unlikely(reg_sr
& AT91_IRQ_BOFF
))
832 new_state
= CAN_STATE_BUS_OFF
;
833 else if (unlikely(reg_sr
& AT91_IRQ_ERRP
))
834 new_state
= CAN_STATE_ERROR_PASSIVE
;
835 else if (unlikely(reg_sr
& AT91_IRQ_WARN
))
836 new_state
= CAN_STATE_ERROR_WARNING
;
837 else if (likely(reg_sr
& AT91_IRQ_ERRA
))
838 new_state
= CAN_STATE_ERROR_ACTIVE
;
840 dev_err(dev
->dev
.parent
, "BUG! hardware in undefined state\n");
844 /* state hasn't changed */
845 if (likely(new_state
== priv
->can
.state
))
848 skb
= alloc_can_err_skb(dev
, &cf
);
852 at91_irq_err_state(dev
, cf
, new_state
);
855 dev
->stats
.rx_packets
++;
856 dev
->stats
.rx_bytes
+= cf
->can_dlc
;
858 priv
->can
.state
= new_state
;
864 static irqreturn_t
at91_irq(int irq
, void *dev_id
)
866 struct net_device
*dev
= dev_id
;
867 struct at91_priv
*priv
= netdev_priv(dev
);
868 irqreturn_t handled
= IRQ_NONE
;
871 reg_sr
= at91_read(priv
, AT91_SR
);
872 reg_imr
= at91_read(priv
, AT91_IMR
);
874 /* Ignore masked interrupts */
879 handled
= IRQ_HANDLED
;
881 /* Receive or error interrupt? -> napi */
882 if (reg_sr
& (AT91_IRQ_MB_RX
| AT91_IRQ_ERR_FRAME
)) {
884 * The error bits are clear on read,
885 * save for later use.
887 priv
->reg_sr
= reg_sr
;
888 at91_write(priv
, AT91_IDR
,
889 AT91_IRQ_MB_RX
| AT91_IRQ_ERR_FRAME
);
890 napi_schedule(&priv
->napi
);
893 /* Transmission complete interrupt */
894 if (reg_sr
& AT91_IRQ_MB_TX
)
895 at91_irq_tx(dev
, reg_sr
);
903 static int at91_open(struct net_device
*dev
)
905 struct at91_priv
*priv
= netdev_priv(dev
);
908 clk_enable(priv
->clk
);
910 /* check or determine and set bittime */
911 err
= open_candev(dev
);
915 /* register interrupt handler */
916 if (request_irq(dev
->irq
, at91_irq
, IRQF_SHARED
,
922 /* start chip and queuing */
923 at91_chip_start(dev
);
924 napi_enable(&priv
->napi
);
925 netif_start_queue(dev
);
932 clk_disable(priv
->clk
);
938 * stop CAN bus activity
940 static int at91_close(struct net_device
*dev
)
942 struct at91_priv
*priv
= netdev_priv(dev
);
944 netif_stop_queue(dev
);
945 napi_disable(&priv
->napi
);
946 at91_chip_stop(dev
, CAN_STATE_STOPPED
);
948 free_irq(dev
->irq
, dev
);
949 clk_disable(priv
->clk
);
956 static int at91_set_mode(struct net_device
*dev
, enum can_mode mode
)
960 at91_chip_start(dev
);
961 netif_wake_queue(dev
);
971 static const struct net_device_ops at91_netdev_ops
= {
972 .ndo_open
= at91_open
,
973 .ndo_stop
= at91_close
,
974 .ndo_start_xmit
= at91_start_xmit
,
977 static int __init
at91_can_probe(struct platform_device
*pdev
)
979 struct net_device
*dev
;
980 struct at91_priv
*priv
;
981 struct resource
*res
;
986 clk
= clk_get(&pdev
->dev
, "can_clk");
988 dev_err(&pdev
->dev
, "no clock defined\n");
993 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
994 irq
= platform_get_irq(pdev
, 0);
995 if (!res
|| irq
<= 0) {
1000 if (!request_mem_region(res
->start
,
1007 addr
= ioremap_nocache(res
->start
, resource_size(res
));
1013 dev
= alloc_candev(sizeof(struct at91_priv
), AT91_MB_TX_NUM
);
1019 dev
->netdev_ops
= &at91_netdev_ops
;
1021 dev
->flags
|= IFF_ECHO
;
1023 priv
= netdev_priv(dev
);
1024 priv
->can
.clock
.freq
= clk_get_rate(clk
);
1025 priv
->can
.bittiming_const
= &at91_bittiming_const
;
1026 priv
->can
.do_set_bittiming
= at91_set_bittiming
;
1027 priv
->can
.do_set_mode
= at91_set_mode
;
1028 priv
->can
.ctrlmode_supported
= CAN_CTRLMODE_3_SAMPLES
;
1029 priv
->reg_base
= addr
;
1032 priv
->pdata
= pdev
->dev
.platform_data
;
1034 netif_napi_add(dev
, &priv
->napi
, at91_poll
, AT91_NAPI_WEIGHT
);
1036 dev_set_drvdata(&pdev
->dev
, dev
);
1037 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1039 err
= register_candev(dev
);
1041 dev_err(&pdev
->dev
, "registering netdev failed\n");
1045 dev_info(&pdev
->dev
, "device registered (reg_base=%p, irq=%d)\n",
1046 priv
->reg_base
, dev
->irq
);
1055 release_mem_region(res
->start
, resource_size(res
));
1062 static int __devexit
at91_can_remove(struct platform_device
*pdev
)
1064 struct net_device
*dev
= platform_get_drvdata(pdev
);
1065 struct at91_priv
*priv
= netdev_priv(dev
);
1066 struct resource
*res
;
1068 unregister_netdev(dev
);
1070 platform_set_drvdata(pdev
, NULL
);
1074 iounmap(priv
->reg_base
);
1076 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1077 release_mem_region(res
->start
, resource_size(res
));
1084 static struct platform_driver at91_can_driver
= {
1085 .probe
= at91_can_probe
,
1086 .remove
= __devexit_p(at91_can_remove
),
1089 .owner
= THIS_MODULE
,
1093 static int __init
at91_can_module_init(void)
1095 printk(KERN_INFO
"%s netdevice driver\n", DRV_NAME
);
1096 return platform_driver_register(&at91_can_driver
);
1099 static void __exit
at91_can_module_exit(void)
1101 platform_driver_unregister(&at91_can_driver
);
1102 printk(KERN_INFO
"%s: driver removed\n", DRV_NAME
);
1105 module_init(at91_can_module_init
);
1106 module_exit(at91_can_module_exit
);
1108 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
1109 MODULE_LICENSE("GPL v2");
1110 MODULE_DESCRIPTION(DRV_NAME
" CAN netdevice driver");